/ Cha pte r(2) l_n str uc tio n Se t and

Programming of 8085

I Probable marks : 43
I
Scope of the syllabus :-
• Addressing modes in 8085
.. fi:?gramming model of 8085
• Instruction Set and
• Programming of 8085
• Study of instruction set :
instructions.
• Data transfer, Arithmetic, Logic,' Branching, Stack, 1/0 and machin e control
• Assembly language program ming based on instructions.

addressing
Q. 1 What do you mean by addressing modes of a microprocessor ? Enlist the
modes in 8085.
Ans.:
ying one operands
(1) · Addressing mode of a IlllLa.1processor is the variou s forma ts of specif
r or it can
(direc_tly, indirectly etc). The operan d can be data (8 or 16 bit), addres s, registe
be implicit.
uses one
(2) Every microproces-'lr has its own set of instruc tions. Each of these instruc tions
of the addres sing modes. ·
:
(3) The microprocessor 8085 has five addres sing mode_s, which are given below
i) Direct addres sing
ii) · Register addres sing
iii) Immed iate addres sing
iv) Register indirect addres sing
v) Implie d addres sing

Q. 2 Explain any two addressing modes in 8085. OR

Explain all addressing modes in 8085. OR
·
Explain direct and implic. it addressing mode s of 8085 m1cro processor.
OR
&dJ
. · . . used ·n 80 m · mwe,all•~
E lai·n any tw0
What are differ ent addres sing modes 85 1 1croprocessor 1. xp ~

of them with a suitab le example. tMEii• ►l•iM•ii•ki#IJ■ i•&l4mPl11H1jl!UP'

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 TPS CL)mputer Science - l] 2-2 lnslrnct10n S(,t and Programming of 8Ck~5

Ans. : (I) Direct addressing mode : (Jul 201i, March 2018

(1) In direct add ressin& the address appears after ovrode of instruction in program
memorY.
(2) The address of operand is specified within the instruction.
(3) The instructions using direct addressing m ode are three b~ie instructions. B~i e 1 is
opcode of instruction, Byte 2 is lower order address an d By te 3 is high order
address.
(-1) For e.g. LDA 9FF}:H
i.e. This instruction loads accumulator with content of memory location 9FFF H.
ITT) Register addressing mode : (March 200-1)
(1) In register addressing mode, the source operanas are general p urpose registers
whose name is specified within the instruction.
a (2) These instructions are single byte instructions.
(3) All actions occur within the CPU.
(4) For e.g. MOVA, B.
i.e. This instruction transfers the content of registe r B to accumulator \dthou t
modifying the e:ontent of B.
(Ill) Immediate addressing mode : (~larch201S,Julv1019)
(1) In immediate addressing the data appears immediately after opcod e of instruction
in program memory.
(2) In these instructions the actual data is specified ·within the instruction .
(3) These operations are specified "\-\'1th either 2 or 3 byte instructions.
For e.g. ADI 05H
(4)
i.e. this instruction adds immediate data OS H to the content of accumulah)r. Th~
result is stored in accumulator.
(IV) Register indirect addressing mode : (Oct. '.:?005, 2009; Julv 2017
(1) In register indirect addressing the
content of register p a ir p oints tc, the ,11.i d r'=':S:S ,)t
the operand.
(2) A register pair (H-L pair) is specified for addressing 16-bit addre~ . of nw nHm·
location.
(3) These .a re gene rally 1-byte instruction.
(4) For e.g. ADO M
i.e. this ins truction w ill ad d the rnntent of m e rnNv lnc1t ilm w hl):-t' clli.dre:S:- i:-
stored in H-L pair to the content of a(cumulMor.
(V) Implicit addressing mode : tME:i@
(1) In this type of ins h·urt ions, ge ner<1lly npt>rc\n\.i is rh)t sre,:ifil"i. ,,·ithin the "in:--trn,·th,n
and it is p red eterm in t>d.
(2) Gene rally the operan d is acCLlmuld tor.
(3) Mos ~of the logicn l g rou p instruc tinm bt:'long h, th 1:,; ,hld rl'~"in~ nH,,fr

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 --
TI'S Compu tt>r SciM,<'t? - U 2-3 ln~tru ction Set 1:1nd Progra mm ing nf 808.s

{4) These ar,e single by te instruc tions.

(S) All actions occur within the C PU .
(6) Fo r e .g . 0..iA
Le . this instr uctmn will complement the conte11 t of accumulator . Here, the actual
opera nd is not specified in the instruction , but is predetermin ed (accumulato r). The
resul t is stored in accumulato r .

Q. 3 Explain register indirect. and immediate addressing modes in case of 8085

m icmp l'O<'essor with the help of s'Uitable examples.
(Oct. 03,07,0S; June lb; Jul · 17, March 20:?0)
Ans.: n Register indirect addressing mode:
1) Regist-er indirect instructions reference memory using the contents of a register pair to
pom t the add ress of the operand .
2) A regis ter pair {H-L pair) is specified for addressing 16-bit address of memory loca tion.
3) These are generally l byt~ instructions.
4) Fo r .example :
ADD M (add memory)
This instruction ad,d s the con ten ts of the accumulator to the contents of memory pointed
to by tht? ad dress in the HL register pair.

Accumulator 1 1 1 1 1 l 1 1 / l OOOO OOO O! Accumulator

c--A~D~D~M~=:>

D.ata cr1ie.1:nory - - - - - -
405\l ...,0_ 0 _0_0_0_0_0_1_ ~ 1°1 1 1~1 1 1-1 1 1-11 1
S Z AC P CY
~ L Fla gs
-->;btt>r f
--- ~-'(.)_ __}_ _SO _
H Lpl'(.li r
&-fort!' O JX' I atmn After operation

ln th t> ,;t,·en t'X<lmpl~, the H L register pai r points to mem ory loca tion 4050 H . T he data in
th .i s Jo canon (t(X)U OOOl )i 11, Hum .tddt>d to tne n mt~nts o f the accumulator (l l 11 111 l )i.
Tile su1n IS Sh.l r ~ in a<.'Cu.mulato r and appropria t.e flags are also set dnd reset based on
the .re51uJt.
U) J.m:med i~te addrt>i~h1g mod~ ; tl\l.11l"h :!OOI.))
1) Jn 1mrn00Ja f~ addres.~uig tlw d a ta a pp~ars immediately aft.er opcode of ins tnicti(,n i.n
p rograui rnl"mtJr}'
2) ·n11."lt' clfC >;.:-nH,l ll r 2 or ) r yt<: iH'-lrucfoms.

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TPS Computer Science - II 2-4 Instruction Set and Programming of 8085

3) For example ADI 08 H

Accumulator ~
·~ O O 1o
I OO ~ ---~~ / ~ L_o_o_Q_!__0_l_Q_O_...I Accumulato r

CADI08=:>
Opcode
Program
m emory C6H ~ 1°1°1 -11 1-111-1°1
4050 0000 1000 S Z AC P CY
data Flags
Before operation After operation

In the example, MPU fetches the opcode (C6) from program memory and after decoding
it. MPU finds the immediate data (0000 lOOO)z in the next consecutive program memory
location. This data is added to the contents of the accumulator and result is placed in the
accumulator.
Q. 4 What do you understand by register indirect and implicit addressing modes ?
Explain with suitable example. List the names of any four instructions which make
accumulator content clear. . «•IIJunijj
Ans. : Register indirect addressing : Please refer to Q. 3 (I).
Implicit addressing: Please refer to Q. 3 (II).
Following four instructions make accumulator content clear :
(1) ANI OOH (2) XRA A · (3) SUB A (4) MVI A, OOH

Q. 5 What are the different ways of clearing Accumulator (A = OOH) in single

instruction? (:\larch :?.011, :?.017)
Ans : (i) MVI A, OOH (ii) SUB A
(iii) XRA A (iv) ANIOOH

Q. 6 What are the groups in which instructions in 8085 are classified? i•S•M
Ans. : The instructions in 8085 can be classified into following five groups, depending upon
their function :
1) Data transfer group 2) Arithmetic group
3) Logical group 4) Branching group
5) Machine control group
1) Data Transfer Group :
This group of instruction copies data from a location called source to another location
called a destination without modifying the content of source. These instructions move
data between registers or between memory locations and regjs ters. For eg. MOV,
MVletc.
2) Arithmetic Group :
The instruction of this group performs arithmetic operations such as ad dition,
subtraction, increment or decrement etc. on d ata in registers or memory . For eg. ADD,
SUU, fNR, OCR etc.

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·n >S Compute r Sdence - II 2-5 Instruction Set and Programming of 8085

3) Logical Group :
The logical group instructions perform logical operations such as AND, OR, XOR,
complement etc. generally with the accumulator.
4) Branching Group :
The branching group instructions allow programmer to change the sequence of
execution of program either conditionally or unconditionally.
For e.g. JMP, JC, JZ etc.
5) Machine Control Group : · .
These instructions control machine operations such as Halt, Interrupt
For e.g. NOP, HLT.

Q. 7 How instructions of 8085 are grouped according to its len.gth ?

Ans. : Instructions of microprocessor 8085 are grouped into three groups according to its
length as follows:-
(i) One byte instructions (One word)
(ii) Two byte instructions (Two word)
(iii) Three·byte instructions (Three word)
(i) One byte instructions :
These instructio~ are having opcode and operand both in m~e byte. These require only
one byte to store m memory. - · - - •· · .
I OPCODE & OPERAND j 1 Byte
e.g. MOV A BJ ADD B etc.
(ii) Two byte instructions :
These instru~ons require two bytes to store in memory. First byte gives opcode and
second byte gives operand, which is generally 8-bit immediate data.
OPCODE First Byte
Data/ Address Second Byte
e.g. SUI 35 H, ADI FF H etc.
(iii) Three byte instructions:
These instructions require three bytes to store . _ . .
second and third_byte gives 16_b't dd f m memory. Firs t byte giv es opcode and
1 a ress o mem - 1 • . .- .
Note that second byte gives lower O d ddr ory ocation or 16-bit 1mmed1ate data.
order address/ data byte. r er a ess / d ata byte and third b y te gives higher

_ P_C_O_D_E_ ____J First Byte

r-O
Low order 8-bit Second byte
of address / d ata
High order 8-bit Third byte
of addre1;s/ data
-- ----- .
e.g. LOA BAFF H,
LXI H, FFE3 H

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TPS Comput er Science - II 2-6 Instruction Set and Program ming of 8085

Q. 8 Explain the followi ng instructions of 8085 microprocessor with suitable example.

(a) SPHL (b) PCHL (Mar. 02, 2010, 03, Oct. 08. 10)
Ans. : (a) SPHL: [Copy Hand L register to SP]
Format [SPL] r LL]
[SPtt] r [HJ
Addressing Register addressing
Group Machin~ control group [stack operation]
Bytes 1 byte
Flag None
Comment : · This instruction copies the content of register L into lower order byte
of
stack pointer and the content of register H into. higher order byte stack pointer . The
content of registers Hand Lare not affected. This instruction is used for initializing the
stack pointer.
Example Let, [H] = 25 Hand [L] = 59 H
Instruction : SPHL
After execution : [SP] = 2559 H
(b) PCHL :
[LOAD PROGRAM COUNTER WITH HL REGISTER PAIR CONTENT]
GMetil•I@
Format [PCtt] ~ [H]
[PCL] f-- [L]
Addressing Register addressing
Group Branching group
Bytes 1 byte
Flag None
Comme nt : This instruction moves the content of register H to higher order byte
of program
counter and the content of register L to lower order byte of program counter.
This instruction is equivalent to one byte unconditional jump instruction, with jump
address stored in H-L pair. ,
Example : Let, [H] =25 Hand [L] = 39 H
Instruction : PCHL
After execution : [PC] = 2539 H
After execution of PCHL instruction, 'the control will be transferred to memory location
2539 H.

Q. 9 Explain PCHL Instruction of micro-processor 8085 and justify the stateme nt that
it is
equival ent to 3 byte uncond itional jump instruct ion. !•tJl@j t)j
Ans. : For only Explanation of PHCL Please refer Q. B(b), Pg. No. 2-6.
In PCHL progra~ _counter is loas{eq \,\{i U1 _memol'y ad_dress stored in HL _pair,.. ln JMP
a1dr_ess y r~gram _c~unter is loaded_ with memory address specified in instruction.
Workin g of both instruct ion is same i.e. load PC ,-vith 1nemory -address hence PCI IL
is
equival ent to uncondi tiona l jump

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V, lO

Ans. ; 1 (1111 11 , u1 11 11 1111

, 'Pl\11'1.I Pt ll,,1 \ 111 ,,11 ,;~1
Tl it· lf'~tnw t,N \,., w!ul'I, P ll\•W ll!ii:1 I\\ d11111} w tlit>
(U
~11v , allC< t I.ho l•r,,nd 11n
~ 11\ltl lrw tl11.11~
11.,1 10 1, 111
h ,, ,,11 ll\!i tl' \u ·tit111-. 11111 •1,1iditi11,1.1I Mid 11111;!11
tq~ •~ ,1t 11
(~) Th e," ' a r,· two t1~111 rd1 11 1111, tt lrll u,i ,11· 111\ u 11r
itl, ,n ,~ l~ll ltld tn \'l'lldilllll!AI
UIW(\t\,llti.,,11 " l h~l \"tfv1 , \\\l ~'( \\ld 1 t 1l'<\ IWh in h 1 Iii.' v \ r.w 11l'f; d
1
111 11 11 1
c nnl l1t' wlw tlw 1 th1
ttw fl <lf:. l1< h·~trd tv dd
1\~ o t)' f'( ll'!l \)l 1w.1\~• t,,~ti \ll'lt<•I\~ ,11r ,,~ fnlh 1\V/i
() ) lJr, cx,1,dHh 1nr,l 111mp :
ln~tru ('tmn JMl' '°'drlr
t, orm at It\ <- tt1Mr 1
}

lt11n1( di,1h·· ,uk ht ¥i~J inp.

11

A dd re~itn~
G n,u p ttr,1nchln~ r:r, 111p
Hytr9 ,'\ by h'S
Fla1,; No-tw
-1 r1
tm l l:i tr,m ~fo rt't·d 1nH .'\1.ndJthm ally to llw 1rw111urv l~ 1,·MliH1 1 whor
Co mm ent : Th,• ~)n
,n.
add r~,s 111o sptx-lfit'd in tht- imi tructh
(4} ConcHtio na l It.imp : v If ,tw
..t:.t.!J}dl th 111 l.1 tru, 1. l'lit:•
ctk ,n~ . thr• /m np 1~ tak N, nnl
1n com:Utinnal jum p in~tru
dlth,n~ fU't 1 ltk Hlvt•n lwlow .
ron d1tl,,n ,d jum p in~tructlon~ nnd con
i) JN Z n('fdr Jum p on not i t•ro (Z ~ 0)
1i) JZ "'dctr Jump cil\ ~,•ft,
(Z 1) i;;

iii) )NC ad dr lum p on O\\ t Cfl fr)' (Cy • 0)

iv) IC dd dr Jump <)n c;arry (Cy ,."' I)
v) JPO ndd r Jum p on od d pnrlty (I' ,. 0)
vi) JPE add r Jump 01, t·v,•n p{l dty (l' I)
vii) JJ> f.ti..i d r Jum p vn plu~ (S ~ 0)
Jump l'n l'\\inu:-1 (~ rz I)
vi ii) JM odd r k d 111 llt1•
is ~i1tif1fi td. tlw n onl y tlw ,1ddn·1-1N pf u"l1.•mn1y lt,\.' (ttk,n ~p, ,df
1f the condHJOn
in!» lrU <.' tiP n ii- lo,1J ~ I in PW81'ilOI vount(•r.

be "'al led nm dit ion all y ,rnd lrn

cor,dltlon"llY ? Oi l
Q. H Ho w a s ub rou tin e C'ilf i
mlcropriu·,·tHun·. Ul l
f1CpJaln CAI.L Jttslru cUon of Rotty; JU lm H\ l~
lal11 \11 \\'0 lhll tlnt Hd - -~l\d \'()O
flih\i,DIIIQiilGBiliF\iCMDI~.
o( 808 5 mk rop ,·or~11t:1or, oxp
In caHe~
h-..
ins tru r taons wHh t;uHable <·Mltltp
An s. ; i,
,,f 111 ·<,}1.rtl1n lt11-1 tn11 ·th,11 H w rllh 'n ~•l'J'n t'uWh•' tnu11 tlw p\,,1
(.l) A L-1 ufir(lut lt w 1~ ~t ~ho rf ~rt ro~ fo tll ,
riu form 1 flltH llti n th. it or4 11r:-. 1'••1w ,11t-dl v in llw m uin p
•
pw ~rt1rn to

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iPS Computer Science - U 2-8 Instruction Set and Programming of &J85

(2) A subroutine can be called by two ways :

(a) Unconditional call :
Instruction CALLaddT
Format [[SP] -1) f-1 Pett l
[[SP] - 2] f- [ PCL ]
[SP] f- [SP] - 2
[PC} f- addr
Addressing Immediate addressing
Group Branching group
Bytes 3 bytes
Comment CALL instruction is used to call a subroutine unconditionally. Before the
control is transferred to the subroutine, the address of next instruction to be executed of
the main program is stored in the stack. The content of SP are decremented by 2 Then,
the program jumps to the subroutine whose starting address is specified in the
instruction.
(b) Conditional Call:

In conditional call, the subroutine is called only if the condition is satisfied. In

conditional call, following J)rocedure is followed, if the condition is true.
Format : · [[SP] - 1] f- [ PCH]
[[SP] - 2] f-- [ PCL]
[SP] f- [SP] - 2
[PC] f- addr
The conditional call instructions and conditions are as listed below :
i) CC addr Call if carry (Cy= 1)
ii) CNC addr Call if no carry (Cy = 0)
iii) CZ addr Call if zero (Z = 1)
iv) CNZaddr Call if no zero (Z = 0)
v) CP addr Call if plus (S = 0)
vi) CM addr Call if minus (S = 1)
vii) CPOaddr Call if odd parity (P = 0)
viii) CPE addr Call if even parity (P = 1)

Q. 12 Explain return procedure in RET instruction.

Ans. :
(l ) The RET instructions are used to return from s ubroutine to main program.
(2) The return instruction bi written at the end of the s ubroutine indicatin~ end of
subrou ti nf'.

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(3) lnstr nction : RET
[PCt ) +--- [[SP JJ, [PCHJ r- [ fSP} .£. lJ
Fom lat
[SPJ f-- {SPJ + 2
Add ress ing Regi ster i:.ncli.rect
Gro up Bran chin g grou p
Byte s 1 byte
se addr ess is specified in stac k pot-..::::-
Com men t: The cont ent of memory loca tion, \.,,-ho
coun ter. The cont ent of tlte memory !ocz::.::-
are mo~·ed to the lowe r orde r byte of prog ram
SP mov ed to the high er orde r byte of p::og z:
who se addr es.s is one :nore than the cont ent of
eme nted by 2.
counter. The cont ents of stac k poin ter are incr
instr uctio n is exec uted \-'-T uch~ ~
(4) On com pleti ng the exec utio n of subr outi ne the RET
ucti on follo-..ving CAL L instr ucri.on. :-
back the stac k cont ents i.e. addr esse s of the instr
mai n prog ram .
prog ram coun ter. Thu s the cont rol retu rns into

Q. 13 Exp lain the use of stac k and stac k pain ter regi
ster in Inte l 8085 . 49 ii
Ans .:
is used for tem pora ry stor age of En..:a:-:-
1) The stac k is a part of Read / Writ e mem ory that
.
inior ma tion duri ng the exec utio n of a prog ram
te resu lts and the retu rn add.i..'""ESS fr: 2-..'-c'
2) The b inar y info rmat ion is basi cally the imm edia
o f subr outi ne prog ram s:
micr opro cess or.
3) The stac k is shar ed by the prog ram mer and the
ents of a regi steI pair by usin g F~.'~-:'.-:
4) The prog ram mer can stor e and retri eve the cont
and POP instr uctio ns.
es the cont ents of the pn~ ram C\.)t:f i:-£
5} Simi larly, the micr opro cess or auto mati cally stor
whe n subr outi ne is calle d.
ial mem o.rv poin ter ~ ca.He--.1 :.:~
6J The stac k is imp leme nted with the help of spec ·
0

s tack poin ter.

[>LJ iing P USH and POP oper ation stac k
poin ter reg i~r gi\·e s the add r~ of rnc.:n'-":·.
71
.
whe n? the informat ion is to be stor ed or to be read
.::,tac k pt.,' inte r is cnlJe d as top oi ::;tac.k.
8) The memo ry J.oca hon curr ently provided by

be co.n tent of accumul at.o r atttr

Q . 14 Acc umu Ltlo r contains data 2A H . Wha t will
ex.e-cutio n of each ins truc tion inde pend entl y?
(i ) C MA (ji) At\ l 05 H ( i ii) STC

{iJ C M A : ( \,rn pltm ent Hu- J ff um uL1

tur
Ans . :
&fort' t:•u>(utiu n I.•\J -::: 2.J\ H :.:: 1) 0 1 U l O l O
fn~tr·uclt on C~I 4.
fA J ::. l I O 1 l ) t l) } --' l ).5 f I

j(' f \ } - n ::; H

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 iPS Compute r Science - II 2-10 ln.struction Set and Programming of 8085

(ii) ANI 05 H AND immediate da ta 05 H with [A]

Before execution [A] = 2A H = 0010101 0
Instruction AN105H
2AH = 00 10 10 10
AND 05 H = 00000101
0 0 0 0 0 0 0 0 = 00 H
i.e. (A] = 00 H
(iii) STC : Set carry
Before execution: [A]= 2AH
Instruction : STC ·
This instruction will only set carry flag to 1 and contents of accumulator will remain as it
is.
After execution : [A]= 2AH
i.e. [A]= 2AH and [Cy]= 1

Q. 15 Accumulator contains data E3H. What will be the content of accumulator after
stepwise execution of each of following instructions ?
•&•0M*
t1
(i) ANI 58 H (ii) RRC (iii) CMA
Ans. : (i) ANI 58 H : Logically ANDed 58 H with [A]
Before execution: [A] = E3H '
Instruction : ANI 58 H
E3 H = 11100011
AND 58 H = 01011000
01000000 =40H
After execution [A] = 40 H
(ii) RRC : Rotate accumulator right by one bit.
Before execution : [A]= 40 H = 010000000
Instruction : RRC
After execution [A]= 0 0 100 0 0 0 = 20 H
and [Cy ] = 0 H
[A] = 20 H
(iii) CMA : Complement the contents of accumula tor
Before execution : (A J = 20 H :::: 0 0 1 00 0 0 0
In struction : CMA
After execution : (AJ = 1 1 0 1 1 11 1 :;:; DFH ' A] :::: DFH
1

Q. 16 The accumulator in 8085 contains the data BSH and register B contains dat.i 40 H.
What will be the content of accum u lator after execution of each of tht! following
instructions independe ntl y ? (l\1,ufh 1002)
(a) RLC (b) ORI 2'J H (d AN A B

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 •t _an
u_ct_i<_)n_s_·c_ gramm ing of
_d_ Pr_o.:::_
_T_P_s _c_o_m_p_u_te_r_S_c_ic_n_ce_-_1_1_ __ _ __ _ _ _2_-'1_1_ _ ._ _1n_s_tr_ -- 8v0,
-----..___ - '-J

Ans.:
(a) RLC: Rotate accum ulator left throug h carry.
Before execu tion: (A] = B8H = 10111000
Instru ction : RLC
After execu tion: (A]= 0 1 1 1 0 0 0 1 = 71 H
:. [Al= 71 Hand [Cy]= 1 H
(b) ORI 29 H: Logica lly ORed 29 H with [A]
Before execu tion: [A)= B8H = 10111000
Instru ction ORI 29 H
B8H = 1 0 1 1 1 0 0 0
OR 29 H = 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 = B9H
After execut ion : [A] = B9H
(c) ANA B: Logically AND [Reg. B] with [A]
Before execut ion: [A]= B8H = 1011 100 0
[Reg. B] = 40 H = 0 1 0 0 0 0 0 0
Instruc tion : ANA B
1011 1000
AND 0100 0000
0000 0000 =00H
After execut ion:
[A] = 00 H
execution of
Q. 17 The accumulator contains the data A4H. What will be its conten ts after
follow ing instructions indepe ndentl y. iiiBNiS!
i) XRI 08H ii) CMA iii) SUB A

Ans.:
Accumulator = A4 H
= 1010 0100

0 XRI 08 H:
Logically Ex-ORed 08H with conten ts of accum ulator.
Before execut ion: [A)= A4 H
Instru ction: XRI 08 H
A4 H = 10100100
XOR OB H = 0 0 0 010 0 O
1010 1100
= ACH
After execu tion: lAJ = ACH

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 llJS C()mputt"r Science - l1 2-1 2 Instruction Set and Programming of 8085

ii) CMA :
Complement the accumulator
Before execution : [A] = A4 H
=10100100 '
Instruction : CMA
After execution :
[A] = 01011011
= SBH
i.e. [A] = SB H
iii} SUB A:
Subtract accumulator from itseU.
Before execution : [A] = A4 H
Instruction : SUB A
[A] : A4 H =10100100
2's complement of A4 = 0 1 0 111 0 0
+ [A] : A4 = 1 0 1 0 0 1 0 0
IT] 00000000
complement carry .J..

0 00000000
Result [A] = 00 H

Q. 18 The accumulator of 8085 contains data 43H. What will be its co.n tents after the
execution of follo~g instructions independently ?

(i) CMA (ii) ANI 09H (iii) JNR A

Niii
Ans.:
H CMA : Before executions accumulator content is :
[A} = 43 H
::;: 01000011
CMA insbuction compft,m(:nt~ th(• contents of accLHl\lllator dnd result i~ ston-'\i in tht>
accumulator itself
IA] = J O1 l 1 1 00
= BCH
Aftt>r execu t10n : IAJ= BCI l

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TPS Comp uter Scien ce• JI 2-13 Instru ction Set and Progr ammi ng of 8085

conte nts of accum ulato r.

ii) ANI 09H : This instru ction logica lly AND ed 09H with the
Before execu tion: [A] = 43 H
= 0100 0011
[A) = 43H = 0 1 0 0 0 0 1 1
AND 09H = 0 0 O O 1 0 0 1
0 0 0 0 0 0 0 1 = 01 ~
:. After execu tion : [Al = OlH
ulato r by one and result
iii) INR A : This instru ction incre ment s the conte nts of accum
store d in the accum ulato r itself.
Befor e execu tion:
[Al = 43 H = o 1 o O O O 1.1
[A] = 43 H :a: 0 1 0 0 0 0 11
+ 0 lH - 0 0 0 0 0 0 0 1
0100 0100 =44 H
After execu tion : [A] = 44 H
data 45 H and register E
Q. 19 The accumulator of 8085 microprocessor conta ins the
mula tor after execution of
contains the data 7BH. What will be the conte nt of ~ccu
each of follow ing instructions indep ende ntly ? (Mar . 04, 2011)
conte nts of regis ter ·E i.e. 7BH with
Ans. : (i) XRA E. : This instru ction logic ally EX-O Red the
the conte nts of accum ulato r i.e. 45H.
Befor:e execu tion :
[A] = 45H = 01000101

[E] = 7BH = 0 11110 1 1

Then , 45H = 010 001 01

XOR 7BH = 0 1111011

0 0 1 1 1 1 1 0 = 3E H
So after execu tion of instru ction I

{A) = 3E H
(ii) ADI C5H :

This instru ction adds the data CSH to th e con tent of accu mula tor i.e. 45H.
(AJ ; 451-f = 0 1 00 0 1 O 1

+CSH == ll...OOO 1 O 1
~

0 0 0 0 1 O 1 o = OA H
After execut-ion, fA] ::; Oooo 1 o 1 0
= OAH

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TP5 Computer Science - 11 2-14 Instruction Set and Programming of 8085

(iii) ORI 58H:

Thjs instruction logically ORed the data SBH with the content of accumulator i.e. 45H.
[A]= 45H = 01000101
OR SBH = 01011011
0 1 0 1 1 1 1 1 = SF H
After execution, [A]= 0 101 1 111 = SF H

Q. 20 Accumulator of 8085 contains data 56 H. What will be the contents after the
execution of following instruction independently. ('.\larch 200'.i)

(i) CMA (ii) ANI ACH (iii) INR A

Ans. : [A] = 56H = 0 1 0 1 0 1 1 0
(i) CMA:
This instruction complements the contents of accumulator and result is placed
in accumulator itself.
[A]= 56 H = 01010110
After execution : CMA
[A] = 101 0 1 0 0 1 = A9H
:. [A] = A9H

(ii) ANI ACH :

This instruction is logically ANDed ACH with the contents of accumulator.

Before execution :
[A] = 56 H = 0 1 0 1 0 11 0
Data = ACH = 10 101100
[A) = 56 H = 0 1 0 1 0 11 0
AND ACH = 10101100
00000100 =04H
After execution : [A) =04H

(iii) INR A : This instruction increments the c<;mtents of accumulatqr by one and result
stored in the accumulator itself.
Before execution :
[A] = 56 H = 0 10101 1 0
[A] = 56 H = 0 101011 0
+ 01H = 0 0 0 0 0 0 U1
0 1 0 1 0 l 1 l = 57 H
After execution : IA] = 57 H

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TPS Computer Science - II 2-15 Instruction Set and Programming of
8085

Q. 21 If ACC contains data BCH, register C contains ADH. What will be the content of
accumulator after execution of each of the following iruJtructions independently?
(i) SUB C (ii) CMA (iii) XRA C -
Ans. : Accumulator = BCH = 1 O1111 0 O
(i) SUB C : Subtract contents of register C from accumulator.

Before execution :
[A] = BCH = 1 0 111 1 0 0 .
[C] = ADH = 1 0 1 0 1 1 0 1
Instruction : SUB C
[A]= BCH = 1 0 11 1 1 0 0

[C] =ADH = 10101101

2's complement of [C] , = 01010011
[A] = 1 0 1111 0 0
+ 2's complement of [C] = 01010011
CD 00001111
complement carry J.
[QJ 000001111

Result [A] = 0 0 0 0 1111 =OF H

(ii ) CMA: Complement the accumulator.
Before execution :
[A] = BCH = 101111 0 O
Instruction : CMA
After execution :
[AJ = o1 o·ooo11 = 43 H
Result= [A] = 43H
( iii) XRA C : Logically Ex-ORed contents of C with contents of accumulator ..
Before execution : [A] = BCH
Instruction XRA C
[AJ = BCH = 1 0 1 1 11 Oo
XOR [CJ =ADH · = 1 01 O1 1 O1
000 1 0001
= llH
· After execution: [A] ::: 11 H

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 TPS Computer Science - 11 lm trnrti11n ~•d <'\ lid l' n,~1'•111111111,~ 111 tilt!1't

Q. 22 The accumulator of 8085 proces..!lor et>nt•ins delta tUU-.t and regll ter fl c-uf\l'flin- iJ~ ft ,
What will be the content of a{-eumulator after e~~rution nf e4tr h of the f'ollowh1 0
instruction indepe.ndentJy ? l~l.111 h J tll ll
(i) ORI FOH (ii) ANA B um XtU O.FH
Ans.:
Accu:mulator A= B 8 H =10111000
(i) ORI F0 H - logically OR ed FO H with [A]
B8 H = 10 11 1000
ORI F0 H = 11 11 0000
11 11 1000 = F 8 H
After execution [A]= F 8 H
(ii) ANA B - Logically AND (Reg B) with [A]
B8 H = 10 11 1000
AND B-44 H = 0100 0100
00 00 0000 = 00 H
After execution [A]= 00 H
(iii) XRI OF H - Logically Ex-ored OF H with [A]
BBH = 10111000
XRI OF H = 00001111
10 11 0111 = B 7 H
After execution [A] = B7 H

Q. 23 If Accumulator -Contains the Data 23H and B Register Contains 35H. What will bt
the contents of Accumulator. After execution of each of the following instruction
independently : . fMMiJljj
(i) XRA (ii) ANI FOH (iii) CPI OAH
Ans.:
A = 23 H = ·0010 0011
B = 35 H = 0011 0101
(i) XRA B - Ex.ored reg. B with contents of A.
23 H = 0010 0011
XOR with 35 H = 0011 0101

= 00010110
---
1 6
A = 16H

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 of 8085
2-17 Ins truc tion Set and Pro gra mm ing
TPS Co mp ute r Science - Il

wit h con ten ts of A.

(ii) AN IFO H - Log ica lly AN D FO H
FO = 1111 0000
AN D 23 = 0010 0011
0010 0000

2 0
A= 20 H
A reg.
(ill ) CP IOA H - Co mp are OA H wit h
A = 23 Hf - Bef ore exe cut ion
ain s
Wh ile com pai rin g Ac rum ula tor rem
Un cha nge d hen ce A = _2 3 H
G9 H. Wh at are the
and Re gis ter B con ten ts are
Accumulator contents are B81{
Q. 24
tor an aF iag reg iste r aft er exe cut ion of ins ~c tio ns AN A B . .... ,

contents of Accumula t
. (;\l arc h 20] . I)
SU B B independenUy. '
Ans.:
(A) = BBH = 10111000
(B) = C9 H = 11001001
ula tor
'1) ANAB : Logically AN D wit h Ac cum
10. ll 1000
110 010 01
~q~q1lOO0
A 88H '=
Fla gs ➔ S =1, Z =0, AC = 0, P ~
i,
CY = O
cum ula tor
(2) SUB B : Sub tra ct B Reg. fro m Ac
B = llOO 1001
l's com ple me nt of B = 0011 011
0
+ 1 + 1
2's com ple me nt of B 0011 0111
Ad d A wit h 2's com ple me nt of B
001 101 11
+ 1011 1000
@) 111 011 11

Co mp lem ent car ry i

OJ 111 011 11

Res ult ➔ A = EF H
Fla gs - , S = 1, Z = 0, AC == o, p = 0,
CY = 1

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TI'S Computer Science - U 2-18 Instruction Set and Programming of 8085

Q. 25 For the following instructions, write the addressing mode, instruction group and
the length of,the rnstruction (in terms of bytes). (if)a•fijj
(i) LHLD ABCDH (ii) LDAX B

(iii) LXI H, BABAH (iv) SPHL

Ans. : (i) LHLD ABCDH: Pleue refer Appendix I (9).
(ii) LDAX B: Please refer Appendix I (11).
(iii) LXI H, BABAH: Please refer Append.ix I (6).
(iv) SPHL: Please refer Appendix V (6).

Q . 26 The following instructions are intended to clear ten (10) memory locations starting
from th-e memory address 0009H. Explain why a large memory bl-0ek will be erased
or cleared and the program will stay in an infinite loop. Nfli•@l
LXI H, 0009H
LoopMVI M,OOH
DCXH
JNZLoop
HLT
Ans.:
(1) In given loop, large memory block will be erased or cleared and the program will stay in
an infinite loop.
(2) In the given loop, the sequence is repeated by the instruction JNZ Gump on No zero)
until the count becomes zero. However, the instruction DCX does not set the zero flag.
Therefore, the instruction JNZ would be unable to recognize when the count has
reached zero and the program would remain in a continuous loop.

Q. 27 Explain following instructions of 8085 microprocessor. 1\1.m.:h 200~)

{i) ORI data (ii) STAX rp (iii) LHLD addr
Ans. : Refer Appendix

Q. 28 What ue different addressing modes ? Which type of addressin_g mode is used for
following instructions ? MIQ@jj
(i) XCHG (ii) XRI (iii) SUB M (iv) CMC
Am. : Ref-erQ.l and appendix.
Q. 29 ldecntify the addressing modes of the following instructions and justify your
.mswer. W LOA 2000 H (ii) LDAX B (iii) STC (iv) ADC 0
Ant. : Ri:~e~~ ~ . 0 : to_~nd addressing mode and re.fer Q 2_to justif221nsw!::r·
Q. 30 Describe fo llowing instTuctfons of 8085 microprocessor. ~ 4ii111iiiiii@
iiiiiw!i,
ti} XCHG (ii) RA R (i ii) ADC R
Ans. : Ple~ refer appendix.

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TPS Computer Science - 11 2-19 lnstn1ction Set and Programming f
o Boss
Q. 31 Explain the following instructions of 8085 microprocessor with suitable e '
(i) RLC (ii) DAA
Ans. : Refer appendix.
Q. 32 ~xplain the following instructions. IMBi@iJ}ifjj,i
h) PCHL (ii) PUSH PSW (iii) OUT (iv) NOP ~
Ans. : Refer appendix.
Q. 33 Explain the addressing modes of following instructions: ~
(i) LOA (ii) STAX - (iii) CMA ~
Ans. : Refer appendix.
i) Group I (7) ii) Group I (12) iii) Group ID (17)
Q. 34 Accumulator contains 45H [(A)= 451, Register E contains data 3BH [(E) =3B] w;;--
the contents of Accumulator after execution of following instructions
independently : i) SUB E ii) XRA E iii) RRC iv) MOV E,A (Oct. 2009, 20lOJ
Ans: a) [A] = 45 H = 0100 0101
[E] = 3BH = 0011 1011
i) SUB E : Subtract contents of register E from accumulator.
[A] = 45 H =0100 QlOl
[E] = 3BH = 0011 1011
2' s complement of [E]
= l's complement of [E] + 1_
= 11000100+1
= 11000101
[A] = 0 1 0 .O O 1 0 -1
2's complement of [E] = 11000101
=ill
00001010
complement carry [QJ O O O O 1 0 1 0
:. Result [A] = 0 0 0 0 101 0
= OAH
ii) XRA E: Logically Ex-ORed contents of E with contents of accumulator.
[A] = 45 H = 0 1000 1 0 1
XOR [E] = 3BH = 0 011 1011
01111110 = 7E H
Result : {A] = 7EH
iii) RRC : Rotate accumulator right by one bit
Before execution :
[AJ = 45 H =0 1 0 0 0 1 0 1
After execution :
[Al = 1 o1 ooO1 o
= A2H
[A] = A2H
iv) Mov E, A : Copy accumulator contents to register E.
Before execution :
[A] = 45 H =0 1 0 0 0 1 O1
lEJ = 3BH = OO11 1 O1 1

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TPS Computer Science - II 2-20 Instruction Set and Programming of 8085

After execution :
[A] = 45 H = 0 1 0 0 0 1 0 1
[E] = 45 H = 0 1 0 0 0 1 0 1
[A] = 45H
Q. 35 The accumulator contains 05H and register B contains 08H. What will be the effect of
'SUB B' instruction on flags ? Explain it with diagram. (March 2010)
Ans-: ACC = 05 H = 0000 0101
B = 08 H = 0000 1000
After execution of SUB B _
Accumulator contains 2's compliment of magnitude of result
i.e. ACC = 11111101 = FDH
Mentioning the status of carry flag
Q. 36 Differentiate DAD and ADD Instruction of 8085 Micro-Processor
lt•&►·Mill
Ans.:
DAD ADD
1. In this lll!3truction contents of register In this instruction register r or content of
pair rp are added to the contents of memory location whose address is stored in
HL pair & result is placed in register H-L pair is added with content of
Hand L. accumulator and result is placed in
accumulator.
2. Only carry flags in affected. All flags are affected.
3. Register pairs BC, DE are used. Only register A, B, C, D, H, E, Lare used.
4. Used for 16 bit addition Used for 8 bit addition
Q. 37
.
Differentiate between PUSH and POP. CllNP111 NI
Ans.:
PUSH . POP
1. The contents of the higher order register The contents of the memory location
of register pair rp are moved to memory whose address is specified by the stack
location whose address is one less than pointer are moved to low order register
the content of stack pointer. of register pair rp.
2. The contents of the low order register of The contents of the memory location,
register pair rp are moved to the whose address is one more than the
memory location whose address is two content of stack pointer are moved to
less than the content of stack pointer. high order register of register pair rp.
3. In this instruction, stack pointer is In this instruction, stack pointer is
decremented by two. incremented by two.
4. Let [SP] = D01 5, [BJ = 25 H and Let [SP] = 2001 H
(CJ= 55 H (2001] = 10 H, [2002] =20 H
After execution of PUSH B After execu tion of POP H
ID014J = 25 H [H] ;:: 20H, [L] = lOH
[D013] = SSH and [SP] = 0013 H [SPJ =2003 H

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 2-21
TPS Com pu ter Science - U
a-ftff ~ tin,:
dat a B7h . Wh at wil l be its con t.enh
Q . 38 The acc um ula tor of 8085 con tain s
nde ntly ?
of the fo1 Jow ing ins truc tion s ind epe
CM A (iii) AN I f3 H
S PC -
(i) OR I 58 H ( ii)

An_s. :
Acc umula tor = B7H
= 10 1 1 0 11 1

(i ) O RI 58 H
Log jcal ly OR ed 58H " i th [A)
0 11 l
Be fore Exe cuti on [A] = B7H =10 11
B7H = 1 0 1 1 0 1 1 l
OR SSH = 0 10 1 100 0
l l l l l l l l =FF H

After ext.,>eution fAl = FFH

um ula tor
(ii l CMA - Com plem ent the con ten ts of acc
1 10 11 1
Bef ore executJon fA J =87H = 10

inst ruct ion CM A

After executi on fA J =OI 001 (XX) =48
H

A!\.1 E3H ~ Logically Mr oed E.3H wit

h [AJ
(w )
0 111
Before ex{>('.U tion fA J = B7H =1 0 l 1
lnstl'UCWm - Az"-.1E3H
B7H = 1 0 1 1 01 11
OH f '.\H = 1 1 10 00 l I
1 0 1 0 0 0 l 1 = A3H

Aite-r exn "Utmn f A J = AJH --

- - -- . ·· -· -- -- -- -- - ----- - -- - - full o'4 .r:.
t-fftt'>t o n its con ten t if
h.at wil l bl" the
Q . )q Th. - .cc um \lla tor ron aus 3CH , w

m s.tn id ,on s ilN n tt1.tted ind ep~ nde

ntl) ?
@d
h iJ RR C (Hi ) MO V 8 , A
W Al\' l 05H
An s, . ,, - 1l H . • 'll l H \.l
1

H . i.A..~ lult i, ~w 1_,,; H htt h l'\\.-.' Ufll U.hl tll?

(l! " ' ' ' ()!i.
1
~'"' H tir11.u 1<'l

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 rP5 Computer Science - II 2-22 Instruction Set and Programming of 8085

(ii) RRC - Rotate Accumulator Right

A= 3C H = 00111100
After Execution of RRC A will contain 00011110 = lE H
(iii) MOV B, A - Move contents of A reg in B register
Accumulator contents remain unchanged i.e. B & A will be 3C H

Q. 40 The accumulator in 8085 Micro-processor contains th~ data 78H and register D
contains data 33H. What will be the content of accumulator after execution of each
of the following instructions independently. lt•HIDOd)
(i) SUB D · (ii) AND D (iii) CMA
Ans,:
Accumulator = A =78 H = 0111 1111
D = 33H = 0011 0011
(ii) SUB D (Subtract D from Accumulator)
is complement of D = 1100 1100
' + 1 + 1

2's Complement of D = 1100 1101

A =
= 0111 11 11
111 11 11

= (] 01001100

Complement carry @] 01001100

Result = A = 4 CH
(ii) AND D: Logically and with accumulator
A= 78 H = 0111 1111
AND = 0011 0011
0011 0011
A = 33H
(iii) CMA : Complement Accumulator
A = 78 H = 0111 1111
After CMA, A = 1000 0000
A ~ 80H

Q.41 The accumulator in 8085 microprocfssor contains data 71H register E contains data
39H. What will be the contents of accumulator in Hexadecimal after execution of the
( l\ t.1rd1 2tl I :"I
following instructions independently ?
(i) ADD E (ii) ORA E (iii) RRC
Ans.: (i) AAH, (ii) 79H, (iii) B8H

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TPS Computer Science - TI 2-23 Instructi' on Set an d p rogramming of 8085

the conten
Q. 42 Accumulator contai ns data A4H and Register E contains data 69H write
ing instructt ts
of Accum ulator in hex digits after execution of each of the follow
indep enden tly :
Ans.:
(i) ANA E = 20 H ·(ii) CMP E = A4H (iii) ORA = EDH

will be the
Q. 43 The· registers A and c of 8085 contains the cJata E2H and 47H. What
the following
conten ts of Accumulator in Hex digits after execution of each of
instru ctions indep enden tly?
IMfil@lfM!)
(i) SUB C (ii) XRA C (iii) ADD C

Ans.:
(i) SUB C = 9BH
(ii) XRA C = ASH
(iii) . ADD C = 29 H Cy = 1
will be the
Q. 44 Accumulator contain data 45H and register B contain data 82H. What
y.
result in Accumulator after execution of each instruction indepe ndentl
m XRA B <m ADI 54H (iii) NI sm aw"d
Ans.:
(i) XRA B Accumulator = 45H
regB = 82H
Ace = 45H = 0100 0101
B = 82H = 1000 001,0
1100 0111
B 7
XRAB = B7H
(ii) ADI 54H Ace= 45H = 0100 0101
54H = 54H = 0101 0100
-1001 1001
9 9
ADI54H = 99H
(iii) ANI 57H Ace = 45H = 0100 0101
57H = 57H = 0lDl 0111
0100 0101
4 5
ANI57H = 45H

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 2-24 Instruction Set and Program ming of BOBS
TFS Computer Science - II

Q. 45 Write the appropriate instructions for the followin g task:

(i) Load accumulator from B register.
(ii) Comple ment the accumulator
(iii) Add OlH with the accumulator
(iv) Store the content of accumulator at the memory location address ed by the BC
register pa1r.]
(v) Clear the accumulator.
Ans.:
(i) Loa~ accumulator from B register - LDAXB /MOVA , B
(ii) Complement the accumulator - CMA
(iii) Add OlH with the accumulator - ADI0lH
(iv) Store the content of accumulator at - STAXB
the memory location address ed by
the BC register pair.] .
(v) Clear the accumulator. .:.. XRA A I SUB A I MVI A, 00

(!\larch 2019)
Q. 46 Give any two instructions of followin g address ing modes :
(i) Immedi ate (ii) Register Indirect (iii) Registe r

Ans.:
(i) Immediate - ADI 05H I MVI B, 04H
(ii) Register Indirect - ADD M / MOV M, D
(iii) Register - MOV A, B / ADD C

Q. 47 The accumulator contains AA H and register C contains 55 H. What will be the .

contents of accumulator if following instructions are executed indepen dently ?
(i) CMP C (ii) ANA C
(iii) ORA C (iv) SUB C (March 2019)
Ans.:

(i) CMPC It's CMP means subtraction of A-C. But after subtrac tion Accumu lator content
remains unchang ed. Means after CMPC.
A= AAH
(ii) ANAC
A = AAH = 1010 1010
C = SSH = 0101 0101
logical AND operation = 0000 0000
.. ANAC = OOH Accumu lator Content

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 2-25 Instruction Set and Prog ramrn·
TPS Computer Science - II
- - - - - -- - - - - - -- -- - - - - - -- --- =- - · II1g of ~ .
- - ~
(iii) ORAC
A = AA H = 1010 1010
C = SSH = 0101 0101

logical OR ope rati on = 1111 1111

.. OR AC = FFH Accumulator Con tent
(iv) SUBC
A = AA H = 1010 1010
0101 0101
C = SSH =
1010 1010 l's com plem ent
l Add 1
+
1010 1011 2's com plem ent

1010 1010 l's no.

0101 :. SUB C = SSH

-- --
Substraction
-- -- -- -- -- -:
0 0101
-- -= -~ foll
--
owi
= -- -- -- -- -- -
ng.
and rew rite the
Q. 48 Select the correct alternative
gro up of inst ruct ion set of 8085.
1 ............ instruction belongs to data transfer
(ii) CMA (iii) JMP (iv) POP
(i) LHLD
Ans. : (i) LHLD
RRC of 8085.
2. .. .......... flag is affected by the instruction
(ii) parity (iii) carr y (iv) all
(i) zero
Ans .: (iii) carry
not affect any flag .... ....... .
3. Which of the following instruction does
(ii) RAR (iii) STC (iv) PCHL
(i) ADD
Ans .: (iv) PCHL
ress ing mod e.
4. Instruction STAX belongs to ............ add
(i) Direct (ii) Register (iii) Register indi rect · (iv) Imm edia te
Ans. : (iii) Register indirect
ster.
5. In 8085 ............ instruction affects flag regi
(iii) MVI A, data (iv) CPI data
(i) MO V B, A (ii) CMA
Ans . : (iv) CPI data
up
6. Ins truction PCHL belongs to· ....... ..... gro
(i) Arithmetic operation
(ii) Logical operation
(iii) Data tran sfer
(iv) Branching ope rati on
Aris. : (iv) Branching ope rati on
7. LXI H, add r is ........ .... byte instruction. Wfihid
(i) 1 (ii) 2 (iii) 3 (iv) 4
Ans . : (iii) 3

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