CD4085BMS

CMOS Dual 2 Wide 2 Input

December 1992
AND-OR-INVERT Gate

Features Pinout
• High Voltage Type (20V Rating) CD4085BMS
TOP VIEW
• Medium Speed Operation
- tPHL = 90ns
- tPLH = 125ns (Typ.) at 10V A1 1 14 VDD

• Individual Inhibit Controls B1 2 13 D1

• 5V, 10V and 15V Parametric Ratings E1 = INHI + A1B1 + C1D1 3 12 C1

• Standardized Symmetrical Output Characteristics E2 = INH2 + A2B2 + C2D2 4 11 INHIBIT 2

A2 5 10 INHIBIT 1
• 100% Tested for Quiescent Current at 20V
B2 6 9 D2
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC VSS 7 8 C2

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard Functional Diagram
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
10
INHIBIT 1
1
Description A1
2
B1 3
CD4085BMS contains a pair of AND-OR-INVERT gates, each E1
12
consisting of two 2 input AND gates driving a 3 input NOR gate. C1
13
D1
Individual inhibit controls are provided for both A-O-I gates..
11
The CD4085BMS is supplied in these 14 lead outline pack- INHIBIT 2
ages: 5
A2
6
B2 4
Braze Seal DIP H4H E2
8
Frit Seal DIP H1B C2
9
D2
Ceramic Flatpack H5W
E = INHIBIT + AB + CD
LOGIC 1 = HIGH
LOGIC 0 = LOW

VDD = 14
VSS = 7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3327
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1046
 Specifications CD4085BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125 C o

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25 oC - 2 µA
2 +125oC - 200 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25o C -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented. is 0.050V max.
2. Go/No Go test with limits applied to inputs.

7-1047
 Specifications CD4085BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 450 ns
Data
10, 11 +125oC, -55oC - 608 ns
Propagation Delay TPLH1 VDD = 5V, VIN = VDD or GND 9 +25oC - 620 ns
Data
10, 11 +125oC, -55oC - 837 ns
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns
Inhibit
10, 11 +125oC, -55oC - 405 ns
Propagation Delay TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 500 ns
Inhibit
10, 11 +125oC, -55oC - 675 ns
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH
10, 11 +125oC, -55oC - 270 ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 1 µA
+125oC - 30 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 2 µA
+125oC - 60 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 2 µA
+125oC - 120 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - 50 mV
-55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 4.95 - V
-55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 9.95 - V
-55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -2.6 mA

7-1048
 Specifications CD4085BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - 3 V
-55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, +7 - V
-55oC
Propagation Delay Data TPHL1 VDD = 10V 1, 2, 3 +25oC - 180 ns
o
VDD = 15V 1, 2, 3 +25 C - 130 ns
o
Propagation Delay Data TPLH1 VDD = 10V 1, 2, 3 +25 C - 250 ns
o
VDD = 15V 1, 2, 3 +25 C - 180 ns
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25oC - 120 ns
Inhibit o
VDD = 15V 1, 2, 3 +25 C - 80 ns
o
Propagation Delay TPLH2 VDD = 10V 1, 2, 3 +25 C - 200 ns
Inhibit
VDD = 15V 1, 2, 3 +25oC - 140 ns
Transition Time TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
TTLH
VDD = 15V 1, 2, 3 +25oC - 80 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-1 IDD ± 0.2µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading

7-1049
 Specifications CD4085BMS

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC

PARAMETER SYMBOL DELTA LIMIT

Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
Static Burn-In 1 3, 4 1, 2, 5-13 14
Note 1
Static Burn-In 2 3, 4 7 1, 2, 5, 6, 8-14
Note 1
Dynamic Burn- - 7 14 3, 4 1, 2, 5, 6, 8, 9, 10, 11
In Note 1 12, 13
Irradiation 3, 4 7 1, 2, 5, 6, 8-14
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

7-1050
 CD4085BMS

Schematic

INHIBIT 1 10 *
VDD

p p

VDD
n

A1 1 * p
p p
n

B1 2 * p
n
VSS p p
VDD

n n 3 E1
p p n
n n

n
VSS
C1 12 *

D1 13 *

VSS
VDD

p p

VDD
n

A2 5 * p
p p
n

B1 6 * p
n
VSS p p
VDD

n n 4 E2
p p n
n n

n
TERM. 14 = VDD VSS VDD
C2 8 * TERM. 7 = VSS

D2 9 *

VSS * ALL INPUTS PROTECTED BY

INHIBIT 2 11 * CMOS PROTECTION NETWORK VSS

FIGURE 1. CD408B SCHEMATIC DIAGRAM

7-1051
 CD4085BMS

Typical Performance Characteristics

17.5
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
15 SUPPLY VOLTAGE (VDD) = 15V 15 MAX
6
CURRENT MIN
VDD VDD

DRAINCURRENT (ID) - mA
PEAK
OUTPUT VOLTAGE (VO) - V

OUTPUT VOLTAGE (VO) - V

5 12.5
14
VDD VDD
10V
10 VO 4 10
VI 14
7 VSS
CURRENT 3 7.5 VI VO
PEAK ID
5V
5 2 5 7 VSS

1 2.5

0 0
0 5 10 15 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5
INPUT VOLTAGE (VI) - V INPUT VOLTAGE (VI) - V

FIGURE 2. TYPICAL VOLTAGE AND CURRENT TRANSFER FIGURE 3. MINIMUM AND MAXIMUM VOLTAGE TRANSFER
CHARACTERISTICS CHARACTERISTICS

300
105 AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC

HIGH-TO-LOW LEVEL PROPAGATION

POWER DISSIPATION (PD) (µW)

250
104

DELAY TIME (tPHL) (ns)

SUPPLY VOLTAGE (VDD) = 15V
200 SUPPLY VOLTAGE (VDD) = 5V
103
10V

10V 150
102
5V 10V
100
15V
101 CL = 50pF
CL = 15pF
50

100
10-1 100 101 102 103 104
0 20 40 60 80 100
FREQUENCY (f) (kHz) LOAD CAPACITANCE (CL) (pF)

FIGURE 4. TYPICAL POWER DISSIPATION vs FREQUENCY FIGURE 5. TYPICAL DATA HIGH-TO-LOW LEVEL PROPAGA-
TION DELAY TIME vs LOAD CAPACITANCE

AMBIENT TEMPERATURE (TA) = +25oC

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

AMBIENT TEMPERATURE (TA) = +25oC

LOW-TO-HIGH LEVEL PROPAGATION

LOAD CAPACITANCE (CL) = 50pF

DELAY TIME (tPLH) (ns)

1250
400
SUPPLY VOLTAGE (VDD) = 5V
350 1000
300
750
250
200 tPLH
500
150 10V
100 15V 250

50 tPHL

0 2.5 5 7.5 10 12.5 15 17.5 20

0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) SUPPLY VOLTAGE (VDD) (V)

FIGURE 6. TYPICAL DATA LOW-TO-HIGH PROPAGATION FIGURE 7. TYPICAL DATA PROPAGATION DELAY TIME vs
DELAY TIME vs LOAD CAPACITANCE SUPPLY VOLTAGE

7-1052
 CD4085BMS

Typical Performance Characteristics (Continued)

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 8. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 9. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

AMBIENT TEMPERATURE (TA) = +25oC -15 -10 -5 0
0
AMBIENT TEMPERATURE (TA) = +25oC
TRANSITION TIME (tTHL, tTLH) (ns)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
200
-10

SUPPLY VOLTAGE (VDD) = 5V

150 -15

-10V
-20
100
10V -25
15V
50 -15V
-30

0
0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF)

FIGURE 10. TYPICAL TRANSITION TIME vs LOAD FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CAPACITANCE CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-5

-10V
-10

-15V
-15

FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

7-1053
 CD4085BMS

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are derived from

the basic inch dimensions as indicated. Grid graduations are in
mils (10-3 inch).

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA EUROPE ASIA
Intersil Corporation Intersil SA Intersil (Taiwan) Ltd.
P. O. Box 883, Mail Stop 53-204 Mercure Center Taiwan Limited
Melbourne, FL 32902 100, Rue de la Fusee 7F-6, No. 101 Fu Hsing North Road
TEL: (321) 724-7000 1130 Brussels, Belgium Taipei, Taiwan
FAX: (321) 724-7240 TEL: (32) 2.724.2111 Republic of China
FAX: (32) 2.724.22.05 TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

1054