Set 2

1. The Internal Architecture of the 8088

Microprocessor (Programming Model)
2. Memory Address Generation
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 Normal Operation of 8088p

1. p fetches instruction from memory

2. Decoding

3. p executes it

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Normal Operation of 8088p
The internal structure of the 8088 consists of:
1. Bus Interface Unit BIU
2. Execution Unit EU

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Micro-Architecture: Hardware Circuit

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BIU Contains:

Pre-fetch queue
Bus controller
Segment registers
Instruction pointer IP
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 BIU: Pre-fetch queue (pipelining)
Internal queue with a byte-wide and 4 bytes deep
FIFO memory
Shift left register
It allows EU to obtain the next instruction directly
from BIU instead of the memory
Executes instruction much faster

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 BIU Functions
 Keep the pre-fetch queue filled with instructions
 Generate and accept the system control signals
 Provide the system with memory address or IO port
number
 Act as a window between EU and memory for data
Performs all external bus operation such as instruction
fetching, reading, writing of data operands for memory
and inputting/outputting data for IO Operation
Responsible for instruction queuing and address
generation
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 EU contains:
◦Arithmetic logic unit ALU
◦Instruction register IR
◦Register array
Instruction Pointer(IP):
 it identifies the location of the next word of
instruction to be fetched from memory
 Register Array are scratchpad memory hold
information temporarily

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 EU: Functions
Decoding and executing instructions

Consists of ALU, flags (status & Control), General Purpose

registers

Read Byte by byte from queue and decode it

ALU permits arithmetic, logic and shift operations on

memory/register data
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 How do BIU & EU Work?
 Fetch and execute cycles overlap:
 BIU outputs the contents of the IP onto address bus
 IP is incremented by one or more for the next
instruction fetch
 Once inside BIU, the instruction is passed to the
queue (FIFO)
 EU immediately takes instruction from queue and
begins executing
 While executing this instruction, BIU proceeds to
fetch a new instruction
 Cycle continues
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 8085
Fetch Decode Execute Fetch Decode Execute Microprocessor
…...
1 1 1 2 2 2

Busy Idle Busy Busy Idle Busy …... Bus

8088

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 What is a register?
A storage element inside the microprocessor
Almost all the operations would involve using registers
The 8086 has 14 16 bit registers
◦ 4 general purpose registers AX, BX, CX, and DX
◦ 4 addressing registers SI, DI, SP, and BP
◦ 4 segmentation registers CS, DS, SS and ES
◦ Instruction pointer IP
◦ Flags register

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Register Array

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1. General Purpose Registers

Accumulator

Base

Counter

Data
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 Each of the registers is 16 bits wide (AX, BX, CX, DX)
 Also, they can be accessed as 8 bits registers AL, AH, BL, BH, CL, CH, DL, DH
 AX (accumulator) often holds the temporary result after an arithmetic and
logic operation
 BX (base) often holds the base (offset) address of data located in the memory

Register operations
AX Word multiply, word divide, word IO
AL Byte multiply, Byte divide, Byte IO, translate
AH Byte multiply, Byte divide
BX translate
CX String operations, loops
CL Shift and rotate
DX Word multiply, word divide, Indirect IO

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2. Pointers & Index Registers
IP
Instruction Pointer

Source Index

Destination Index

Base pointer

Stack Pointer
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 Each of them is 16 bits wide, L/H bytes are not accessible
 They are used as memory pointers (Offsets)
 Example: MOV AH, [SI]Move the byte stored in memory location
whose address is contained in the register SI to register AH
 IP is not under direct control of the programmer
 SP (stack pointer) used to address data in a LIFO (last-in, first-out)
stack memory
 BP (base pointer) often used to address an array of data in the
stack memory

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3. Flag Register

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 3a. Status Flags
Six flags (CF, AF, ZF, SF, OF, & PF) are used as indicators
reflecting properties of the last arithmetic or logical
instruction.
 C(carry) indicates carry after addition or a borrow
after subtraction
 O(overflow) is a condition that can occur when
signed numbers are added or subtracted
 Z(zero) indicates that the result of an arithmetic or
logic operation is zero
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Example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then:
1. AL = 80h & CF = 0; there is no carry out of bit 7
2. PF = 0; 80h has an odd number of ones
3. AF = 1; there is a carry out of bit 3 into bit 4
4. ZF = 0; the result is not zero
5. SF = 1; bit seven is one
6. OF = 1; the sign bit has changed
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 Example
Which flag(s) is affected by those instructions?

 MOV AL, 3H

 MOV BL, 2H

 INC BL

 SUB AL,BL

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 3b. Control Flags
1. Three flags (DF, IF, & TF)
2. DF is used with string commands. If DF = 0; the
memory address is increased; otherwise it is
decreased.
3. IF: if IF = 1; then p accepts request from
peripherals; otherwise not.
4. TF: if TF = 1; p executes one instruction at a
time.
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 Example
0010 0011 0100 0101
+ 0011 0010 0001 1001 S 0
= 0101 0101 0101 0001 Z 0
P 0
C 0
A 0
O 0
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 Example
0101 0100 0011 1001
+ 0100 0101 0110 1010 S 1
= 1001 1001 1010 0011 Z 0
P 1
C 0
A 1
O 1
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4. Segment Registers
DS
Data Segment Register

ES
Extra Segment Register

CS
Code Segment Register

SS
Stack Segment Register

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 Real Mode Memory Addressing
All 80x86 processors operates in the real mode by
default
All real mode memory addresses consist of a
segment address plus an offset address
◦the segment address (in one of the segment
registers) defines the beginning address of any
64K byte memory segment
◦the offset address selects a location within the
64K byte memory segment
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 Segmented Memory
A mechanism that allows the extend the addressability of a Processor
In case of 8088, it allowed the processor to extend the maximal addressable
memory from 64K to 1megabyte!!
It uses 2 components to specify memory locations: a segment value and an offset
value within that segment.
In the 8086 processor each 20bit address is expressed as:
◦ 16 bit segment
◦ 16 bit offset
◦ Example: 2000H:0BAFH
Converting a segmented address to the actual address:
◦ Add a 0 to the right hand side of the segment
◦ Add to this the offset
◦ Example: 020A:1BCD =>> 020A0H +1BCDH = 036DH
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 The programmer at any time can access four memory segments.
 Code segment to write the code.
 Data segment to store data
 Extra data segment
 Stack segment to be used with subroutines
 Each segment is 64Kbytes  216Bytes
 The segments maybe contiguous, adjacent, disjointed, and overlapped.
 Segment registers generate memory addresses along with other registers in the
microprocessor

 CS(code) defines the starting address of the section of memory-holding

code(programs and procedures used by programs) and son on.

 Boundary addresses means the starting (least/min) address and the ending
(highest/max) address of the corresponding memory segment.

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 Examples
(1) Linear address for Segment:Offset = 2222:3333 = 25553
Segment:offset address for Linear address=25553:
Many Answers - One possibility: 2222:3333
Many Answers - One possibility: 2000:5553

 (2) Linear address for Segment:Offset = 1200:F445 = 21445

Segment:offset address for Linear address=21445:
 Many Answers - One possibility: 1200:F445
 Many Answers - One possibility 2000:1445

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Software Model

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Hardware Organization of the Memory Address Space

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31
 Memory Address Generation
 20 bit address bus are required to address the (1 MB) memory,
 But 88p has only 16 bit registers
 So, 20-bit addresses are obtained by combining a segment number (in a
segment register) and an offset address (in another processor register)

 The segment register address (16-bits) is appended with a 0H or 00002 (or

multiplied by 10H or 16d) to form a 20-bit start of segment address

 Then the effective memory address (EA) = this 20-bit segment start address +
the 16-bit offset address in another processor register

 Addresses within a segment can range from address 0 to address FFFFh. This
corresponds to the 64Kbyte length of the segment.
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DR. NEMA SALEM SPRING 2020 33
Example: DS = 7FA2h & Offset = 438Eh

a. Physical address = 7FA20 + 438E =

83DAEh
b. Lower range = 7FA20 + 0000 = 7FA20h
c. Upper range of data segment = 7FA20 +
FFFF = 8FA1Fh
d. Logical address = 7FA2:438E

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 Input/output Addressing

The input/output address space is 64k byte  216

bytes
There is a need to only 16 bits for addressing (A0
to A15)
Remember: To address the memory; 20 address
bits are required from A0 to A19.

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