Pe aS eee ae 8086 Architecture: Features of 8086 . an « Itis a 16-bit Microprocessor (up).lt’s ALU, intemal rogisters works with 16bit binary word. 2 Se + 8086 has a 20 bit address bus can access up to 2°=1 MB memory locations. ‘ + 8086 has a [Obit data bus. It can read or write data to a memory/port either 16bits or 8 bit ata time. Itcan support up to 64K I/O ports. : Itprovides 14, 16 -bit registers. = ; Frequency range of $086 is 6-10. MHz Tthas multiplexed address and data bus ADO- ADIS and A16— A19. It requires single phase clock with 33% duty cycle to provide internal timing. Itcan prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. Itrequires +5V power supply. ‘A 40 pin dual in line package. 8086 is designed to operate in two modes, Minimum mode and Maximum mode. © The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. ~-— The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration. Register Organization of 8086 General purpose registers The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer. It is divided into four groups. They are: + Four General purpose registers + Four Index/Pointer registers + Four Segment registers + Two Other registers” aby General purpose registers: General Purpose Registers 6 Accmnolator aX ‘Multiply Base Bx Pointer to base addresss (data) Count for oops, shitts Count x Data Dx Multiply, divide, 10 Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low order byte of the word, and AH contains the high-order byte. Accumulator can be used for /O. operations andstring manipulation. Base register consists of two 8-bit registers BL and BH, which combined, and used as a 16-bit register BX, BL in this case contains the low-or¢ or oer word, contains the high-order byte. BX register usually contains a data pointer used for based, indexed or register indirect addressing. ee es Count register consists of two 8-bit registers CL and CH, which can be combined and used as a 16-bit register CX. When combined, CL register contains the low order byte the word, and CH contains the high-order byte, Count register can be used in Loop, shifVrotate instructions and as a counter in string manipulation —_— Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in VO operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. Index or Pointer Registers These registers can also be called as Special Purpose registers. Pointer and Index Registers 5 0 C Stack Pointer SP Pointer to top of stack {Base Pointer BP Pointer to hase address stack) ‘Source Index sI Source string/index pointer Destination Index DI Destination string/index pointer 8 0 Stack Pointer (SP) is a 16-bit register pointing to program stack, i.e. it is used to hold the address of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack segment (specified by the SS segment register).Unlike the SP register, the BP can be used to specify the offset of other program segments, Base Pointer (BP) is a 16-bit register pointing to data'in stack segment. It is usually used by subroutines to locate variables that were passed on the stack by a calling program. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Used in conjunction with the DS register to point to data locations in the data segment, Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in, string operations. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. In short, Destination Index and SI Source Index registers are used to hold address. t Registers “ies een on of the registers contain data/instruction offfets within 64 KB memory segment, There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses f nie(CS) is a 16-bit register containing address of 64 KI the processor uses CS segment for all accesses to in instruction pointer (IP) register. CS register cannot be changed directly. The automatically updated Turing far jump, far call and far return instructions. Bis rr Stack segment (SS) is a 16-bit register containing address of 64KB By default, the processor assumes that all data referenced by tl ee ase pointer (BP) registers is located in the stack segment. SS register can directly using POP instruction. — ae Data segment (DS) is a 16-bit register containing address of 64KB segment with program — data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment (ES) used to hold the starting address of Extra segment. Extra segment is provided for programs that need to access a second data segment. Segment registers cannot be used in arithmetic operations. Other registers of 8086 Instruction Pointer (IP) is a 16-bit register, This is a crucially important register which is used to contro! which instruction the CPU executes. The IP, or-program counter, is used to store the memory location of the next instruction to be executed, The CPU checks the program counter 10 ascertain which instruction to carry out next. It then updates the program counter to point to the” next instruction. Thus the program counter. will always point to_ the_next instruction to executed, i — Flag Register contains a group of status bits called flags that indicate the status of the CI the result of arithmetic operations. There are two types of flags:these bits to control the CPU's operation. ‘Nine individual bits of the status register are used as control flags (3 of them) and flags (6 of them).The remaining 7 are not used. ‘A flag can only take on the values 0 and 1. We say a flag is set if it has the value LeThe status flags are used to record specific characteristics of arithmetic and of logical ~ instructions. 7) % O-Flag TFhg Sty ~The Flags Regt perky | Tr | ZFleg AFlag P-Fleg NSS SN Interrupt Control Flags: There are three control flags 1. The Direction Flag (D): Affects the direction of moving data blocks by_such instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and | = down and can be set/reset by the STD (set D) and CLD (clear D) instructions. a 2, The Interrupt Flag (1): Dictates whether or not system interrupts can occur. Interrupts are actions initiated by hardware block such as input devices that will interrupt the normal execution of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated by the CLI (clear 1) and STI (set D inséructions. 3 3, The Trap Flag (11): Determines whether or not the CPU is halted after the execution of each instruction. When this flag is set (ie. = 1), the programmer can single step through Ris program to debug any errors, When this flag ~ 0 this feature is off. This flag can be set by the INT 3 instruction. : Status Flags: There are six status flags et. when the result of an unsigned arithmetic operation is 1. The Carry Flag (C): This flag is s This happens when there is an end catry in an addition too large to fit in the destination register. in a subtraction operation. A value of 1 = carry and 0 = no operation or there an end borrows ii carry. when the result of a signed arithmetic operation is too 2, The Overflow Flag (O): This flag is set large fo fit in the destination register (i.c. when an ov rflow occurs). Overflow can occur when adding two jjumbers with the same sign (i.c. both positive or both negative). A value of 1 =, Ori dans ion ae eh of L Pevensie value el ei ifthe nimber of lps oda eee ts ecture of 8086 or Functional Block dingram of 8086 ‘8086 has two blocks Bus Interface Unit (BIU) and Execution Unit (BU). The BIU performs all bus operations such as instruction fet EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and Sfficient use of the — execution mechanism which is called as Pipelining. This results in system bus and system performance. + BlU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.g 3 3 = & = < Fig. 6.2 8086 Internal block. diagram DySus << eSExplanation of Architecture of 8086 ~ Bus Interface Unit: Sus Interface Unit: . It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: Instruction fetch Instruction queuing, Operand fetch and Storage, Address relocation and Bus control.1g : sequential instruc ng instructions are held in its FIFO queue. instruction bytes in a single memory cycle. . After a byte is loaded at the input end of the queue, it automatically FIFO to the empty location nearest the output, The EU accesses the queue from the output end. It reads one instruc other from the output of the queue. If the queue is full and the EU is not ‘operand in memory. ee intervals of no bus activity, which may occur between bus cycles are known + Ifthe BIU is already in the process of fetching an instruction when the BU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. = The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. truction to be fetched is formed by = For example: The physical address of the next ins current contents of the combining the current contents of the code segment CS register and the instruction pointer IP register. «The BIU is also responsible for generating bus control signals such as those for memory read” or write and /O read or write. Execution Unit «The Execution unit is responsible for decoding and executing all instructions. «The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or twrite bus eyeles to memory ot /O and perform the operation specified by the instruction on the operands. . During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. = If the queue is empty, the EU waits for the next instruction byte to be fetched and s to top of the queue. ° When the EU executes a branch or jump instruction, it transfers control to a loc: ‘corresponding to another set ‘of sequential instructions. i Whenever this happens, the BIU automatically resets the queue iction from this new location to refill the queue. i andSESE stracbiag is MNIMOC pin aie Se In this mode, Gare : — ‘+ There isa single microprocessor in the minimum mode system. Pin Diagram of 8086 and Pin description of 8086 Figure shows the Pin diagram of 8086. The description follows it. Pin Diagram of 8086 ms 2 4 [Vor oe 5 39 | ape aD, 3 38 [Ate S a. <4 carte ee 3s an «fe Ve Fo ase ce |, a ses, owen aD +18 8086 33 [i ap <—l5 2 |p AD. +—19 CPU eee —» RQ) GT, (HOLD) ees so > BOER pay : es 29 [> Dock Wa) aa aD +8 3 H———> &_ mie) yen a «ia af OTR aber Wynsaete| Rest iy Se a} & Gh pard Enable i ae 23 |} & al) a) x ay a [> os OTA) gosh ve(wan) INTR +—| 15 alte Tesh-l> wenn) ax +79 2 pany haat GND il eee ee 2 eT * The Microprocessor 8086 is a 16-bit CPU available in different clock rates: and packs in a 40 pin CERDIP or plastic package. _« The 8086 operates in single processor or multiprocessor configuration performance. The pins serve a particular function in minimum m© Address remains on the lines during TI state, while the data is available on bus during T2, T3, Tw and T4. These lines are active high and float to a during interrupt acknowledge and local bus hold acknowledge cycles. - + A19/S6, A18/S5, A17/S4, and A16/S3: These are the time multiplexed address and status lines. © During T! these are the most significant address lines for memory operations. © During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for 2, T3, Tw and T4. The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. The $4 and S3 combine indicate which segment registers is presently being used for memory accesses as in below fig These lines float to tri-state off during the local bus hold acknowledge. ‘The status line _ S6 is always low. The address bit is separated from the status bit using latches controlled by the ALE signal. —Data ‘Whole word Upper byte from or to even address Lower byte from ar toeven address. + BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order (P15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during. TI for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during Ti for the first pulse of the interrupt acknowledge cycle. + RD — Read: This signal on low indicates the peripheral that the processor is performing memory or V/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. : «READY: This is the acknowledgement from the slow ‘device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high. « INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle, This can be intemally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized intemally during each clock oycle on leading edge of clock. * CLK- Clock Input: The clock input provides the basi g bus control activity. It’s an asymmetric square wave with 33% duty cycle. ei aaatd Figure shows the Pin functions of 8086.T The following pin functions are for the minimum mode operation of 8086, + M/O — Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an /O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge “. + INTA — Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. ie. when it goes low, the processor has accepted the interrupt. ALE — Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated. DT/R — Data Transmit/Receive: This output is used to decide the direction of data flow through the transceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. DEN — Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during ‘hold acknowledge’ cycle. HOLD, HLDA- Acknowledge: When the HOLD line goes high; it indicates to the Processor that another master is requesting the bus access, The processor, after receiving 1 HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the: clock cycle after completing the current bus cycle. * At the same time, the processor floats the local bus and control lines. When of« The first byte is a complete opcode in case of some instruction (one by = 1. The request occurs on or before 12 state of the cunient eyele, 2. The current cycle is not operating over the lower byte ofa word, __ 2: The current eyele is not the frst acknowledge of an interrupt acknowledge s 4. A Lock instruction is not being executed, The following pin functions are applicable for maximum mode operation of $086. * 82, Sl, and SO — Status Lines: These are the status lines which reflect the type: operation, being carried out by the processor. These become activity during TA of previous cycle and active during T1 and T2 of the current bus cycles. + LOCK: This output pin indicates that other system bus master will be prevented fom gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK” prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK Prefix instruction ensures that other processors connected in the system will not gain the control of the bus. The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an extemal bus controller. By prefetching the instruction, there is considerable speeding up in instruction execution in 8086. This is known as instruction pipelining. : Indication mnterrupt Acknowledge Read 1/0 port write 1/0 port wralt ‘Code Access Read Memory Write memory Passive « Atthe starting the CS: IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty and the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS: IP address is 0 or two bytes at a time, if the CS: IP address is even, za part of opcode, in case of som: g part of code lie in second byte. ‘The second byte is then decoded in continuation wi 0 continuatic ith Tength and the number of subsequent bytes eb be ra ee d ae after every byte is read from the queue but the fetch cycle is ly if at least two bytes of the queue ate empty and the EU mai executing the fetched instructions, + The next byte after the instruction is completed is again the first opcode byte instruction, A similar procedure is repeated till the complete execution of the fetch operation of the next instruction is overlapped with the execution of th instruction. As in the architecture, there are two separate ‘units, namely Execution | Bus interface unit. + While the execution unit is busy in exeeuting an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status. Qs: [aso Indication s}e | No Operation © | + | First Byte ofthe opcode from the queue yz] Empty Queue 2 Subsequent Byte from the Queue * RQ/GTO, RQ/GTI — Request/Grant: These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle. « Each of the pin is bidirectional with RQ/GTO having higher priority than RQ/GTI. ROJGT pins have internal pull-up resistors and may be left unconnected, Request/Grant sequence is as follows: 1. A pulse of one clock wide from another bus master requests the bus access to 8086. Tl(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the ‘hold acknowledge’ state at next cycle. The CPU bus | interface unit is likely to be disconnected from the local bus of the system. v During T4(current) or 3, A one clock wide pulse from ‘another master indicates to the 8086 that the h request is about to end and the 8086 may regain control of the local bu next clock cycle. Thus each master to master exchange of the loca 7 sequence of 3 pulses. There must be at least one dead clock cycle