OPERATING SYSTEM

BY
SWAPNA.C
ASST.PROF
IT DEPARTMENT
CHAPTER 1: INTRODUCTION

What is an Operating System?

Computer-System Organization
Operating-System Structure
Operating-System Operations
Process Management
Memory Management
Storage Management
Protection and Security
Kernel Data Structures
Computing Environments
Open-Source Operating Systems
Computer-System Architecture
OBJECTIVES

To describe the basic organization of computer systems

To provide a grand tour of the major components of operating systems
To give an overview of the many types of computing environments
To explore several open-source operating systems
 WHAT IS AN OPERATING SYSTEM?

A program that acts as an intermediary between a user of a computer and the

computer hardware
Operating system goals:
 Execute user programs and make solving user problems easier
 Make the computer system convenient to use
 Use the computer hardware in an efficient manner
 COMPUTER SYSTEM STRUCTURE

Computer system can be divided into four components:

 Hardware – provides basic computing resources
 CPU, memory, I/O devices
 Operating system
 Controls and coordinates use of hardware among various applications and
users
 Application programs – define the ways in which the system resources are used
to solve the computing problems of the users
 Word processors, compilers, web browsers, database systems, video games
 Users
 People, machines, other computers
FOUR COMPONENTS OF A COMPUTER SYSTEM
WHAT OPERATING SYSTEMS DO

The operating system controls the hardware and coordinates its use among the
various application programs for the various users.
We can also view a computer system as consisting of hardware, software, and
data.
The operating system provides the means for proper use of these resources in the
operation of the computer system.
An operating system is similar to a government. Like a government, it performs no
useful function by itself. It simply provides an environment within which other
programs can do useful work.
To understand more fully the operating system's role, we explore operating
systems from two viewpoints:
 The user
 The system.
USER VIEW

The user's view of the computer varies according to the

interface being used
Single user computers (e.g., PC, workstations). Such systems are designed
for one user to monopolize its resources. The goal is to maximize the
work (or play) that the user is performing. the operating system is
designed mostly for ease of use and good performance.
Multi user computers (e.g., mainframes, computing servers). These users
share resources and may exchange information. The operating system
in such cases is designed to maximize resource utilization -- to assure
that all available CPU time, memory, and I/O are used efficiently and
that no individual users takes more than their air share.
 SYSTEM VIEW

From the computer's point of view, the operating system is

the program most intimately involved with the hardware.
There are two different views:
The operating system is a resource allocator
 Manages all resources
 Decides between conflicting requests for efficient and fair resource use
The operating systems is a control program
 Controls execution of programs to prevent errors and improper use of the
computer
 DEFINING OPERATING SYSTEM

No universally accepted definition of what an OS:

Operating systems exist to offer a reasonable way to solve the problem of

creating a usable computing system.
The fundamental goal of computer systems is to execute user programs
and to make solving user problems easier.
Since bare hardware alone is not particularly easy to use, application
programs are developed.
 These programs require certain common operations, such as those
controlling the I/O devices.
 The common functions of controlling and allocating resources are
brought together into one piece of software: the operating system.
DEFINING OPERATING SYSTEM (CONT.)
No universally accepted definition of what is part of the OS:

A simple viewpoint is that it includes everything a vendor

ships when you order the operating system. The
features that are included vary greatly across
systems:
 Some systems take up less than a megabyte of space and lack
even a full-screen editor,
 Some systems require gigabytes of space and are based
entirely on graphical windowing systems.
DEFINING OPERATING SYSTEM (CONT.)
No universally accepted definition of what is part of the OS:

A more common definition, and the one that we usually

follow, is that the operating system is the one
program running at all times on the computer --
usually called the kernel.
Along with the kernel, there are two other types of
programs:
 System programs, which are associated with the operating
system but are not necessarily part of the kernel.
 Application programs, which include all programs not
associated with the operation of the system.
 DEFINING OPERATING SYSTEM (CONT.)

The emergence of mobile devices, have resulted in an increase in the

number of features that constituting the operating system.
Mobile operating systems often include not only a core kernel but also
middleware -- a set of software frameworks that provide additional
services to application developers.
For example, each of the two most prominent mobile operating systems --
Apple's iOS and Google's Android -- feature a core kernel along with
middleware that supports databases, multimedia, and graphics (to
name only a few).
EVOLUTION OF COMPUTER SYSTEMS

Users

Applications

Database System
Operating System
Hardware
COMPUTER-SYSTEM ORGANIZATION

A modern general-purpose computer system consists of one or more CPUs

and a number of device controllers connected through a common bus
that provides access to shared memory.
Each device controller is in charge of a specific type of device (for example,
disk drives, audio devices, or video displays). Each device controller has
a local buffer.
CPU moves data from/to main memory to/from local buffers.
The CPU and the device controllers can execute in parallel, competing for
memory cycles. To ensure orderly access to the shared memory, a
memory controller synchronizes access to the memory.
MODERN COMPUTER SYSTEM
COMPUTER STARTUP

Bootstrap program is loaded at power-up or reboot

 Typically stored in ROM or EPROM, generally known as firmware
 Initializes all aspects of system
 Loads operating system kernel and starts execution
COMPUTER-SYSTEM OPERATION

Once the kernel is loaded and executing, it can start providing services to the
system and its users.
Some services are provided outside of the kernel, by system programs that are
loaded into memory at boot time to become system processes, or system
daemons that run the entire time the kernel is running.
On UNIX, the first system process is init and it starts many other daemons.
Once this phase is complete, the system is fully booted, and the system
waits for some event to occur.
The occurrence of an event is usually signaled by an interrupt.
INTERRUPTS

There are two types of interrupts:

 Hardware -- a device may trigger an interrupt by sending a signal to
the CPU, usually by way of the system bus.
 Software -- a program may trigger an interrupt by executing a
special operation called a system call.
A software-generated interrupt (sometimes called trap or exception)
is caused either by an error (e.g., divide by zero) or a user request
(e.g., an I/O request).
An operating system is interrupt driven.
 COMMON FUNCTIONS OF INTERRUPTS

When an interrupt occurs, the operating system preserves the state of the
CPU by storing the registers and the program counter
Determines which type of interrupt has occurred and transfers control to
the interrupt-service routine.
An interrupt-service routine is a collection of routines (modules), each of
which is responsible for handling one particular interrupt (e.g., from a
printer, from a disk)
The transfer is generally through the interrupt vector, which contains the
addresses of all the service routines
Interrupt architecture must save the address of the interrupted instruction.
INTERRUPT TIMELINE
Interrupt-driven I/O cycle.
Intel Pentium processor event-vector table
STORAGE STRUCTURE

Main memory – the only large storage media that the CPU can access directly
 Random access
 Typically volatile
Secondary storage – extension of main memory that provides large nonvolatile
storage capacity
 Hard disks – rigid metal or glass platters covered with magnetic recording
material
 Disk surface is logically divided into tracks, which are subdivided into sectors
 The disk controller determines the logical interaction between the device and
the computer
 Solid-state disks – faster than hard disks, nonvolatile
 Various technologies
 Becoming more popular
Tertiary storage
 STORAGE DEFINITION

The basic unit of computer storage is the bit. A bit can contain one of two
values, 0 and 1. All other storage in a computer is based on
collections of bits.
A byte is 8 bits, and on most computers it is the smallest convenient chunk
of storage.
A less common term is word, which is a given computer architecture’s
native unit of data. A word is made up of one or more bytes.
 STORAGE DEFINITION (CONT.)

Computer storage, along with most computer throughput, is generally

measured and manipulated in bytes and collections of bytes.
 A kilobyte, or KB, is 1,024 bytes
 a megabyte, or MB, is 1,0242 bytes
 a gigabyte, or GB, is 1,0243 bytes
 a terabyte, or TB, is 1,0244 bytes
 a petabyte, or PB, is 1,0245 bytes
 exabyte, zettabyte, yottabyte
Computer manufacturers often round off these numbers and say that a
megabyte is 1 million bytes and a gigabyte is 1 billion bytes. Networking
measurements are an exception to this general rule; they are given in
bits (because networks move data a bit at a time).
 STORAGE HIERARCHY

Storage systems organized in hierarchy

 Speed
 Cost
 Volatility
Caching – copying information from “slow” storage into faster storage
system;
 Main memory can be viewed as a cache for secondary storage
Device Driver for each device controller to manage I/O
 Provides uniform interface between controller and kernel
Storage-device hierarchy
I/O STRUCTURE
A general-purpose computer system consists of CPUs and multiple device
controllers that are connected through a common bus.
Each device controller is in charge of a specific type of device. More than one
device may be attached. For instance, seven or more devices can be
attached to the small computer-systems interface (SCSI) controller.
A device controller maintains some local buffer storage and a set of special-
purpose registers.
The device controller is responsible for moving the data between the
peripheral devices that it controls and its local buffer storage.
Typically, operating systems have a device driver for each device controller.
This device driver understands the device controller and provides the rest
of the operating system with a uniform interface to the device.
I/O STRUCTURE (CONT.)

To start an I/O operation, the device driver loads the appropriate registers
within the device controller.
The device controller, in turn, examines the contents of these registers to
determine what action to take (such as “read” a character from the
keyboard).
The controller starts the transfer of data from the device to its local buffer.
Once the transfer of data is complete, the device controller informs the
device driver via an interrupt that it has finished its operation.
The device driver then returns control to the operating system, possibly
returning the data or a pointer to the data if the operation was a read.
For other operations, the device driver returns status information.
DIRECT MEMORY ACCESS STRUCTURE

Interrupt-driven I/O is fine for moving small amounts of data but can produce
high overhead when used for bulk data movement such as disk I/O.
To solve this problem, direct memory access (DMA) is used.
 After setting up buffers, pointers, and counters for the I/O device, the device
controller transfers an entire block of data directly to or from its own buffer
storage to memory, with no intervention by the CPU.
 Only one interrupt is generated per block, to tell the device driver that the
operation has completed. While the device controller s performing these
operations, the CPU is available to accomplish other work.
Some high-end systems use switch rather than bus architecture. On these
systems, multiple components can talk to other components concurrently,
rather than competing for cycles on a shared bus. In this case, DMA is even
more effective. The figure in next slide shows the interplay of all
components of a computer system.
HOW A MODERN COMPUTER WORKS

A von Neumann architecture and a depiction of the interplay of

all components of a computer system.
 COMPUTER-SYSTEM ARCHITECTURE

Single general-purpose processor

 Most systems have special-purpose processors as well
Multiprocessors systems growing in use and importance
 Also known as parallel systems, tightly-coupled systems
 Advantages include:
 Increased throughput
 Economy of scale
 Increased reliability – graceful-degradation/fault-tolerance
 Two types:
 Symmetric Multiprocessing – each processor performs all tasks
 Asymmetric Multiprocessing – each processor is assigned a specific
task.
SYMMETRIC MULTIPROCESSING ARCHITECTURE
 MULTICORE SYSTEMS

Most CPU design now includes multiple computing cores on a single

chip. Such multiprocessor systems are termed multicore.
Multicore systems can be more efficient than multiple chips with single
cores because:
 On-chip communication is faster than between-chip communication.
 One chip with multiple cores uses significantly less power than multiple
single-core chips, an important issue for laptops as well as mobile
devices.
Note -- while multicore systems are multiprocessor systems, not all
multiprocessor systems are multicore.
A dual-core with two cores placed on the same chip
CLUSTERED SYSTEMS

Like multiprocessor systems, but multiple systems working

together
Usually sharing storage via a storage-area network (SAN)
Provides a high-availability service which survives failures
 Asymmetric clustering has one machine in hot-standby mode
 Symmetric clustering has multiple nodes running applications, monitoring
each other
Some clusters are for high-performance computing (HPC)
 Applications must be written to use parallelization
Some have distributed lock manager (DLM) to avoid conflicting operations
CLUSTERED SYSTEMS
MULTIPROGRAMMED SYSTEM

Single user cannot keep CPU and I/O devices busy at all times
Multiprogramming organizes jobs (code and data) so CPU always has one
to execute
A subset of total jobs in system is kept in memory
Batch systems:
 One job selected and run via job scheduling
 When it has to wait (for I/O for example), OS switches to another job
Timesharing systems:
 Logical extension of batch systems -- CPU switches jobs so frequently
that users can interact with each job while it is running, creating
interactive computing
 TIMESHARING SYSTEMS

Timesharing is also referred to as multitasking.

Response time should be < 1 second
Each user has at least one program executing in memory. Such a program is
referred to as a process
If several processes are ready to run at the same time, we need to have CPU
scheduling.
If processes do not fit in memory, swapping moves them in and out to run
Virtual memory allows execution of processes not completely in memory
MEMORY LAYOUT FOR MULTIPROGRAMMED SYSTEM
 MODES OF OPERATION

A mechanism that allows the OS to protect itself and other system

components
Two modes:
 User mode
 Kernel mode
Mode bit (0 or 1) provided by hardware
 Provides ability to distinguish when system is running user code or
kernel code
 Some instructions designated as privileged, only executable in kernel
mode
 Systems call by a user asking the OS to perform some function changes
from user mode to kernel mode.
 Return from a system call resets the mode to user mode.
TRANSITION FROM USER TO KERNEL MODE
TIMER

To prevent process to be in infinite loop (process hogging

resources), a timer is used, which is a hardware device.
Timer is a counter that is decremented by the physical clock.
Timer is set to interrupt the computer after some time period
Operating system sets the counter (privileged instruction)
When counter reaches the value zero, and interrupt is generated.
The OS sets up the value of the counter before scheduling a process to
regain control or terminate program that exceeds allotted time
PROCESS MANAGEMENT

A process is a program in execution. It is a unit of work within the system. Program

is a passive entity, process is an active entity.
Process needs resources to accomplish its task
 CPU, memory, I/O, files, etc.
 Initialization data
Process termination requires reclaim of any reusable resources
A thread is a basic unit of CPU utilization within a process.
 Single-threaded process. Instructions are executed sequentially, one at a time,
until completion
 Process has one program counter specifying location of next instruction to
execute
Multi-threaded process has one program counter per thread
Typically, a system has many processes, some user, some operating system running
concurrently on one or more CPUs
 Concurrency by multiplexing the CPUs among the threads
 PROCESS MANAGEMENT ACTIVITIES

The operating system is responsible for the following activities in

connection with process management:
Creating and deleting both user and system processes
Suspending and resuming processes
Providing mechanisms for process synchronization
Providing mechanisms for process communication
Providing mechanisms for deadlock handling
MEMORY MANAGEMENT

To execute a program all (or part) of the instructions must be in memory

All (or part) of the data that is needed by the program must be in memory.
Memory management determines what is in memory and when
 Optimizing CPU utilization and computer response to users
Memory management activities
 Keeping track of which parts of memory are currently being used and by
whom
 Deciding which processes (or parts thereof) and data to move into and out of
memory
 Allocating and deallocating memory space as needed
 STORAGE MANAGEMENT

OS provides uniform, logical view of information storage

Abstracts physical properties to logical storage unit - file
Files are stored in a number of different storage medium.
 Disk
 Flash Memory
 Tape
Each medium is controlled by device drivers (i.e., disk drive, tape drive)
 Varying properties include access speed, capacity, data-transfer rate,
access method (sequential or random)
FILE SYSTEM MANAGEMENT

Files usually organized into directories

Access control on most systems to determine who can access what
OS activities include
 Creating and deleting files and directories
 Primitives to manipulate files and directories
 Mapping files onto secondary storage
 Backup files onto stable (non-volatile) storage media
SECONDARY-STORAGE MANAGEMENT

Usually disks used to store data that does not fit in main memory or data that
must be kept for a “long” period of time
Proper management is of central importance
Entire speed of computer operation hinges on disk subsystem and its
algorithms
OS activities
 Free-space management
 Storage allocation
 Disk scheduling
Some storage need not be fast
 Tertiary storage includes optical storage, magnetic tape
 Still must be managed – by OS or applications
CACHING

Important principle, performed at many levels in a computer (in hardware,

operating system, software)
Information in use copied from slower to faster storage temporarily
Faster storage (cache) checked first to determine if information is there
 If it is, information used directly from the cache (fast)
 If not, data copied to cache and used there
Cache are smaller (size-wise) than storage being cached
 Cache management important design problem
 Cache size and replacement policy
PERFORMANCE OF VARIOUS LEVELS OF STORAGE

Movement between levels of storage hierarchy can be explicit or implicit

MIGRATION OF DATA “A” FROM DISK TO REGISTER

Multitasking environments must be careful to use most recent value, no matter

where it is stored in the storage hierarchy

Multiprocessor environment must provide cache coherency in hardware such that

all CPUs have the most recent value in their cache
Distributed environment situation even more complex
 Several copies of a datum can exist
 Various solutions covered in Chapter 17
I/O SUBSYSTEM

One purpose of an operating system is to hide peculiarities of hardware

devices from the user
I/O subsystem responsible for
 Memory management of I/O including buffering (storing data temporarily
while it is being transferred), caching (storing parts of data in faster storage
for performance), spooling (the overlapping of output of one job with input of
other jobs)
 General device-driver interface
 Drivers for specific hardware devices
PROTECTION AND SECURITY

Protection – A mechanism for controlling access of processes (or users) to

resources defined by the OS
Security – A defense of the system against internal and external attacks
 Huge range, including denial-of-service, worms, viruses, identity theft, theft of
service
Systems generally first distinguish among users, to determine who can do what
 User identities (user IDs, security IDs) include name and associated number,
one per user
 User ID is associated with all files and processes of that user to determine
access control
 Group identifier (group ID) allows set of users to be defined and controls
managed, then also associated with each process, file
 Privilege escalation allows user to change to effective ID with more rights
VIRTUALIZATION

Allows operating systems to run applications within other OSes

 Vast and growing industry
Emulation used when the source CPU type is different from the target type
(i.e., PowerPC to Intel x86)
 Generally slowest method
 When computer language not compiled to native code – Interpretation
Virtualization – OS natively compiled for CPU, running guest OSes also
natively compiled
 Consider VMware running WinXP guests, each running applications, all on
native WinXP host OS
 VMM (virtual machine Manager) provides virtualization services
 VIRTUALIZATION ON LAPTOPS AND DESTOPS

A VMM allow the user to install multiple operating systems to run application
written for operating systems other than the native host.
 Apple laptop running Mac OS X host Windows as a guest
 Developing apps for multiple OSes without having multiple systems
 Testing applications without having multiple systems
 Executing and managing compute environments within data centers
VIRTUALIZATION ARCHITECTURE STRUCTURE
 COMPUTING ENVIRONMENTS - TRADITIONAL

Stand-alone general purpose machines

But blurred as most systems interconnect with others (i.e., the Internet)
Portals provide web access to internal systems
Network computers (thin clients) are like Web terminals
Mobile computers interconnect via wireless networks
Networking becoming ubiquitous – even home systems use firewalls to
protect home computers from Internet attacks
COMPUTING ENVIRONMENTS - MOBILE

Handheld smartphones, tablets, etc

What is the functional difference between them and a “traditional” laptop?
Extra features – more OS features (GPS -- Waze)
Allows new types of apps like augmented reality
Use IEEE 802.11 wireless, or cellular data networks for connectivity
Leaders are Apple iOS and Google Android
 UNIT 2
CPU SCHEDULING
CHAPTER 5A: CPU SCHEDULING

Basic Concepts
Scheduling Criteria
Scheduling Algorithms
Thread Scheduling
Multiple-Processor Scheduling
Real-Time CPU Scheduling
Operating Systems Examples
Algorithm Evaluation
OBJECTIVES

To introduce CPU scheduling, which is the basis for multiprogrammed operating

systems
To describe various CPU-scheduling algorithms
To discuss evaluation criteria for selecting a CPU-scheduling algorithm for a
particular system
To examine the scheduling algorithms of several operating systems
BASIC CONCEPTS

Maximum CPU utilization obtained with

multiprogramming
Most processes exhibit the following
behavior:
CPU burst followed by I/O burst
CPU–I/O Burst Cycle – Process execution
consists of a cycle of CPU execution and
I/O wait
CPU burst distribution is of main concern
CPU SCHEDULER

 Whenever the CPU becomes idle, the operating system must select one of
the processes in the ready queue to be executed.
 The selection process is carried out by the CPU scheduler.
 The ready queue may be ordered in various ways.
 CPU scheduling decisions may take place when a process:
1. Switches from running state to waiting state
2. Switches from running state to ready state
3. Switches from waiting state to ready state
4. When a process terminates
 For situations 1 and 4, there is no choice in terms of scheduling. A new
process (if one exists in the ready queue) must be selected for execution.
 There is a choice, however, for situations 2 and 3.
NONPREEMPTIVE SCHEDULING

When scheduling takes place only under circumstances 1 and 4.

Under nonpreemptive scheduling, once the CPU has been allocated
to a process, the process keeps the CPU until it releases the
CPU either by terminating or by switching to the waiting state.
PREEMPTIVE SCHEDULING

 When scheduling takes place only under circumstances 2 and 3

 Preemptive scheduling can result in race conditions when data are
shared among several processes.
 Consider the case of two processes that share data. While one
process is updating the data, it is preempted so that the second
process can run. The second process then tries to read the data,
which are in an inconsistent state.
 Consider preemption while in kernel mode
 Consider interrupts occurring during crucial OS activities
 Virtually all modern operating systems including Windows, Mac OS X,
Linux, and UNIX use preemptive scheduling algorithms.
DISPATCHER

Dispatcher module gives control of the CPU to the

process selected by the CPU scheduler; this
involves:
 switching context
 switching to user mode
 jumping to the proper location in the user program
to restart that program
Dispatch latency – time it takes for the dispatcher to
stop one process and start another running
SCHEDULING CRITERIA

CPU utilization – keep the CPU as busy as possible

Throughput – number of processes that complete their execution per
time unit (e.g., 5 per second)
Turnaround time – amount of time to execute a particular process
Waiting time – total amount of time a process has been waiting in the
ready queue
Response time – amount of time it takes from when a request was
submitted until the first response is produced, not output (for time-
sharing environment)
 OPTIMIZATION CRITERIA FOR SCHEDULING

Max CPU utilization

Max throughput
Min turnaround time
Min waiting time
Min response time
 SCHEDULING ALGORITHM

First –come, First-serve (FCFS)

Shortest-Job-First Scheduling (SJF)
Round-Robin Scheduling (RR)
Priority Scheduling
Multilevel Queue Scheduling
FIRST- COME, FIRST-SERVED (FCFS) SCHEDULING

Consider the following three processes and their burst time

ProcessBurst Time
P1 24
P2 3
P3 3
Suppose that the processes arrive in the order: P1 , P2 , P3
We use Gantt Chart to illustrate a particular schedule

P1 P2 P3
0 24 27 30

Waiting time for P1 = 0; P2 = 24; P3 = 27

Average waiting time: (0 + 24 + 27)/3 = 17
FCFS SCHEDULING (CONT.)

Suppose that the processes arrive in the order:

P2 , P3 , P1
The Gantt chart for the schedule is:

P2 P3 P1
0 3 6 30

Waiting time for P1 = 6; P2 = 0; P3 = 3

Average waiting time: (6 + 0 + 3)/3 = 3
Much better than previous case
Convoy effect - short process behind long process
 Consider one CPU-bound and many I/O-bound processes
SHORTEST-JOB-FIRST (SJF)

Associate with each process the length of its next CPU burst
 Use these lengths to schedule the process with the shortest time
SJF is optimal – gives minimum average waiting time for a given set of
processes
 How do we know what is the length of the next CPU request
 Could ask the user
 what if the user lies?
EXAMPLE OF SJF

 Consider the following four processes and their burst time

ProcessArriva l Time Burst Time

P1 0.0 6
P2 2.0 8
P3 4.0 7
P4 5.0 3
SJF scheduling chart

P4 P1 P3 P2
0 3 9 16 24
Average waiting time = (3 + 16 + 9 + 0) / 4 = 7
DETERMINING LENGTH OF NEXT CPU BURST

Can only estimate (predict) the length – in most cases should be similar to
the previous CPU burst
 Pick the process with shortest predicted next CPU burst
Can be done by using the length of previous CPU bursts, using exponential
averaging

1. t n  actual length of n th CPU burst

2.  n 1  predicted value for the next CPU burst
3.  , 0    1
4. Define :  n 1   t n  1    n .
Commonly, α set to ½
SHORTEST-REMAINING-TIME-FIRST
Preemptive version of SJF is called shortest-remaining-time-first
Example illustrating the concepts of varying arrival times and preemption.
ProcessA arri Arrival TimeT Burst Time
P1 0 8
P2 1 4
P3 2 9
P4 3 5
Preemptive SJF Gantt Chart

P1 P2 P4 P1 P3
Average waiting
0
time
1
= [(10-1)+(1-1)+(17-2)+5-3)]/4
5 10
=1726/4 = 6.5 msec 26
ROUND ROBIN (RR)

Each process gets a small unit of CPU time (time quantum q). After this time
has elapsed, the process is preempted and added to the end of the ready
queue.
If there are N processes in the ready queue and the time quantum is q, then
each process gets 1/N of the CPU time in chunks of at most q time units at
once. No process waits more than (N-1)q time units.
Timer interrupts every quantum to schedule next process
Performance
 q large  FIFO
 q small  q must be large with respect to context switch, otherwise
overhead is too high
PRIORITY SCHEDULING

A priority number (integer) is associated with each process

The CPU is allocated to the process with the highest priority (smallest integer 
highest priority)
 Preemptive
 Nonpreemptive

SJF is priority scheduling where priority is the inverse of predicted next CPU burst
time

Problem  Starvation – low priority processes may never execute

Solution  Aging – as time progresses increase the priority of the process

 EXAMPLE OF PRIORITY SCHEDULING

 Consider the following five processes and their burst time

ProcessA arri Burst TimeT Priority

P1 10 3
P2 1 1
P3 2 4
P4 1 5
P5 5 2

Priority scheduling Gantt Chart

P1 P2 P1 P3 P4
0 1 6 16 18 19
Average waiting time = 8.2 msec
 COMBINING PRIORITY SCHEDULING AND RR

 System executes the highest priority process; processes with the

same priority will be run using round-robin.

 Consider the following five processes and their burst time

ProcessA arri Burst TimeT Priority
P1 4 3
P2 5 2
P3 8 2
P4 7 1
P5 3 3
Priority scheduling Gantt Chart

Average waiting time = 8.2 msec

SEPARATE QUEUE FOR EACH PRIORITY
MULTILEVEL QUEUE SCHEDULING
MULTILEVEL FEEDBACK QUEUE

A process can move between the various queues; aging can be implemented this
way
Multilevel-feedback-queue scheduler defined by the following parameters:
 number of queues
 scheduling algorithms for each queue
 method used to determine when to upgrade a process
 method used to determine when to demote a process
 method used to determine which queue a process will enter when that process
needs service
 EXAMPLE OF MULTILEVEL FEEDBACK QUEUE

Three queues:
 Q0 – RR with time quantum 8 milliseconds
 Q1 – RR time quantum 16 milliseconds
 Q2 – FCFS

Scheduling
 A new job enters queue Q0 which is served FCFS
 When it gains CPU, job receives 8 milliseconds
 If it does not finish in 8 milliseconds, job is
moved to queue Q1
 At Q1 job is again served FCFS and receives 16
additional milliseconds
 If it still does not complete, it is preempted
and moved to queue Q2
MAIN MEMORY
 MEMORY MANAGEMENT

Background
Swapping
Contiguous Memory Allocation
Segmentation
Paging
Structure of the Page Table
Example: The Intel 32 and 64-bit Architectures
Example: ARM Architecture
OBJECTIVES

To provide a detailed description of various ways of organizing memory

hardware
To discuss various memory-management techniques, including paging
and segmentation
To provide a detailed description of the Intel Pentium, which supports
both pure segmentation and segmentation with paging
BACKGROUND

A program must be brought (from disk) into memory and placed within a
process for it to be run
A program can be written in machine language, assembly language, or high-
level language.
Main memory and registers are the only storage entities that a CPU can
access directly
The CPU fetches instructions from main memory according to the value of the
program counter.
Typical instruction execution cycle – fetch instruction from memory, decode the
instruction, operand fetch, possible storage of result in memory.
MEMORY PROTECTION

A base register (holding the smallest legal physical address of a program in

memory) and a limit register (specifies the size of the program) define the
boundary of a program in memory.
CPU must check that every memory access generated in user mode is
between the base and base+limit for that user
HARDWARE ADDRESS PROTECTION
ADDRESS BINDING

A program residing on the disk needs to be brought into memory in order

to execute. Such a program is usually stored as a binary executable
file and is kept in an input queue.
In general, we do not know a priori where the program is going to reside in
memory. Therefore, it is convenient to assume that the first physical
address of a program always starts at location 0000.
Without some hardware or software support, program must be loaded into
address 0000
It is impractical to have first physical address of user process to always
start at location 0000.
Most (all) computer systems provide hardware and/or software support
for memory management,
BINDING OF INSTRUCTIONS AND DATA TO MEMORY
Address binding of instructions and data to memory
addresses can happen at three different points in time:

Compile time: If memory location known a priori, absolute code can be

generated; must recompile code if starting location changes
Load time: If memory location is not known at compile time and no
hardware support is available, relocatable code must be generated
Execution time: Binding delayed until run time if the process can be
moved during its execution from one memory segment to another
 Need hardware support for address maps (e.g., base and limit registers)
MULTISTEP PROCESSING OF A USER PROGRAM
 LOGICAL VS. PHYSICAL ADDRESS SPACE

The concept of a logical address space that is bound to a separate physical

address space is central to proper memory management
 Logical address – generated by the CPU.
 Physical address – address seen by the memory unit
Logical and physical addresses are:
 The same in compile-time and load-time address-binding schemes;
 They differ in execution-time address-binding scheme. In that case the logical
address is referred to as virtual address.
We use Logical address and virtual address interchangeably
Logical address space is the set of all logical addresses generated by a
program
Physical address space is the set of all physical addresses corresponding to a
given logical address space.
MEMORY-MANAGEMENT UNIT (MMU)

Hardware device that at run time maps virtual addresses to physical address

Many methods possible, covered in the rest of this chapter

The user program deals with logical addresses; it never sees the real physical
addresses
 Execution-time binding occurs when reference is made to location in memory
 Logical address bound to physical addresses
DYNAMIC RELOCATION USING A RELOCATION REGISTER

To start, consider simple scheme where the value in the base register is added
to every address generated by a user process at the time it is sent to
memory
 Base register now called relocation register
 MS-DOS on Intel 80x86 used 4 relocation registers
DYNAMIC LOADING

 Until now we assumed that the entire program and data

has to be in main memory to execute
 Dynamic loading allows a routine (module) to be loaded into
memory only when it is called (used)
 Results in better memory-space utilization; unused routine
is never loaded
 All routines kept on disk in relocatable load format
 Useful when large amounts of code are needed to handle
infrequently occurring cases (e.g., exception handling)
 No special support from the operating system is required
 It is the responsibility of the users to design their
programs to take advantage of such a method
 OS can help by providing libraries to implement
dynamic loading
DYNAMIC LINKING

Dynamically linked libraries – system libraries that are linked to user programs
when the programs are run.
 Similar to dynamic loading. But, linking rather than loading is postponed
until execution time
Small piece of code, stub, used to locate the appropriate memory-resident
library routine
Stub replaces itself with the address of the routine, and executes the routine
Operating system checks if routine is in processes’ memory address
 If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries
CONTIGUOUS ALLOCATION

Main memory must support both OS and user processes

Limited resource -- must allocate efficiently
Contiguous allocation is one early method
Main memory is usually divided into two partitions:
 Resident operating system, usually held in low memory with interrupt vector
 User processes are held in high memory
 Each process contained in single contiguous section of memory
CONTIGUOUS ALLOCATION (CONT.)

Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
 Base register contains value of smallest physical address
 Limit register contains range of logical addresses – each logical address
must be less than the limit register
 MMU maps logical address dynamically
 Can then allow actions such as kernel code being transient – comes and
goes as needed. Thus, kernel can change size dynamically.
HARDWARE SUPPORT FOR RELOCATION AND LIMIT
REGISTERS
MULTIPLE-PARTITION ALLOCATION
Variable-partition -- sized to a given process’ needs.
Hole – block of available memory; holes of various size are scattered
throughout memory
When a process arrives, it is allocated memory from a hole large enough
to accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (holes)
DYNAMIC STORAGE-ALLOCATION PROBLEM

How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough
 Best-fit: Allocate the smallest hole that is big enough; must search entire
list, unless the list is ordered by size.
 Produces the smallest leftover hole
 Worst-fit: Allocate the largest hole; must also search entire list, unless the
list is ordered by size
 Produces the largest leftover hole
First-fit and best-fit are better than worst-fit in terms of speed and storage
utilization
FRAGMENTATION

External Fragmentation – total memory space exists to satisfy a request,

but it is not contiguous and therefore cannot be used.
 First fit analysis reveals that given N allocated blocks, another 0.5 N
blocks will be lost to fragmentation
 1/3 of memory may be unusable -> 50-percent rule
Internal Fragmentation – allocated memory may be slightly larger than
requested memory.
 Can happen if there is hole of size 15,000 bytes and a process needs
14,900 bytes; Keeping a hole of size 100 bytes is not worth the effort so
the process is allocated 15,000 bytes.
 The size difference of 100 bytes is memory internal to a partition, but not
being used
FRAGMENTATION (CONT.)

Reduce external fragmentation by compaction

Shuffle memory contents to place all free memory together in one large
block
Compaction is possible only if relocation is dynamic, and is done at
execution time
I/O problem -- cannot perform compaction while I/O is in progress
involving memory that is being compacted.
 Latch job in memory while it is involved in I/O
 Do I/O only into OS buffers
NON-CONTIGUOUS ALLOCATION

Partition the a program into a number of small units, each of which can
reside in a different part of the memory.
Need hardware support.
Various methods to do the partitions:
 Segmentation.
 Paging
 paged segmentation.
 SEGMENTATION

Memory-management scheme that supports user’s view of memory

A program is a collection of segments -- a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Each segment can to reside in different parts of memory. Way to circumvent
the contiguous allocation requirement.
USER’S VIEW OF A PROGRAM
TWO DIMENSIONAL ADDRESSES
LOGICAL AND PHYSICAL MEMORY
SEGMENTATION ARCHITECTURE

Logical address consists of a two tuple:

<segment-number, offset>
Need to map a two-dimensional logical addresses to a one-dimensional
physical address. Done via Segment table:
 base – contains the starting physical address where the segments reside in
memory
 limit – specifies the length of the segment
Segment table is kept in memory
 Segment-table base register (STBR) points to the segment table’s location
in memory
 Segment-table length register (STLR) indicates number of segments used
by a program;
segment number s is legal if s < STLR
SEGMENTATION HARDWARE
EXAMPLE OF SEGMENTATION
PAGING

Physical address space of a process can be non-contiguous.

Process is divided into fixed-size blocks, each of which may reside in a
different part of physical memory.
Divide physical memory into fixed-sized blocks called frames
 Size of a frame is power of 2 between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size as frames called pages
Backing store, where the program is permanently residing, is also split
into storage units (called blocks), which are the same size as the
frame and pages.
Physical memory allocated whenever the latter is available
 Avoids external fragmentation
 Still have Internal fragmentation
PAGING (CONT.)

Keep track of all free frames

To run a program of size N pages, need to find N free frames and load program
from backing store.
Set up a page table to translate logical to physical addresses
Page table is kept in memory.
 Page-table base register (PTBR) points to the page table
 Page-table length register (PTLR) indicates size of the page table
Still have Internal fragmentation (more later)
ADDRESS TRANSLATION SCHEME

Assume the logical address space is 2m. (How is m determined?)

Assume page size is 2n
Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table which contains base
address of each page in physical memory. Size of p is “m – n”
 Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit. Size of d is “n”.
PAGING HARDWARE
PAGING MODEL OF LOGICAL AND PHYSICAL MEMORY
PAGING EXAMPLE

Assume m = 4 and n = 2 and 32-byte memory and 4-byte pages

INTERNAL FRAGMENTATION

Calculating internal fragmentation

 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
By implementation process can only access its own memory
ALLOCATING FRAMES TO A NEW PROCESS

Before allocation After allocation

TLB -- ASSOCIATIVE MEMORY

If page table is kept in main memory every data/instruction access requires two
memory accesses
 One for the page table and one for the data / instruction
The two memory access problem can be solved by the use of a special fast-lookup
hardware cache called associative memory or translation look-aside buffers (TLBs)
Associative memory – parallel search

Page # Frame #

Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in memory
TLB ISSUES

TLB is typically small (64 to 1,024 entries)

On a TLB miss, the value of the (missed page-table and frame-number),
is loaded into the TLB for faster access next time that address is
used.
 What if there is no free TLB entry? Replacement policies must be
considered
 Some entries can be wired down for permanent fast access
Some TLBs store address-space identifiers (ASIDs) in each TLB entry –
uniquely identifies each process to provide address-space protection
for that process
 Otherwise need to flush TLB at every context switch
PAGING HARDWARE WITH TLB
EFFECTIVE ACCESS TIME

Associative Lookup =  time unit

 Can be < 10% of memory access time
Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative registers

Effective Access Time (EAT)

EAT = (1 + )  + (2 + )(1 – )
=2+–
Consider  = 20ns for TLB search and 100ns for memory access
 if  = 80%:
 EAT = 0.80 x 100 + 0.20 x 200 = 120ns
 Consider more realistic hit ratio of  = 99%
 EAT = 0.99 x 100 + 0.01 x 200 = 101ns
MEMORY PROTECTION

Memory protection implemented by associating protection bits with each

frame to indicate if “read-only “ or “read-write” access is allowed
 Can also add more bits to indicate “execute-only” and so on
Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the process’ logical
address space, and is thus is a legal page
 “invalid” indicates that the page is not in the process’ logical address
space
 Or use page-table length register (PTLR)
Any violations result in a trap to the kernel
VALID (V) OR INVALID (I) BIT IN A PAGE TABLE
SHARED PAGES

Shared code
 One copy of read-only (reentrant) code shared among processes (i.e., text
editors, compilers, window systems)
 Similar to multiple threads sharing the same process space
 Also useful for inte-rprocess communication if sharing of read-write pages is
allowed
Private code and data
 Each process keeps a separate copy of the code and data
 The pages for the private code and data can appear anywhere in the logical
address space
SHARED PAGES EXAMPLE
STRUCTURE OF THE PAGE TABLE

Memory structures for paging can get huge using straight-forward methods
 Consider a 32-bit logical address space
 Page size of 1 KB (210)
 Page table would have 4 million entries (232 / 210)
 If each entry is 4 bytes -> Page table is of size 16 MB
 That amount of memory used to cost a lot.
 Do not want to allocate that contiguously in main memory
What about a 64-bit logical address space?
PAGE TABLE FOR LARGE ADDRESS SPACE

Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
HIERARCHICAL PAGE TABLES

Break up the logical address space into multiple page tables

A simple technique is a two-level page table
We then page the page table
TWO-LEVEL PAGING EXAMPLE

A logical address (on 32-bit machine with 1K page size) is divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits

Since the page table is paged, the page number is further divided into:
 a 12-bit page number
 a 10-bit page offset

Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the displacement within the
page of the inner page table
Known as forward-mapped page table
ADDRESS-TRANSLATION SCHEME
64-BIT LOGICAL ADDRESS SPACE

Even two-level paging scheme not sufficient

If page size is 4 KB (212)
 Then page table has 252 entries
 If two level scheme, inner page tables could be 210 4-byte
entries
 Address would look like

 Outer page table has 242 entries or 244 bytes

64-BIT LOGICAL ADDRESS SPACE (CONT.)

One solution is to divide the outer page table. Various ways of doing so.
Example – three-level page table

 Even with 2nd outer page table, the outer-outer table is still 234 bytes
in size.
 And possibly 4 memory access to get to one physical memory
location.
The next step would be four-level. But ….
64-BIT LOGICAL ADDRESS SPACE (CONT.)

Several schemes for dealing with very large logical

address space
Hashed Page Table.
Clustered Page Tables
Inverted Page Table
HASHED PAGE TABLE

Common in address spaces > 32 bits

The virtual page number is hashed into a page table
 This page table contains a chain of elements hashing to the same
location
Each element contains:
1. The virtual page number
2. The value of the mapped page frame
3. A pointer to the next element
Virtual page numbers are compared in this chain searching for a match
 If a match is found, the corresponding physical frame is extracted
HASHED PAGE TABLE
CLUSTERED PAGE TABLES

Variation for 64-bit addresses is clustered page tables

Similar to hashed but each entry refers to several pages (such as 16) rather
than 1
Especially useful for sparse address spaces (where memory references are
non-contiguous and scattered)
INVERTED PAGE TABLE

Rather than each process having a page table and keeping track of all
possible logical pages, track all the physical pages
Use inverted page-table, which has one entry for each real page of
memory
An entry the inverted-page table consists of the virtual address of the
page stored in that real memory location, with information about the
process that owns that page.
What is maximum size of the inverted page-table?
INVERTED PAGE TABLE ARCHITECTURE
INVERTED PAGE TABLE (CONT.)

Decreases memory needed to store each individual page table, but

increases time needed to search the inverted page table when a
page reference occurs
Use hash table to limit the search to one — or at most a few — page-
table entries
 TLB can accelerate access
But how to implement shared memory?
 One mapping of a virtual address to the shared physical address
ORACLE SPARC SOLARIS
Consider modern, 64-bit operating system example with tightly integrated
HW
 Goals are efficiency, low overhead
Based on hashing, but more complex
Two hash tables
 One kernel and one for all user processes
 Each maps memory addresses from virtual to physical memory
 Each entry represents a contiguous area of mapped virtual memory,
 More efficient than having a separate hash-table entry for each page
 Each entry has base address and span (indicating the number of pages
the entry represents)
ORACLE SPARC SOLARIS (CONT.)

TLB holds translation table entries (TTEs) for fast hardware lookups
 A cache of TTEs reside in a translation storage buffer (TSB)
 Includes an entry per recently accessed page
Virtual address reference causes TLB search
 If miss, hardware walks the in-memory TSB looking for the TTE corresponding to the
address
 If match found, the CPU copies the TSB entry into the TLB and translation
completes
 If no match found, kernel interrupted to search the hash table
 The kernel then creates a TTE from the appropriate hash table and stores it in
the TSB, Interrupt handler returns control to the MMU, which completes the
address translation.
 EXAMPLE: THE INTEL 32 AND 64-BIT
ARCHITECTURES

Dominant industry chips

Pentium CPUs are 32-bit and called IA-32 architecture
Current Intel CPUs are 64-bit and called IA-64 architecture
Many variations in the chips, cover the main ideas here
 EXAMPLE: THE INTEL IA-32 ARCHITECTURE

Supports both segmentation and segmentation with paging

 Each segment can be 4 GB
 Up to 16 K segments per process
 Divided into two partitions
 First partition of up to 8 K segments are private to process (kept in local
descriptor table (LDT))
 Second partition of up to 8K segments shared among all processes (kept in
global descriptor table (GDT))
 EXAMPLE: THE INTEL IA-32 ARCHITECTURE (CONT.)

CPU generates logical address

 Selector given to segmentation unit
 Which produces linear addresses

 Linear address given to paging unit

 Which generates physical address in main memory
 Paging units form equivalent of MMU
 Pages sizes can be 4 KB or 4 MB
LOGICAL TO PHYSICAL ADDRESS TRANSLATION IN IA-32
INTEL IA-32 SEGMENTATION
INTEL IA-32 PAGING ARCHITECTURE
 INTEL IA-32 PAGE ADDRESS EXTENSIONS
 32-bit address limits led Intel to create page address extension (PAE),
allowing 32-bit apps access to more than 4GB of memory space
 Paging went to a 3-level scheme
 Top two bits refer to a page directory pointer table
 Page-directory and page-table entries moved to 64-bits in size
 Net effect is increasing address space to 36 bits – 64GB of physical
memory
INTEL X86-64

 Current generation Intel x86 architecture

 64 bits is ginormous (> 16 exabytes)
 In practice only implement 48 bit addressing
 Page sizes of 4 KB, 2 MB, 1 GB
 Four levels of paging hierarchy
 Can also use PAE so virtual addresses are 48 bits and physical
addresses are 52 bits
EXAMPLE: ARM ARCHITECTURE

 Dominant mobile platform chip

(Apple iOS and Google Android 32 bits
devices for example)
outer page inner page offset
 Modern, energy efficient, 32-bit
CPU
 4 KB and 16 KB pages
4-KB
 1 MB and 16 MB pages (termed or
16-KB
sections) page

 One-level paging for sections, two-

level for smaller pages
 Two levels of TLBs 1-MB
or
 Outer level has two micro 16-MB
section
TLBs (one data, one
instruction)
 Inner is single main TLB
 First inner is checked, on
miss outers are checked,
and on miss page table
walk performed by CPU
SWAPPING

A process can be swapped temporarily out of memory to a backing store and

then brought back into memory for continued execution
 Total physical memory space of all processes can exceed the real physical
memory of the system.

Backing store – fast disk large enough to accommodate copies of all

memory images for all processes; must provide direct access to these
memory images

System maintains a ready queue of ready-to-run processes which are either

in memory or have memory images on disk.

Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
SCHEMATIC VIEW OF SWAPPING
SWAPPING (CONT.)
Does the swapped out process need to swap back in to same physical
addresses?
 Depends on address binding method
 Plus must consider pending I/O to / from process memory space
Modified versions of swapping are found on many systems (i.e., UNIX, Linux,
and Windows). A common variation:
 Swapping is normally disabled
 Swapping is started if the amount of free memory (unused memory
available for the operating system or processes to use) falls below a given
threshold.
 Swapping is disabled again once memory demand reduced below the
threshold
Another variation. Swapping portions of processes--rather than entire
processes--to decrease swap time.
Typically, these modified forms of swapping work in conjunction with virtual
memory (covered soon).
CONTEXT SWITCH TIME INCLUDING SWAPPING

If next processes to be located a CPU (say A) is not in memory and there is not
enough physical memory to accommodate A, then we need to swap out
one of the processes in memory (say B) and swap in process A.
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of 50MB/sec
 Swap out time of 2000 ms
 Plus swap in of same sized process
 Total context switch swapping component time of 4000ms (4 seconds)
Can reduce context switch time by knowing how much memory is really being
used. System calls to inform OS of memory use:
 request_memory() and release_memory()
 CONTEXT SWITCH TIME AND SWAPPING (CONT.)

Other constraints as well on swapping

 Pending I/O – can’t swap out as I/O would occur to wrong process
 Or always transfer I/O to kernel space, then to I/O device
 Known as double buffering, adds overhead
Standard swapping not used in modern operating systems
 But modified version common
 Swap only when free memory extremely low
SWAPPING ON MOBILE SYSTEMS

Not typically supported. Mobil systems use Flash memory:

 Limited number of write cycles
 Poor throughput between flash memory and CPU on mobile platform
Mobile systems use other methods to free memory if low
 iOS asks apps to voluntarily relinquish allocated memory
 Read-only data thrown out and reloaded from flash if needed
 Failure to free can result in termination
 Android terminates apps if low free memory, but first writes application state to
flash for fast restart
 Both operating systems support paging.
END OF CHAPTER 9
PAGING

Physical address space of a process can be non-contiguous; process is

allocated physical memory whenever the latter is available
 Avoids external fragmentation
 Avoids problem of varying sized memory chunks (e.g., segments)
Divide physical memory into fixed-sized blocks called frames
 Size of a frame is power of 2 between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size as frames called pages
Backing store, where the program is permanently residing, is also split
into storage units (called blocks), which are the same size as the
frame and pages.
Still have Internal fragmentation
STRUCTURE OF THE PAGE TABLE

Memory structures for paging can get huge using straight-forward

methods
 Consider a 32-bit logical address space
 Page size of 1 KB (210)
 Page table would have 4 million entries (232 / 210)
 If each entry is 4 bytes -> Page table is of size 16 MB
 That amount of memory used to cost a lot.
 Do not want to allocate that contiguously in main memory
 What about a 64-bit logical address space?
Hierarchical Paging
Hashed Page Tables
Inverted Page Tables
TWO-LEVEL PAGE-TABLE SCHEME
INVERTED PAGE TABLE

Rather than each process having a page table and keeping track of all
possible logical pages, track all the physical pages – using an inverted
page-table.
The inverted page-table has one entry for each real page of memory.
An entry the inverted-page table consists of the virtual address of the
page stored in that real memory location, with information about the
process that owns that page.
What is maximum size of the inverted page-table?
COMPUTING ENVIRONMENTS – DISTRIBUTED

Collection of separate, possibly heterogeneous, systems networked together

 Network is a communications path, TCP/IP most common
 Local Area Network (LAN)
 Wide Area Network (WAN)
 Metropolitan Area Network (MAN)
 Personal Area Network (PAN)
Network Operating System provides features to allow sharing of data between
systems across a network.
 Communication scheme allows systems to exchange messages
 Illusion of a single system
COMPUTING ENVIRONMENTS – CLIENT-SERVER

Dumb terminals supplanted by smart PCs

Many systems now servers, responding to requests generated by clients
 Compute-server system provides an interface to client to request services (i.e.,
database)
 File-server system provides interface for clients to store and retrieve files
COMPUTING ENVIRONMENTS - PEER-TO-PEER
Another model of distributed system. P2P does not distinguish clients and
servers
 Instead all nodes are considered peers
 Each node may act as client, server, or both
 Node must join P2P network
 Registers its service with central lookup service on network, or
 Broadcast request for service and respond to requests for service via
discovery protocol
 Examples include Napster and Gnutella, Voice over IP (VoIP) such as Skype
COMPUTING ENVIRONMENTS – CLOUD COMPUTING

Delivers computing, storage, even apps as a service across a network

Logical extension of virtualization because it uses virtualization as the base for it
functionality.
 Amazon EC2 has thousands of servers, millions of virtual machines, petabytes of
storage available across the Internet, pay based on usage
Many types
 Public cloud – available via Internet to anyone willing to pay
 Private cloud – run by a company for the company’s own use
 Hybrid cloud – includes both public and private cloud components
 Software as a Service (SaaS) – one or more applications available via the Internet
(i.e., word processor)
 Platform as a Service (PaaS) – software stack ready for application use via the
Internet (i.e., a database server)
 Infrastructure as a Service (IaaS) – servers or storage available over Internet (i.e.,
storage available for backup use)
 COMPUTING ENVIRONMENTS – CLOUD COMPUTING

Cloud computing environments composed of traditional OSes, plus VMMs, plus

cloud management tools
 Internet connectivity requires security like firewalls
 Load balancers spread traffic across multiple applications
COMPUTING ENVIRONMENTS – REAL-TIME SYSTEMS

Real-time embedded systems most prevalent form of computers

 Vary considerable, special purpose, limited purpose OS, real-time OS
 Use expanding
Many other special computing environments as well
 Some have OSes, some perform tasks without an OS
Real-time OS has well-defined fixed time constraints
 Processing must be done within constraint
 Correct operation only if constraints met
OPEN-SOURCE OPERATING SYSTEMS

Operating systems made available in source-code format rather than just binary
closed-source
Counter to the copy protection and Digital Rights Management (DRM) movement
Started by Free Software Foundation (FSF), which has “copyleft” GNU Public
License (GPL)
Examples include GNU/Linux and BSD UNIX (including core of Mac OS X), and
many more
Can use VMM like VMware Player (Free on Windows), Virtualbox (open source and
free on many platforms - http://www.virtualbox.com)
 Use to run guest operating systems for exploration