Verilog Arrays and Memories
Verilog Arrays and Memories
Introduction
What is Verilog?
Introduction to Verilog
Data Types
Verilog Syntax
Verilog Arrays
Building Blocks
Verilog Module
Verilog Port
Verilog Operators
Verilog Concatenation
Verilog in a nutshell
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Simulation
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Code Examples
Hello World!
JK Flip-Flop
D Flip-Flop
T Flip-Flop
D Latch
Counters
4-bit counter
Ripple Counter
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Gray Counter
Misc
Priority Encoder
4x1 multiplexer
Full adder
Array Assignment
1 y1 = 0; // Illegal - All
2
3 y2[0] = 8'ha2; // Assign 0xa2 to index=0
4 y2[2] = 8'h1c; // Assign 0x1c to index=2
5 y3[1][2] = 8'hdd; // Assign 0xdd to rows=1 cols
6 y3[0][0] = 8'haa; // Assign 0xaa to rows=0 cols
Array Example
The code shown below simply shows how different arrays can
be modeled, assigned and accessed. mem1 is an 8-bit vector,
mem2 is an 8-bit array with a depth of 4 (specified by the range
[0:3]) and mem3 is a 16-bit vector 2D array with 4 rows and 2
columns. These variables are assigned different values and
printed.
1 module des ();
2 reg [7:0] mem1; // re
3 reg [7:0] mem2 [0:3]; // 8-bit w
4 reg [15:0] mem3 [0:3][0:1]; // 16-bit wide ve
5
6 initial begin
7 int i;
8
9 mem1 = 8'ha9;
10 $display ("mem1 = 0x%0h", mem1);
11
12 mem2[0] = 8'haa;
13 mem2[1] = 8'hbb;
14 mem2[2] = 8'hcc;
15 mem2[3] = 8'hdd;
16 for(i = 0; i < 4; i = i+1) begin
17 $display("mem2[%0d] = 0x%0h", i, mem2[i]);
18 end
19
20 for(int i = 0; i < 4; i += 1) begin
21 for(int j = 0; j < 2; j += 1) begin
22 mem3[i][j] = i + j;
23 $display("mem3[%0d][%0d] = 0x%0h", i, j,
24 end
25 end
26 end
27 endmodule
Simulation Log
ncsim> run
mem1 = 0xa9
mem2[0] = 0xaa
mem2[1] = 0xbb
mem2[2] = 0xcc
mem2[3] = 0xdd
mem3[0][0] = 0x0
mem3[0][1] = 0x1
mem3[1][0] = 0x1
mem3[1][1] = 0x2
mem3[2][0] = 0x2
mem3[2][1] = 0x3
mem3[3][0] = 0x3
mem3[3][1] = 0x4
ncsim: *W,RNQUIE: Simulation is complete.
What are memories ?
Register Vector
Verilog vectors are declared using a size range on the left side of
the variable name and these get realized into flops that match
the size of the variable. In the code shown below, the design
module accepts clock, reset and some control signals to read
and write into the block.
Memory Example
Grammarly
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