Verilog Posts

Introduction

 What is Verilog?

 Introduction to Verilog

 Chip Design Flow

 Chip Abstraction Layers

Data Types

 Verilog Syntax

 Verilog Data types

 Verilog Scalar/Vector

 Verilog Arrays

Building Blocks

 Verilog Module

 Verilog Port

 Verilog Module Instantiations

 Verilog assign statements

 Verilog assign examples

 Verilog Operators

 Verilog Concatenation

 Verilog always block

 Combo Logic with always

 Sequential Logic with always

 Verilog initial block

 Verilog in a nutshell

 Verilog generate

Behavioral modeling

 Verilog Block Statements

 Verilog Assignment Types

 Verilog Blocking/Non-blocking

 Verilog Control Flow

 Verilog if-else-if

 Verilog Conditional Statements

 Verilog for Loop

 Verilog case Statement

 Verilog Functions

 Verilog Tasks

 Verilog Parameters

 Verilog `ifdef `elsif

 Verilog Delay Control

 Verilog Inter/Intra Delay

 Verilog Hierarchical Reference

 Verilog Coding Style Effect

Gate/Switch modeling

 Gate Level Modeling

 Gate Level Examples

 Gate Delays

 Switch Level Modeling

 User-Defined Primitives

Simulation

 Verilog Simulation Basics

 Verilog Testbench

 Verilog Timescale

 Verilog Scheduling Regions

 Verilog Clock Generator

System Tasks and Functions

 Verilog Display tasks

 Verilog Math Functions

 Verilog Timeformat

 Verilog Timescale Scope

 Verilog File Operations

Code Examples

 Hello World!

 Flops and Latches

 JK Flip-Flop

 D Flip-Flop

 T Flip-Flop

 D Latch
 Counters

 4-bit counter

 Ripple Counter

 Straight Ring Counter

 Johnson Counter

 Mod-N Counter

 Gray Counter

 Misc

 n-bit Shift Register

 Binary to Gray Converter

 Priority Encoder

 4x1 multiplexer

 Full adder

 Single Port RAM

 Verilog Pattern Detector

 Verilog Sequence Detector

Verilog Arrays and Memories

1. What is a Verilog array ?

1. Array Assignment
2. Array Example
2. What are memories ?
1. Register Vector
2. Memory Example
What is a Verilog array ?

An array declaration of a net or variable can be either scalar or

vector. Any number of dimensions can be created by specifying
an address range after the identifier name and is called a multi-
dimensional array. Arrays are allowed in Verilog for reg ,
wire , integer and real data types.

1 reg y1 [11:0]; // y is an scalar re

2 wire [0:7] y2 [3:0] // y is an 8-bit vec
3 reg [7:0] y3 [0:1][0:3]; // y is a 2D array r

An index for every dimension has to be specified to access a

particular element of an array and can be an expression of other
variables. An array can be formed for any of the different data-
types supported in Verilog.

Note that a memory of n 1-bit reg is not the same as an n-

bit vector reg.

Array Assignment

1 y1 = 0; // Illegal - All
2
3 y2[0] = 8'ha2; // Assign 0xa2 to index=0
4 y2[2] = 8'h1c; // Assign 0x1c to index=2
5 y3[1][2] = 8'hdd; // Assign 0xdd to rows=1 cols
6 y3[0][0] = 8'haa; // Assign 0xaa to rows=0 cols

Array Example

The code shown below simply shows how different arrays can
be modeled, assigned and accessed. mem1 is an 8-bit vector,
mem2 is an 8-bit array with a depth of 4 (specified by the range
[0:3]) and mem3 is a 16-bit vector 2D array with 4 rows and 2
columns. These variables are assigned different values and
printed.
1 module des ();
2 reg [7:0] mem1; // re
3 reg [7:0] mem2 [0:3]; // 8-bit w
4 reg [15:0] mem3 [0:3][0:1]; // 16-bit wide ve
5
6 initial begin
7 int i;
8
9 mem1 = 8'ha9;
10 $display ("mem1 = 0x%0h", mem1);
11
12 mem2[0] = 8'haa;
13 mem2[1] = 8'hbb;
14 mem2[2] = 8'hcc;
15 mem2[3] = 8'hdd;
16 for(i = 0; i < 4; i = i+1) begin
17 $display("mem2[%0d] = 0x%0h", i, mem2[i]);
18 end
19
20 for(int i = 0; i < 4; i += 1) begin
21 for(int j = 0; j < 2; j += 1) begin
22 mem3[i][j] = i + j;
23 $display("mem3[%0d][%0d] = 0x%0h", i, j,
24 end
25 end
26 end
27 endmodule

 Simulation Log

ncsim> run
mem1 = 0xa9
mem2[0] = 0xaa
mem2[1] = 0xbb
mem2[2] = 0xcc
mem2[3] = 0xdd
mem3[0][0] = 0x0
mem3[0][1] = 0x1
mem3[1][0] = 0x1
mem3[1][1] = 0x2
mem3[2][0] = 0x2
mem3[2][1] = 0x3
mem3[3][0] = 0x3
mem3[3][1] = 0x4
ncsim: *W,RNQUIE: Simulation is complete.
What are memories ?

Memories are digital storage elements that help store a data

and information in digital circuits. RAMs and ROMs are good
examples of such memory elements. Storage elements can be
modeled using one-dimensional arrays of type reg and is
called a memory. Each element in the memory may represent a
word and is referenced using a single array index.

Register Vector

Verilog vectors are declared using a size range on the left side of
the variable name and these get realized into flops that match
the size of the variable. In the code shown below, the design
module accepts clock, reset and some control signals to read
and write into the block.

It contains a 16-bit storage element called register which simply

gets updated during writes and returns the current value during
reads. The register is written when sel and wr are high on the
same clock edge. It returns the current data when sel is high
and wr is low.
 1 module des ( input clk,
2 input rstn,
3 input wr,
4 input sel,
5 input [15:0] wdata,
6 output [15:0] rdata);
7
8 reg [15:0] register;
9
10 always @ (posedge clk) begin
11 if (!rstn)
12 register <= 0;
13 else begin
14 if (sel & wr)
15 register <= wdata;
16 else
17 register <= register;
18 end
19 end
20
21 assign rdata = (sel & ~wr) ? register : 0;
22 endmodule

The hardware schematic shows that a 16-bit flop is updated

when control logic for writes are active and the current value is
returned when control logic is configured for reads.

Memory Example

In this example, register is an array that has four locations with

each having a width of 16-bits. The design module accepts an
additional input signal which is called addr to access a
particular index in the array.
 1 module des ( input clk,
2 input rstn,
3 input [1:0] addr,
4 input wr,
5 input sel,
6 input [15:0] wdata,
7 output [15:0] rdata);
8
9 reg [15:0] register [0:3];
10 integer i;
11
12 always @ (posedge clk) begin
13 if (!rstn) begin
14 for (i = 0; i < 4; i = i+1) begin
15 register[i] <= 0;
16 end
17 end else begin
18 if (sel & wr)
19 register[addr] <= wdata;
20 else
21 register[addr] <= register[addr];
22 end
23 end
24
25 assign rdata = (sel & ~wr) ? register[addr] : 0;
26 endmodule

It can be seen in the hardware schematic that each index of the

array is a 16-bit flop and the input address is used to access a
particular set of flops.
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Interview Questions

 Verilog Interview Set 1

 Verilog Interview Set 2

 Verilog Interview Set 3

 Verilog Interview Set 4

 Verilog Interview Set 5

 Verilog Interview Set 6

 Verilog Interview Set 7

 Verilog Interview Set 8

 Verilog Interview Set 9

 Verilog Interview Set 10

 Related Topics

 Digital Fundamentals

 Verilog Tutorial

 Verification

 SystemVerilog Tutorial

 UVM Tutorial

Verilog Testbench
 Verilog Coding Style Effect

Verilog Conditional Statements

Verilog Interview Set 10

Synchronous FIFO

SystemVerilog Interview Set 10

SystemVerilog Interview Set 9

SystemVerilog Interview Set 8

SystemVerilog Interview Set 7

SystemVerilog Interview Set 6

UVM Singleton Object

UVM Component [uvm_component]

UVM Object [uvm_object]

UVM Root [uvm_root]

UVM Interview Set 4

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