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Exercise1 Digital System (LAB)

The document provides an overview of topics in digital systems including number systems and codes, logic gates and Boolean algebra, and combinational logic circuits. It discusses binary, octal, decimal, and hexadecimal number systems and conversions between them. It also covers Boolean logic, logic gates, Boolean expressions, and simplification techniques. Finally, it discusses combinational logic circuits including sum-of-products and product-of-sums forms, canonical forms, Karnaugh maps for simplification, and the conversion between forms.

Uploaded by

Phong Đây
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
47 views

Exercise1 Digital System (LAB)

The document provides an overview of topics in digital systems including number systems and codes, logic gates and Boolean algebra, and combinational logic circuits. It discusses binary, octal, decimal, and hexadecimal number systems and conversions between them. It also covers Boolean logic, logic gates, Boolean expressions, and simplification techniques. Finally, it discusses combinational logic circuits including sum-of-products and product-of-sums forms, canonical forms, Karnaugh maps for simplification, and the conversion between forms.

Uploaded by

Phong Đây
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Systems

Exercise 1
CONTENT
• Number System and Codes
– Binary, Octal, Decimal, Hexadecimal
– Conversions between number systems
– Codes: Gray, Alphanumeric Codes
– Parity Method for Error Detection
• Logic Gates and Boolean Algebra
– Boolean Laws and Theorems
– Basic gates: AND, OR, NOT, NOR, NAND,…
– Simplifying Boolean expressions using Boolean Algebra
• Combinational Logic Circuits
– Sum-of-Product (SOP), Product-of-Sum (POS)
– Simplifying Logic Circuits using K-map method
– Designing Combinational Logic Circuits
2
Chapter 1

NUMBER SYSTEM AND CODES

3
Number System and Codes
1.1 Choose the right answer to complete the diagram for
a precision temperature regulation system.

A. (2) Digital-to-analog converter – (1) Analog-to-digital converter


B. (2) Analog-to-analog converter – (1) Digital-to-digital converter
C. (2) Analog-to-digital converter – (1) Digital-to-analog converter
D. (2) Digital-to-digital converter– (1) Analog-to-analog converter

4
Number System and Codes
1.2. Which of the following is the most widely used
alphanumeric code for computer input and output?
A. Gray C. BCD
B. Parity D. ASCII

1.3. Convert binary 1111111100102 to hexadecimal.


A. EE216 C. 2FE16
B. FF216 D. FD216

1.4. How many binary digits are required to count


to 10010?
A. 7 C. 3
B. 2 D. 100 5
Number System and Codes
1.5. A binary number's value changes most
drastically when the ________ is changed.
A. MSB C. LSB
B. Frequency D. Duty Cycle
1.6. Digital electronics is based on the ________
numbering system?
A. Decimal C. Binary
B. Octal D. Hexadecimal
1.7. The octal value corresponding to CF.1A16?
A. 617.032 C. 633.062
B. 613.034 D. 317.064
Number System and Codes
1.8. Find the address range of a memory. Known
that the memory size is 16Kb, the size of each
memory cell is 1 Byte, and the starting of memory
address is 0:
A. 0000-FFFF C. 0000- 7FFF
B. 0000-1FFF D. 0000-3FFF

1.9. If a typical PC uses a 20-bit address code, the


size of each memory cell is 1 Byte. How much
memory can the CPU address?
A. 1MB C. 20MB
B. 10MB D. 580MB
Number System and Codes

1.10. Assign the proper odd parity bit to the code


111001
A. 1111011 C. 0111111
B. 1111001 D. 0011111

1.11. Assign the proper even parity bit to the code


1100001
A. 11100001 C. 01100001
B. 1100001 D. 01110101

8
Chapter 2

LOGIC GATES AND BOOLEAN


ALGEBRA

9
10
Logic Gates and Boolean Algebra
2.1. The output of a logic gate is 1 when all its
inputs are at logic 0. The gate is either
A. a NAND or an EX-OR
B. an OR or an EX-NOR
C. an AND or an EX-OR
D. a NOR or an EX-NOR
2.2. One of the DeMorgan’s theorems shows the
equivalence of
A. OR gate and Exclusive OR gate
B. NOR gate and Bubbled AND gate
C. NOR gate and NAND gate
D. NAND11 gate and NOT gate
Logic Gates and Boolean Algebra

2.3. A universal logic gate is one, which can be


used to generate any logic function. Which of the
following is a universal logic gate?
A. OR B. AND C. XOR D. NAND

2.4. The expression for Absorption law is given by


_________
A. A + AB = A C. AB + AA’ = A
B. A + AB = B D. A + B = B + A

12
Logic Gates and Boolean Algebra
2.5. Which images is suitable the most with this
description: “Output Z will go LOW only when A or B
is LOW and C or D is LOW”.
A. a
B. b
C. c
D. All of them

13
Logic Gates and Boolean Algebra

14
Logic Gates and Boolean Algebra
2.6. Define the combination of inputs for the circuit
to make LED ON:

A. LED ON when B = 0 and C = 0 and D = 1 and E = 1


B. LED ON when A = 1 and B = 0 and C = 0 and D = 0 and E = 1
C. LED ON when A = 0 and B = 0 and C = 0 and D = 1 and E = 0
D. LED ON when
15
A = 1 and B = 0 and C = 1 and D = 0 and E = 0
Logic Gates and Boolean Algebra
2.7. Find Boolean expression of the following logic
circuit_________

A. 𝑋 = 𝐴𝐵ത + 𝐴𝐵
ҧ + 𝐵𝐶ҧ B. 𝑋 = 𝐴⨁𝐵 + 𝐵𝐶ҧ
C. 𝑋 = (𝐴ҧ𝐵ത + 𝐴𝐵)(𝐵ത + C) D. All of them
Combinational Logic Circuits

2.8. Which of the following Boolean expressions


NOT equal to F
Logic Gates and Boolean Algebra
2.9. Choose the TRUE statement:

A. X = A’ when B = 1 or C = 1, otherwise X = 1
B. X = A when B = 0 and C = 0, otherwise X = 0
C. X = A’ when B = 1 and C = 1, otherwise X = 1
D. All is not correct

18
Logic Gates and Boolean Algebra

2.10. Given F = A’B + (B+D)’B’D , the reverse


expression of F is:
A. F’ = AB’
B. F’ = A + B’
C. F’ = AB
D. Tất cả đều sai

19
Logic Gates and Boolean Algebra
2.11. Simplifying the circuit below
Logic Gates and Boolean Algebra

2.12. Use the rules of Boolean Algebra, simplify the


following:
𝑭 𝑿, 𝒀, 𝒁 = 𝑿 𝒀 + 𝒁 + 𝒁( 𝒀𝑿 𝒀)

21
Logic Gates and Boolean Algebra

2.13 Simplifying the Boolean expressions


g = (ab’ + b(c’ + (c d)’))’

22
Logic Gates and Boolean Algebra

2.14. The following function is in minimum sum of


products form. Implement it using only two-input
NAND gates.
ഥ𝑩
• 𝑲=𝑨 ഥ 𝑿 + 𝑨𝑩
ഥ𝑿ഥ +𝑨
ഥ 𝑩𝑿
ഥ + 𝑨𝑩𝑿

23
Logic Gates and Boolean Algebra

2.15. The following function is in minimum sum of


products form. Implement it using only two-input
NAND gates.
ഥ + 𝑾𝑿𝒁
• 𝑭 = 𝑾𝒀 ഥ+𝒀
ഥ 𝒁 + 𝑾𝑿
ഥ𝒁
=

24
Chapter 3

COMBINATIONAL LOGIC CIRCUITS

25
Combinational Logic Circuits
1. Sum of Products – SoP:
- A SoP expression will appear as two or more AND
terms Ored together
- E.g.: ABC + A’B’C
AB + A’BC’+ C’D’ +D

2. Product of Sums – PoS:


- A PoS expression will appear as two or more OR
terms ANDed together
- E.g.: (A + B’ + C)(A + C)
(A + B’)(C’ + D)
Canonical forms
 Canonical forms
 Standard forms for a Boolean expression
 Provide unique algebraic signatures for an expression
 Generally are not the simplest form (can be
minimized)
 Derive directly from a Boolen function’s truth table
 Two canonical forms:
 Sum-of-Products ( SoP – minterms)
 Product-of-Sums (PoS – maxterms)
Sum-of-Products canonical form
Also known as the disjunctive normal form
 Commonly called a minterm expansion

28
Minterms

Variables appears exactly once in each minterm, in


true or inverted form (but not both)

29
Product-of-sums canonical form
Also known as the conjunctive normal form
 Commonly called a maxterm expansion

30
Maxterms

Variables appears exactly once in each maxterm, in


true or inverted form (but not both)

31
Conversion between canonical forms
 Minterm to Maxterm
 Use maxterms that do not appear in minterm expansion
 E.g., F(A,B,C) = ∑𝑚 1,3,5,6,7 = ς 𝑀(0,2,4)
 Maxterm to Minterm
 Use minterms that do not appear in maxterm expansion
 E.g., F(A,B,C) = ς 𝑀(0,2,4) = ∑𝑚 1,3,5,6,7
 Minterm expansion of F to minterm expansion of F’
 Use minterms that do not appear
 E.g., F(A,B,C) = ∑𝑚 1,3,5,6,7 => F’(A,B,C) = ∑𝒎 𝟎, 𝟐, 𝟒
 Maxterm expansion of F to maxterm expansion of F’
 Use maxterms that do not appear
 E.g., F(A,B,C) =ς 𝑀(0,2,4) => F’(A,B,C) =ς 𝑀(1,3,5,6,7)
Combinational Logic Circuits

33
Combinational Logic Circuits
2. Find the minterm expansion of the following
expression:
f = a'(b'+d)+acd'
= ∑m(0,1,2,3,5,7,10,14)

34
Karnaugh Map Technique

K-Maps, like truth tables, are a way to show the


relationship between logic inputs and desired outputs.

K-Maps are a graphical technique used to simplify a logic


equation.

K-Maps are very procedural and much cleaner than


Boolean simplification.

K-Maps can be used for any number of input variables,


BUT are only practical for fewer than six.
35
K-Map Each minterm (or maxterm) in a truth
Format table corresponds to a cell in the K-Map.

K-Map cells are labeled so that both


horizontal and vertical movement differ
only in one variable.
A
B 0 1 A
AB
0 CD 00 01 11 10
0 2
00
1 0 4 12 8
1 3
01
1 5 13 9
A D
AB 11
C 00 01 11 10 3 7 15 11
C
0 10
2 6 14 10
0 2 6 4

1 B
1 3 7 5

B Numbering Scheme: 00, 01, 11, 10


Truth Table -TO- K-Map
A B C f1
f1(A,B,C) = m1 + m2 + m4 + m6
m0
0 0 0 0
= A’B’C + A’BC’ + AB’C’ + ABC’ 0 0 1 m1 1
0 1 0 m2 1
0 1 1 m3 0
1 0 0 m4 1
A
AB
1 0 1 m5 0
C 00 01 11 10

0 00 1 2 16 1 4 1 1 0 m6 1
1 11 0 3 0 7 0 5 1 1 1 m7 0
B
Groupings
Grouping a pair of adjacent 1’s eliminates the
variable that appears in complemented and
uncomplemented form.

Grouping a quad of 1’s eliminates the two


variables that appear in both complemented
and uncomplemented form.

Grouping an octet of 1’s eliminates the three


variables that appear in both complemented
and uncomplemented form, etc…..

38
Kmap

Use Karnaugh maps to reduce function to minimum SOP


forms:

F(ABCD) =  m (1, 5, 6, 7, 9, 11, 15) +  d (0, 2, 3, 8, 12, 14);


D = LSB.

a) Draw K-maps to reduce F

b) Write all the minimum sum-of-product forms (SOPs) of the


function F

c) Implement a minimized circuit F using only two-input NAND


gates
39

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