UNIT - 4

I/0-Organisation
Peripheral devices
1) Input or output devices attached to the computer are also called peripherals.
2) When input information is transferred to the processor via a slow keyboard, the processor will
be idle most of the time while waiting for the Formation to arrive. To use a computer efficiently,
many programs and data must be prepared in advance and transmitted into a storage medium
such as magnetic tapes or disks. The information in the disk is then transferred into computer
memory at a rapid rate.
3) COMMON I/O
a) Video monitors are the most commonly used peripherals. They consist of a keyboard as the
input device and a display unit as the output device.
i) The CRT contains an electronic gun that sends an electronic beam to a phosphorescent
screen in front of the tube. The beam can be deflected horizontally and vertically. To
produce a pattern on the screen.
ii) The display terminal can operate in a single-character mode where all characters
entered on the screen through the keyboard are transmitted to the computer
simultaneously. In the block mode, the edited text is first stored in a local memory inside
the terminal. The text is transferred to the computer as a block of data
b) Printers provide a permanent record on paper of computer output data or text. There are
three basic types of character printers: daisywheel, dot matrix, and laser printers.
c) magnetic tape c tapes are used mostly for storing files of data.
i) m. It is one of the cheapest and slowest methods for storage and has the advantage that
tapes can be removed when not in use
ii) . Access is sequential and consists of records that can be accessed one after another
d) Disks are used mostly for bulk storage of programs and data
4) The input-output organization of a computer is a function of the size of the computer and the
devices connected to it.

ASCII Alphanumeric Characters

• Input and output devices that communicate with people and the computer are usually
involved in the transfer of alphanumeric information to and from the device and the
computer. The standard binary code for the alphanumeric characters is ASCII (American
Standard Code for Information Interchange).
• It uses seven bits to code 128 characters.
• The ASCII code contains 94 characters that can be printed and 34 nonprinting characters
used for various control functions
• ASCII is a 7-bit code, but most computers manipulate an 8-bit quantity as a single unit called
a Byte. Therefore, ASCII characters most often are stored one per byte.
• The extra bit is sometimes used for other purposes, depending on the application.
DMA
What is DMA?

The transfer of data between a fast storage device such as magnetic disk and memory is often
limited by the speed of the CPU. Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of transfer. This transfer technique is
called direct memory access (DMA).

A DMA controller takes over the buses to manage the transfer directly between the I/O device and
memory.

The bus request (BR) input is used by the DMA controller to request the CPU to relinquish control of
the buses. When this input is active, the CPU terminates the execution of the current instruction and
places the address bus, the data bus, and the read and write lines into a high-impedance state.

The CPU activates the bus grant (BG) output to inform the external DMA that the buses are in the
high-impedance state.

The DMA that originated the bus request can now take control of the buses to con- duct memory
transfers without processor intervention. When the DMA terminates the transfer, it disables the bus
request line. The CPU disables the bus grant, takes control of the buses, and returns to its normal
operation

- burst transfer, a block sequence consisting of several memory words is transferred in a continuous
burst while the DMA controller is master of the memory buses

- cycle stealing allows the DMA controller to transfer one data word at a time
DMA Controller

The DMA controller needs the usual circuits of an interface to communicate with the CPU and I/O
device.

The registers in the DMA are selected by the CPU through the address bus by enabling the DS (DMA
select) and RS (register select) inputs.

The RD (read) and WR (write) inputs are bidirectional.

+When the BG (bus grant) input is 0, the CPU can communicate with the DMA registers through the
data bus to read from or write to the DMA registers.

+ When BG = 1, the CPU has relinquished the buses and the DMA can communicate directly with the
memory by specifying an address in the address bus and activating the RD or WR control.

The DMA controller has three registers: an address register, a word count register, and a control
register.

The address register contains an address to specify the desired location in memory. The address bits
go through bus buffers into the address bus. The address register is incremented after each word
that is transferred to memory.

The word count register holds the number of words to be transferred. This register is decremented
by one after each word transfer and internally tested for zero. The control register specifies the
mode of transfer.

The DMA is first initialized by the CPU. After that, the DMA starts and continues to transfer data
between memory and peripheral unit until an entire block is transferred.
The CPU initializes the DMA by sending the following information through the data bus:

1. The starting address of the memory block where data are available (for read) or where data are to
be stored (for write)

2. The word count, which is the number of words in the memory block

3. Control to specify the mode of transfer such as read or write

4. A control to start the DMA transfer

DMA Transfer

The CPU communicates with the DMA through the address and data buses as with any interface
unit.

The CPU initializes the DMA through the data bus. Once the DMA receives the start control
command, it can start the transfer between the peripheral device and the memory.
When the peripheral device sends a DMA request, the DMA controller activates the BR line,
informing the CPU to relinquish the buses. The CPU responds with its BG line, informing the DMA
that its buses are disabled. The DMA then puts the current value of its address register into the
address bus, initiates the RD or WR signal, and sends a DMA acknowledge to the peripheral device.

When the peripheral device receives a DMA acknowledge, it puts a word in the data bus (for write)
or receives a word from the data bus (for read). Thus, the DMA controls the read or write operations
and supplies the address for the memory.

For each word that is transferred, the DMA increments its address register and decrements its word
count register.

If the word count register reaches zero, the DMA stops any further trans- fer and removes its bus
request. It also informs the CPU of the termination by means of an interrupt.

If we have more than 1 DMA converter we daisy chain them.

COMPUTER ORGANIZATION

INTERFACE-CIRCUITS
• An I/O Interface consists of the circuitry required to connect an I/O device to a computer-bus.
• On one side of the interface, we have bus signals.
On the other side, we have a data path with its associated controls to transfer data between the
interface and the I/O device known as port.
• Two types are:
1. Parallel Port transfers data in the form of a number of bits (8 or 16) simultaneously to or
from the device.
2. Serial Port transmits and receives data one bit at a time.
• Communication with the bus is the same for both formats.
• The conversion from the parallel to the serial format, and vice versa, takes place inside the interface-
circuit.
• In parallel-port, the connection between the device and the computer uses
→ a multiple-pin connector and
→ a cable with as many wires.
• This arrangement is suitable for devices that are physically close to the computer.
• In serial port, it is much more convenient and cost-effective where longer cables are needed.
Functions of I/O Interface
1) Provides a storage buffer for at least one word of data.
2) Contains status-flags that can be accessed by the processor to determine whether the buffer
is full or empty.
3) Contains address-decoding circuitry to determine when it is being addressed by the
processor.
4) Generates the appropriate timing signals required by the bus control scheme.
5) Performs any format conversion that may be necessary to transfer data between the bus and
the I/O device (such as parallel-serial conversion in the case of a serial port).

1
COMPUTER ORGANIZATION
PARALLEL-PORT
KEYBOARD INTERFACED TO PROCESSOR

• The output of the encoder consists of

→ bits representing the encoded character and
→ one signal called valid, which indicates the key is pressed.
• The information is sent to the interface-circuits (Figure 7.10).
• Interface-circuits contain
1) Data register DATAIN &
2) Status-flag SIN.
• When a key is pressed, the Valid signal changes from 0 to1.
Then, SIN=1  when ASCII code is loaded into DATAIN.
SIN = 0  when processor reads the contents of the DATAIN.
• The interface-circuit is connected to the asynchronous bus.
• Data transfers on the bus are controlled using the handshake signals:
1) Master ready &
2) Slave ready.

2
COMPUTER ORGANIZATION
INPUT-INTERFACE-CIRCUIT

Figure 4.29: Input-interface-circuit

• Output-lines of DATAIN are connected to the data-lines of bus by means of 3-state drivers (Fig 4.29).
• Drivers are turned on when
→ processor issues a read signal and
→ address selects DATAIN.
• SIN signal is generated using a status-flag circuit (Figure 4.30).
SIN signal is connected to line D0 of the processor-bus using a 3‐state driver.
• Address-decoder selects the input-interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when Master‐ready is active.
• Processor activates the Slave‐ready signal, when either the Read‐status or Read‐data is equal to 1.

3
COMPUTER ORGANIZATION
PRINTER INTERFACED TO PROCESSOR

• Keyboard is connected to a processor using a parallel-port.

• Processor uses
→ memory‐mapped I/O and
→ asynchronous bus protocol.
• On the processor-side of the interface, we have:
→ Data-lines
→ Address-lines
→ Control or R/W line
→ Master‐Ready signal and
→ Slave‐Ready signal.
• On the keyboard-side of the interface, we have:
→ Encoder-circuit which generates a code for the key pressed.
→ Debouncing-circuit which eliminates the effect of a key.
→ Data-lines which contain the code for the key.
→ Valid line changes from 0 to 1 when the key is pressed. This causes the code to be loaded
into DATAIN and SIN to be set to 1.

4
COMPUTER ORGANIZATION
GENERAL 8 BIT PARALLEL PROCESSING

Figure 4.34: General 8 bit parallel interface

• Data-lines P7 through PO can be used for either input or output purposes (Figure 4.34).
• For increased flexibility,
→ some lines can be used as inputs and
→ some lines can be used as outputs.
• The DATAOUT register is connected to data-lines via 3-state drivers that are controlled by a DDR.
• The processor can write any 8-bit pattern into DDR. (DDR  Data Direction Register).
• If DDR=1,
Then, data-line acts as an output-line;
Otherwise, data-line acts as an input-line.
• Two lines, C1 and C2 are used to control the interaction between interface-circuit and I/0 device.
Two lines, C1 and C2 are also programmable.
• Line C2 is bidirectional to provide different modes of signaling, including the handshake.
• The Ready and Accept lines are the handshake control lines on the processor-bus side.
Hence, the Ready and Accept lines can be connected to Master-ready and Slave-ready.
• The input signal My-address should be connected to the output of an address-decoder.
The address-decoder recognizes the address assigned to the interface.
• There are 3 register select lines: RS0-RS2.
Three register select lines allows up to eight registers in the interface.
• An interrupt-request INTR is also provided.
INTR should be connected to the interrupt-request line on the computer-bus.

5
COMPUTER ORGANIZATION
STANDARD I/O INTERFACE
• Consider a computer system using different interface standards.
• Let us look in to Processor bus and Peripheral Component Interconnect (PCI) bus (Figure 4.38).
• These two buses are interconnected by a circuit called Bridge.
• The bridge translates the signals and protocols of one bus into another.
• The bridge-circuit introduces a small delay in data transfer between processor and the devices.

• The 3 major standard I/O interfaces are:

1) PCI (Peripheral Component Interconnect)
2) SCSI (Small Computer System Interface)
3) USB (Universal Serial Bus)
• PCI defines an expansion bus on the motherboard.
• SCSI and USB are used for connecting additional devices both inside and outside the computer-box.
• SCSI bus is a high speed parallel bus intended for devices such as disk and video display.
• USB uses a serial transmission to suit the needs of equipment ranging from keyboard to game
control to internal connection.
• IDE (Integrated Device Electronics) disk is compatible with ISA which shows the connection to an
Ethernet.

6
COMPUTER ORGANIZATION
PCI
• PCI is developed as a low cost bus that is truly processor independent.
• PCI supports high speed disk, graphics and video devices.
• PCI has plug and play capability for connecting I/O devices.
• To connect new devices, the user simply connects the device interface board to the bus.

DATA TRANSFER IN PCI

• The data are transferred between cache and main-memory.
• The data is a sequence of words which are stored in successive memory-locations.
• During read-operation,
 When the processor specifies an address, the memory responds by sending a sequence of
data-words from successive memory-locations.
• During write-operation,
 When the processor sends an address, a sequence of data-words is written into successive
memory-locations.
• PCI supports read and write-operation.
• A read/write-operation involving a single word is treated as a burst of length one.
• PCI has 3 address-spaces. They are
1) Memory address-space
2) I/O address-space &
3) Configuration address-space.
• I/O Address-space  Intended for use with processor.
Configuration space  Intended to give PCI, its plug and play capability.
• PCI Bridge provides a separate physical connection to main-memory.
• The master maintains the address information on the bus until data-transfer is completed.
• At any time, only one device acts as Bus-Master.
• A master is called “initiator” which is either processor or DMA.
• The addressed-device that responds to read and write commands is called a Target.
• A complete transfer operation on the bus, involving an address and burst of data is called a
transaction.

• Individual word transfers are called “phases’.

7
COMPUTER ORGANIZATION

• During Clock cycle-1,

 The processor a
→ asserts FRAME# to indicate the beginning of a transaction;
→ sends the address on AD lines and command on C/BE# Lines.
• During Clock cycle-2,
 The processor removes the address and disconnects its drives from AD lines.
 Selected target
→ enables its drivers on AD lines and
→ fetches the requested-data to be placed on bus.
 Selected target
→ asserts DEVSEL# and
→ maintains it in asserted state until the end of the transaction.
 C/BE# is
→ used to send a bus command and it is
→ used for different purpose during the rest of the transaction.
• During Clock cycle-3,
 The initiator asserts IRDY# to indicate that it is ready to receive data.
 If the target has data ready to send then it asserts TRDY#. In our eg, the target sends 3
more words of data in clock cycle 4 to 6.
• During Clock cycle-5
 The indicator uses FRAME# to indicate the duration of the burst, since it read 4 words, the
initiator negates FRAME# during clock cycle 5.
• During Clock cycle-7,
 After sending 4th word, the target
→ disconnects its drivers and
→ negates DEVSEL# during clock cycle 7.

8
COMPUTER ORGANIZATION
DEVICE CONFIGURATION OF PCI
• The PCI has a configuration ROM that stores information about that device.
• The configuration ROM’s of all devices are accessible in the configuration address-space.
• The initialization software read these ROM’s whenever the system is powered up or reset.
• In each case, it determines whether the device is a printer, keyboard or disk controller.
• Devices are assigned address during initialization process.
• Each device has an input signal called IDSEL# (Initialization device select) which has 21 address-
lines (AD11 to AD31).
• During configuration operation,
 The address is applied to AD input of the device and
 The corresponding AD line is set to 1 and all other lines are set to 0.
AD11 - AD31  Upper address-line
A0 - A10  Lower address-line: Specify the type of the operation and to access the
content of device configuration ROM.
• The configuration software scans all 21 locations. PCI bus has interrupt-request lines.
• Each device may requests an address in the I/O space or memory space

SCSI Bus
• SCSI stands for Small Computer System Interface.
• SCSI refers to the standard bus which is defined by ANSI (American National Standard Institute).
• SCSI bus the several options. It may be,

Narrow bus It has 8 data-lines & transfers 1 byte at a time.

Wide bus It has 16 data-lines & transfer 2 byte at a time.
Single-Ended Transmission Each signal uses separate wire.
HVD (High Voltage Differential) It was 5v (TTL cells)
LVD (Low Voltage Differential) It uses 3.3v

• Because of these various options, SCSI connector may have 50, 68 or 80 pins. The data transfer rate
ranges from 5MB/s to 160MB/s 320Mb/s, 640MB/s. The transfer rate depends on,
1) Length of the cable
2) Number of devices connected.
• To achieve high transfer rate, the bus length should be 1.6m for SE signaling and 12m for LVD
signaling.
• The SCSI bus us connected to the processor-bus through the SCSI controller. The data are
stored on a disk in blocks called sectors.
Each sector contains several hundreds of bytes. These data will not be stored in contiguous
memory-location.
• SCSI protocol is designed to retrieve the data in the first sector or any other selected sectors.
• Using SCSI protocol, the burst of data are transferred at high speed.
• The controller connected to SCSI bus is of 2 types. They are1) Initiator * 2) Target
1) Initiator
 It has the ability to select a particular target & to send commands specifying the operation to
be performed.
 They are the controllers on the processor side.
2) Target
 The disk controller operates as a target.
 It carries out the commands it receive from the initiator.
 The initiator establishes a logical connection with the intended target.

9
COMPUTER ORGANIZATION
Steps for Read-operation
1) The SCSI controller contends for control of the bus (initiator).
2) When the initiator wins the arbitration-process, the initiator
→ selects the target controller and
→ hands over control of the bus to it.
3) The target starts an output operation. The initiator sends a command specifying the required read-
operation.
4) The target
→ sends a message to initiator indicating that it will temporarily suspend connection b/w them.
→ then releases the bus.
5) The target controller sends a command to the disk drive to move the read head to the first sector
involved in the requested read-operation.
6. The target
→ transfers the contents of the data buffer to the initiator and
→ then suspends the connection again.
7) The target controller sends a command to the disk drive to perform another seek operation.
8) As the initiator controller receives the data, it stores them into the main-memory using the DMA
approach.
9) The SCSI controller sends an interrupt to the processor indicating that the data are now available.

BUS SIGNALS OF SCSI

• The bus has no address-lines. Instead, it has data-lines to identify the bus-controllers involved in the
selection/reselection/arbitration-process.
• For narrow bus, there are 8 possible controllers numbered from 0 to 7. For a wide bus, there are 16
controllers.
• Once a connection is established b/w two controllers, there is no further need for addressing & the
data-lines are used to carry the data.

• All signal names are proceeded by minus sign.

• This indicates that the signals are active or that the data-line is equal to 1, when they are in the
low voltage state.

10
COMPUTER ORGANIZATION
PHASES IN SCSI BUS
• The phases in SCSI bus operation are:
1) Arbitration
2) Selection
3) Information transfer
4) Reselection

1) Arbitration
• When the –BSY signal is in inactive state,
→ the bus will be free &
→ any controller can request the use of bus.
• SCSI uses distributed arbitration scheme because
each controller may generate requests at the same time.
• Each controller on the bus is assigned a fixed priority.
• When –BSY becomes active, all controllers that are requesting the bus
→ examines the data-lines &
→ determine whether highest priority device is requesting bus at the same time.
• The controller using the highest numbered line realizes that it has won the arbitration-process.
• At that time, all other controllers disconnect from the bus & wait for –BSY to become inactive again.

2) Information Transfer
• The information transferred between two controllers may consist of
→ commands from the initiator to the target
→ status responses from the target to the initiator or
→ data-transferred to/from the I/0 device.
• Handshake signaling is used to control information transfers, with the target controller taking the role
of the bus-master.
3) Selection
• Here, Device
→ wins arbitration and
→ asserts –BSY and –DB6 signals.
• The Select Target Controller responds by asserting –BSY.
• This informs that the connection that it requested is established.
4) Reselection
• The connection between the two controllers has been reestablished, with the target in control of the
bus as required for data transfer to proceed.

11
COMPUTER ORGANIZATION
USB
• USB stands for Universal Serial Bus.
• USB supports 3 speed of operation. They are,
1) Low speed (1.5 Mbps)
2) Full speed (12 mbps) &
3) High speed (480 mbps).
• The USB has been designed to meet the key objectives. They are,
1) Provide a simple, low-cost and easy to use interconnection system.
This overcomes difficulties due to the limited number of I/O ports available on a computer.
2) Accommodate a wide range of data transfer characteristics for I/O devices.
For e.g. telephone and Internet connections
3) Enhance user convenience through a “plug-and-play” mode of operation.
• Advantage: USB helps to add many devices to a computer system at any time without opening the
computer-box.
Port Limitation
 Normally, the system has a few limited ports.
 To add new ports, the user must open the computer-box to gain access to the internal
expansion bus & install a new interface card.
 The user may also need to know to configure the device & the s/w.
Plug & Play
 The main objective: USB provides a plug & play capability.
 The plug & play feature enhances the connection of new device at any time, while the system
is operation.
 The system should
→ Detect the existence of the new device automatically.
→ Identify the appropriate device driver s/w.
→ Establish the appropriate addresses.
→ Establish the logical connection for communication.

DEVICE CHARACTERISTICS OF USB

• The kinds of devices that may be connected to a computer cover a wide range of functionality.
• The speed, volume & timing constrains associated with data transfer to & from devices varies
significantly.
Eg: 1 Keyboard
 Since the event of pressing a key is not synchronized to any other event in a computer
system, the data generated by keyboard are called asynchronous.
The data generated from keyboard depends upon the speed of the human operator which is
about 100 bytes/sec.
Eg: 2 Microphone attached in a computer system internally/externally
 The sound picked up by the microphone produces an analog electric signal, which must be
converted into digital form before it can be handled by the computer.
 This is accomplished by sampling the analog signal periodically.
 The sampling process yields a continuous stream of digitized samples that arrive at regular
intervals, synchronized with the sampling clock. Such a stream is called isochronous (i.e.)
successive events are separated by equal period of time.
 If the sampling rate in „S‟ samples/sec then the maximum frequency captured by sampling
process is s/2.
 A standard rate for digital sound is 44.1 KHz.

12
COMPUTER ORGANIZATION
USB ARCHITECTURE
• To accommodate a large number of devices that can be added or removed at any time, the USB has
the tree structure as shown in the figure 7.17.
• Each node of the tree has a device called a Hub.
• A hub acts as an intermediate control point between the host and the I/O devices.
• At the root of the tree, a Root Hub connects the entire tree to the host computer.
• The leaves of the tree are the I/O devices being served (for example, keyboard or speaker).
• A hub copies a message that it receives from its upstream connection to all its downstream ports.
• As a result, a message sent by the host computer is broadcast to all I/O devices, but only the
addressed-device will respond to that message.

13
COMPUTER ORGANIZATION
USB ADDRESSING
• Each device may be a hub or an I/O device.
• Each device on the USB is assigned a 7‐bit address.
• This address
→ is local to the USB tree and
→ is not related in any way to the addresses used on the processor-bus.
• A hub may have any number of devices or other hubs connected to it, and addresses are assigned
arbitrarily.
• When a device is first connected to a hub, or when it is powered-on, it has the address 0.
• The hardware of the hub detects the device that has been connected, and it records this fact as part
of its own status information.
• Periodically, the host polls each hub to
→ collect status information and
→ learn about new devices that may have been added or disconnected.
• When the host is informed that a new device has been connected, it uses sequence of commands to
→ send a reset signal on the corresponding hub port.
→ read information from the device about its capabilities.
→ send configuration information to the device, and
→ assign the device a unique USB address.
• Once this sequence is completed, the device
→ begins normal operation and
→ responds only to the new address.

USB PROTOCOLS
• All information transferred over the USB is organized in packets.
• A packet consists of one or more bytes of information.
• There are many types of packets that perform a variety of control functions.
• The information transferred on USB is divided into 2 broad categories: 1) Control and 2) Data.
• Control packets perform tasks such as
→ addressing a device to initiate data transfer.
→ acknowledging that data have been received correctly or
→ indicating an error.
• Data-packets carry information that is delivered to a device.
• A packet consists of one or more fields containing different kinds of information.
• The first field of any packet is called the Packet Identifier (PID) which identifies type of that
packet.
• They are transmitted twice.
1) The first time they are sent with their true values and
2) The second time with each bit complemented.
• The four PID bits identify one of 16 different packet types.
• Some control packets, such as ACK (Acknowledge), consist only of the PID byte.
• Control packets used for controlling data transfer operations are called Token Packets.

14
COMPUTER ORGANIZATION
Problem 1:
The input status bit in an interface-circuit is cleared as soon as the input data register is read. Why is
this important?
Solution:
After reading the input data, it is necessary to clear the input status flag before the program
begins a new read-operation. Otherwise, the same input data would be read a second time.

Problem 2:
What is the difference between a subroutine and an interrupt-service routine?
Solution:
A subroutine is called by a program instruction to perform a function needed by the calling
program.
An interrupt-service routine is initiated by an event such as an input operation or a hardware
error. The function it performs may not be at all related to the program being executed at the
time of interruption. Hence, it must not affect any of the data or status information relating to
that program.

Problem 3:
Three devices A, B, & C are connected to the bus of a computer. I/O transfers for all 3 devices use
interrupt control. Interrupt nesting for devices A & B is not allowed, but interrupt-requests from C may
be accepted while either A or B is being serviced. Suggest different ways in which this can be
accomplished in each of the following cases:
(a) The computer has one interrupt-request line.
(b) Two interrupt-request lines INTR1 & INTR2 are available, with INTR1 having higher priority.
Specify when and how interrupts are enabled and disabled in each case.
Solution:
(a) Interrupts should be enabled, except when C is being serviced. The nesting rules can be
enforced by manipulating the interrupt-enable flags in the interfaces of A and B.
(b) A and B should be connected to INTR , and C to INTR. When an interrupt-request is received
from either A or B, interrupts from the other device will be automatically disabled until the request
has been serviced. However, interrupt-requests from C will always be accepted.

Problem 4:
Consider a computer in which several devices are connected to a common interrupt-request line. Explain
how you would arrange for interrupts from device j to be accepted before the execution of the interrupt
service routine for device i is completed. Comment in particular on the times at which interrupts must
be enabled and disabled at various points in the system.
Solution:
Interrupts are disabled before the interrupt-service routine is entered. Once device i turns off its
interrupt-request, interrupts may be safely enabled in the processor. If the interface-circuit of
device i turns off its interrupt-request when it receives the interrupt acknowledge signal,
interrupts may be enabled at the beginning of the interrupt-service routine of device i. Otherwise,
interrupts may be enabled only after the instruction that causes device i to turn off its interrupt-
request has been executed.

Problem 5:
Consider the daisy chain arrangement. Assume that after a device generates an interrupt-request, it
turns off that request as soon as it receives the interrupt acknowledge signal. Is it still necessary to
disable interrupts in the processor before entering the interrupt service routine? Why?
Solution:
Yes, because other devices may keep the interrupt-request line asserted.

15
3. What•do•you•mean•by•Asynchronous•data•transfer?•Explain•
Strobe•control•in•detail.•
Asynchronous•data•transfer•
Data transfer between two independent units, where internal timing in each unit is independent
from the other. Such two units are said to be asynchronous to each other.

Strobe•Control•
· The Strobe control method of asynchronous data transfer employs a single control line to
time each transfer.

Source-initiated•strobe•for•data•transfer•
· The strobe may be activated by either the source or the destination unit. Figure 8.3
shows a source-initiated transfer.
· The data bus carries the binary information from source unit to the destination unit.
· The strobe is a single line that informs the destination unit when a valid data word is
available in the bus.
· The source unit first places the data on the data bus.
· After a delay to ensure that the data settle to a steady value, the source activates the
strobe pulse.
· The information on the data bus and the strobe signal remain in the active state for a
sufficient time period to allow the destination unit to receive the data.
· The source removes the data from the bus a brief period after it disables its strobe pulse.

4
 Figure 8.3: Source-initiated strobe for data transfer Figure 8.4: Destination-initiated strobe for data
transfer

Destination-initiated•strobe•for•data•transfer•
· Figure 8.4 shows a data transfer initiated by the destination unit. In this case the
destination unit activates the strobe pulse, informing the source to provide the data.
· The source unit responds by placing the requested binary information on the data bus.
· The data must be valid and remain in the bus long enough for the destination unit to
accept it.
· The falling edge of the strobe pulse can be used again to trigger a destination register.
· The destination unit then disables the strobe. The source removes the data from the bus
after a predetermined time interval.
· The transfer of data between the CPU and an interface unit is similar to the strobe
transfer just described.
Disadvantage•of•Strobe•method:•
· The disadvantage of the strobe method is that the source unit that initiates the transfer
has no way of knowing whether the destination unit has actually received the data item
that was placed in the bus
· Similarly, a destination unit that initiates the transfer has no way of knowing whether the
source unit has actually placed the data on the bus.

5
4. Explain•Asynchronous•data•transfer•with•Handshaking•method.•
· The handshake method solves the problem of Strobe method by introducing a second
control signal that provides a reply to the unit that initiates the transfer.

Source-initiated•transfer•using•handshaking•
· One control line is in the same direction as the data flow in the bus from the source to
the destination.
· It is used by the source unit to inform the destination unit whether there are valid data in
the bus.

Figure 8.5: Source-initiated transfer using handshaking

· The other control line is in the other direction from the destination to the source.
· It is used by the destination unit to inform the source whether it can accept data.
· The sequence of control during the transfer depends on the unit that initiates the
transfer.
· Figure 8.5 shows the data transfer procedure initiated by the source.
· The two handshaking lines the data valid, which is generated by the source unit, and
data accepted, generated by the destination unit, the timing diagram shows the
exchange of signals between the two units.
· The sequence of events listed in figure 8.5 shows the four possible states that the system
can be at any given time.
· The source unit initiates the transfer by placing the data on the bus and enabling its data
valid signal.

6
 · The data accepted signal is activated by the destination unit after it accepts the data
from the bus.
· The source unit then disables its data valid signal, which invalidates the data on the bus.
· The destination unit then disables its data accepted signal and the system goes into its
initial state.
· The source does not send the next data item until after the destination unit shows its
readiness to accept new data by disabling its data accepted signal.
· This scheme allows arbitrary delays from one state to the next and permits each unit to
respond at its own data transfer rate.
Destination-initiated•transfer•using•handshaking•
· The destination-initiated transfer using handshaking lines is shown in figure 8.6.
· Note that the name of the signal generated by the destination unit has been changed to
ready for data to reflect its new meaning.
· The source unit in this case does not place data on the bus until after it receives the
ready for data signal from the destination unit.
· From there on, the handshaking procedure follows the same pattern as in the source-
initiated case.
· Note that the sequence of events in both cases would be identical if we consider the
ready for data signal as the complement of data accepted.
· In fact, the only difference between the source-initiated and the destination-initiated
transfer is in their choice of initial state.

Figure 8.6: Destination-initiated transfer using handshaking

7
 MODES OF TRANSFER

WHY ARE THEY USED?

➢ CPU merely executes instruction and accepts data temporally from

I/O devices.
➢ Ultimate source and destination is memory.
➢ Data transfer is handled in a variety of modes.

WHAT ARE THE DIFFERENT MODES?

• Data transfer can be handled in one of Three Modes:

➢ Programmed I/O
➢ Interrupt-Initiated I/O
➢ Direct Memory Access (DMA)

PROGRAMMED I/O:
➢ Each data item transfer is initiated by an I/O instruction written in a
computer program.
➢ Transferring data under program control requires constant monitoring of
the peripheral by CPU.
➢ In this method, the CPU stays in a program loop until I/O unit is ready for
data transfer.
➢ This time-consuming process keeps the processor needlessly busy.

An example of data transfer from an I/O device through an interface into a

CPU in given below:
INTERRUPT-INITIATED I/O
➢ Instead of continuous monitoring of CPU, interface will be
informed to issue an interrupt request signal.
➢ Meanwhile, CPU proceeds to execute another program and the
interface keeps monitoring the device.
➢ When device is ready for data transfer, it generates interrupt
request.
➢ Here the CPU stops the task it is performing, processes the data
transfer then resumes the original task.
Priority Interrupt
In a typical application, a number of I/O devices are attached to computer, with
each device being able to originate an interrupt request, so to provide services to
device which initiate interrupt request, the task of interrupt system is to identify
the source(device) of interrupt and then provide services to them.

Priority Interrupt are systems, that establishes a Priority over the various
sources(interrupt devices) to determine which condition is to be serviced first
when two or more requests arrive simultaneously.This system may also
determine which condition are permitted to interrupt to the computer while
another interrupt is being serviced.

Usually, in Priority Systems, higher-priority interrupt levels are served first, as if

they delayed or interrupted, could have serious consequences.And the devices
with high-speed transfer such as magnetic disks are given high-priority, and slow
devices such as keyboards receives low-priority.

1. Polling:

Polling is the software method of establishing priority of simultaneous

interrupt.In this method, when the processor detects an interrupt, it
branches to an interrupt service routine whose job is to pull each I/O module
to determine which module caused the interrupt.

The poll could be in the form of separate command line(e.g., Test I/O).In this
case, the processor raises the Test I/O and places the address of particular I/O
module on the address line.If it has interrupt that is, if interrupt is identified in it.

And, it is the order in which they are tested i.e., the order in which they appear
on address line(Service Routine) determine the priority of each interrupt.As while
testing, highest priority source(devices) are tested first then lower-priority
devices.
 This is very simple method of establishing priority on simultaneous
interrupt.But the disadvantage of polling is that it is very time consuming.

2. Daisy-Chaining Priority:

The Daisy–Chaining method of establishing priority on interrupt sources uses

the hardware i.e., it is the hardware means of establishing priority.

In this method, all the device, whether they are interrupt sources or not,
connected in a serial manner.Means the device with highest priority is placed in
the first position, which is followed by lowest priority device.And all device share
a common interrupt request line, and the interrupt acknowledge line is daisy
chained through the modules.

The figure shown below, this method of connection with three devices and the
CPU.
 VECTORED INTERRUPTS
• A device requesting an interrupt identifies itself by sending a special-code to
processor over bus.
• Then, the processor starts executing the ISR.
• The special-code indicates starting-address of ISR.
• The special-code length ranges from 4 to 8 bits.
• The location pointed to by the interrupting-device is used to store the staring
address to ISR.
• The staring address to ISR is called the interrupt vector.
• Processor
→ loads interrupt-
vector into PC & →
executes
appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTA
line.
• Then, I/O-device responds by sending its interrupt-vector code & turning off
the INTR signal.
• The interrupt vector also includes a new value for the Processor Status
Register.

Priority Encoder
The priority encoder is a circuit that executes the priority function. The logic of the
priority encoder is such that two or more inputs appear at an equal time, the input
having the largest priority will take precedence. The truth table of a four-input
priority encoder is given in the table. The X’s in the table designate don’t care
conditions. Input I0 has the largest priority, so indifferent of the values of other
inputs when this is input is 1, the output creates an output xy=00.
I1 has the next priority level. The output is 01 if I1=1 supported that I0=0, regardless
of the values of the other two lower-priority inputs. The output for I2 is generated
only if higher-priority inputs are 0, etc. down the priority level. The interrupt status
IST is set only when one or more inputs are equal to 1.
Priority Encoder for the truth table:

If all inputs are 0, IST is cleared to 0 and the other outputs of the encoder are not
used, so they are signified with don’t care condition. This is because the vector
address is not shared with the CPU when IST=0. The Boolean function showed in
the table determines the internal logic of the encoder. Generally, a computer will
have more than four interrupt sources. A priority encoder with eight inputs, for
example, will create an output of three bits.
The output of the priority encoder can form part of the vector address for each
interrupt source. The other bits of the vector address can be created any value. For
instance, the vector address can be formed by joining six zeroes to the x and y
outputs of the encoder. With this choice, the interrupt vector for the four I/O
devices is created binary numbers 0, 1, 2, and 3.

Parallel Priority Interrupt

• The parallel priority interrupt method uses a register whose bits are set
separately by the interrupt signal from each device.
• Priority is established according to the position of the bits in the register.
• In addition to the interrupt register, the circuit may include a mask register
whose purpose is to control the status of each interrupt request.

• The mask register can be programmed to disable lower-priority interrupts

while a higher-priority device is being serviced.
• It can also provide a facility that allows a high-priority device to interrupt the
CPU while a lower-priority device is being serviced.
• The priority logic for a system of four interrupt sources is shown in Fig. 14.
• It consists of an interrupt register whose individual bits are set by external
conditions and cleared by program instructions.
• The magnetic
disk, being a high-
speed device, is
given the highest
priority. The
printer has the
next priority,
followed by a
character reader
and a keyboard.
• The mask
register has the
same number of
bits as the
interrupt register.
By means of
program
instructions, it is
possible to set or
reset any bit in the
mask register.
• Each interrupt
bit and its
corresponding
mask bit are
applied to an AND
gate to produce the four inputs to a priority encoder.
• In this way an interrupt is recognized only if its corresponding mask bit is set
to 1 by the program. The priority encoder generates two bits of the vector
address, which is transferred to the CPU.
• Another output from the encoder sets an interrupt status flip-flop lST when
an interrupt that is not masked occurs. The interrupt enable flip-flop lEN can
be set or cleared by the program to provide an overall control over the
interrupt system.
 • The outputs of IST ANDed with IEN provide a common interrupt signal for
the CPU.

Interrupt Cycle
The interrupt enable flip-flop lEN shown in Fig. 1 1-14 can be set or cleared by
program instructions. When lEN is cleared, the interrupt request coming from
IST is neglected by the CPU. The program-controlled lEN bit allows the programmer
to choose whether to use the interrupt facility. If an instruction to
clear lEN has been inserted in the program, it means that the user does not
want his program to be interrupted. An instruction to set lEN indicates that
the interrupt facility will be used while the current program is running. Most
computers include internal hardware that clears lEN to 0 every time an interrupt
is acknowledged by the processor.
At the end of each instruction cycle the CPU checks lEN and the interrupt
signal from !ST. If either is equal to 0, control continues with the next instruction.
If both lEN and IST are equal to 1, the CPU goes to an interrupt cycle.
During the interrupt cycle the CPU performs the following sequence of
microoperations:

SP +- SP - 1
M[SP] +-PC
Decrement stack pointer
Push PC into stack
INTACK <--1
PC <- VAD
lEN <--0
SECTION 1 1 ·5 Priority Interrupt 413
Enable interrupt acknowledge
Transfer vector address to PC
Disable further interrupts

Go to fetch next instruction

The CPU pushes the return address from PC into the stack. It then acknowledges
the interrupt by enabling the INTACK line. The priority interrupt unit
responds by placing a unique interrupt vector into the CPU data bus. The CPU
transfers the vector address into PC and clears lEN prior to going to the next
fetch phase. The
instruction read from
memory during the next
fetch phase will
be the one located at
the vector address.

Software Routines
A priority interrupt
system is a combination
of hardware and
software techniques.
So far we have
discussed the hardware
aspects of a priority
interrupt
system. The computer
must also have software
routines for servicing
the
interrupt requests and for controlling the interrupt hardware registers.
Figure 1 1-15 shows the programs that must reside in memory for handling the
interrupt system. Each device has its own service program that can be reached
through a jump GMP) instruction stored at the assigned vector address. The
symbolic name of each routine represents the starting address of the service
program. The stack shown in the diagram is used for storing the return address
after each interrupt.

To illustrate with a specific example assume that the keyboard sets its
interrupt bit while the CPU is executing the instruction in location 749 of the
main program. At the end of the instruction cycle, the computer goes to an
interrupt cycle. It stores the return address 750 in the stack and then accepts
the vector address 0000001 1 from the bus and transfers it to PC . The instruction
in location 3 is executed next, resulting in transfer of control to the KBD routine.
Now suppose that the disk sets its interrupt bit when the CPU is executing the
instruction at address 255 in the KBD program. Address 256 is pushed into the
stack and control is transferred to the DISK service program. The last instruction
in each routine is a return from interrupt instruction. When the disk
service program is completed, the return instruction pops the stack and places
256 into PC . This returns control to the KBD routine to continue servicing the
keyboard. At the end of the KBD program, the last instruction pops the stack
and returns control to the main program at address 750. Thus, a higher-priority
device can interrupt a lower-priority device. It is assumed that the time spent
in servicing the high-priority interrupt is short compared to the transfer rate
of the low-priority device so that no loss of information takes place.
Interrupt priority
- It is possible that several interrupts would be pending at the same time

- The CPU cannot serve more than one interrupt at the same time.

- CPU has to decide which interrupt to serve first –> the interrupts should be prioritized.

- The ISR of the highest priority interrupt is executed first

- The interrupt that has higher vector address has higher priority, e.g., /IRQ has the higher priority
than timer channel 0.

- However, we can raise one of the maskable interrupts to the highest level so that it can get quicker
service.

Fig : priority Interrupt hardware

A complete Interrupt priority service cycle

1. When an event occurs, a flag bit should be set to interrupt the CPU.

2. This interrupt request is served if:-

(1) I bit and local interrupt enable bit are enabled in case of maskable interrupts

(2) It is the only interrupt or the highest priority interrupt if there are several interrupts pending for
service

3. To serve the interrupt, the CPU automatically pushes all the registers (except SP) on the stack (9
bytes total). This includes the return address stored in PC and CCR register do not mess up stack!

5. The CPU prevents further interrupts from occurring till the ISR is done by setting the I bit. Nested
interrupts are not allowed.

6. Resolve the interrupt vector and transfer control to the interrupt service routine (ISR). PC = the ISR
starting address

7. Cancel the interrupt request by clearing the interrupt flag. Without this step the interrupt will be
executed over and over again and the main program would never execute again

8- Execute the ISR instructions. Use all the CPU registers without fear of interfering with the main
program, but for memory locations, it is the programmer’s responsibility to ensure that the ISR does
not change memory locations used by the main program

9. The last instruction in an ISR is always “RTI” (return from interrupt) - RTI retrieves the registers’
original values before executing the interrupt from the stack. Enable I bit and return back to the
main program

Parallel Priority Interrupt

The parallel priority interrupt method uses a register whose bits are set separately by the interrupt
signal from each device. Priority is established according to the interrupt register, the circuit may
include a mask register whose purpose is to control the status of each interrupt request. The mask
register can be programmed to disable lower priority interrupts while higher priority is being served.
It can also provide facility that allows higher priority device to interrupt the CPU while lower priority
is being served.

Another output from the encoder sets interrupt status flip flop IST when an interrupt that is not
masked occurs. The interrupt enable flip flop IEN can be set or cleared by the program to provide an
overall control over the interrupt system. The outputs of IST and with IEN provide a common
interrupt signal for CPU.
One stage of daisy chain priority arrangement
 Unit 4 - part 2
Parallel processing
Parallel processing is a term used to denote a large class of techniques that are used to provide
simultaneous data-processing tasks for the purpose of increasing the computational speed of a
computer system

classification introduced by M. J. Flynn considers the organization of a computer

system by the number of instructions and data items
• Single instruction stream, single data stream (SISD)
-may not be a parallel processing computer
• Single instruction stream, multiple data stream (SIMD)
-represents an organization that includes many processing units under the supervision of a
common control unit.
• Multiple instruction stream, single data stream (MISD)
-theoritical
• Multiple instruction stream, multiple data stream (MIMD)
-MIMD organization refers to a computer system capable of processing several programs at
the same time
Pipelining
Pipelining is a technique of decomposing a sequential process into suboperations, with each
subprocess being executed in a special dedicated segment that operates concurrently with all other
segments

The name "pipeline" implies a flow of information analogous to an industrial assembly line
Arithmetic Pipeline
example of a pipeline unit for floating-point addition and subtraction.Steps-

1. Compare the exponents.

2. Align the mantissas.

3. Add or subtract the mantissas.

4. Normalize the result.

Data

Step 2-

Step 3-

Step 4-
Instruction pipeline
An instruction pipeline reads consecutive instructions from memory while previous instructions are
being executed in other segments

1. Fetch the instruction from memory.

2. Decode the instruction & calculate the effective address.

3. Fetch the operands from memory.

4. Execute the instruction & store the result in the proper place.

Example: Four-Segment Instruction Pipeline

an instruction is being executed in segment 4

next instruction in sequence is busy fetching an operand from memory in segment 3

Thus up to four suboperations in the instruction cycle can overlap and up to four different
instructions can be in progress of being processed at the same time.

Assume now that instruction 3 is a branch instruction. As soon as this instruction is decoded in
segment DA in step 4, the transfer from FI to DA of the other instructions is halted until the branch
instruction is executed in step 6. If the branch is taken, a new instruction is fetched in step 7. If the
branch is not taken, the instruction fetched previously in step 4 can be used. The pipeline then
continues until a new branch instruction is encountered.

pipeline conflicts
1. Resource conflicts caused by access to memory by two segments at the same time. Most of these
conflicts can be resolved by using separate instruction and data memories.

2. Data dependency conflicts arise when an instruction depends on the result of a previous
instruction, but this result is not yet available.

3. Branch difficulties arise from branch and other instructions that change the value of PC.
Data Dependency
A data dependency occurs when an instruction needs data that are not yet available.

• hardware interlocks- An interlock is a circuit that detects instructions whose source

operands are destinations of instructions farther up in the pipeline. Detection of this
situation causes the instruction whose source is not available to be delayed by enough clock
cycles to resolve the conflict.
• operand forwarding- operand forwarding uses special hardware to detect a conflict and then
avoid it by routing the data through special paths between pipeline segments.

Handling of Branch Instructions

A branch instruction can be conditional or unconditional. An unconditional branch always alters the
sequential program flow by loading the program counter with the target address. In a conditional
branch, the control selects the target instruction if the condition is satisfied or the next sequential
instruction if the condition is not satisfied.

• prefetch target instruction- One way of handling a conditional branch is to prefetch the
target instruction in addition to the instruction following the branch. Both are saved until
the branch is executed.
• branch target buffer- Another possibility is the use of a branch target buffer or BTB. The BTB
is an associative memory included in the fetch segment of the pipeline. Each entry in the
BTB consists of the address of a previously executed branch instruction and the target
instruction for that branch.
• loop buffer- A variation of the BTB is the loop buffer. This is a small very high speed register
file maintained by the instruction fetch segment of the pipeline. When a program loop is
detected in the program, it is stored in the loop buffer in its entirety, including all branches.
The program loop can be executed directly without having to access memory until the loop
mode is removed by the final branching out.
• branch prediction- A pipeline with branch prediction uses some additional logic to guess the
outcome of a conditional branch instruction before it is executed. The pipeline then begins
prefetching the instruction stream from the predicted path.
• delayed branch- A procedure employed in most ruse processors is the delayed branch . In
this procedure, the compiler detects the branch instructions and rearranges the machine
language code sequence by inserting useful instructions that keep the pipeline operating
without interruptions.
RISC Pipeline
The simplicity of the instruction set can be utilized to 3 16 CHAPTER NINE Pipeline and Vector
Processing single-cycle instruction execution compiler support implement an instruction pipeline
using a small number of suboperations, with each being executed in one clock cycle.

The instruction pipeline can be implemented with two or three segments. One segment fetches the
instruction from program memory, and the other segment executes the instruction in the ALU. A
third segment may be used to store the result of the ALU operation in a destination register.

Example: Three-Segment Instruction Pipeline

The ALU is used for three different functions, depending on the decoded instruction. It performs an
operation for a data manipulation instruction, it evaluates the effective address for a load or store
instruction, or it calculates the branch address for a program control instruction.

Delayed Load

If the three-segment pipeline proceeds without interruptions, there will be a data conflict in
instruction 3 because the operand in R2 is not yet available in the A segment.