Introduction

• Sequential logic circuits are those, whose output depends on both present and past
values of their inputs.
• Sequential circuits act as storage elements and have memory.
• They can store, retain, and then retrieve information when needed at a later time.
• It can be considered as combinational circuit with feedback.
• It uses a memory element like flip – flops as feedback circuit in order to store past
values. The block diagram of a sequential logic is shown below.
• The block diagram consists of a combinational circuit to which storage elements
are connected to form a feedback path.
• The storage elements are devices capable of storing binary information.
• The binary information stored in these elements at any given time defines the
“State” of the sequential circuit at that time.
• The external inputs also determine the condition for changing the state in the
storage elements.
• The output in a sequential circuit are a function of the inputs and present state of
the storage elements.
• The next state of the storage elements is also a function of external inputs and
the present state.
• Thus, a Sequential circuit is specified by a time sequence of inputs, outputs, and
internal states.
Combinational Circuits vs Sequential Circuits
 Classification of Sequential Circuits
• Based on the clock signal input, the sequential circuits are classified into two
types.
• Synchronous sequential circuit
• Asynchronous sequential circuit
 Synchronous sequential circuit
• It is a system whose behaviour can be defined from the knowledge of its signals at
discrete instants of time.
• Synchronization is achieved by a timing device called a clock generator, producing
clock pulses.
• The output depends on present and previous states of the inputs at the clocked
instances.
• The circuits use a memory element to store the previous state. The memory elements
in these circuits will have clocks. All these clock signals are driven by the same clock
signal.
• Using clock signal, state changes will occur across all storage elements.
• These circuits are bit slower compared to asynchronous because they wait for the
next clock pulse to arrive to perform the next operation.
• These circuits can be clocked or pulsed.
• The storage elements used in clocked sequential circuits are called as flip-flops.
• A flip-flop is a binary storage device capable of storing one bit of information.
• The Synchronous sequential circuits that use clock pulses in their inputs are called
clocked-sequential circuits. They are very stable.
• The sequential circuits that change their state using the pulse and these are
called pulsed or un-clocked sequential circuits.
• Applications of Synchronous Sequential circuits:
• Used in the design of MOORE-MEALY state machines.
• They are used in synchronous counters, flip flops etc.

• Limitations of Synchronous Sequential Circuits

• All the flip – flops in synchronous sequential circuits must be connected to clock
signal. Clock signals are very high frequency signals and clock distribution
consumes and dissipates a large amount of heat.
• Critical path or the slowest path determines the maximum possible clock
frequency. Hence they are slower than asynchronous circuits.
 Asynchronous Sequential Circuits
• The Sequential circuits which do not operate by clock signals are called
“Asynchronous sequential circuits”.
• The behaviour of the circuit depends upon the input signals at any instant of time
and the order in which the inputs change.
• The storage elements used are time delay devices. (latches)
• They do not operate in pulse mode.
• They have better performance but hard to design due to timing problems.
• Mostly we use the asynchronous circuits when we require the low power
operations.
• They are faster than synchronous sequential circuits as they do not need to wait
for any clock signal.
• Applications of Asynchronous Sequential Circuits
• These are used when speed of operation is important. As they are independent
of internal clock pulse, they operate quickly. So they are used in Quick response
circuits.
• Used in the communication between two units having their own independent
clocks.
• Used when we require the better external input handling.

• Limitations of Asynchronous Sequential Circuits

• Asynchronous sequential circuits are more difficult to design.
• Though they have a faster performance, their output is uncertain.
 Clock Signal in Sequential Circuits
• A clock is a signal, which oscillates between logic level 0 and logic level 1,
repeatedly.
• Square wave with constant frequency is the most common form of clock signal.
• A clock signal has “edges”. These are the instants at which the clock changes from
0 to 1 (a positive edge) or from 1 to 0 (a negative edge).

• Clock signals control the outputs of the sequential circuit. It determines when and
how the memory elements change their outputs .
 Triggering
• The change in output of a flip flop can be done by bringing a small change in the
input signal. This small change can be done with the help of a clock pulse. This
clock pulse is known as a Trigger pulse.
• A flip – flop is said to be “Triggered”, when a trigger pulse is applied to the input
that brings changes in the output.
• Flip – flops are basic components in registers and counters, which store data in
the form of multi – bit numbers.
• Number of flip – flops are connected to form a sequential circuit and all these flip
– flops require trigger pulse.
• The number of trigger pulses applied to the input determines the number in a
counter.
• There are two type of triggering: Level Triggering and Edge Triggering
 Level Triggering
• The triggering process in which the change in the output state is according to the
active level of inputs is called “Level Triggering”.
• Level triggering is of two types - High level and Low level triggering.
• In High Level Triggering, the output of the flip – flop changes only when its enable
input is at a high state i.e. logic high or logic 1.
• In Low Level Triggering, the output of the flip – flop changes only when its enable
input is at a low state i.e. logic low or logic 0.
 Edge triggering
• In Edge Triggering, the output changes only when the inputs are present at either
of the transitions of the clock pulse i.e. either from low to high (0 to 1) or from
high to low (1 to 0).
• Edge triggering is of two types - Positive and Negative edge triggering.
• In Positive Edge Triggering, the output changes only when the input is at the
positive edge of the clock pulse input i.e. a transition from low to high (0 to 1).
• In Negative Edge Triggering, the output changes only when the input is at the
negative edge of the clock pulse input i.e. a transition from high to low (1 to 0).
 Storage Elements
• A storage element in a digital circuit can maintain a binary state indefinitely, until
directed by an input signal to switch states.

• Storage elements that operate with signal levels are referred to as latches.

• Storage elements controlled by a clock transition are referred to as flip flops.

• Latches are said to be level sensitive devices

• Flip flops are edge sensitive devices.

• Latches are the basic building blocks for the construction of flip flops.

• Latches are useful for storing binary information and for the design of asynchronous
circuits.
 Latches

• Latch is an electronic logic circuit with two stable states i.e. it is a bistable
multivibrator.

• Latch has a feedback path to retain the information. Hence a latch can be a
memory device.

• Latch can store one bit of information as long as the device is powered on.

• When enable is asserted, latch immediately changes the stored information when
the input is changed i.e. they are level triggered devices.
 Latches

• It continuously samples the inputs when the enable signal is on.

• Latch circuits can work in two states depending on the triggering signal being high
or low: Active – High or Active – Low.

• In case of Active – High latch circuits, normally both the inputs are low. The circuit
is triggered by a momentary high on either of the inputs.

• In case of Active – Low latch circuits, normally both the inputs are high. The
circuit is triggered by a momentary low on either of the inputs.
 SR Latch
• SR (Set-Reset) Latch – SR Latch is a circuit with:
(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
(ii) 2 input S for SET and R for RESET.
(iii) 2 output Q, Q’.
SR Latch with NOR gates
SR Latch with NAND gates
 SR latch with NOR gates
• Under normal conditions, both the input remains 0.
Truth table of NOR gate:
• Case (i): R = 0, S = 1, Q=? and Q’ =?

If any one of the input is 1, NOR gate output is 0. So, R = 0, S = 1, Q =1 And Q’ = 0

If the input S = 1 is removed, then S = 0, R = 0, Q =1 and Q’ = 0.

No change in the output. It acts as a memory element.

• Case (ii): R = 1, S = 0, Q=? and Q’ =?

If any one of the input is 1, NOR gate output is 0. So, R = 1, S = 0, Q =0 And Q’ = 1

If the input R = 1 is removed, then R = 0, S = 0, Q = 0 and Q’ = 1.

No change in the output. It acts as a memory element.

• Case (iii): R = 1, S = 1, Q=? and Q’ =?
S R Q Q’
0 0 Memory Element
RESET 0 1 0 1

SET 1 0 1 0
1 1 Not Used

If any one of the input is 1, NOR gate output is 0. So, R = 1, S = 1, Q = 0 And Q’ = 0 (Not valid- Undefined state)

If both the inputs are removed, then R = 0, S = 0, Q = 0 and Q’ = 0.

Both the outputs are not complementing each other. This condition is not used in latches.
 SR latch using NAND gates
• It operates with both inputs normally at 1.

S’ R’ Q Q’
0 0 Not Used
0 1 1 0
1 0 0 1
1 1 Memory Element

Note: In comparing the NAND with the NOR latch, the input signals for the NAND
require the complement of those values used for the NOR latch.
 GATED S-R LATCH
• Generally, latches are transparent i.e. the output changes immediately when there is a change in
the input.

• But for many applications, it is desirable to have an isolated period where the output doesn’t
change even when there is a change in the input. During this period, the outputs are said to be
truly ‘latched’.

• This can be achieved with the use of an extra input (enable or clock or gate). If the enable (or
clock or gate) signal is not asserted, the inputs are ignored and the outputs are latched to the
previous values.

• In order to use this extra signal, additional logic should be added. These circuits are called Gated
or Clocked Latches.
• Gated SR latch can be made in two ways: by adding second level of AND gates to SR latch or by
adding second level of NAND gates to S’R’ latch (Inverted SR latch).
Gated SR latch constructed from NOR gates
Gated SR latch constructed from NAND gates
• The output S* and R* can be written as

• S* = (S.E)’ = S’ + E’ and R* = (R.E)’ = R’ + E’

• When E = 0, S* and R* becomes 1 and is dependent only on enable signal

irrespective of the inputs. So, there is no change in the output. This is the
quiescent condition for the SR latch.

• When E = 1, input from S or R affects the output of latch.

• When all the inputs are 1, output is in indeterminate state.

• This indeterminate state makes it difficult to use in practical case, but can be used
for constructing other flip flops.
 Truth Table

E S R Next state of Q
0 X X No change
1 0 0 No change
1 0 1 Q = 0; RESET
1 1 0 Q = 1; SET
1 1 1 Indeterminate
 D Latch ( Transparent Latch)
• One way to eliminate the undesirable condition of the indeterminate state in the
SR latch is to ensure that S and R are never equal to 1 at the same time.
• This is done in the D latch.
• This latch has only two inputs: D (data) and E (Enable).
• The D input goes directly to the S input, and its complement is applied to the R
input.
• When E = 0, the input to SR latch is 1 level and the circuit cannot change
regardless of the value of D.
• When E= 1, and D = 1, the Q output goes to 1 (SET)
• When E= 1, and D = 0, the Q output goes to 0 (RESET), hence named as
transparent latch.
• Function table:
E D Next state of Q
0 X No change
1 0 Q = 0, RESET
1 1 Q = 1, SET
SR Flip Flop
Truth table of SR latch

S* R* Q Q’
0 0 Not Used
0 1 1 0
1 0 0 1
1 1 Memory Element
• The output S* and R* can be written as
• S* = (S.Clk)’ = S’ + Clk’ and R* = (R.Clk)’ = R’ + Clk’
• When Clk = 0, S* = 1 , R* = 1, then SR FF acts like memory element.
• When Clk = 1, S*= S’ , R* = R’

• Function Table:
Clk S R Q Q’
0 X X Memory Element
1 0 0 Memory Element
1 0 1 0 1
1 1 0 1 0
1 1 1 Not Used
 Truth Table: Characteristic Table: Clk = 1
Q(t) S R Q(t+1)
Clk S R Q(t+1)
0 0 0 0
0 X X Q(t)
0 0 1 0
1 0 0 Q(t) 0 1 0 1
1 0 1 0 0 1 1 X
1 1 0 1 1 0 0 1
1 1 1 Invalid 1 0 1 0
1 1 0 1
Excitation Table: 1 1 1 X

Q(t) Q(t+1) S R K map for Q(t+1):

SR
0 0 0 X 00 01 11 10
Q(t)
0 1 1 0 0 0 0 X 1
1 0 0 1
1 0 X 1
1 1 X 0 1

Q(t+1) = S + Q(t) R’
 D Flip Flop
Characteristic Table:
Truth Table:
Q(t) D Q(t+1)
Clk D Q(t+1)
0 0 0
0 X Q(t)
0 1 1
1 0 0
1 0 0
1 1 1
1 1 1

Excitation Table:
Q(t+1) = D
Q(t) Q(t+1) D
0 0 0
0 1 1
1 0 0
1 1 1
 JK Flip Flop
Truth Table:

Clk J K Q(t+1)
0 X X Memory; Q(t)
1 0 0 Memory; Q(t)
1 0 1 0
1 1 0 1
1 1 1 Toggle; Q(t)’

• The truth table for SR and JK flip flops are same for the first four combinations.
• In SRFF, S=1 and R=1, Q(t+1) is invalid
• Whereas in JK FF, J=1 and K =1, Q(t+1) = Q(t)’
Truth Table: Characteristic Table:
Clk J K Q(t+1) Q(t) J K Q(t+1)
0 X X Q(t) 0 0 0 0
1 0 0 Q(t) 0 0 1 0
1 0 1 0 0 1 0 1

1 1 0 1 0 1 1 1
1 0 0 1
1 1 1 Q(t)’
1 0 1 0
Excitation Table: 1 1 0 1
1 1 1 0

Q(t) Q(t+1) J K
K map for J: K map for K:
0 0 0 X
Q(t+1) Q(t+1)
0 1 1 X
Q(t) 0 1 Q(t) 0 1
1 0 X 1 0 1 X X
0 0
1 1 X 0 1 X X 1 1 0

J = Q(t+1) K = Q(t+1)’
 K map for Q(t+1):
Clk J K Q(t+1) Q(t+1)’
JK 0 X X Q(t) Q(t)’
00 01 11 10
Q(t) 1 0 0 Q(t) Q(t)’
0 0 0 1 1
1 0 1 0 1
1 0 0 1
1
1 1 0 1 0
Q(t+1) = J.Q(t)’ + K’.Q(t) 1 1 1 ? ?

Race around Condition:

Condition to overcome Racing:

1) T/2 < propagation delay of FF.
2) Use edge triggering
3) Master – Slave operation is same as –ve edge triggering
 T Flip Flop
• T flip – flop is also known as “Toggle Flip – flop”.
• To avoid the occurrence of invalid state in SR flip – flop, one input is given to the
flip – flop called
the Trigger input or Toggle input (T).
• Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing the next
state output to complement of the present state output’.

Clk T Q(t+1)
0 X Q(t); Memory
1 0 Q(t); Memory
1 1 Q(t)’; Toggling
 Truth Table: Characteristic Table:

Clk T Q(t+1) Q(t) T Q(t+1)

0 X Q(t) 0 0 0
1 0 Q(t) 0 1 1
1 1 Q(t)’ 1 0 1
1 1 0

Excitation Table:

Q(t) Q(t+1) T Q(t+1) = Q(t) Ꚛ T

0 0 0
T = Q(t) Ꚛ Q(t+1)
0 1 1
1 0 1 Odd 1’s detector
1 1 0
 Flip Flop Conversions
• Steps:
1. Identify the available and required flip flop

2. Make the excitation table for available flip flop

3. Make the characteristic table for required flip flop

4. Write the Boolean expression for available flip flop

5. Draw the circuit.

 JK to D Flip Flop
1. Available FF = JK & Required FF = D 4. Boolean expression for available JKFF:

2. Excitation table for JK FF:

D
Q(t) 0 1
Q(t) Q(t+1) J K
0 0 1 J=D
0 0 0 X
X X
0 1 1 X 1
1 0 X 1 D
1 1 X 0 0 1
Q(t) 0
X X
3. Characteristic table for D FF:
1 0 K = D’
1
Q(t) D Q(t+1) J K
0 0 0 0 X 5. Circuit Diagram:
0 1 1 1 X
1 0 0 X 1
1 1 1 X 0
 SR to JK Flip Flop
1. Available FF = SR FF ; Required FF = JK FF 3. Characteristic table for JK FF:

2. Excitation table of SR FF:

Q(t) J K Q(t+1) S R
Q(t) Q(t+1) S R 0 0 0 0 0 X
0 0 0 X 0 0 1 0 0 X
0 1 1 0 0 1 0 1 1 0
1 0 0 1 0 1 1 1 1 0
1 1 X 0 1 0 0 1 X 0
1 0 1 0 0 1
1 1 0 1 X 0
1 1 1 0 0 1
 4. Boolean expression for available SR FF:
5. Circuit Diagram:

JK
00 01 11 10
Q(t)
0 0 0 1 1

1 X 0 0 X

S = J Q(t)’

JK
00 01 11 10
Q(t)
0 X X 0 0

1 0 1 1 0

R = K Q(t)
Characteristic Equations and Table

JK FF

DFF

TFF:
 Preset and Clear Inputs
• They are the direct inputs or overriding inputs or
asynchronous inputs (preset and clear).
• The synchronous inputs are S, R, J , K, D and T.
• Preset = 0 ----- Q = 1
• Clear = 0 --------- Q = 0
• Whatever be the value of clock and synchronous
inputs

Preset Clear Q(t)

0 0 Not used
0 1 1
1 0 0
1 1 FF perform
normally
 Registers
• A Flip flop is 1-bit memory cell.
• To increase the storage capacity, flip flops are grouped together known as
REGISTERS.
• A register is a group of flip flops, each one of which shares a common clock and is
capable of storing one bit of information.
• An n-bit register consists of a group of n flip flops capable of storing n bits of
binary information.
• A register consists of a group of flip flops together with gates that affect their
operation.
• The flip flops hold the binary information, and the gates determine how the
information is transferred into the register.
Four Bit Register
• Data storage can be done by independent control called as load input.
• Types:
• Synchronous load – Clock and load are high
• Asynchronous load – Only load is high.
• Data can be entered in serial (temporal code) or parallel (special code)form.

D D D D
Clock
Clear
Load Q Q Q Q

• Serial : 1 bit at a time

• Parallel: all bits at the same time
 Classification of Registers

• Depending on Input and output:

1. SISO – Serial In and Serial Out
2. SIPO- Serial In and Parallel Out Shift Register

3. PISO- Parallel In and Serial Out

4. PIPO- Parallel In and Parallel Out Storage Register

• Depending on Application:
• 1. Shift Register
• 2. Storage Register (PIPO)
 Shift Register
• A register capable of shifting the binary information held in each cell to its
neighbouring cell, in a selected direction is called a shift register.

• It consists of chain of flip flops in cascade, with the output of one flip flop
connected to the input of the next flip flop.

• All flip flops receive common clock pulses, which activate the shift of data from
one stage to the next.

• The bits stored in such registers can be made to move within the registers and
in/out of the registers by applying clock pulses.

• The registers which will shift the bits to left are called “Shift left registers”
Basic Data Movement in Shift Registers
Serial In and Serial Out Shift Register SISO

Assume the data input to be stored is 1010

Data input = 1 0 1 0
Load / storing the data
CLK Q0 Q1 Q2 Q3
Initial 0 0 0 0
1 0 0 0 0
2 1 0 0 0
3 0 1 0 0
4 1 0 1 0
Timing Diagram.

• To store/load the
data in 4 bit SISO
0 1 0 1 shift register, 4
clk pulses are
required.

1 • To retrieve/read
the data (4+3) =
7 clk pulses are
0 required.

0
Serial In Parallel Out (SIPO) Shift register
• SIPO:
• Assume the data to be 1101.

CLK Q0 Q1 Q2 Q3
Initial 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 0 1 0
4 1 1 0 1

• 4 clk pulses are required to load the data.

• To retrieve/read the data, 1 clk pulse is required. i.e. In the 4th Clk pulse itself we
get the data.
Parallel In Serial Out (PISO) Shift register
To Load/write the data 1001.
• PISO:
• Write: To Load the data 1001, 1 clk pulse is required.

CLK Q0 Q1 Q2 Q3 Shift/Load’
Initial 0 0 0 0 -
1 1 0 0 1 0

• Read: (n-1) clk pulses are required. i.e. 3 clk pulse. Q3 data is already out at the
end of 1st clk pulse.

CLK Serial Output Shift/Load’

1 1 0
2 0 1
3 0 1
4 1 1
 Parallel In and Parallel Out (PIPO) –Storage Register

In a single clock pulse both load (read) and write (retrieve) of data is done.
Analysis of Clocked Sequential Circuits
 Introduction
• Analysis describes the behaviour of a clocked sequential circuits under certain
operating conditions.
• It can be determined from the inputs, outputs and state of flip flops.
• The outputs and the next state are both a function of the inputs and the present
state.
• The analysis of a sequential circuit consists of obtaining a state table or a state
diagram.
• It is also possible to write Boolean expressions that describes the behaviour of
the sequential circuits.
• A logic diagram is recognized as a clocked sequential circuit if it includes flip flops
with clock inputs.
• The FF may be of any type and the logic diagram may or may not include
combinational logic gates.
 Introduction to State equation, State table and State diagram

• The behaviour of a clocked sequential

circuit can be described by means of state
equations.

• A state equation (transition equation)

specifies the next state as a function of the
present state and inputs.

• For convenience, omit “t”

• State Table: The time sequence of inputs, outputs and flip flops can be
enumerated in a state table. It consists of four sections such as present state,
input, next state, and output.
• State Diagram: The information available in a state table can be represented
graphically in the form of a state diagram.
• A state is represented by a circle and the transitions between states are indicated
by directed lines connecting the circles.
• State assignments:
• S0 = 0 0
• S1 = 0 1
• S2 = 1 0
• S3 = 1 1
 Truth Table: Characteristic Table: Clk = 1
Q(t) S R Q(t+1)
Clk S R Q(t+1)
0 0 0 0
0 X X Q(t)
0 0 1 0
1 0 0 Q(t) 0 1 0 1
1 0 1 0 0 1 1 X
1 1 0 1 1 0 0 1
1 1 1 Invalid 1 0 1 0
1 1 0 1
Excitation Table: 1 1 1 X

Q(t) Q(t+1) S R K map for Q(t+1):

SR
0 0 0 X 00 01 11 10
Q(t)
0 1 1 0 0 0 0 X 1
1 0 0 1
1 0 X 1
1 1 X 0 1

Q(t+1) = S + Q(t) R’
Characteristic Equations and Table

JK FF

DFF

TFF:
 Analysis of Clocked Sequential Circuit with D Flip Flop

QA
QB

Clk
Step 1: Find the input and output equations: Characteristic equation:

DA = X QA + QB DB = Q’A QB Q(t+1) = D

Y= X QA + X’ Q’B
• State Table:
QA+ = DA = X QA + QB QB+ = DB = Q’A QB Y= X QA + X’ Q’B

Present State Input Next State Output

QA QB X QA + QB+ Y
0 0 0 0 0 1

0 0 1 0 0 0

0 1 0 1 1 0

0 1 1 1 1 0

1 0 0 0 0 1

1 0 1 1 0 1

1 1 0 1 0 0

1 1 1 1 0 1
• State diagram:
• 2 FF, hence 4 states 1/0 0/1
• QAQB
00
• S0 = 0 0
• S1 = 0 1
• S2 = 1 0 0/1
0/0 01
• S3 = 1 1
11 1/0

1/1

0/0
10

1/1
Analysis of Clocked Sequential Circuit with JK Flip Flop
• Step 1: Find the input and output equation.
• There is no output combinational logic, hence no output equation.
• JA = QB Q(t) J K Q(t+1)
• KA = X’ QB = X’ JA 0 0 0 0
0 0 1 0
• JB = X’ 0 1 0 1
• KB = X Ꚛ QA 0 1 1 1
1 0 0 1
• Characteristic table and equation: 1 0 1 0
1 1 0 1
1 1 1 0
• Step 2: State Table
• Step 3: State Diagram.
Analysis of Clocked Sequential Circuit with T Flip Flop
• Step 1: Find the input and output equation.
• TA = X QB
• TB = X
• Y = QA QB
• Characteristic table and equation:

QA+ = QA Ꚛ TA
+
QB = QB Ꚛ TB
• Step 2: State Table.

Present State Input Next State Output

+
QA QB X TA TB QA + QB Y
0 0 0 0 0 0 0 0

0 0 1 0 1 0 1 0

0 1 0 0 0 0 1 0

0 1 1 1 1 1 0 0

1 0 0 0 0 1 0 0

1 0 1 0 1 1 1 0

1 1 0 0 0 1 1 1

1 1 1 1 1 0 0 1
• Step 3: State Diagram.
0/0
0/0

1/0
00 01

1/1
1/0

11 10
1/0
0/0
0/1
Synchronous Binary Up Counter
LSB

1st Clk Output = 0 0 0 1

2nd Clk Output = 0 0 1 0
Clk A3 (MSB) A2 A1 A0 (LSB)
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 Synchronous binary down
5 0 1 0 1 counter can be constructed
from the same circuit of
6 0 1 1 0 upcounter with a small change.
7 0 1 1 1
8 1 0 0 0 Input to the AND gates should
be taken from Q complement.
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 Design of Synchronous Counters

• Step 1:Decide the number of flip flops and type of FF

• Step 2: Excitation table of FF chosen.
• Step 3: State diagram and
• Step 4: Circuit excitation table.
• Step 5: Obtain simplified equation using K map.
• Step 6: Draw the logic diagram.
 Design of 2-
bit
• Step 1: synchronous
n = 2 bit, number of FF = 2
Type of FF = JK
up counter
Range = 22 – 1 = 3; (0,1,2,3);
Number of states = 4
• Step 2:

Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
• Step 3: Step 4: Circuit Excitation table
State diagram Q1 Q2 Q1 + Q2+ J1 K1 J2 K2
0 0 0 1 0 X 1 X
00 0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
11 01

Step 5: K map
Q2 Q2
10 0 1 0 1
Q1 Q1
0 1 0 X X
0
X X 1 0 1
1

Q2 J1 = Q2 K1 = Q2
Q2
0 1 0 1
Q1 Q1
0 1 X 0 X 1
J2 = 1
1 1 X 1 X 1 K2 = 1
 • Step 6: Logic diagram: Q1 Q2

J1 Q1 J2 Q2

K1 Q1’
K2 Q2’

Clk Logic 1
 Design of 3-
bit
• Step 1: synchronous
n = 3 bit, number of FF = 3
Type of FF = T
up counter
Range = 23 – 1 = 7 ; (0,1,2,3,4,5,6,7);
Number of states = 8
• Step 2:
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0
Step 3: State Diagram
Step 4: Circuit Excitation table

Present state Next State Input

QC QB QA Q+ C Q+ B Q+ A TC TB TA
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
 Step 5: K map Reduction
K map for TC K map for TA
QB QA
01 11 QB QA
00 10
QC 00 01 11 10
0 0 0 1 0 QC
0 1 1 1 1
1 0 0 1 0
1 1 1 1 1
TC = QA QB
TA = 1

K map for TB

Q B QA
QC 00 01 11 10
0 0 1 1 0

1 0 1 1 0

TB = QA
Step 6: Logic diagram

Design of3- bit synchronous up counter

 Control Input Present state Next State Input
3 bit Up/Down Synchronous counter M QC QB QA Q+ C Q+ B Q+ A TC TB TA
0 0 0 0 1 1 1 1 1 1
M = 1 --- Up counter 0 0 0 1 0 0 0 0 0 1

M = 0 --- Down counter 0 0 1 0 0 0 1 0 1 1

0 0 1 1 0 1 0 0 0 1
0 1 0 0 0 1 1 1 1 1
0 1 0 1 1 0 0 0 0 1
0 1 1 0 1 0 1 0 1 1
0 1 1 1 1 1 0 0 0 1
1 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 0 1 1
1 0 1 0 0 1 1 0 0 1
1 0 1 1 1 0 0 1 1 1
1 1 0 0 1 0 1 0 0 1
1 1 0 1 1 1 0 0 1 1
1 1 1 0 1 1 1 0 0 1
1 1 1 1 0 0 0 1 1 1
 Q B QA QB QA
M QC 00 01 11 10 M QC 00 01 11 10
00 1 0 0 0 00 1 0 0 1

1 0 0 0 01 1 0 0 1
01
0 0 1 0 0 1 1 0
11 11
0 0 1 0 0 1 1 0
10 10

TC = M QB QA + M’ Q’B Q’A TB = M QA + M’Q’A

QB Q A
M QC 00 01 11 10
TA = 1
00 1 1 1 1

1 1 1 1 TB = M QA + M’Q’A
01
1 1 1 1 TC = M QB QA + M’ Q’B Q’A
11 TA = 1
1 1 1 1
10
3 bit Up/Down Synchronous counter
3 bit Up/Down Synchronous counter
Modulo, Ring and Johnson Counters
 Modulo – N Counter

• Counters can be designed to generate any desired sequence of states.

• A divide by N counter is a counter that goes through a repeated sequence
of N
states also known as Modulo- N counter.
• The sequence may follow the binary count or may be any other
arbitrary sequence.
• Eg. 2 bit ripple counter (4 states) is called as MOD- 4 or modulus 4 counter
• 3 bit ripple counter (8 states) is called as MOD-8 or modulus 8 counter.
• Modulus will give the number of states in the counter.
• 2 bit up/down counter – MOD -4
• 3 bit Up/Down counter – MOD-8
• n = bit and modulus number = 2n
3 Bit Asynchronous counter
3 Bit Asynchronous counter
Timing Diagram
 MOD- 6 counter
• Design of MOD-6 counter (using MOD-8 counter)

• States = 6

• Number of FF = 3

• Maximum count = 6; Range = (0,1,2,3,4,5)

• Choose D FF

• 000--- 001-- 010-- 011--100---101 --(110 & 111—Not

required---Should be Reset).
 Ring Counter
• A ring counter is a circular shift register with only one flip flop being set at any
particular time; all others are cleared.
• The single bit is shifted from one flip flop to the next to produce the sequence of
timing signals.
• To generate 2n timing signals, we need either a shift register with 2n flip flops or
an n-bit binary counter together with an n to 2n decoder.
• Number of states = Number of flip flops
Alternative Design:
 Johnson
counter
• Johnson’s counter is also known Twisted/Switch tail ring counter.
• Number of states = 2 x number of flip flops.