BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus

INSTRUCTION DIVISION
FIRST SEMESTER 2023-2024
Course Handout Part II
Dated : 11 Aug 2023
In addition to part I (General Handout for all courses appended to the time-table) this portion gives further
specific details regarding the course.

Course No. : MEL G623

Course Title : ADVANCED VLSI DESIGN
Instructor-in-charge : ANU GUPTA

1. Course Description:
The field of Digital very large-scale integrated circuits has gone through dramatic evolutions and changes.
This course builds on previous course MEL G621 VLSI DESIGN. It is intended to give a detailed
knowledge and experience in design of advanced VLSI circuits and chips in today's and future nano-scale
CMOS technologies. Design of high-performance digital systems, failure issues, and remedies of
problems. Topics will focus on current issues including: wiring resistance and how to deal with it, power
and Ground noise and regulation, clock (or asynchronous) system design and how to minimize clocking
overhead, high-speed I/O design, energy minimization including leakage control. Major VLSI design
challenges followed by careful treatment of several versatile digital, and mixed analog-digital circuit
building blocks frequently utilized in VLSI chips
2. Scope and Objective of the Course: The development of digital technology over the past 50 years has
revolutionized the design and performance of everything from mobile phones to cars and entertainment
systems; and engineers continue to enhance the performance of these devices. Recent developments in
nanotechnology promise further large increases in processing power with lower power requirements, and
will open up a whole new world of applications for digital techniques. The course aims to learn new
techniques to keep up-to-date with developments in an industrial and/or research setting, and will have
hands-on experience of the different stages of the design of a modern digital system.
2. Text Book :
J. M. Rabaey, A. Chandrakasan, “Digital integrated Circuits-A design perspective”,
Second Edition, Prentice Hall Electronics and VLSI Series
Reference Books :

1. IEEE journals
2. William J Dally, John W Poulton, " Digital Systems Engineering"; Cambridge University Press
3. A. Bellaour, M. Elmasry, “Low power digital VLSI design-circuits and systems” , Second Edition,
Kluwer academic publishers,
4. R. Best, “Phase Locked Loop”,McGraw Hill Publishers.
5. S. S. Rofail, K. S. Yeo, “Low voltage, Low power Digital BiCMOS Circuits”, Prentice Hall Inc.

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6. K. Roy, S.C. Prasad, “Low Power CMOS VLSI Circuit Design”, Wiley Interscience Publication.
7. M. J. S. Smith, “Application Specific Integrated Circuits”, Pearson Education ( Singapore) Pte Ltd.
8. Bhaskhar Jayram, "AVHDL PRIMER", Prentice Hall.
9. IEEE Journals of solid state circuits, VLSI system.
10. Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman, “ Digital Systems testing and testable
design,” September 1994, Wiley-IEEE Press
11. Martin. Ken, “Digital Integrated Circuit Design”, Oxford University Press, Inc.
12. Michael. L. Bushnell, and Vishwani. D. Agrawal, “Essentials Of Electronic Testing For Digital,
Memory And Mixed Signal VLSI Circuits. Kluwer Academic Publishers, Third Edition, 2004
13. Behrooz Parhami, “Computer Arithmetic-algorithms and Hardware design”, Oxford University
Press Inc , 2000
14. Sutherland. I., Harris. David, Sproull. Bob, “ Logical Effort-Designing Fast CMOS Circuits”,
Morgan Kaufmann Publishers.
15. Eric Bogatin, " Signal integrity Simplified", Prentice Hall Modern Semiconductor Design Series

3. Course Plan :

Modules Lecture References Learning Outcomes

Sessions
General Introduction-digital system, 2 Student will have Knowledge of System
data rate, pin count, serial/ parallel design issues that can cause non
communication, eye diagram functional system
Signal encoding, and signaling modes, 6 Ref-2, IEEE Knowledge of , signal encoding
voltage/ current Input/output drivers journals techniques, driver design, noise immunity
(with low power constraint) for C, and
LRC loads
Timing issues in synchronous VLSI 10 Text book ( ch. Knowledge of timing conventions and
systems . 7) / IEEE synchonization in digital systems
journals

Text book ( ch. Knowledge of hand shaking protocols in

Asynchronous system design 10) / IEEE design
journals
Wire design models in nanometer 7 Ref-2, Text Knowledge of Driver circuits design
region- lumped, distributed, book chapter 3, techniques, lumped/ transmission line
transmission line, termination , IEEE papers modelling , signal integrity issuesetc.

High performance / low power circuit Text book Knowledge of Techniques for high speed
logic , delay/ power minimization 7 Chapter-14, circuits
using Logical effort IEEE papers
Clock signals distribution and clock Text book Knowledge of Clock distribution
generation , clock drivers, 10 Chapter -10 , networks
Digital phase locked loop , digital Ref-3 Generation of clock using PLL and its
delay locked loop, synchronizer - design
design and meta-stability issues
42

Noise management, power supply 6 Ref-2 , IEEE Knowledge of noise sources-power

distribution papers supply, cross talk, inter-symbol

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interference, noise management

techniques,
power distribution, regulation, isolation
Memory design (self reading) Text book Knowledge of Memory organization and
Chapter-12, design of memory cells
IEEE papers
40

4. Evaluation Scheme:

Component Duration Marks Date & Time Venue Remarks

Midsem Test 90 Mts. 25 CB/OB

Assignments (Continuous) 40 Spread across the semester OB
/Project/ Quiz/
seminar / Take
home/ Viva -voce
Comp. Exam 120 min 35 OB/CB
100

5. Assignments /Project/ Quiz/ seminar / Take home/ Viva -voce: Regular Assignments covering use of
VERILOG, CADENCE TOOLS for Simulation of Advanced VLSI Circuits will be given.

7. Make up Policy: Make up will be given only on genuine reasons. Applications for make up
should be given in advance and prior permission should be obtained for Scheduled tests.

8. Chamber Consultation Hour/s: will be announced, Fix a time prior to meeting through email

9. Notices: All notices related to the course will be put on NALANDA.

Instructor-In-Charge
MEL G623

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