Instructions: Language

of the computer
Lecture # 3
Course Instructor: Dr. Afshan Jamil
Outline
• Basic operation cycle
• Instruction
• Register Set
• Operand address
• Addressing modes
• Operations of the computer hardware
• Operands of the computer hardware
• Load instruction
• Store instruction
• Spilling registers
Recall
Basic Operation Cycle
Fetch
instruction

Store Decode
results instruction

Locate &
Execute Fetch
operands
 Instruction
• It is a bit stream of zeros and ones having multiple
fields and can be understood by a computer
– Opcode: operation to be performed
– Address Fields: Memory or Register Address
– Mode: specifies the way the address field is to be
interpreted.
– Special Fields
• field that gives the number of positions to shift in a
shift-type instruction
• An operand field in an immediate operand instruction
 Register Set
• Register set consists of all registers in the CPU
that are accessible to the programmer
– General Purpose registers
– Processor status register (PSR)
– Stack pointer (SP)
• Instruction register, registers in the register file
that are accessible only to hardware controls
and/or micro-programs, and pipeline registers
are not part of the register set
Operand Address
• Implied Address
– Address is specified either by the Opcode of
the instruction or by an address assigned to
one of the other operands.
– No need for a memory or register address
field for the operand in the instruction
• Explicit Address
– Operand has an address in the instruction
 Addressing Modes
• How the operands are selected during program execution is
dependent on the addressing mode of the instruction
• Addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the
operand is referenced.
• effective address: operand address from where operand is
referenced.
• Computers use addressing-mode techniques
– To give programming flexibility to the user
– To reduce the number of bits in the address fields of the
instruction
Addressing Modes
• Implied Mode
– needs no address field at all
– operand is specified implicitly in the definition of
the Opcode
• Examples
– instruction that uses an accumulator without a
second operand is an implied-mode instruction
• Complement accumulator
– data-manipulation instructions in a stack
computer
• ADD (the operands are implied to be on top of stack)
Immediate Mode

opcode R1 R2 600

600 is the value.

Register Direct Mode:

opcode R1 R2 600

Processor Registers

600 is the address of register having value.

Register Indirect Mode:

opcode R1 R2 600

Memory
Processor
Registers

600 is the address of

register having actual
memory address of
value.
Relative Addressing Mode:

opcode R1 R2 600
Memory
⊕

PC

600 is the offset.

Indexed Addressing Mode:

opcode R1 R2 600
Memory
⊕

IR

600 is the offset.

Operations of the computer hardware
• Design Principle 1: Simplicity favors regularity
• Every computer must perform arithmetic operations.
• RISC-V requires every instruction to perform single
operation and have exactly three operands/variables,
no more and no less, to keep the hardware simple
• Hardware for a variable number of operands is more
complicated than hardware for a fixed number.
• Operand order is fixed (e.g., destination first)
Operations of the computer Hardware
• Example 1:
C code: a = b + c

RISC-V code: add a, b, c

• Example 2:
C code: a = b + c + d + e

RISC-V code: add a, b, c // a=b+c

add a, a, d // a=a+d
add a, a, e // a=a+e 16
CONTD…
• Example 3:
C code: a = b + c;
d = a – e;
RISC-V code: add a, b, c
sub d, a, e
CONTD…
Example 4:
C code: f = (g + h) – (i + j);
RISC-V code:
add t0,g,h
add t1,i,j
sub f,t0,t1
Operands of the Computer
Hardware
• Design Principle 2: Smaller is faster
– Arithmetic instructions operands must be in registers
– Size of register is 64 bits (group of 64 bits is called
doubleword)
– The RISC-V convention is x followed by the number of
the register.

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CONTD…
– RISC-V has 32 registers. Reasons of keeping only 32
registers are:
1. A very large number of registers may increase the
clock cycle time.
2. The number of bits it would take in the instruction
format
RISC-V Register conventions
Example

• Example 1: f = (g + h) – (i + j);
The variables f, g, h, i, and j are assigned to the registers x19,
x20, 221, x22 and x23 respectively.
add x5,x20,x21
add x6,x22,x23
sub x19,x5,x6
Memory operands
• What about programs with lots of variables (arrays and
structures)?
– Use memory,
• Remember RISC-V arithmetic operands are registers, not
memory locations.
• RISC-V must include instructions that transfer data between
memory and registers.
• Such instructions are called data transfer instructions.
• Memory is just a large, single-dimensional array, with the
address acting as the index to that array, starting at 0.
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Memory addresses and contents of
memory at those addresses
CONTD…
• Since 8-bit bytes are useful in many programs,
virtually all architectures today address individual
bytes. Therefore, the address of a doubleword
matches the address of one of the 8 bytes within
the doubleword and addresses of sequential
doublewords differ by 8.
CONTD…
Load Instruction
“Used to load a doubleword from memory”
• The real RISC-V name for this instruction is ld,
standing for load doubleword
• ld x1, offset(x2)
• The address is computed by adding the contents
of register x2 to the sign-extended offset (which
is an immediate value).

27
CONTD…
• Value from address computed above is then
loaded into register x1
• Example:
• ld x6, 20(x19) // x6 = Memory[x19 + 20]
STORE Instruction
“Used to store a doubleword to memory”
• The actual RISC-V name for this instruction is
sd, standing for store doubleword.
• sd x1, offset(x2)
• The address is computed by adding the
contents of register x2 to the sign-extended
offset (which is an immediate value).

29
CONTD…
• Value from register x2 is then copied to the
memory address computed.
• Example:
• sd x6, 20(x19) // Memory[x19+ 20] = x6
CONTD…
• Example 1:
– g = h + A[8];
• ld x9,64(x22) // Temporary reg x9 gets A[8]
• add x20,x21,x9 // g = h + A[8]

• Example 2:
– A[12] = h + A[8];
• ld x9,64(x22) // Temporary reg x9 gets A[8]
• add x9,x22,x9 // Temporary reg x9 gets h + A[8]
• sw x9,96(x22) // Stores h + A[8] back into A[12]
Spilling registers
• Many programs have more variables than computers have
registers.
• Consequently, the compiler tries to keep the most
frequently used variables in registers and places the rest in
memory.
• The process of putting less commonly used variables (or
those needed later) into memory is called spilling registers.
• Registers take less time to access and have higher
throughput than memory, making data in registers both
faster to access and simpler to use.
CONTD…
• Accessing registers also uses less energy than
accessing memory.
• To achieve highest performance and conserve
energy, an instruction set architecture must have
sufficient number of registers, and compilers must
use registers efficiently.