388 CHAPTER 11 / DIGITAL LOGIC

C 0 = A 0B 0 (11.4)
C 1 = A 1B 1 + A 1A 0B 0 + B 1A 0B 0 (11.5)
Following the same procedure, we get
C 2 = A 2B 2 + A 2A 1B 1 + A 2A 1A 0B 0 + A 2B 1A 0B 0 + B 2A 1B 1
+ B 2A 1A 0B 0 + B 2B 1A 0B 0
This process can be repeated for arbitrarily long adders. Each carry term can be
expressed in SOP form as a function only of the original inputs, with no dependence
on the carries. Thus, only two levels of gate delay occur regardless of the length of
the adder.
For long numbers, this approach becomes excessively complicated. Evaluating
the expression for the most significant bit of an n-bit adder requires an OR gate
with 2n - 1 inputs and 2n - 1 AND gates with from 2 to n + 1 inputs. Accordingly,
full carry lookahead is typically done only 4 to 8 bits at a time. Figure 11.21 shows
how a 32-bit adder can be constructed out of four 8-bit adders. In this case, the carry
must ripple through the four 8-bit adders, but this will be substantially quicker than
a ripple through thirty-two 1-bit adders.

11.4 SEQUENTIAL CIRCUITS

Combinational circuits implement the essential functions of a digital computer.

However, except for the special case of ROM, they provide no memory or state
information, elements also essential to the operation of a digital computer. For the
latter purposes, a more complex form of digital logic circuit is used: the sequential
circuit. The current output of a sequential circuit depends not only on the current
input, but also on the past history of inputs. Another and generally more useful way
to view it is that the current output of a sequential circuit depends on the current
input and the current state of that circuit.
In this section, we examine some simple but useful examples of sequential
circuits. As will be seen, the sequential circuit makes use of combinational circuits.

Flip-Flops
The simplest form of sequential circuit is the flip-flop. There are a variety of flip-
flops, all of which share two properties:
• The flip-flop is a bistable device. It exists in one of two states and, in the
absence of input, remains in that state. Thus, the flip-flop can function as a
1-bit memory.
• The flip-flop has two outputs, which are always the complements of each
other. These are generally labeled Q and Q.

THE S–R LATCH Figure 11.22 shows a common configuration known as the S–R
flip-flop or S–R latch. The circuit has two inputs, S (Set) and R (Reset), and two outputs,
Q and Q, and consists of two NOR gates connected in a feedback arrangement.
 11.4 / SEQUENTIAL CIRCUITS 389
R
Q

Q
S

Figure 11.22 The S–R Latch Implemented

with NOR Gates

First, let us show that the circuit is bistable. Assume that both S and R are 0
and that Q is 0. The inputs to the lower NOR gate are Q = 0 and S = 0. Thus, the
output Q = 1 means that the inputs to the upper NOR gate are Q = 1 and R = 0,
which has the output Q = 0. Thus, the state of the circuit is internally consistent
and remains stable as long as S = R = 0. A similar line of reasoning shows that the
state Q = 1, Q = 0 is also stable for R = S = 0.
Thus, this circuit can function as a 1-bit memory. We can view the output Q as
the “value” of the bit. The inputs S and R serve to write the values 1 and 0, respec-
tively, into memory. To see this, consider the state Q = 0, Q = 1, S = 0, R = 0.
Suppose that S changes to the value 1. Now the inputs to the lower NOR gate are
S = 1, Q = 0. After some time delay ^t, the output of the lower NOR gate will be
Q = 0 (see Figure 11.23). So, at this point in time, the inputs to the upper NOR gate
become R = 0, Q = 0. After another gate delay of ^t the output Q becomes 1. This
is again a stable state. The inputs to the lower gate are now S = 1, Q = 1, which
maintain the output Q = 0. As long as S = 1 and R = 0, the outputs will remain
Q = 1, Q = 0. Furthermore, if S returns to 0, the outputs will remain unchanged.
The R output performs the opposite function. When R goes to 1, it forces
Q = 0, Q = 1 regardless of the previous state of Q and Q. Again, a time delay of
2^t occurs before the final state is established (Figure 11.23).
The S–R latch can be defined with a table similar to a truth table, called a
characteristic table, which shows the next state or states of a sequential circuit as
a function of current states and inputs. In the case of the S–R latch, the state can
be defined by the value of Q. Table 11.10a shows the resulting characteristic table.
Observe that the inputs S = 1, R = 1 are not allowed, because these would pro-
duce an inconsistent output (both Q and Q equal 0). The table can be expressed
more compactly, as in Table 11.10b. An illustration of the behavior of the S–R latch
is shown in Table 11.10c.
CLOCKED S–R FLIP-FLOP The output of the S–R latch changes, after a brief
time delay, in response to a change in the input. This is referred to as asynchronous
operation. More typically, events in the digital computer are synchronized to a clock
pulse, so that changes occur only when a clock pulse occurs. Figure 11.24 shows this
390 CHAPTER 11 / DIGITAL LOGIC

1
S
0

1
R
0

t
1
2 t t
Q
0

1
t 2 t
Q
0
Figure 11.23 NOR S–R Latch Timing Diagram

Table 11.10 The S–R Latch

(a) Characteristic Table (b) Simplified Characteristic Table

Current Current Next S R Qn  1

Inputs State State
0 0 Qn
SR Qn Qn+1 0 1 0
00 0 0
1 0 1
00 1 1
1 1 —
01 0 0
01 1 0
10 0 1
10 1 1
11 0 —
11 1 —

(c) Response to Series of Inputs

t 0 1 2 3 4 5 6 7 8 9
S 1 0 0 0 0 0 0 0 1 0
R 0 0 0 1 0 0 1 0 0 0
Qn1 1 1 1 0 0 0 0 0 1 1
 11.4 / SEQUENTIAL CIRCUITS 391
R
Q

Clock

Q
S

Figure 11.24 Clocked S–R Flip-Flop

Clock

Q
D

Figure 11.25 D Flip-Flop

arrangement. This device is referred to as a clocked S–R flip-flop. Note that the
R and S inputs are passed to the NOR gates only during the clock pulse.
D FLIP-FLOP One problem with S–R flip-flop is that the condition R = 1, S = 1
must be avoided. One way to do this is to allow just a single input. The D flip-flop
accomplishes this. Figure 11.25 shows a gate implementation of the D flip-flop. By
using an inverter, the nonclock inputs to the two AND gates are guaranteed to be
the opposite of each other.
The D flip-flop is sometimes referred to as the data flip-flop because it is, in
effect, storage for one bit of data. The output of the D flip-flop is always equal to the
most recent value applied to the input. Hence, it remembers and produces the last
input. It is also referred to as the delay flip-flop, because it delays a 0 or 1 applied to
its input for a single clock pulse. We can capture the logic of the D flip-flop in the
following truth table:

D Qn  1
0 0
1 1

J–K FLIP-FLOP Another useful flip-flop is the J–K flip-flop. Like the S–R flip-flop,
it has two inputs. However, in this case all possible combinations of input values are
valid. Figure 11.26 shows a gate implementation of the J–K flip-flop, and Figure 11.27
shows its characteristic table (along with those for the S–R and D flip-flops). Note
that the first three combinations are the same as for the S–R flip-flop. With no input
asserted, the output is stable. If only the J input is asserted, the result is a set function,
392 CHAPTER 11 / DIGITAL LOGIC

K Q

Clock

J Q

Figure 11.26 J–K Flip-Flop

causing the output to be 1; if only the K input is asserted, the result is a reset function,
causing the output to be 0. When both J and K are 1, the function performed is
referred to as the toggle function: the output is reversed. Thus, if Q is 1 and 1 is applied
to J and K, then Q becomes 0. The reader should verify that the implementation of
Figure 11.26 produces this characteristic function.

Name Graphical Symbol Truth Table

S Q S R Qn1

0 0 Qn
S–R Ck 0 1 0
1 0 1
R Q 1 1 –

J Q J K Qn1

0 0 Qn
J–K Ck 0 1 0
1 0 1
K Q 1 1 Qn

D Q D Qn1

0 0
D Ck 1 1

Figure 11.27 Basic Flip-Flops

 11.4 / SEQUENTIAL CIRCUITS 393
Data lines

D18 D17 D16 D15 D14 D13 D12 D11

D Q D Q D Q D Q D Q D Q D Q D Q

Clk Clk Clk Clk Clk Clk Clk Clk

Clock
Load
D08 D07 D06 D05 D04 D03 D02 D01

Output lines

Figure 11.28 8-Bit Parallel Register

Registers
As an example of the use of flip-flops, let us first examine one of the essential ele-
ments of the CPU: the register. As we know, a register is a digital circuit used within
the CPU to store one or more bits of data. Two basic types of registers are com-
monly used: parallel registers and shift registers.
PARALLEL REGISTERS A parallel register consists of a set of 1-bit memories that
can be read or written simultaneously. It is used to store data. The registers that we
have discussed throughout this book are parallel registers.
The 8-bit register of Figure 11.28 illustrates the operation of a parallel register
using D flip-flops. A control signal, labeled load, controls writing into the register
from signal lines, D11 through D18. These lines might be the output of multiplexers,
so that data from a variety of sources can be loaded into the register.
SHIFT REGISTER A shift register accepts and/or transfers information serially.
Consider, for example, Figure 11.29, which shows a 5-bit shift register constructed
from clocked D flip-flops. Data are input only to the leftmost flip-flop. With each
clock pulse, data are shifted to the right one position, and the rightmost bit is
transferred out.
Shift registers can be used to interface to serial I/O devices. In addition, they
can be used within the ALU to perform logical shift and rotate functions. In this

Serial in D Q D Q D Q D Q D Q Serial out

Clk Clk Clk Clk Clk

Clock

Figure 11.29 5-Bit Shift Register