Analog Layout Design

Learn a little about semiconductors and integrated circuits

THIS DOCUMENT INTRODUCES AN OVERVIEW METHODOLOGY FOR ANALOG LAYOUT DESIGN, IT GIVES VISUAL REPRESENTATION OF
SEMICONDUCTOR DEVICES AND INTEGRATED CIRCUITS

SHUBHAM KUMAR
2nd Edition, Date: 1/JULY/2023
Contents
1. Introduction to Analog Layout Design........................................................................................................ 3

2. Basic Linux Command ........................................................................................................................ 5

3. IC Fabrication .................................................................................................................................... 7
4. MOSFET ........................................................................................................................................... 22
➢ N-MOSFET Fabrication ..................................................................................................................... 24
➢ MOSFET Principle .............................................................................................................................. 30

5. Layout Layer introduction.

➢ Poly ………………………………………………….……………………………………………………….....…...…….…...31
➢ NWELL ............................................................................................................................................. 32
➢ DNWELL .......................................................................................................................................... 33
➢ Device Fingers …………………………………………………… ......................................................………………..35
➢ Metal Routing ............................................................................................................................... 37
➢ MOSFET Layers in Layout ................................................................................................................. 41

6. Devices Available in layout

➢ Resistor……………………………………………………… ................................................…………………….....45
➢ Capacitor…………………………………………………….. .................................................………………...…..48
➢ Inductor…………………………………………………… ................................................ ……………………......59
➢ Diode……………………………………………………….. ..................................................……………….……....61
➢ Transistor………………………………………..……… ................................................... ………………….…….63
➢ MOSFET…………………………………………………… ................................................... ……………………….65
• Planer…………………………………………… ................................................... …………….…………66
• Finfet……………………………………………..…………….…............................................ …..….……68
• FD-Soi…………………………………… ........................................................................................ 74
• GAAFET ............................................................................................................................... 79
• Ribbon FET.......................................................................................................................... 82

7. Logic cells ……………………..……………………..………………………….. ......................................... ……..……....84

8. Device Matching .......................................................................................................................................... 91
➢ Circuits that required matching “Current Mirror & Differential pair” .................................... 92
➢ Layout matching…………………………………………… .................................................. ……….…………..98
➢ Dummy……………………………………………………….……………… ...............................................……...108
➢ Resistor matching ......................................................................................................................... 111

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9. Device Matching Effects
➢ Length of diffusion (LOD effect) ………………………………….. ...… ................................... ..….…...113
➢ Well proximity……………………………………………………… ................................................…….……..116
➢ STI ………………………………………………………..…… ................................................………………….…..117

10. Guardring…………………………………………………….................................................................………….…….…119
11. General Layout Guidelines……………………………………… ................................................ ……………….…...123
12. Routing Importance
➢ Signal Routing matching………………………………… ..................................................………………...125
➢ Physical design routing process……………………..… ...............................................…….……….….131
➢ Noise and Shielding………………………………………….. ..............................................………….…..…134
➢ Buffer …………………………………………………………..…… .............................................……….……..…140
➢ Double patterning (metal coloring) ...………………… .. .............................................……….……..143

13. DRC and LVS ………………………………………………………………… ...............................................……………..…146

14. SXCUT and PSUB2 layer…………………………………….…………… .................................................………..……147
15. Parasitic Capacitance and Resistance…………………………………….…………….......................... ………..……148
16. Sheet Resistance……………………………………..…………………… ...............................................……….….……152
17. EM ………………………………………………… .................................................................................... …….……...158
18. IR ……………………………………………… ........................................................................................…….………..160
19. Antenna ………………………………………………………………….. ......................................................…….….…….162
20. Latch-Up …………………………………………..……………………… ........................................................…..……….169
21. ESD……………………………………………………………………. ................................................................... …………176
22. Clamp .......................................................................................................................................................... 189
23. I/O pads / Bond Pads & Wire bonding………….…………… ................................................ ……….……...…206
24. Electrical Rule Check (ERC)/Softcheck………….…………..… ..............................................……….…….……208
25. Density…………………………………………………..………………… .............................................. …………..………..209
26. High Speed Layout Design………………………….………………................................................………….….……213
27. Basic Circuits ……………………………………………………………… ..............................................…………….…….223
28. SERDES………………………………………………………….……………… ................................................ …………….…225
29. Buffer Chips / Data Buffer……………………………………………… ................................................………..…….232
30. Temperature sensor………………………………………………………….……………… ......................... …………….…234
31. Example of Analog Circuit ………………………………………………….. .............................................. …….…… 236
32. Wafer Level Packaging………………………………………………………… ..............................................……….….237
33. Industry example……………………………………………….………………… ............................................. ………….251

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 1. Introduction to Analog layout design

Analog layout design is a crucial aspect of integrated circuit (IC) design that focuses on
creating the physical layout of analog circuits on a semiconductor wafer. Analog circuits
are responsible for processing continuous signals and are widely used in various
applications, including audio amplifiers, power management, data converters, and sensor
interfaces.

Here are some key points to understand about analog layout design:

1. Design Considerations: Analog layout design requires careful consideration of various

factors to ensure the circuit's performance, reliability, and manufacturability. Some
important considerations include:

- Signal Integrity: Layout techniques should minimize parasitic effects, such as noise,
crosstalk, and electromagnetic interference, to maintain signal integrity and reduce
unwanted signal degradation.

- Matching and Symmetry: Analog circuits often require precise matching of devices to
achieve desired performance. Layout techniques are employed to ensure accurate
matching and symmetry between components.

- Parasitic Capacitance and Resistance: Parasitic capacitance and resistance can

adversely affect circuit performance. Layout techniques aim to minimize these parasitic
elements to maintain signal integrity and reduce unwanted effects.

- Power Distribution: Efficient power distribution networks should be designed to

deliver stable and clean power to analog circuitry, minimizing voltage drops and noise.

- Thermal Considerations: Heat dissipation is critical in analog circuits. Layout

techniques focus on optimizing thermal paths and ensuring adequate spacing for proper
heat dissipation.

2. Floorplanning: Analog layout design involves selecting an appropriate circuit topology

and determining the placement and orientation of circuit components. Floorplanning

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refers to the process of assigning specific areas on the semiconductor wafer for different
circuit blocks, considering factors such as signal flow, device density, and noise isolation.

3. Component Placement: Once the floorplan is defined, the next step is component
placement. Analog layout designers carefully position transistors, resistors, capacitors,
and other components to optimize electrical performance, minimize parasitics, and
achieve desired matching.

4. Routing: Analog layout design includes routing the interconnects between circuit
components. Routing must consider factors like impedance control, signal integrity, noise
reduction, and avoiding cross-coupling effects. Special attention is given to critical nets
and sensitive nodes to ensure proper functionality.

5. Design Rule Checks (DRC): DRC is a crucial step in analog layout design. Design rule
checking tools analyze the layout against predefined manufacturing rules to identify
potential issues and violations. DRC ensures that the layout adheres to fabrication process
requirements, mask limitations, spacing rules, and other specifications.

6. Iterative Optimization: Analog layout design often involves an iterative optimization

process. Designers may need to refine the layout, adjust component sizing, modify
routing, or make other changes to achieve desired performance, minimize parasitics, or
meet design constraints.

Successful analog layout design requires a deep understanding of circuit behavior, layout
techniques, manufacturing processes, and design constraints. It combines creativity,
engineering principles, and attention to detail to ensure the final layout meets
performance specifications while maximizing yield and reliability.

NOTE: - “This document presents a compilation of information

sourced from reputable online sources, supplemented with insights
contributed by the author ‘Shubham Kumar’. “

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 2. Basic Linux Command

• pwd: Prints the current working directory, displaying the path of the current
directory: e.g. if you are at your home directory then it will print something like
/home/<username>
• ls: list directory: This command will list the items of a directory. If you don’t specify
a directory then it will list work directory, the place where you currently are.
• Ls -a: will show the hidden files
• ls -al: will list the files and directories with detailed information like the
permissions, size, owner, etc
• cd: changes the current directory. It will change the work directly as specified.
• cd..: change directory one level up.
• cp: Copy Command. It will copy a file or directory. It is similar to Copy-Paste in GUI.
Ex: cp (file name) (location), cp file.txt new_file.txt
• mv :Move or rename files and directory. It is like renaming a file or cut-paste in GUI.
• rm,rm -r, rm -rf : remove file or directory. ex: rm file.txt
• rmdir: remove empty directory. This will not remove content of the directory but it
will delete a directory if it is empty.
• mkdir: Creates a new directory. For example, mkdir myfolder will create a
directory named "myfolder" in the current directory.
• chmod: It is used to change file permission. chmod stands for change mode in
Linux., ex: chmod 775 (file name), chmod775 file.txt
basic permission of a file can have : r(read), w(write), x(execute)
• clear: clear Screen: Use clear command to clear the terminal screen.
• grep: Searches for a specific pattern in files. For example, grep "hello" myfile.txt
will search for the word "hello" in "myfile.txt".
• zip: The command “zip” is used to compress one or more files and store them in a
new file with .zip extension.
• unzip: The command “unzip” is used to decompress a .zip file and extract all the
files within to current directory.

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• history: The simple command “history” displays the list of all commands entered
since the user started the session.
• evince and acroread: This command is for pdf file open.
• du –sh: check the file size.
• touch : The touch command allows to update the access and modification times of
the specified files
• find: used to search for files in a directory or a hierarchy based.
Ex: find [flags] [path] –name [expression]
• ping: used for network connectivity test, ex: ping google.com, ping 8.8.8.8
• whoami: used to display the username currently in use
• passwd: used to change the password of user account
• kill: for terminate the tool, ex: kill 532452, kill firefox
• exit: exit from terminal.
• shutdown: To power off your computer immediately.

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 3. IC Fabrication

What is IC?
Integrated circuits (IC) sometimes called a chip or microchip is a semiconductor
wafer on which thousands or millions or trillions of tiny resistors, capacitors and
transistors are fabricated.

ICs are widely used in various electronic devices, ranging from smartphones and
computers to automotive systems and medical devices. They play a crucial role in
modern technology by providing compact and highly integrated solutions for
complex electronic functions.

An IC can function as an oscillator, amplifier, timers, computer memory or

microprocessor.
An IC is categorized as linear (analog), discrete (digital) or Mixed-Signal (analog +
digital) depending on its intended applications.

1. Digital Integrated Circuits: These ICs are designed to process digital signals
and perform logic operations. They are the building blocks of digital systems
and can be found in microprocessors, memory chips, and digital signal
processors.
2. Analog Integrated Circuits: Analog ICs are designed to process continuous
signals, such as audio and video signals. They are used in applications like
amplifiers, filters, and power management circuits.
3. Mixed-Signal Integrated Circuits: These ICs combine both analog and digital
circuitry on the same chip. They are commonly used in systems that require
both analog signal processing and digital control, such as data converters,
sensor interfaces, and communication systems.

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Moore’s law
In the year 1965 Gordon Moore Intel Co-Founder and Chairman predicted that
transistors would continue to shrink, allowing
• Doubled transistors density every 18-24 month
• Doubled performance every 18-24 month
• The period often quoted as 18 month

Basic steps of IC fabrication

• Wafer production
• Epitaxial growth
• Photolithography
• Masking
• Etching
• Doping
• Atomic diffusion
• Ion implantation
• Metallization
• Assembly and packaging

Wafer Production
• The Wafer is round slice of semiconductor material such as silicon. Silicon is
preferred due to its characteristics; it is more suitable for manufacturing IC.
• It is base or substrate to entire chip
• First purified polycrystalline silicon is created from the sand. Than it is
heated to produce molten liquid.
• A small piece of solid silicon is dipped on the molten liquid.
• Then the solid silicon is dipped on the molten liquid.
• A thin round wafer of silicon is cut using wafer slicer. Wafer slicer is a
precise cutting machine and each slice having thickness about 0.01 to 0.025
inches.

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• When wafer is sliced, the surface will be damaged. It can be smoothening by
polishing. After polishing the wafer. It must thoroughly clean and dried.
• The wafers are cleaned using high purity low particle chemicals. The silicon
wafers are exposed to ultra pure oxygen

Starting substrates are cut and polished from huge single crystals of silicon. Not
done by the foundries.

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Epitaxial growth

• It means the growing of single silicon crystal upon original silicon substrate.
• A uniform layer of silicon dioxide is formed on the surface of wafer.

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Photolithography
• Photolithography is a technique that is used to define the shape of micro-
machined structured on the wafer.

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Masking
• To protect some area of wafer when working on another area, a process called
photolithography is used.
• The process of photolithography includes masking with a photographic mask
and photo etching.
• A photoresist film is applied on the wafer.
• The wafer is aligned to a mask using photo aligner.
• Then it is exposed to ultraviolet light through mask.
• Before that the wafer must be aligned with the mask.

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Etching

• Selectively removing unwanted material from the surface of the wafer.

• The pattern of the photo-resist is transferred to the wafer by means of etching
agents
• The parts of material are protected by this etching mask.

Doping
• To alter the electrical character of silicon, atom with one less electron than
silicon such as boron and atom with one electron greater then silicon such as
phosphorous are introduced into the area.
• The P-type(boron) and N-type (phosphorous) are created to reflect their
conducting characteristics.

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Atomic diffusion
• Diffusion is defined as the movement of impurity atom is semiconductor
material at high temperature.
• Then the wafer are heated at a temperature of about 1500-2200F. The inert gas
carries the dopant chemical. The dopant will get deposited on the wafer.
• This method can only be used for large areas. For small areas it will be difficult
and it may not be accurate.

Ion implantation

• Ion implantation is a low-temperature process by which ions of one element are

accelerated into a solid target, thereby changing the pysical, chemical, or
electrical properties of the target.
• Ion implantation is used in semiconductor device fabrication and in metal
finishing, as well as in material science research.

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• The ions can alter the elemental composition of the target (if the ions differ in
composition from the target) if they stop and remain in the target.
• Ion implantation also causes chemical and physical changes when the ions
impinge on the target at high energy.

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Metallization
• It is used to create contact with silicon and to make interconnections on
chip.
• A thin layer of aluminum is deposited over the whole wafer.
• Aluminum is selected because it is a good conductor, has good mechanical
bond with silicon, forms low resistance contact and it can be applied and
patterned with single deposition and etching process.
• It must be patterned and etched to form the actual wires connecting
individual device into a circuit.

Assembly and packaging

• Each of the wafers contains hundreds of chip. These chips are separated and
packaged by a method called scribing and cleaving.
• The wafer is similar to a piece of glass. A diamond saw cut the wafer into
single chip.
• The diamond tripped tool is used to cut the lines through the rectangular
grid which separated the individual chip.
• The chip that are failed in the electrical test are discarded.
• Before packaging, remaining chips are observed under microchip. The good
chip is then mounted into a package.

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 Wafer and chips:

1. Chip: a tiny piece of silicon with electronic circuit patterns

2. Scribe Lines: thin, non-functional spaces between the functional pieces, where a
saw can safely cut the wafer without damaging the circuits
3. TEG (Test Element Group): a prototype pattern that reveals the actual physical
characteristics of a chip (transistors, capacitors, resistors, diodes and circuits) so
that it can be tested to see whether it works properly
4. Edge Die: dies (chips) around the edge of a wafer considered production loss;
larger wafers would relatively have less chip loss
5. Flat Zone\Notch: one edge of a wafer that is cut off flat to help identify the
wafer’s orientation and type

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Video link:
1.https://youtu.be/c9arR8T0Qts
2. https://youtu.be/fwNkg1fsqBY
3.https://www.computerhistory.org/revolution/digital-
logic/12/288/2220

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 4. mosfet

MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a widely used

type of field-effect transistor that is essential in modern integrated circuits (ICs)
and electronic devices. It is a three-terminal device that operates based on the
modulation of an electric field in a semiconductor channel.

The MOSFET consists of four main components:

1. Substrate: The substrate serves as the foundation and provides physical

support for the MOSFET. It is typically made of a semiconductor material, such as
silicon.

2. Gate: The gate is a terminal that controls the flow of current through the
MOSFET. It is separated from the channel by a thin insulating layer, usually made
of silicon dioxide (SiO2). The gate terminal is typically made of a conductive
material, such as doped polycrystalline silicon (polysilicon) or metal.

3. Source: The source is one of the two terminals through which current can flow
in the MOSFET. It is typically connected to the region of the substrate where
majority charge carriers (either electrons or holes, depending on the type of
MOSFET) are abundant.

4. Drain: The drain is the other terminal through which current can flow in the
MOSFET. It is typically connected to the region of the substrate where majority
charge carriers are depleted.

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N-MOSFET Fabrication

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Video link :https://youtu.be/1Lad28K3Xi0

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MOSFET Principle

The main principle of the MOSFET device is to be able to control the voltage and
current flow between the source and drain terminals. It works almost like a switch
and the functionality of the device is based on the MOS capacitor. The MOS
capacitor is the main part of MOSFET.

NMOSFET: In the case of an N-type switch, the body or back gate terminal is
connected to the most negative supply (usually GND in single power supply
systems) and the gate is used as the switch control.
Whenever the gate voltage exceeds the source voltage by at least a threshold
voltage, the MOSFET conducts.

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 5. Layout Introduction

Poly: Polysilicon is a high purity, polycrystalline form of silicon.

polycrystalline silicon, is a material that consists of small silicon crystals.

Fig : 3D view of mosfet the poly layer

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 NWELL:
The N-well layer is created within a p-type substrate by introducing n-type dopants, such
as phosphorus or arsenic, through a process called doping. This results in a localized
region with a higher concentration of electrons, creating an n-type region within the p-
type substrate.

The purpose of the N-well layer is to form the body region for pMOSFETs (p-channel
Metal-Oxide-Semiconductor Field-Effect Transistors) in a CMOS process. In a CMOS
technology, both pMOSFETs and nMOSFETs (n-channel Metal-Oxide-Semiconductor Field-
Effect Transistors) are integrated onto the same chip to achieve complementary
functionality.

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DNWell layer (It is use to isolate P-well):
Generally, DeepNwell is used to isolate NMOS from the substrate of other NMOS.

Mostly this layer is used to substrate noise coupling injected by Digital Logic in Mixed
Signal environment through bulk or substrate.

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Video link :https://youtu.be/fpKx4hj8MYM

3D view link: https://skfb.ly/oGTIz

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Device Fingers: Simply it is a multiplier or parallel connected
device. If 4 parallel connected device is there so we can say the device
have 4fingers.

Fig : Four finger devices with drain and source merge

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 ❖ Why should increase fingers and reduction of width is
good?

Capacitance diffusion substrate

CSB =CDB= (W+2ldiff)(LD+2ldiff)

Resistance of the poly gate

Rgate=Lgate .Rsq,poly

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Metal Routing:
Metal routing, also known as metal interconnect or routing, is a key step in the
design and fabrication of integrated circuits. It involves creating metal wires or
paths on the surface or within the layers of the chip to connect different
components. The process includes planning, designing, and optimizing the
paths to ensure proper signal transmission, power efficiency, and
manufacturability. The metal interconnects are formed by depositing and
patterning multiple metal layers separated by insulating dielectric layers. Via
structures are used to establish connections between layers. The routing
process is guided by design rules and considerations for signal integrity and
timing. Once completed, the metal routing enables the desired circuit
functionality and is crucial for the proper functioning of the integrated circuit.

Fig: Connection in between Metal 1(M1) to Metal3 (M3)

Fig: 3D view of VIA and Metal connection

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Fig: 3D view of VIA and Metal connection

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Fig: Cross-section of a 0.12µm/120nm technology (Courtesy Fujitsu)

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 • Metal ratio: It is defined with respect to first metal (metal1)
Assume that metal1 height is 1um and metal2 is 2X so metal2 height is 2um.
Metal1 height is very with respect to technology.

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MOSFET layeres in layout

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 Fig: Layout view of an Inverter /Not Gate

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Effective channel length:

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 6. Device available in layout

Resistor: The generic layout of an integrated resistor is shown in figure.

We have a resistive layer, which is properly shaped to obtain the required
resistance. Contacts to an interconnect layer (metal 1 in the example) are
placed at both end of the resistive shape, creating the two resistor
terminals. The rectangular shape that is included between the contacts is
the resistor section, or resistor body.

• There are two types of resistors currently use in layout

1. Poly resistor
2. Metal resistor

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• Poly Resistor:
Layout sample of a poly resistor

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• Metal Resistor:

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 Capacitor:

• MOS capacitors:
1. Transistors can be used as a cap using the thin oxide layer from the gate
as an insulator. The Gate acts as the top plate and the Drain and Source
as the bottom plate
2. The drawback is that if the voltage at the gate varies, the depletion area
changes at the gate varying the dielectric properties and modifying the
capacitance. So, the MOS capacitor’s value is very dependent on the
applied DC voltage.
3. The capacitance per unit area is higher than the MIM caps, because the
insulator of the gate (SiO2) is much thinner than the insulator between
the metal layers. But the variation with the voltage is a big
disadvantage.
4. They are useful for local supply decoupling where the DC voltage is
constant. Another drawback is the parasitic resistance of the bottom
plate.

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NMOSCAP:

PMOSCAP:

3d view link:
1. N-type device cap: https://skfb.ly/oGTII
2. P-type device cap: https://skfb.ly/oGTJy

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• MIM capacitors:
1. It is formed by two parallel metal layers and has a high k-dielectric
between them. The bottom layer forms a small parasitic cap with the
substrate.
2. This type is the most used, because of the high capacitance per unit
area with the lowest parasitic. The drawback is that they require more
process steps during the fabrication. Mainly, a new mask and step are
added to deposit the insulator between the metal layers. Therefore, a
fabrication process with MIM caps is more expensive than others using
only MOM-caps.
3. They can be single, double, triple, etc. It depends on the number of
layers of metal and insulators. The thickness of the insulator layer is in
the range of 25 nm (depending on the fabrication technology).
4. The quality factor is very high because both plates are made out of
metal and the voltage dependency is negligible

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Fig: CTM and CBM is the layer of mim cap

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Fig: MIM Capacitor

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• MOM capacitors:

1. The advantage of the MOM capacitor is that it does not require

additional process steps, because it can be obtained using only
standard metal layers.
2. MOM capacitors are generally capable of withstanding much higher
voltages.
3. The main drawback is that, for the same used area, the capacitances
that can be obtained are smaller than allowed by MIM capacitors.
4. This problem can be overcome using multi-layer MOM capacitors,
which involve several metal layers connected by means of vias.

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Fig:-(a) MIM capacitor. (b) MOM capacitor: interdigitated parallel wires. (c) MOM capacitor: woven.
(d) MOM capacitor: parallel stacked wires. (e) MOM capacitor: vertical bars.
(f) MOM capacitor: multi-layer sandwich.

Fig: MOM CAP

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• Poly-Poly capacitors:

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• Poly-diffusion capacitors:

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 Inductor: Structure of spiral inductor

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 Diode:
Layout view:

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 Shubham Kumar
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Transistor / BJT :

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Video link of BJT : 1. https://youtu.be/7ukDKVHnac4
2. https://youtu.be/zFLmuZa4tDE

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MOSFET:

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Planer MOSFET:
The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS
FET), also known as the metal–oxide–silicon transistor (MOS transistor, or MOS), is a
type of insulated-gate field-effect transistor that is fabricated by the controlled
oxidation of a semiconductor, typically silicon. The voltage of the covered
gate determines the electrical conductivity of the device; this ability to change
conductivity with the amount of applied voltage can be used for amplifying or
switching electronic signals.

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3D view of MOSFET link: https://skfb.ly/oGOKI

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Finfet:
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-
semiconductor field-effect transistor) built on a substrate where the gate is placed on
two, three, or four sides of the channel or wrapped around the channel, forming a
double gate structure. These devices have been given the generic name "finfets"
because the source/drain region forms fins on the silicon surface. The FinFET devices
have significantly faster switching times and higher current density than
planar CMOS (complementary metal-oxide-semiconductor) technology.

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Silicon nitride (Si3N4) :-Silicon nitride is a chemical compound of the
elements silicon and nitrogen. Si3N4 is the most thermodynamically stable of the silicon nitrides.
Hence, Si3N4 is the most commercially important of the silicon nitrideswhen referring to the term
"silicon nitride". It is a white, high-melting-point solid that is relatively chemically inert, being
attacked by dilute HF and hot H2SO4. It is very hard (8.5 on the mohs scale). It has a high thermal
stability.

Titanium nitride (TiN, sometimes known as Tinite) :- Titanium nitride is an extremely

hard ceramic material, often used as a coating on titanium alloys, steel, carbide,
and aluminum components to improve the substrate's surface properties.

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Silicon dioxide(sio2, also known as silica) :- Silicon dioxide is an oxide of silicon with
the chemical formula SiO2, most commonly found in nature as quartz and in various living
organisms. In many parts of the world, silica is the major constituent of sand. Silica is one of the
most complex and most abundant families of materials, existing as a compound of several
minerals and as synthetic product. Notable examples include fused quartz, fumed silica, silica gel
and aerogels. It is used in structural materials, microelectronics (as an electrical insulator), and
as components in the food and pharmaceutical industries.

Layers of Fin:

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3D view of finfet:

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Current flow in planer and finfet:

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 Fig: image of FinFET

3D view of FinFET link: https://skfb.ly/oGOLK

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FDSOI:
In semiconductor manufacturing, silicon on insulator (SOI) technology is fabrication
of silicon semiconductor devices in a layered silicon–insulator–silicon substrate, to
reduce parasitic capacitance within the device, thereby improving performance. SOI-
based devices differ from conventional silicon-built devices in that the silicon junction
is above an electrical insulator, typically silicon dioxide or sapphire (these types of
devices are called silicon on sapphire, or SOS). The choice of insulator depends largely
on intended application, with sapphire being used for high-performance radio
frequency (RF) and radiation-sensitive applications, and silicon dioxide for
diminished short-channel effects in other microelectronics devices. The insulating
layer and topmost silicon layer also vary widely with application.

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ELTRAN (Epitaxial Layer TRANsfer)

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 Shubham Kumar
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LVT FDSOI

RVT FDSOI

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 Advantage of FD-Soi:

• Better Electrostatics
➢ Faster Operation/ Higher clock speed for mobile
chips
➢ Low Voltage/ only 0.6V power consumption in
mobile device
➢ Less power consumption in mobile device
➢ Lower production cost
• Total dielectric isolation
➢ Lower S/D leakage
➢ Lower S/D Capacitance
➢ Latch-up immunity
• Lower leakage current
➢ Less sensitive to temperature
• No channel doping
➢ Improved Vt Variability
➢ Improved mismatch (SRAM & analog)
➢ Better analog gain
• Less Self heating effect

3D view of FD-Soi link: https://skfb.ly/oGOMr

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GAAFET:
A Gate-All-Around Field Effect Transistor (GAAFET) technology is similar
in function to a FinFET transistor but the gate material surrounds the
channel from all sides. Generally, based on design, GAAFETs can have two
or four gates. Gate-All-Around Field Effect Transistor (GAAFET) technology
is believed to be the successor to FinFETs, as it provides better device
performance at smaller sizes such as below 7 nm. Nanowire and nanosheet
structures are used for the fabrication of GAA transistors. The alignment of
the GAAFET structures can be parallel or perpendicular to the substrate
depending on the implementation.

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Types of GAAFET:
1. nanowire (NW) FETs:
• H-GAAFET

• V-GAAFET

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 • nanosheet (NS) FETs: MBCFET: Multi-Bridge Channel FET

3D view link of GAAFET: https://skfb.ly/oGOMz

MBCFET: https://skfb.ly/oIPSz

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Ribbon FET and PowerVia:
Ribbon-shaped channels are surrounded by the gate to provide better control and
higher drive current at all voltages. A stack of "nano-ribbons" provide the same drive
current with a smaller footprint than multiple fins. RibbonFET was announced along
with a new chip architecture

Fig: FinFET Fig: RibbonFET

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 Fig: PowerVia

Video link for MOSFET :

1.Planer : https://youtu.be/stM8dgcY1CA

2. FinFet: https://youtu.be/TXxw1kdF5_Q

3. FD-Soi: https://youtu.be/uvV7jcpQ7UY

4. FD-Soi: https://youtu.be/qLIwGXhEcl4

5. GAAFET: https://youtu.be/3otqUu-7WUQ

6. Ribbon FET and PowerVia: https://youtu.be/t6Y41zdO3Pc

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 7. Logic cells

INVERTER
• The simplest of the logic gates is the Inverter. It is an essential part of digital
design and understanding the operation and properties of an Inverter will make
it significantly easier to study NAND Gates, Adders, Multiplexers and even
Microprocessors.

• Following is the circuit of a CMOS Inverter Gate along with its symbols.

• CMOS Inverter is also known as the NOT Gate. From the above circuit, you can
see that a CMOS Inverter consists of an N-channel MOSFET (NMOS) and a P-
channel MOSFET (PMOS).

• When the input A is LOW i.e. Logic 0, the NMOS Transistor is OFF and the
PMOS Transistor is ON. The P-channel MOSFET provides a path for the VDD to
appear at the Output. Hence, the output is HIGH i.e. Logic 1.

• Similarly, when the input is HIGH, NMOS is ON and PMOS is OFF. The output
is connected to GND and the output is LOW.

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Layout view
Video link: https://youtu.be/oSrUsM0hoPs
3D view link: 1. Finfet inverter: https://skfb.ly/oGOLU
2 cmos inverter: https://skfb.ly/oGOLC

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All steps of how to create an inverter layout:
https://www.siue.edu/~gengel/ece484LabMaterial/con_pnmos.htm

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NAND
The following circuit shows a 2-input CMOS NAND Gate. As seen in the image, a 2-
input NAND gate consists of two N-channel MOSFETs connected in series between
output and GND and two P-channel MOSFETs connect in parallel between VDD and
output.

When any of the inputs A or B is LOW, at least one of the NMOS Transistors will be
OFF. For the output to be LOW, both the inputs should be HIGH. For all the other
combinations of the inputs, the output will be HIGH.

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Layout view

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NOR
Circuit of a 2-input CMOS NOR Gate is shown below. It consists of two P-channel
MOSFETs connected in series between VDD and Output and two N-channel
MOSFETs connected in parallel between Output and GND.

When either of the inputs A or B is HIGH, the output is LOW as at least one NMOS
Transistor is ON. For the output to be HIGH, both the inputs must be LOW.

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Layout view

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 8.Device matching

Why Matching is needed:

1.
• What if your headphones started playing songs with more volume in left
than the right? Sounds bad right. So the driver sensitivity needs to be
matched for both left & right side.

• Matching in context of analog layout is an act of creating a similar

environment for a set of transistors, so that they exhibit similar electrical
properties. (i.e, trans conductance, current gain, drain capacitance etc.).

• Actually, due to process variation in fabricating the transistors (i.e like non
uniform doping, oxide thickness, etching etc.), no 2 transistors have exactly
the same electrical properties. By applying techniques such
as Interdigitzer & Common centroid, it is possible to match transistors
reasonably.

• In a differential amplifier, matching would greatly enhance the performance

by improving the ability to reject noise in its differential input. Therefore it
“Common mode rejection ratio (CMRR)” would increase. In a current
mirror, matching would accurately mirror the reference current.

2.
In Analog circuits, we use specific designs like differential pairs and current
mirrors. These designs require us to pay attention to the characteristics of the
devices, especially the threshold voltage (Vt). Even a small difference of a few
millivolts can affect the performance and success (yield) of the design. The
threshold voltage is influenced by factors such as the number of doping atoms in
the channel and the thickness of the gate oxide. To ensure everything works
well, we need to make sure our analog devices match each other. For that, we
need to match the analog device

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 Circuits that required Matching

1. Current Mirror:

The simple current mirror can be obtained from the one transistor
current source by using a second transistor in diode connection that
generates the necessary gate-source voltage of the transistor in the
output stage. The gate source voltage is set by the diode geometry and
the injected input or reference current. Since the gates and the sources
of the two transistors are connected together the gate-source voltage of
the current source will be equal to the gate source voltage of the diode.
The schematic of the circuit is given in below Figure.

Figure . NMOS and PMOS implementations of a simple current mirror

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• Earlier the constant current source was use resistor than it replace by
a mosfet with a constant gate voltage than it replace by a diode
connected mosfet/device.
• It is 2 terminal devices.
• The current source will force current to the diode connected MOSFET
NM0 which intern develop voltage VGS across gate of NM0. This VGS is
given to the gate of Mosfet NM1. If the W/L ratios are same then it will
the same current as current source. So, here we are able to mirror the
current from Mosfet NM0 to mosfet NM1.

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 Cascode MOS current mirror

The cascode current mirror is derived from the simple current mirror by
cascoding both branches of the circuit. The schematic of the resulting
structure is given in Figure.
NMOS and PMOS implementations of a cascode current mirror The bulk
terminal of the transistors is connected either to the lowest potential, or
to VDD for PMOS transistors. In Figure the substrate connections of the
transistors M3 and M4 facilitate the identification of VBS voltages when
calculating the input and the output resistances.

Figure . NMOS and PMOS implementations of a cascode current mirror

Video link: https://youtu.be/GZvLm-mMJlY

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 2. Differential Pair (input Pair):
a. Differential amplifiers apply gain not to one input signal but to
the difference between two input signals. This means that a
differential amplifier naturally eliminates noise or interference that
is present in both input signals
b. Differential amplification also suppresses common-mode signals-in
other words, a DC offset that is present in both input signals will be
removed, and the gain will be applied only to the signal of interest
(assuming, of course, that the signal of interest is not present in both
inputs). This is particularly advantageous in the context of IC
design because it eliminates the need for bulky DC-blocking
capacitors.
c. The subtraction that occurs in a differential pair makes it easy to
incorporate the circuit into a negative-feedback amplifier

Video link: https://youtu.be/dvuG414ZsTQ

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 ❖ How does mismatch affect the performance of the circuit?

I1 = ½ μnCox (W/L )1. (VGS-Vt1)2

I2 = ½ μnCox (W/L )2. (VGS-Vt2)2
Where
I = Drain current
μn = Mobililty carriers of device either minority carrier or
majaority carrier
Cox = Thickness of oxide
W = Width of device (OD)
L = Length of device (OD)
Vgs = gate source voltage
VT = Threshold voltage
f
Defining average and mismatch quantities, we have
I = (I1+I2)/2 ;ΔI = I1-I2; W/L = [(W/L)1+ (W/L)2]/2
Vt = (Vt1+Vt2)/2 ;ΔVt = Vt1-Vt2

Substituting these expressions and neglecting higher order terms we obtain :

ΔΙ/I = [ Δ(W/L) / (W/L) ] – [ ΔVt / ( VGS – Vt)2 ]

Thus, from the above equation we can see that the mismatch in the current
depend upon
1. Mismatch in the (W/L) values of the transistors.
2. Mismatch in the threshold values of the transistors which increases as
the overdrive voltage ( VGS-Vt) is reduced.

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 ❖ Input offset voltage of a differential pair:

Thus, we see that the offset voltage depends upon two parameters:

1. The first component is the threshold voltage mismatch of the

transistors. This depends upon the layout and it can be reduced by
careful layout.
2. The second component of the offset scales with the overdrive
voltage and is related to mismatch in the load elements and
mismatch in the W/L values.

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Layout Matching:

➢ Transistor orientation is very important

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• Etch Effect: Poly silicon does not always etch uniformly.
➢ Large openings etch faster than small openings in mask.
➢ Solution is to use dummy structures.

• Diffusion Effects: Diffusion widens implanted region can affect

doping of neighboring devices.
Solution: Increase distance and use dummy structures that affect all
transistors the same.

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• Stress Effects:
a. The fabrication under high temperatures may leave residual stresses
in chip.
b. Packaging can cause stress in chip.
Solution:
a. Keep critical matched devices in center of chip or on enterlines
b. Avoid using corners for matched devices

• Dealing with Large Transistors:

a. These can be split into many parallel fingers.
b. Contact space in shared amongst transistors.
c. Parasitic capacitance is reduced.

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• Device matching type:
1. Inter-Digitization Techniques
2. Common Centroid

• Inter-Digitization Techniques:
➢ We have to match two components A and B (A and B can be anything
likes Mosfet, transistor, resistor, and capacitor).
Let’s split A and B into 4 small components i.e. A1-A4 and B1-B4
➢ Inter-digitization technique: Placing alternate components.

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• Common Centroid Layouts:
Matching won’t be good!!!

• Solution: Break and distribute parts of a transistor so as to cancel out the

effects of oxide / doping gradient profiles.

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Common centroid technique: Placing components such that both components
have same centroid.

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FIG: Diff pair matching pattern

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• Two Example of common centroid technique

1. Matching between M1 and M2 of differential amplifier

(W/L)M1 =2 (W/L)M2

An alternative approach of M1 M1 M2 M2 M1 M1 can also be used!!!

2. Matching between M3 and M4 of differential amplifier

(W/L)M3 = (W/L)M4

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• Averages process variations :

❖ Why Special attention on Matching?

✓ A large variety of analog circuits rely on matching of transistors.
Circuits like differential pair rely on gate tosource voltage matching
while current mirrors rely oncurrent matching.
✓ Most integrated resistors and capacitors have atolerance of about
20% to 30%. But ratio of two similarcomponents can be controlled to
a tolerance of 15 or even0.1% by proper matching of the
components.0.1% by proper matching of the components.

• Reasons for Mismatch:

Mismatch in integrated circuits are generally of two types :
a. Random mismatches due to microscopic fluctuations
in dimensions, doping, oxide thickness and other
parameters that influence component values
b. Systematic mismatches which are caused by :
▪ Process biases
▪ Mechanical stress
▪ Temperature gradients
▪ Polysilicon etch rates etc

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• Rules for MOS transistor matching:
✓ Place transistors in close proximity.
✓ Orient transistors in the same direction.
✓ Keep the layout of the transistors as compact as possible
✓ Whenever possible use Common centroid layouts.
✓ Place transistors segments in the areas of low stress gradients.
✓ Place transistors well away from the power devices.
✓ For current matching keep overdrive voltage large.
✓ For voltage matching keep overdrive voltage smaller.

• Rules for resistor and capacitor matching:

✓ Construct matched resistors of same type.
✓ Make matched resistors of the same width.
✓ Orient matched resistors in the same direction.
✓ Place matched resistors in close proximity.
✓ Place the matched resistors in such a way that their centroids coincide
i.e. interdigitate arrayed resistors.
✓ Place dummies on either end of the resistor array.
✓ Connect matched resistors to cancel thermoelectric effects.

Diffusion/OD Break matching devices:

All device (MOS, resistor, capacitor…) should be place is identical space and all
device should see same environment. As shown in below fig.

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DUMMY:
• Why Dummy Device is need:
✓ To minimize the etch effects during fabrication. If they are not placed
then it can so happen that one side is slightly more parameter (Vthe.g)
then the other transistor. Hence the matching will not be identical for all
the device. For a good matched layout dummy device must be used.
Generally dummy devices are added to resistors as well so that they
surround the complete resistor.

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 The dummy pattern may be formed to reduce the production
tolerance.

Document link of matching: -

https://core.ac.uk/download/pdf/84832221.pdf

Video links for Layout Matching:

1. need of layout matching: https://youtu.be/i_ejWt7wyEA
2. Layout Matching: https://youtu.be/92m_8kd0J0c
3. Interdigitaion Vs Common Centroid: https://youtu.be/qkKQmtxG_7A
4. How to add dummy: https://youtu.be/5ZRpTDAIpI8
5. current mirror: https://youtu.be/GZvLm-mMJlY

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• Industrial Quality :
a. Includes multiple guardrings.
b. Full common centroid.
c. Dummy structures.

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Resistor matching:

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Video link: https://youtu.be/rJIApmbgFHI

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 9. Device matching effects

2. LOD Effect (Length of oxide diffusion):

LOD (Length of Diffusion): LOD, or Length of Diffusion, refers to the

distance over which dopant atoms diffuse into the semiconductor material
during a diffusion process step. Dopant atoms are intentionally introduced
into the semiconductor material to modify its electrical properties and
create regions with specific conductivity characteristics. The LOD affects
the dimensions and characteristics of the resulting doped regions, such as
the depth of pn junctions or the width of source/drain regions in
transistors. Controlling the LOD is crucial for achieving the desired device
performance and electrical characteristics.

In CMOS source area & drain

area of a single finger device is
equal.

In case of multiple finger the area of source and drain are not equal for
corner transistor.
Example – For below device
Transistor-3 : The source area is equal to drain area.
Transistor-1 : The source area is smaller than drain area.
Transistor-5 : The drain area is larger than source area.

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Due to above condition, unintentionally we increase the size of device,
cause of this the electron mobility & holes mobility effect threshold
voltage VT of the transistor.
The transistor property may varryupto +-10% due to affect in VT.

How VTchange :
ID = ½ μn . Cox . (W/L ).( Vgs– VT )2
Where
ID = Drain current
μn = Mobility carriers of device either minority carrier or
majority carrier
Cox = Thickness of oxide
W = Width of device (OD)
L = Length of device (OD)

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 Vgs = gate source voltage
VT = Threshold voltage
Due to increase in mobility charge carrier the threshold voltage is varying
+-10-20%
Example:
Assume in PMOS we fixed VT = 0.7v
Due to increase in mobility extra majority charge carrier present in PMOS
due to LOD and device becomes turn on in 0.3v or 0.4v.
In PMOS majority charge carrier is holes
Similarly
Assume in NMOS we fixed VT = 0.7v
Due to increase in mobility extra majority charge carrier present in NMOS
due to LOD and device becomes turn on in 0.9v or 1.0v.
In NMOS majority charge carrier is electrons.

• Sources of layout proximity effect

▪ Well proximity effect
▪ Unintentional stressors ƒ: Shallow trench isolation (LOD effect)

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 1. Well proximity effect (WPE) :

The transistors that are close to the well edge have different performance
than ideally placed transistors, because of this effect the transistor speed
can vary by +- 10%.the Vt of transistor got changed.
The transistor placed to the well boundary so it will get many problems
during ion implantation. Implanted ion is coming to the well boundary
and reflected/scatter from the well boundary to transistors Q1 & Q5
boundary and ions are deposited on the Q1 Q5 boundary. Ion particles
are scattered/reflected due to photoresist on both side of Nwell. These
ions are deposited only those transistors who are near to the well
boundary, so any one of the terminals of transistors gets affected by ion
implantation and the rest of the transistor will get uniform ions.

Solution:
• Use dummy surrounded to the active device
• The Well boundary should be 1.5 or 2 um away from the active
device

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2. Shallow trench isolation (STI):
Shallow Trench Isolation, is a technique used to electrically
isolate neighboring transistors and other devices on an
integrated circuit. This isolation is achieved by etching
shallow trenches into the semiconductor substrate and
filling them with insulating material, usually silicon dioxide
(SiO2). The STI effect refers to the impact of these isolation
structures on the electrical characteristics of the devices.
The presence of STI structures can cause variations in
transistor parameters, such as threshold voltage or
parasitic capacitance. Careful design and optimization are
necessary to minimize the STI effect and ensure consistent
device performance.

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 Silicon is dielectric material so it makes bond with active
OD. So STI covalent bond share with active OD covalent
bond & unintentionally the mobility carrier is changed,
cause of this VT also changed and the performance of the
device affected.

Makes bond Makes bond

with OD with OD

Video link:
LOD: https://youtu.be/HPprk_pgPXw
WPE: https://youtu.be/cd5qdHtxogs
STI: https://youtu.be/zOXc-ZfPosY

LinkedIn profile: - https://www.linkedin.com/in/shubham-kumar-4354b7135/

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10. Guardring

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 Shubham Kumar
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Floating Well:

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 11. General Layout Guidelines

Layout Steps:

a. Floor planning - Division of the entire die area among subcomponents

to facilitate interconnection and effectively utilize the area.
b. Placement - Placing the modules in the layout.
c. Routing - Connecting the modules with different metal layers.

Some important guidelines which should follow in

layout:

✓ Add dummy device surrounding any critical matched devices

✓ Uniform Poly and OD spacing
✓ Align/overlap dummy poly can guarantee uniform od spacing
✓ Use mosaic layout
✓ Big transistor array or poly resistor array will have high OD and/ Poly
density, can affect matching. Refer to design manual for density rule.
✓ Avoid OD/Poly for signal routing
✓ Adequate Well/Bulk/Substrate ties
✓ All OD/Poly/NW in rectangular shape
✓ Use even MOS fingers for device merging
✓ Evaluate LOD for MOS unit in an array Especially for PMOS unit when
used in headroom sensitive design or clock driver
✓ Avoid shared OD for MOS with different length
✓ If possible, connect gate from both end for lower gate resistance.

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 Guidelines for analog layout:

✓ Use of more number vias

✓ Fingering and proper orientation
✓ Device matching
✓ Symmetrical and common centroid layout design
✓ Use of Guard ring and substrate trapping

Standard cell design methodology:

✓ VDD and GND should abut (standard height)

✓ Adjacent gates should satisfy design rules
✓ NMOS at bottom and PMOS at top
✓ All gates include well and substrate contacts

❖ Things to remember:

✓ Keep sufficient spacing between power blocks and sensitive blocks.

✓ Two high frequency carrying pins should not be side by side.
✓ Use ground pin to avoid magnetic coupling between two pins.

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 12. Routing Importance

Signal Routing Matching :

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➢ Example of routing in Layout :

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➢ A Few of the options for symmetric Nets :

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➢ Symmetric Routing: Basic Trick

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 ➢ Detailed Solution to Balanced Route example

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➢ Detailed solution to balanced route example :

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 Physical Design Routing Process:

• Metal routing:
a. It involves generating metal wires to connect the pins of same
signal while obeying manufacturing design rules.
b. Before routing is performed on the design, cell placement has to be
carried out wherein the cells used in the design are placed.
c. The connections between the pins of the cells pertaining to same
signal need to be made. At the time of placement, there are only
logical connections between these pins.
d. The physical connections are made by routing. More generally
speaking, routing is to locate a set of wires in routing space so as to
connect all the nets in the netlist taking into consideration routing
channels’ capacities, wire widths and crossings etc.
e. The objective of routing is to minimize total wire length and
number of vias and that each net meets its timing budget. The tools
that perform routing are termed as routers.
f. You typically provide them with a placed netlist along with list of
timing critical nets. These tools, in turn, provide you with the
geometry of all the nets in the design.

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• Stages of routing:

I. GLOBAL ROUTING
II. TRACK ASSIGNMENT
III. DETAIL ROUTING
IV. SEARCH & REPAIR

1. Global Routing
• In global routing, the region to be routed are divided into sectors
(tiles/rectangles) called global routing cells.
• Then it decides tile to tile path for the nets and simultaneously trying to optimize
the length, without actually making any physical connection.
• The routing capacity of each cell depends on the blockages, routing tracks, pin
density inside it.
• This rough routing is done on the basis of available tracks in the region.
• If the required routing resources are greater than the available routing resources,
then it will lead to congestion.
• So it is called coarse grain routing assignment.

Objectives of global routing

• Minimize total overflow

• Minimize total wire length
• Minimize total run time for carrying out routing process

2. Track Assignment
• After the cell estimation, tracks are assigned to each global routes.
• The tracks are assigned in vertical and horizontal direction for each partition
• The direction of routing is dependent on the metal used, which has preferred
routing direction.
For eg. If metal1 has routing direction Horizontal, then Metal2 has direction
Vertical
• In this stage, the global routes are replaced with metal layer, which has many
DRC violations, Signal Integrity (SI) and timing violations

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 3. Detailed Routing
• In detailed routing, the router uses the scheme made in the global routing and
track assignment phases to lay metals to connect the nets to the pins
• The violations that were created in the previous stage, will be fixed by multiple
iterations of routing, so that no connections will be left short, open or spacing
violations.
• First, the block is divided into specific areas called the sboxes (switch boxes)
which comprises of multiple cells
• These boxes are in alignment with the cell boundary.

4. Search and Repair

• It is done along with detailed routing, specifically after the primary iteration
• The shorts and spacing violations are sorted and is fixed

Fill Stage

Fill stage comes after routing optimization, where filler cells and metal fills are added to
meet the DRC rules. Two steps are mainly performed in this stage.

1. Adding filler Cells

2. Adding Metal Fills

Adding Filler Cells

• Filler cells are used for rail continuity and to fill up gaps between standard cells in
the row, and thereby reducing the DRC violations created by the base layers
• Filler cells are physical-only cells designed in such a way that they contain only n-
well, p-well and power rails
• It is also possible to reduce the IR drop by inserting de-cap filler cells, but this
comes at a cost of higher leakage current

Adding Metal Fills

• The metal fills also known as dummy metal layer, are small, floating metal nets,
inserted in empty spaces in the design after post-route optimization in order to
maintain uniformity in metal layer density
• These are added to meet to metal density DRC rules (density violations) which are
mandatory by most manufacturing processes

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Noise and Shielding:
Interconnect shielding is used in VLSI designs to avoid noise interference from the
cross-coupling capacitance between adjacent signals. This paper takes advantage of
the shields already present in the design, and uses them to tune the propagation delay
of the clock signals, thus eliminating expensive dedicated delay buffers. The problem
of obtaining the desired delay at a minimum shielding cost (silicon area) is
formulated as a calculus of variations problem. An analytical solution shows that a
square root shield profile is optimal. The shield should connect to a quiet low-
impedance node such as an analog ground line.

Noise in Power and Ground:

• For the low noise circuit, a p-well ring, which is tied to VSS is recommended to
surround all PMOS device in each analog circuit block
• For the low noise circuit, a N-well ring, which is tied to VDD, is recommended to
surround all NMOS device in each analog circuit block
• Put NMOS in RW (NW hole in DNW) is a good practice of isolating critical circuit
from substrate noise. Make sure every NW connected to DNW must be the same
potential
• Use separate power supplies and ground buses for the noisy and sensitive
circuit and also for the analog and digital circuits
• Keep enough distance b/w the noisy and sensitive area use guard ring to
stabilize substrate and well potential
• For low noise OTA circuit, recommend input pair to be surrounded by identical
dummy device tied to ground or power

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Signal name that needs to be shield:
• CLK line (minimum cross-talk)
• DATA Line (minimum cross-talk)
• Reference Signal
• Bias / Current signal

Type of noise:
• Inherent noise
▪ Noise resulting from the discrete and random movement of charge in a
device
▪ Thermal noise, Flicker noise, shot noise
▪ The noise floor depends on the circuit design quality
• Quantization noise
▪ Noise resulting from the finite digital word size
▪ The SNR (signal-to-noise ratio) depends on the accuracy of ADC and DAC
• Coupled noise (Crosstalk)
▪ Noise resulting from the signals adjacent circuits deeding into each other
▪ The noise immunity depends on a layout.
Noise in Signal:

• Keep high frequency signal in higher metal layer

• Use metal shield for victim line that is noise sensitive
• Use metal and poly shield for attacker line that travels through long distance
• Prevent feedback path through chip seal-ring between critical input and output.
Use additional guard ring to isolate the coupling.

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Fig: Feedback connection reference

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Shielding of interconnects:
Shielding of interconnects in analog layout design is an important consideration to
minimize unwanted noise and interference that can degrade the performance of analog
circuits. Shielding techniques aim to isolate sensitive signals from external sources of
noise and to reduce the coupling between adjacent signals.

Metal Shielding: Metal shields, often made of the same metal layer as the interconnects,
can be placed around sensitive signal paths to protect them from external
electromagnetic interference (EMI). These shields can be grounded to divert the noise
currents away from the sensitive signals. Metal shields can be designed as a continuous
layer, encasing the sensitive signal traces, or as segmented shields placed strategically
around the sensitive areas.

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Bilateral Shielding:
Bilateral shielding, also known as dual-sided shielding, it provides enhanced isolation and
protection against noise and interference from various directions. The techniques
mentioned earlier, such as full metal shields, segmented shields, and grounded planes on
both sides, can be utilized for bilateral shielding.

Coaxial Shielding:
Coaxial Shielding is a technique commonly used in analog layout design to provide
effective shielding and reduce interference for sensitive analog signals. It involves the use
of a coaxial cable structure for transmitting the analog signal, which consists of an inner
conductor surrounded by an outer conductor (shield) with a dielectric material in
between.

The outer conductor, typically a metal shield, is connected to a reference potential, often
ground, and provides a protective barrier against external electromagnetic interference.
This shielding layer helps to minimize electromagnetic radiation and the pickup of
unwanted noise by the inner conductor, which carries the desired analog signal.

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Buffers
In analog design, buffers play an important role in maintaining the integrity and stability
of signals. A buffer is essentially an amplifier that helps overcome signal degradation or
loading effects when a signal needs to be transmitted from one part of a circuit to
another.

• Its Increases the fan-out capacity

• Inserting buffer decreases the transition time, which decreases the wire delay
• Due to buffer, Area and power consumption become increase.

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 • Reduce the fanout by load splitting by buffering or cloning.

Fig. (a) shows a buffer driving four other cells. In fig. (b), the load is split using Cloning. The
first buffer is cloned and each buffer now drives half of the load. In fig.(c), the load is split
using buffering. Two new buffers are added at the output of buffer A. Now buffer A is driving
C1 and C2 and each of them are driving half of the load.

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Clock Tree conection by using buffers:
In digital integrated circuit design, clock trees are used to distribute a clock signal uniformly to
different parts of the circuit. Buffers play a crucial role in connecting the various components of
the clock tree.

The clock signal generated by the clock source needs to be propagated to multiple destinations
across the chip. However, as the clock signal travels through the chip, it can experience signal
degradation due to factors such as parasitic capacitance, resistance, and inductance. This
degradation can lead to timing issues and unreliable operation of the circuit.

To mitigate these problems, buffers are inserted in the clock tree at strategic locations. Buffers
act as signal amplifiers and help to maintain the signal integrity and synchronization across the
chip. They drive the clock signal with sufficient strength to overcome the loading effects and
noise encountered along the signal path.

By using buffers, the clock signal can be distributed to different parts of the chip more efficiently.
The buffers drive the clock signal to multiple branches, ensuring that the clock arrival times are
balanced and that each part of the circuit receives the clock signal at the desired timing.

The clock tree is typically designed with a hierarchy of buffers, starting from the clock source and
branching out to various levels of the circuit. The buffer placement is carefully optimized to
ensure proper clock distribution, minimal skew (variation in arrival times), and balanced clock
tree paths.

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Double patterning (metal coloring)
Technology- advance node
Multiple patterning (or multi-patterning) is a class of technologies for manufacturing
integrated circuits (ICs), developed for photolithography to enhance the feature density.
It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and
beyond. The premise is that a single lithographic exposure may not be enough to provide
sufficient resolution. Hence additional exposures would be needed, or else positioning
patterns using etched feature sidewalls (using spacers) would be necessary.

Even with single exposure having sufficient resolution, extra masks have been
implemented for better patterning quality such as TSMC at its 22nm node. Even
for electron-beam lithography, single exposure appears insufficient at ~10 nm half-pitch,
hence requiring double patterning.

How double patterning works:

In single-pattern lithography, a wafer is covered with a light-sensitive material, known as
a photoresist. Light is then streamed through a patterned photomask (a template of the
chip, essentially). The light strikes the photoresist and changes the chemical properties of
the material. The wafer is then bathed in a chemical solution, which washes away the
areas the light touched. This process is repeated multiple times, and the end result is
(hopefully) a microprocessor.

When the silicon features become too small relative to the wavelength of light being used
to etch them, however, the defect density skyrockets. Double patterning — using two
photomasks, each with half of a pattern — can correct this, as shown below.

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Double patterning:
• M1 metal require a set of 2 masks
• Masks are referred as E1/E2 (Exposure1, Exposure2)
• The process of generating the two masks is call decomposing or coloring

• The decomposing can be done manually or with the DRC deck

• Decomposition can be done at the cell or chip level
• The basic requirement to allow decomposition is to avoid odd cycles

What is an odd cycle?

• Is a set of 3 or more metal patterns which can’t be decomposed because coloring

would lead to spacing violation on one of the masks (E1 or E2).
• The solution is to increase separation in at least one of the space between the
patterns

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Conclusion: Layout should be DRC checked to be odd cycle clean.

Video link :
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 13. DRC and LVS
Design Rule Check (DRC):
• Determines whether the layout satisfies the MOSIS design rules
• Checks for widths, separations and overlaps
• Differ with the process technology used
• DRC is computationally intensive – used on parts of ASIC separately
• Some commercial tools available for DRC are
1. Caliber by Mentor Graphics
2. PVS and Assura by Cadence
3. Hercules by Synopsys

Layout Vs Schematic (LVS):

• LVS tests for the functionality of the layout – created layout is functionally
same as schematic
• Performs 3 important steps
1. Extraction – Determines the semiconductor components represents in
the drawing
2. Reduction – Connects them in parallel or series to complete the circuit
3. Comparison – Compares layout netlist with schematic netlist to test the
functionality
• Reported Errors are
1. Shorts and Opens
2. Components Mismatch and Missing
3. Parameters Mismatch

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 14. SXCUT and PSUB2 layer
• SXCUT is the name used by GLOBALFOUNDRIES and Samsung for a CAD layer used
to define two or more region of substrate (ground/vss) for LVS purposes that are
electrically connected but has different name in schematic, and PSUB2 used in the
TSMC.
• The SXCUT/PSUB2 layer is also a useful layer for separating out analog and digital
grounds (e.g : VSSA and VSSD) for LVS purposes only
• SXCUT/PSUB must be used very carefully and only when it is absolutely necessary

SXCUT/ PSUB2 usage guidelines

• If the SXCUT layer must be used, please make sure the layout does not have any
SXCUT layer overlapping the DNW layer (DNW,S3,T3), as this may hide some real
shorts in the layout during LVS
• Overlap of SXCUT and DNW layer are usually flagged in ERC checks, but in some
cases, it may not be flagged, If SXCUT layer is used in the design, it is strongly
recommended that the LVS methodology described in the next slide is done before
tapeout
• Please note that ERC is not on by default, but it is STRONGLY recommended that
ERC is run for all tapeouts

SXCUT/PSUB2 usage – Recommended additional LVS check

If the SXCUT layer is used in a design, it is recommended that the following additional top
level LVS check is done

• On the schematic side, instantiate the top level symbol in a schematic and short
together all the pins connected to the P-substrate (e.g:VSSA and VSSD etc)

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 15. Parasitic capacitance and resistance

• As the Semiconductor industry is growing so does the density of devices on

chip. With the increasing density and decreasing spacing rules, the most
significant effect that takes birth is parasitic. Parasitics can be of resistance or
capacitance types, both have to be handled carefully.
• In VLSI applications the parasitic capacitance between signal lines can deplete
our whole design. At low frequencies parasitic capacitance can usually be
ignored, but in high frequency circuits it can be a major problem. For example,
in amplifier circuits with extended frequency response, parasitic capacitance
between the output and the input can act as a feedback path, causing the circuit
to oscillate at high frequency. These unwanted oscillations are called
parasitic oscillations.
• The parasitic capacitance arises from an electrical coupling between one signal line
and another signal line or a signal line and the substrate. In some designs it
becomes mandatory for us to reduce the parasitic capacitance of a particular net
with respect to other signal

Solution to decrease parasitic capacitance

• Use higher metals for the net in which parasitic capacitance are important.
• Increase the spacing of all the nets from the net which is critical (for which parasitic
capacitance is important).
• Put some other reference signal (with which parasitic capacitance is not so
important) in between the nets for which lower parasitic capacitance required. This
is shielding.
• Avoid too much parallel routing of metals.

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Parasitic Extraction of a MOSFET:

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Crosstalk induced noise:
The near and far end victim line currents sum to produce the near and far end
crosstalk noise.

Coupled currents:

• Current induced by capacitive coupling goes to both directions

• Current induced by inductive coupling goes opposite to the drive current

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 16. Sheet Resistance

Sheet resistance is an important concept in analog layout design. It refers to the

resistance per square that a material exhibits when current flows through it. In the
context of integrated circuits (ICs) and semiconductor devices, sheet resistance plays
a significant role in determining the electrical performance of analog circuits.

When designing analog layouts, the goal is to minimize parasitic resistances to

ensure accurate and efficient signal processing. Sheet resistance is a key parameter
that needs to be considered to achieve this objective. It primarily depends on the
resistivity of the material used and the dimensions of the conductive paths.

In IC fabrication, sheet resistance is influenced by factors such as the type of metal

used for interconnects, the thickness of the metal layer, and the doping
concentration in semiconductor regions. Lower sheet resistance allows for better
current flow and reduces voltage drop, resulting in improved performance and
reduced power consumption.

Resistance of a metal line

Sheet Resistance Concepts

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Sheet Resistance calculation :

Sheet Resistance (R_sheet)

= Resistivity (ρ) (Conductive Path Length (L)) / (Conductive Width (W))
= Rρ (L/W)

Here's a step-by-step guide on how to calculate the sheet resistance:

1. Determine the resistivity (ρ) of the material: The resistivity is a material property that
indicates its inherent resistance to current flow. It is typically provided in units of
ohm-meters (Ω·m). You can obtain the resistivity value from material datasheets or
literature.
2. Measure the dimensions of the conductive path: Determine the width (W) and length
(L) of the conductive path for which you want to calculate the sheet resistance. The
width is the dimension perpendicular to the current flow, while the length is the
dimension along the current flow direction.

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3. Calculate the sheet resistance: Plug the values of resistivity (ρ), width (W), and length
(L) into the formula mentioned above:
R_sheet = Rρ (L/W)

Example:-
• Resistance constance value will be given in the Technology Document,
• R = ƍL/tW, ƍ/t value will be given
• Try to make L/W =1 or make a squer unit
• Total number of squer unit = total length / width
• Total Resistance of wire = (Constance value ) X (total number of squer unit )

metal resistivity (Rρ) = 0.5ohm, W1 = 1um, W2 = 2um, L= 10um

Total Resistance 1 for w1 width = 0.5 x 10 = 5ohm

Total Resistance 2 for w2 width = 0.5 x 5 = 2.5ohm

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• Via Resistance:

• Vias made from Tungsten in Aluminum processes

• Vias made from Copper in Copper processes
• Via resistance significance in TSMC 180nm/0.18um technology

Diffusion –M1 11.0 Ω

Poly – M1 10.4 Ω
M2 – M1 04.5 Ω
M3 – M1 09.5 Ω
M4 – M1 15.0 Ω
M5 – M1 19.6 Ω
M6 – M1 21.8 Ω
• Use Multiple vias in parallel to reduce effective contact resistance
• Copper processes have lower via resistance

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 17. Electromigration (EM)

Electromigration (EM) is a phenomenon that occurs in metal conductors, particularly in

integrated circuits, due to the movement of atoms under the influence of high current
densities. It can lead to the degradation and eventual failure of the conductive paths.

During EM, the momentum transfer of highly accelerated electrons causes the atoms in
the metal conductor to migrate. This movement results in the thinning or void formation
within the metal, disrupting the continuity of the conductive path. Over time, EM-induced
damage can lead to open circuits, short circuits, or device malfunctions.

EM is more likely to occur in narrow and long interconnects where the current density is
higher. It is influenced by factors such as temperature, material properties, and the
magnitude of the current passing through the conductors. Higher temperatures and
higher current densities accelerate the rate of electromigration.

To mitigate the effects of EM, various strategies are employed in integrated circuit design.
These include widening the metal conductors, using materials with higher resistance to
electromigration, and implementing redundancy techniques to distribute the current
across multiple paths. Proper thermal management and current density optimization are
also crucial in reducing the risk of electromigration-related failures.

Overall, electromigration is an important consideration in integrated circuit design, and

appropriate measures are taken to minimize its detrimental effects on the reliability and
lifespan of electronic devices.

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Solution for EM failure:
• Increase Metal Width and Thickness: One approach is to increase the width and
thickness of the metal conductors involved in the EM failure. This helps to reduce
the current density and distribute the current more evenly, minimizing the risk of
electromigration-induced damage.
• Current Density Optimization: Analyse and optimize the current paths to ensure
that the current density is within safe limits. By redistributing the current flow and
adjusting the routing, you can alleviate the stress on specific interconnects prone to
EM failures.
• Implement Current Mirrors: Utilize current mirrors to reduce the current density in
critical paths. Current mirrors can replicate a lower current into higher currents,
reducing the load on vulnerable interconnects and minimizing the risk of EM
failures.
• Metal selection: switch the connected metal into higher metal layer.
• Insertion of Buffers
• Upsizing the driver cell
• Use metal stack
• Use parallel routing

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https://youtu.be/LcWnq6ccNaw

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 18. IR drop
IR drop, also known as voltage drop, refers to the voltage loss that occurs
along a conductive path due to the resistance of the path and the current
flowing through it. In analog layout design, managing IR drop is crucial to
ensure proper voltage levels and accurate signal processing. Excessive IR drop
can lead to degraded performance, reduced signal integrity, and even
functional failures in analog circuits.

To mitigate IR drop in analog layout design, you can follow these steps:

1. Power Planning: Effective power planning involves careful distribution of

power and ground networks to minimize resistance and ensure uniform
voltage distribution. Properly designed power grids and ground networks
with low resistance paths help reduce IR drop.
2. Optimal Routing: Pay attention to the routing of power and ground
traces. Use wider and shorter conductive paths to minimize resistance.
Routing power and ground traces in parallel and avoiding sharp corners
or narrow sections can help reduce IR drop.
3. Via Placement: Strategically place vias to connect power and ground
planes across different metal layers. Vias should be positioned in such a
way that they provide low-resistance paths for current flow, minimizing
IR drop. Proper via density and distribution can ensure efficient power
distribution.
4. Try to reduce the metal Resistance
5. Reduce the metal length by changing placement
6. Increase the width of the wire
7. Switch the net into higher metal layer
8. Use Metal stacking

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❖ How it effects the timing:
IR Drop is Signal Integrity effect caused by wire resistance and current
drawn off from Power (Vdd) and Ground (Vss) grid. According to Ohms law,
V=IR. If wire resistance is too high or the current passing through the metal
layer is larger than the predicted, an unacceptable voltage drop may occur.
Due to this un acceptable voltage drop, The power supply voltage
decreases. That means the required power across the design is not reaching
to the cells. This results in increased noise susceptibility and poor
performance.

• For example: a design needs to operate at 2 volts and has a tolerance of

0.4 volts on either side, we need to ensure that the voltage across its
power pin (Vdd) and ground pin (Vss) in that design does not fall short of
1.6 Volts. The acceptable IR drop in this context is 0.4 volts. That means
the design in this context can allow up-to 0.4 volts drop which does not
effects the timing and functionality of design

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 19. AnteNNa Error
• During chip processing, interconnect components are subject to plasma
etching. If the amount of charge collected on these conductor lines is
sufficient, it may damage or destroy the gate of transistor
• Antenna effect occurs only gate terminal because of present of oxide
layer which form capacitance.

Antenna basics:
• Mechanism -
✓ Damage is induced in the gate oxide due to plasma processing steps
including poly, inter-layer dielectric, contact, via and metal processing
✓ Due to lack of S/D diode to substrate (SOI), Source/Drains are also
susceptible
✓ Antenna protection is needed on all device terminals
• Design rule (refer to design manual antenna design section)
✓ A maximum ration is defined for metal area (or via) to the poly gate area
• Design impact
✓ Design time
✓ Adding diodes impacts parasitic
and linearity.

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❖ How to solve antenna effect ?
a. Reduce metal (or via) area until the maximum ration is met
b. Higher metal jumper to cut the large area lower layer metal (via) to
the gate
c. Use antenna diode (reverse biased) to add more discharge path
(area)
d. Well tie or substrate tie are also counted as “antenna diode” area
e. Most of the time, ESD diodes help fix the antenna violations at I/O
f. Antenna violations on nets with negative voltage swing need to be
fixed using back-to-back diode

• Metal Jumpers:
Charges accumulated with each etching process gets removed during
Planarization process so jumpers help transfer problem to next level

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• Antenna Diodes:
A diode helps dissipate charges accumulated on metals. An antenna
diode should be placed as near as possible to gate of device on lower
level of metal

• Adding Dummies:

➢ A dummy device can be used to increase the gate area. It helps when
ratio is little more than optimum.
➢ For large ratio, it would lead to the adding lot of dummies hence not
preferred.
➢ A dummy device can be used to form a diode and used. This process
takes lesser area than adding conventional antenna diode.
➢ This process has less complex DRC as compare to DRC in real antenna
diode

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Video link:
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 20. Latch-Up
SCR:
• The Forward Conduction Mode is the only mode at which the SCR will be in the ON
state and will be conducting. We can make the SCR conduct in two different ways,
one we can increase the applied forward bias voltage beyond the breakdown
voltage or else we can apply a positive voltage to the gate terminal.

• The IC has very low voltage, so the forward bias voltage it’s not happen. But If the
positive voltage applied at the gate of SCR will help the SCR to move to the
conduction state. During this mode of operation, the SCR will be operating in
forward bias and current will be flowing through it.

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Latch-up:

➢ Latch-up is type of short circuit which occurs in CMOS structure.

➢ Latch-Up is a condition where a low impedance path is created
between a supply pin and ground pin. This condition is caused by a
trigger (current injection or overvoltage)
➢ Latch-Up is not a risk if the voltage and current levels applied to the
device adhere to the absolute maximum ratings.
➢ Common reason due to positive & negative input & output voltage
spike signal.
➢ Exceeding the rail voltage than a diode voltage.
➢ There is a parasitic BJT form in CMOS, this spike signal triggered the
parasitic BJT.
➢ And it creates the low impedance path between VDD & VSS. So short
circuit happens between VDD & VSS.
➢ This will damage the IC permanently.

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 ➢ Another reason ESD & microwave interface & supply voltage is
exceeding the absolute maximum rating
➢ A common cause of latch-up is a positive or negative voltage spike
on an input or output pin of a digital chip that exceeds the rail
voltage by more than a diode drop
➢ Another cause is the supply voltage exceeding the absolute
maximum rating, often from a transient spike in the power supply.

Operation of Latch-Up:
➢ The equivalent circuit of the parasitic components of CMOS inverter
as shown in the below figure.
➢ When the signal at the output node is 0.7V higher than the VDD
(overshooting), the bipolar (VT2) may be turned on first and similarly
the bipolar (LT2) will be turned on while the output signal is lower
than -0.7V (undershooting).
➢ For the fact that the collector of each BJT (i.e. VT2) plays the role as
base of the other transistor (i.e. LT2) and the collected carriers will
reduce the potential difference between emitter and base of the
transistor (LT2).
➢ Under this situation, the positive feedback loop will make the
concentration of minority carrier increased to higher than the doping
concentrations of both the NW and PW
➢ Subsequently, the potential barrier NW and PW will be disappeared
and then obtains a highly conductivity path between VDD and VSS.
This may result in the circuit malfunction, and destroy the device in
the worst case

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 Shubham Kumar
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 ❖ How to solve latch-up problem?

1. NMOS and PMOS should be away from 15um to each other or from
ESD diode.
2. NMOS and PMOS should be close double guard ring
3. ESD circuit
4. STI – Silicon trench isolation (between PMOS & NMOS)
5. Deep N-well method
6. Adding the insulation layer between PMOS & NMOS
7. Device is fabricated with lightly doped epitaxy layer on heavily doped
substrate

Video link for latch-up

1. https://youtu.be/EYHFLBI5fjg
2. https://youtu.be/c-JbhXM0oIo

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 Shubham Kumar
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Condition1:

Solution:
1. NMOS and PMOS of pass gate1 should be in double close guardring or away from 15um to each other.
2. NMOS and PMOS of pass gate2 its need one guardring but it should be close.
3. Diffusion/OD width of guardringshould be follow to the technology minimum required width.

Condition2:

Solution:NMOS and PMOS should be in close guardring (single)or away from 15um-40um and more to
ESD diode.(spacing depend on technology)

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 21. Electro static discharge (esd)
What is an ESD

• Static electricity is the charge generated on the surface of dielectric materials. Static
electricity is discharged when positively and negatively charged objects are brought
into contact with or close to each other. This phenomenon is called an electrostatic
discharge (ESD). When a charged human body touches an electronic device, the
resulting ESD can be several thousand volts.
• Everyone who’s ever walked across a carpet then gotten a shock when they touched a
doorknob knows exactly what an ESD event is. In an integrated circuit (IC), an ESD event
typically induces electrical currents on the order of 0.1–10 amps, which lasts between
10-6 and 10-3 seconds, and dissipates energy on the order of 10–100 watts. ESD
protection methods shunt these ESD currents through unpowered devices (ESD
protection devices) along intended ESD discharge paths, while clamping the voltage at a
safe level, preventing any functional degradation to the protected devices.

Introduction to Electro Static Discharge (ESD) in ICs

ESD (Electrostatic discharge) failure is one of the critical reliability problems which have
been present in the IC industry for a long time. ESD failure accounts for almost 35% of the
total IC field failures and cost several billion dollars to the industry annually. There has
been an external protection method for ESD failures, but the electronics industry started
adopting dedicated on-chip ESD protection methods some time ago. Active research on
ESD fundamentals could answer many issues, but still there are grey areas to be
addressed. Predictive ESD CAD design is one of the areas of recent interest. Since the
development in the IC industry is fast paced, new ESD problems get introduced
continuously. The aim of the current work is to predict the optimum distance (“optimum
distance” in this document represents the “maximum distance” at which the ESD clamp
can be placed in an IO ring with reduced chances of ESD failure) for the placement of ESD
clamps so that chances of an ESD failure is reduced. This helps save time, effort and
money. An Electronic Design Automation (EDA) tool “IO Planner” is developed here so

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that the placement of clamps is done to a level where a chance of IC failure due to ESD
events is reduced. Any IC design engineer can use the “IO planner” tool as it does not
demand deep ESD knowledge from the engineer.

An ESD event is basically a charge balancing act between two objects at different
potentials. It can happen through direct contact or through induced electric field. An ESD
strike from different sources is illustrated in Figure 1-1.

Figure - ESD strikes from different sources

High voltage or current stress occurring for a very short interval of time is the
characteristic of an ESD event. Thus the impact of the event is so high that it can damage
the IC. The different damages caused by ESD failures are shown in Figure 1-2. Study of
ESD is a field where electrical, thermal and mechanical engineering join hands. The
solution to protect ICs from ESD events is to discharge the high current via a low
impedance shunting path or clamp the PAD voltage to a sufficiently low level or ground.

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Figure - Damages caused by ESD failures: (a) junction breakdown, (b) metal/via damage,
(c) gate oxide damage

Common ESD Failures:-

ESD failures are disastrous and can lead to instant malfunction of IC chips.

Junctions and oxides are prone to damages. The basic mechanisms for ESD induced failure
are:

1. Junction burnout in silicon: This is the most common HBM failure mechanism – the
injection of an ESD transient of energy can drive the junction into a breakdown.

2. Oxide breakdown: Another major category of ESD damage arises when a high voltage
applied across the oxide layer – high-voltage overstress – causes the dielectric to
breakdown. As the dielectric breaks down, it starts conducting current. The heat from the
current flow can produce hot spots and melt down the dielectric, silicon, and other
materials.

3. Metallization burnout: This produces openings in the interconnection paths. It

happens when the temperature – the I²R heat – reaches the material’s melting point. It is
commonly a secondary effect, occurring after junction or oxide failure.

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ESD Diode:

Layout top view of conventional (a) P diode stackup and (b) N diode stackup.

The diode stackup has been used as on-chip electrostatic discharge (ESD)
protection for some applications in which the input/output signal swing is
higher than VDD or lower than VSS. A novel ESD protection structure of
diode stackup is proposed for effective on-chip ESD protection

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ESD Protection ckt
There is different on-chip protection methods used for ESD protection. The rail-based ESD
protection circuit is one among them. In general, this scheme has a primary network,
secondary network and an RC-triggered power clamp

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Here, diodes D1, D2 form the primary network and D3, D4 form the secondary network.
M1 represents the clamping device which is triggered by the RC arrangement and three
series inverters. When the positive ESD pulse is induced on the PAD, there is no direct
path from the PAD to GND; diodes D1 and D3 are triggered on and the ESD current flows
through them to the power supply line and to GND through the triggered power clamp.
Design of each of the involved devices is done such that it is able to handle the ESD
current. For a negative ESD pulse, current enters the supply line, flows through the power
clamp and through the diodes D2, D4 to the GND line. Placement of the power supply
clamps determines the effectiveness of the IO protection in a rail-based ESD protection
arrangement. Therefore, it is advantageous if the 51 optimum distances to place power
clamps can be estimated so that the probability of failure in silicon is reduced. The work
presented here analyzes the ESD network and suggests the optimum distance to place
power clamps.

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ESD Test Models
Different test models, categorized by their origin, are used to simulate different ESD
events upon which ESD protection circuits are tested and qualified. The models are the
Human Body Model (HBM)/primary network, and the Charged Device Model
(CDM)/secondary network.

Primary ESD / HBM

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The HBM represents the ESD event which occurs when a charged human body or a
charged material touches the electronic circuit. Charge transfer happens through physical
contact.

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HMB Characteristics

• HBM models the ESD of a human body.

• Qualification level ≈ 2kv
• Pulse width ≈ 150ns
• Peak current ≈ 1.3A
• rise time ≈ 5-30ns

The main goal of ESD protection circuits is to provide a low-resistive discharge path
between any two pins in the chip (Vdd/Vss). The ESD clamp provides the discharge path
for an ESD event that happens between the two power rails (Positive stress at VDD node
while VSS node is grounded (PSD-mode), Positive stress at VSS node while VDD node is
grounded (NDS-mode)).

• Primary ESD protection: as close as possible to pad.

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Secondary ESD / CDM

The charged device model simulates the event where the un-grounded electronic parts
accumulate charge during manufacturing or assembly and then discharge to ground.
Unlike the HBM and MM event, CDM event involves a single pin on the module.

• CDM models the ESD of charged integrated circuits.

• Inductance in the model is mainly due to the inductance of bond wires.
• Peak current ≈ 10A, rise time ≈ 1ns.
• Gate oxide breakdown is the signature failure of CDM stress, in contrast to the
thermal failure signature of HBM stress.
• CDM stress has the fastest transient and has the max. peak current.
• CDM stress is the most difficult ESD stress to protect against.

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CDM Characteristics:

• Qualification Level ≈ 500V

• Pulse Width ~1.5ns
• Rise Time ≈100-300ps
• Peak Current ≈ 1-15A

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ESD to Device connection

Resistance b/w BUMP to diode connection should be less than resistance b/w
BUMP to device connection

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Layout sample of pad ESD protection:

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 22. clamp

The first step in designing an ESD power supply clamp is technology

characterization in which several aspects about the technology used and the
application must be known. Firstly, the breakdown voltage of the circuit core
due to an ESD stress should be known. Secondly, the target ESD protection
level should also be known in order to design an ESD protection circuit that
limits the voltage across the circuit core below the breakdown voltage. For
example, the oxide breakdown voltage for 65 nm CMOS technology is 5 V
and the target HBM is 1.5 kV [4]. Therefore, under 1.5 kV HBM stress the
voltage between the stressed pins should be less than 5 V to ensure the
correct functionality. Thirdly, based on the available components those can
be utilized as ESD clamping elements in the technology used and the target
application, the design decisions can be taken to tradeoff the ESD
performance, the design area, and the leakage current. For instance, silicon
controlled rectifier (SCR) has a high current carrying capability; however, it
cannot be used in an application where ionizing radiation or hot switching is
expected.

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 Shubham Kumar
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Power clamps are present inside each power supply IO. They are used to shunt current to
ground from power supply lines when an ESD event occurs or any event which can
potentially damage the electronic components. At the least, a chip will have three such
pins namely, VDDIO (IO-level power supply), VDDC (core-level power supply) and VGND
(ground for both supplies). The RC-triggered power clamp is a simple and efficient
implementation to achieve the same. One such typical RC-triggered power clamp is given
in Figure

Design of the RC network and the 3-stage inverter circuit is done according to the trigger
requirements for the clamp. The width of M1 (size of the transistor) is based on the
maximum value of current it will have to shunt.

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A power IO functions to provide a power supply for the chip. Power clamps which are part
of the IOs, help reduce risks due to ESD events for the chip. A rule of thumb is to have as
much power IOs, especially for the core power supply, as possible so that the chip is
supplied with stable and robust power.

ESD Clamps can be grouped into two categories: static and transient.

The static clamps provide a static or steady-state current and voltage response. A fixed
voltage level activates static clamps. As long as the voltage is above this level, the clamp
will conduct current. A diode, MOSFET and SCR based clamps are known as static ESD
clamps.

Transient clamps take advantage of the rapid changes in voltage and/or current that
accompanies an ESD event. During this transient, an element is turned on very quickly and
slowly turns off. This type of clamp conducts for a fixed time when it is triggered. An RC
network determines the time constant. These clamps are typically triggered by very fast
events on the supply lines.

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RC- triggered MOSFET

ELECTROSTATIC DISCHARGE (ESD) protection has become an important task in the pursuit
of the increased reliability of semiconductor ICs . Furthermore, while the required ESD
protection level is HBM 2 kV in most cases, in the Smart Power IC market the customer
requirements are more demanding because Smart Power ICs are used in harsher
environment than general logic IC. In smart power technology, high-voltage MOSFETs
have been used as on-chip ESD protection devices. Among them, the lateral diffused MOS
(LDMOS) and the drain extended MOS (DEMOS) have been widely used as common ESD
protection device because it can function both as output driver and as ESD protection

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LATCHUP OR LATCHUP-LIKE FAILURE IN ESD POWER CLAMP:

When high voltage MOSFETs such as LDMOS (lateral double diffused MOS) are used in
ESD protection clamps, they are used in “gate-grounded (gg)” configuration. However, as
stated in the Introduction, these ggLDMOSs have very low snapback holding voltages. The
TLP-measured I-V characteristic of a ggLDMOS. In the TLP measurements, pulses having
100 ns duration and 10 ns rise/fall time were used. theggLDMOS snaps back to only 9 V
after the triggering. This strong snapback characteristic of the LDMOS is related to the
turn-on behavior of the parasitic bipolar transistor and the occurrence of the Kirk effect
(base push-out effect) .

When a ggLDMOS is used as I/O clamps, a low holding voltage is helpful to sustain a much
higher ESD current because it leads to the smaller power dissipation. However, when
these are used in power clamps, a low holding voltage poses a threat. The power clamps
may be triggered on by noise transients or by a glitch on the power lines during normal
circuit operations. If the holding voltage of ESD power clamp devices is smaller than the
power supply voltage, the power clamp may not be turned off after being accidentally
turned on. This may cause very serious “latchup” or “latchup-like” failures and may lead
to IC malfunction or even destruction.

This latchup related danger can be avoided if the power supply clamp is designed in such
a way that the devices in the clamp do not enter the snapback region. No-snapback
LDMOSs are one of the ways to achieve this and active research is going on in this area.
However, the design of a new such device usually involves process modification, which is
very expensive. Therefore, in this work, we developed a circuit-level solution in which the
device in the power clamp does not enter snap-back region.

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 Principle of Operation

Fig: Schematic of the conventional RC-triggered MOSFET ESD power clamps

a: Rise Time Detector / RC- frequency discrimination circuit

b: Inverter drive circuit

c: MOSFET big clamp

We propose the use of “Darlington scheme” to overcome the latchup or latchup-like

issues in the design of power clamps for Smart Power ICs. Darlington scheme is an
enhanced RC-triggered MOSFET ESD power clamp. Therefore, we briefly review the basic
mechanism of RC-triggered MOSFET ESD power clamps first, and then we move on to the
explanation of the proposed power clamp.

Fig. 2 shows a schematic of conventional RC-triggered MOSFET ESD power clamps. It

consists of three elements: a) RC-frequency discrimination circuit, b) inverter drives
circuit, and c) big MOSFET clamp. Under an ESD transient event, the RC-frequency

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discrimination circuit detects a short ESD pulse, and drives the gate of MOSFET into the
active turn-on mode, forming a low-impedance discharge path to shunt ESD current.
Because of the raised gate voltage, the MOSFET operates below the triggering and does
not enter into the snapback region. Therefore, it can reduce the latchup or latchup like
dangers. The draw-back of the RC-triggered power clamps is the large area requirement.
In the RC-triggered MOSFET clamps, ESD current flows only through the channel region of
the MOSFET because of the absence of the parasitic bipolar action associated with the
snapback. Therefore, a very large MOSFET is required. Furthermore, the RC-frequency
discrimination circuit and the inverter drive circuit occupy additional considerable silicon
area.

To alleviate this area budgeting problem, we propose the Darlington scheme in Smart
Power ICs. By using Darlington configuration as the drive circuit, the silicon area of the
discrimination/drive circuit of the power clamp could be reduced by a factor of two when
compared to that of the conventional RC-triggered circuits.

Fig. 3 shows the schematic of the proposed ESD power clamp circuit using the Darlington
scheme. It consists of three parts, similar to the simple RC-triggered power clamp.
However, the inverter drive circuit in the conventional circuit was replaced by a small
LDMOS (M2) and a resistor. In the event of an ESD, M2 is turned on from the gate
coupling effect, and a current flows through the resistor R1. This current raises the
potential at node “n1” turning on the big LDMOS (M1). Because most of the ESD current
flows through M1, M2 does not need to be large. Therefore the inverter stages like the
one in Fig. 2 are not necessary between the RC network and M2. Therefore, the triggering
section of the proposed circuit can be made much smaller than that of the conventional
circuit

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(a): The overflow of electric charge shunts through the pull-up diode, and dissipates
through the power clamp. For the pull-up diode to effectively shunt the ESD currents, the
total resistance value of R0+R1+R3+R7+R9 must be within a maximum allowed limit.

(b): The
overflow of electric charge shunts through the pull-up diode, and dissipates through the
VDD power source. The total resistance value of R0+R1+R3+R7+R11 must be within a
maximum allowed limit.

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 (c): The
possible ESD discharge path runs between power pad VDD and ground pad VSS, which
goes through the power clamp. The total resistance value of R11+R9+R10+R12 must be
within a maximum allowed limit.

(d): The
possible ESD discharge path starts from the ESD resistor, passes through secondary ESD
protection (i.e., a pull-up diode), and ends at the power clamp. The total resistance value
of R5+R7+R9 must be within a maximum allowed limit.

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In (a)-(d), all metal interconnects and vias along the ESD discharge path must be robust
enough to withstand the ESD currents during the ESD event.

(e): The possible ESD discharge path starts at I/O pad A, goes through a pull-up diode, a power clamp, the B2B
diode, the ground bus VSSB, a pull-down diode, and eventually ends at I/O pad B. Not only must all metal
interconnects and vias along this ESD discharge path be robust enough to withstand the ESD currents, but their
effective total resistance value must be within a maximum allowed limit.

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 Shubham Kumar
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 B2B diode

. These elements are combined to form the back-to-back diode. This structure is
appropriate to external, first stage, protection for high voltage ICs. Combining in the same
component, high capacitors for filtering or decoupling, and efficient ESD protection, is a
great challenge in system-level consideration.

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Layout
In the circuit layout it is extremely important to have good floor planning and power
planning in place as well as a clean layout that passes DRC (Design Rule Check) and LVS
(Layout Versus Schematic) checks.

• Metallization is done up to Higher for drivers so that it has the ability to handle the
current even during a malfunction without breaking down.
• Drain routings for drivers extend as fingers and connect to the PAD which ensures that
there is no break down due to inability to handle current.
• Substrate contacts and guard rings are provided so that chances of latch-up are
reduced.
• ESD diodes are laid out as it is in the standard library.
• Decaps are added wherever possible, to help stabilize the power supply.
• Lower metal are used for signal routing.
• Higher metal are used for power routing and also metals are staked ; care is taken to
make the power plan as robust as possible by having wider metals and maximum
number of vias.
• The layout has no LVS or DRC errors.

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ESD Network Analysis
An ESD network analysis is done here in order to suggest the optimum distance for power
clamp placement. The aim of the approach is to find out how much margin is available for
the voltage drop at a power bus. According to the available margin, the optimum distance
at which a power clamp can be placed is suggested. Components of an ESD network are
shown in Figure 4-1. Only the parasitic resistance is considered for this analysis since
parasitic inductance is very small in GPIOs and the parasitic capacitance value which may
exist would actually take up some current and it can only reduce the chances of ESD
related failure.

D1, D2 :- Primary ESD protection network. D1 is referred to the HBM up-diode and D2
refers to the HBM down-diode in the following sessions of the report.

D3, D4 :- Secondary ESD protection network. D3 is referred to the CDM up-diode and D4
refers to the CDM down-diode in the following sessions of the report.

RCDM :- CDM resistance

RCLAMP :- Clamp resistance

RVDD :- VDD bus resistance

RVSS :- VSS bus resistance

R1 :- Diode to supply parasitic resistance

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R2 :- Diode to PAD parasitic resistance

P1 :- PMOS driver

N1 :- NMOS driver

P2, N2 :- Receiver transistors

Two failure mechanisms for transistors are considered here. They are junction breakdown
(source-drain junction) and gate-oxide breakdown during both an HBM event and a CDM
event, for both PMOS and NMOS transistors associated with it. Hence, there are three
variables available and there can be up to eight unique cases to be considered to ensure
that the IC does not fail due to an ESD event. When there is an HBM event, current flow is
from PAD to PAD, whereas for a CDM event, it is from PAD to VSS. Kirchhoff’s voltage law
is applied for the loop related to each case and the maximum possible value for RVDD and
RVSS is calculated. By knowing the resistance per µm for power buses, optimum distance
to place power clamps is calculated and suggested.

Figure 4-2 shows the current flow direction for an HBM event for which a junction
breakdown parameter for NMOS driver (N1 of IO-1) is evaluated. The HBM pulse
originates from PAD1 and flows to PAD2 through R2, D1, R1, RVDD, RCLAMP, RVSS and
D2.

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Figure 4-3 indicates the current flow direction for a CDM event for which the gate-oxide
breakdown parameter for the PMOS transistor (P2 of IO-1) is evaluated. The CDM pulse
originates from VDD and a major portion flows to PAD1 through RCLAMP, RVSS, R1, D2,
R2. A very small amount of current (~0.1%) takes the path through D4, RCDM from RVSS.

Video link for ESD:

1. https://youtu.be/hWxh3HVbcsg

2. https://youtu.be/plZIwt1Mlqw

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23. I/o Pads or Bond Pads or Wire Bonding

• Input/Output circuits (I/O pads) are intermediate structures connecting

internal signals from the core of the integrated circuit to the external pins of the
chip package.
• The circuitry on a chip has to connect with other circuits. These may be chips or
display devices, transducers or electro-mechanical devices and the capacitance
connected to the chip could be very large. In some cases, the devices being
driven will require or supply TTL signal levels, in others they may be liable to
be short circuits, have high noise levels or be liable to discharge spikes of
several kV. Each of these situations will require the imposition of circuitry to
interface the chip to the external environment. Most IC designers avoid the
problem of pad design and take pad drivers from standard libraries.
• Physically, pads are the squares of metal, generally 100-150 um square, that are
connected to the pins of the package with bonding wires. The word pad is often
used to also include the circuitry that is used to interface the CMOS logic within
the IC (typically composed of near minimum-geometry transistors) to the
outside world.
• At least two pads in each circuit will be used to connect the chip to the VDD and
VSS power supply lines, while other pads will be used for input connections and
output connections. Some pads may also be required to be bi-directional, (for
use both with input signals and output signals). In such cases there is usually a
control connection to determine the direction of signal transfer.
• An important function for all pad driver circuitry is the protection of the chip
circuitry against destruction due to overvoltage pulses or sustained
overvoltage’s. These may be due to electrostatic discharges or due to faults on
other circuitry that cause unexpectedly high voltages to be applied to the chip
pins.

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 Shubham Kumar
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24. Electrical Rule check / Softcheck
ERC: Checking for all electrical connections that are considered
dangerous.

Generally, checks the wells and substrate contacts

• Any floating N or P -Wells

• Any floating substrate
• N- Well tap connected to VSS/GND and P-Well tap connected to VDD/PWR
• Any unconnected inputs or shorted outputs
• Input gate of logic cell is directly connected to VDD or GND.
• Any floating poly
• Any floating DNW

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 25. Density

In analog layout design, "density error" refers to a violation or

deviation from the specified density rules or guidelines set by the
semiconductor foundry or design process. It occurs when the layout
design exceeds or falls short of the allowed density constraints in
certain regions or layers of the integrated circuit (IC). Density errors
can have significant implications for the manufacturing process and the
overall performance and reliability of the analog circuit.

There are two types of density errors that are commonly encountered:

1. Over-Density Error: This occurs when the layout design exceeds the
maximum allowed density in a specific area or layer. Over-dense
regions can lead to several issues, including difficulties in etching
and deposition processes, reduced process uniformity, and
increased risk of manufacturing defects. Over-dense areas can also
impact thermal management, electromigration, and signal integrity.

2. Under-Density Error: This occurs when the layout design falls below
the minimum required density in a specific area or layer. Under-
dense regions can result in poor coverage of interconnects,
compromised power distribution, reduced electrical performance,
and weakened mechanical strength. Under-dense areas may also
exhibit increased resistance, increased voltage drop, and
compromised reliability.

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 Instruction of density error
• There are some DRC rules obligating that the density of certain layers in the
layout does not get below or above a certain value.
Ex: Limits are typically 30% < density < 80% for metal
• The Density error not much important at the cell/block level, but usually
they are taken care of at the chip assembly step.
• However we don’t need to meet the density rules manually, usually there are
fill tools that come with the tool that will place dummy layer in the area
where the density is too low.
• Maximum density is exactly the opposite of the minimum density error.
• After the dummy fill is done, we don’t connect them to any potential. They
are left floating in the layout. Leaving the dummy fill floating will not affect
the circuit working because we take care of the DRC rules which will specify
spacing between the metal drawn layer and the metal dummy fill layer.
• If any net in the layout is parasitic critical, we usually don’t put dummy fills
over it to avoid any kind of capacitive effects.
• Due to the density issue, Due to a large variations in density can cause
thermal expansion stress
• Inserting dummy fill can help make uniform layers, this practice may
degrade the performance of sensitive analog circuitry of high-speed digital
blocks due to added parasitic capacitance

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To mitigate density errors in analog layout design, it is important
to follow the density rules and guidelines provided by the foundry
or design process. Here are some key strategies:

1. Design Rule Checking (DRC): Utilize DRC tools to perform thorough

checks for density violations during the layout verification process.
DRC tools can flag regions or layers with density errors, allowing
designers to identify and rectify the issues before fabrication.

2. Layout Optimization: Optimize the placement and routing of

components and interconnects to achieve a balanced density
distribution. Distribute the circuit elements effectively to avoid
over-dense or under-dense regions. Carefully manage the placement
of large components, high-density interconnects, or metal fills to
achieve a uniform density across the layout.

3. Metal Fill: In certain layers, the use of metal fills or dummy

structures can help achieve the required density. Metal fills are
additional metal structures inserted into under-dense regions to
increase density and ensure a more uniform layout. These fills do
not carry any electrical functionality but help to balance the density
distribution.

4. Collaboration with Process Engineers: Work closely with process

engineers and foundry representatives to understand the specific
density rules and guidelines. Seek their guidance during the design
process to ensure compliance with the manufacturing requirements
and to address any density-related concerns.

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How to fix min density of metal/Poly
• Add dummy metals / Poly (device) or dummy device on the vacant
space.

a) Min density error b) solution of min density error

How to fix Max density of metal/Poly

• Make space in between the metals / Poly (Device).

a) Max density error b) solution of max density error

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 26. High speed layout design

High Frequency clock Transmission:

• The effect of random signal lines on the on-chip inductance is quantitatively

investigated, using an S-parameter-based methodology and a full wave solver,
leading to an empirical model for high-frequency inductance. The results clearly
indicate that the random signal lines as well as designated ground lines provide
return paths for gigahertz-frequency signals. In particular, quasi TEM-wave-like
propagation mode is observed above 10 GHz, revealing a unique relationship
between capacitance and inductance of the signal line. Incorporating the
random capacitive coupling effect, our frequency-dependent RLC model is
confirmed to be valid up to 100 GHz.
• Short, medium, and long on-chip interconnections having line widths of 0.45-52
μm are analyzed in a five-metal-layer structure. We study capacitive coupling
for short lines, inductive coupling for medium-length lines, inductance and
resistance of the current return path in the power buses, and line resistive
losses for the global wiring. Design guidelines and technology changes are
proposed to achieve minimum delay and contain crosstalk for local and global
wiring. Conditional expressions are given to determine when transmission-line
effects are important for accurate delay and crosstalk prediction

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 Shubham Kumar
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Crosstalk:
Crosstalk is the unwanted coupling of signals between parallel traces. Proper routing
and layer stack-up through microstrip and stripline layouts can minimize crosstalk.

To reduce crosstalk in dual-stripline layouts, which have two signal layers next to
each other, route all traces perpendicular, increase the distance between the two
signal layers, and minimize the distance between the signal layer and adjacent plane.

Use the following steps to reduces crosstalk in either microstrip or stripline layouts:

• Widen spacing between signal lines as much as routing restrictions will allow. Try
not to bring traces closer than three times the dielectric height.

• Design the transmission line so that the conductor is as close to the ground plane as
possible. This technique will couple the transmission line tightly to the ground plane
and help decouple it from adjacent signals.

• Use differential routing techniques where possible, especially for critical nets (i.e.,
match the lengths as well as the gyrations that each trace goes through).

• If there is significant coupling, route single-ended signals on different layers

orthogonal to each other. Minimize parallel run lengths between single-ended signals.
Route with short parallel sections and minimize long, coupled sections between nets.
Crosstalk also increases when two or more single-ended traces run parallel and are
not spaced far enough apart. The distance between the centers of two adjacent traces
should be at least four times the trace width. To improve design performance, lower
the distance between the trace and the ground plane to under 10 mils without
changing the separation between two traces.

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Forward and reverse crosstalk waves created by capacitive and inductive
coupling:

Video link :https://youtu.be/0A941cqVP2A

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Signal Integrity
For a single-ended trace, like clock transmission line, it could be improved using the
following guidelines:

• Keep clock traces as straight as possible. Use arc-shaped traces instead of right-
angle bends.

• Do not use multiple signal layers for clock signals.

• Do not use via in clock transmission lines. Via can cause impedance change and
reflection.

• Place a ground plane next to the outer layer to minimize noise. If you use an inner
layer to route the clock trace, sandwich the layer between reference planes.

• Terminate clock signals to minimize reflection.

• Use point-to-point clock traces as much as possible.

• Make sure D > 2S to minimize the crosstalk between the two differential pairs.

• To minimize reflection noise, place the differential traces S = 3H as they leave the
device.

• Keep the distance between the differential traces (S) constant over the entire trace
length.

• Keep the length of the two differential traces the same to minimize the skew and
phase difference.

• Avoid using multiple via, because they can cause impedance mismatch and
inductance.

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 Clk routing Bends
A right angle in a trace can cause more radiation. The capacitance increases in the
region of the corner, and the characteristic impedance changes. This impedance
change causes reflections.

• Avoid right-angle bends in a trace and try to route them at least with two 45°
corners. To minimize any impedance change, the best routing would be a round bend
(see Figure).

• Separate high-speed signals (for example, clock signals) from low-speed signals and
digital from analog signals; again, placement is important.

• To minimize crosstalk not only between two signals on one layer but also between
adjacent layers, route them with 90° to each other.

Figure: Poor and Good Right Angle Bends

The use of vias is essential in most routings, but the designer has to be careful when
using them. They add additional inductance and capacitance, and reflections occur
due to the change in the characteristic impedance. Vias also increase the trace length.

• Avoid vias in differential traces. If it is impossible to avoid them, use vias in both
traces or compensate the delay also in the other trace.

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Clock Buffering Mechanisms
• Clock signal is global in nature.
1. Clock lines are typically very long.
2. Long wires have large capacitances, which limit the performance of the
system.
3. RC delay plays a big factor.

• RC delay cannot be reduced by making the wires wider.

1. Resistance reduces, but capacitance increases.

• To reduce RC delay, buffers are used.

1.Also helps to preserve the clock waveform.
2. Significantly reduces the delay.
3. May occupy as much as 5% of the total chip area.

Power Noise Filtering or Decap

To decrease the low-frequency (below 1 kHz) noise caused by the power supply, filter
the noise on power lines at the point where the power connects to the chip and to
each device. Place a capacitor where the power supply lines enter the chip. If you use
a voltage regulator, place the capacitor immediately after the pin that provides the
VDD signal to the device(s). (Capacitors not only filter low-frequency noise from the
power supply, but also supply extra current when many outputs switch
simultaneously in a circuit.) To filter power supply noise, place decoupling capacitors
as close as possible to each VDD and GND, make it less resistance from Decap to
pwr/Gnd pump or regulator.

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Power Distribution
A system can distribute power throughout the chip with either power planes or a
power bus network/grid. You can use power planes on multi-layer metals that consist
of two or more metal layers that carry VDD and GND to the devices. Because the
power plane covers the full area of the chip, its DC resistance is very low. The power
plane maintains VDD and distributes it equally to all devices while providing very
high current-sink capability, noise protection, and shielding for the logic signals on
the chip. It is recommended to use lower planes to distribute power. The power bus
network which consists of two or more wide metal traces that carry VDD and GND to
devices. When designing with power bus networks, be sure to keep the trace widths
as wide as possible. The main drawback to using power bus networks is significant
DC resistance. It is recommended to separate analog and digital power planes. For
fully digital systems that do not already have a separate analog power plane, it can be
expensive to add new power planes. However, you can create partitioned islands
(split planes). An example board layout with phase-locked loop (PLL) ground islands
is shown on Figure.

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If your system shares the same plane between analog and digital power supplies,
there may be unwanted interaction between the two circuit types. The following
suggestions will help to reduce noise:

• For equal power distribution, use separate power planes for the analog (PLL) power
supply. Avoid using trace or multiple signal layers to route the PLL power supply.

• Use a ground plane next to the PLL power supply plane to reduce power-generated
noise.

• Place analog and digital components only over their respective ground planes.

Ground Bounce
As digital devices become faster, their output switching times decrease. Faster
switching times cause higher transient currents in outputs as they discharge load
capacitances. These higher currents, which are generated when multiple outputs of a
device switch simultaneously from a logic high to a logic low, can cause a board-level
phenomenon known as Ground Bounce. Many factors contribute to ground bounce.
Therefore, no standard test method predicts ground bounce magnitude for all
possible chip environments. Determine each condition and each device’s relative
contributions to ground bounce by testing the device under these conditions. Load
capacitance, socket inductance, and the number of switching outputs are the
predominant conditions that influence the magnitude of ground bounce in
programmable logic devices.

It is recommended to follow some design methods to reduce ground bounce:

• Use wide, short traces between the via and capacitor pads, or place the via adjacent
to the capacitor pad.

• Traces stretching from power pins to a power plane (or island, or a decoupling
capacitor) must be as wide and as short as possible. This reduces series inductance,
and therefore, reduces transient voltage drops from the power plane to the power
pin.Thus, reducing the possibility of ground bounce.

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 • Connect each ground pin or via to the ground plane individually. A daisy chain
connection to the ground pins shares the ground path, which increases the return
current loop and thus inductance.

• Add the recommended decoupling capacitors for as many VDD/GND pairs as

possible.

• Place the decoupling capacitors as close as possible to the power and ground pins of
the device.

• Add external buffers at the output of a counter to minimize the loading on silicon
device pins.

• Configure the unused I/O pin as an output pin and then drive the output low. This
configuration acts as a virtual ground. Connect this low driving output pin to GNDINT
and/or the boards ground plane.

• Turn on the slow slew rate logic option when speed is not critical.

• Place the power and ground pins next to each other. The total inductance will be
reduced by mutual inductance, since current flows in opposite directions in power
and ground pins.

• Use a bigger via size to connect the capacitor pad to the power and ground plane to
minimize the inductance in decoupling capacitors.

• Use surface mount capacitors to minimize the lead inductance.

• Each GND pin/via should be connected to the ground plane individually.

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 27. Basic Circuits

• Tie-Hi & Tie-lo

The Ti cell is used for protect the transistor. With its very few connections
and a relatively simple circuit, tie-hi cell is found to be one of the most
important place in IC design, thus protecting all your logic gates from the
spurious disturbances happening at VDD, normally called as ‘voltage
droop’
The general idea is if you know or intend to provide constant logic ‘0’ or
logic ‘1’ to any inputs of your gates (for tie-hi, its logic ‘1’), then refrain
from directly connecting it to VDD, instead add a tie-hi cell in between VDD
and gate static input. Let tie-high receive the VDD and provide a clean
output of logic ‘1’ to static input of gate. And there’s proof, that any
disturbance in power or VDD line will just be filtered out at output of tie-hi
cell, thus protecting your gate oxide from damage

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 • Level shifter
A logic level shifter, or a voltage level translator, is used to translate
signals from one logic level (voltage) to another. Nowadays, most of the
system runs on 3.3V or 5V. Logic level is simply a HIGH and LOW level
of voltage for a certain board or IC. Knowing this, a logic level shifter is
necessary to create a path between processors, sensors, or boards of
different voltage levels.

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 28. SERDES
What is a SERDES?
• SERDES = serializer – deserializer
• Used to transmit high speed IO-data over a serial link in I/O interfaces to speeds
upward of 2.5Gbps.
• SerDes TX: transmit parallel data to receiver over high-speed serial-link.
• SerDes RX: receive data from serial link and deliver parallel data to next-stage.

SERDES LINKS: In modern times to take advantage of both topologies, often

applications involve both parallel and serial communications. A SerDes transceiver is one
such application. The main function of the SerDes system is to transmit data at high
speeds over a channel and receive the correct data at the receiver end. It facilitates the
transmission of data between parallel I/O ports over a serial link by sequential zing data.
Thus, the number of channels and pins are reduced. The SerDes becomes especially
beneficial for high data rates when the issues with parallel buses are more heightened.
For the implementation, CMOS technology proves to be the ideal choice due to its low
cost and low power consumption. The SerDes is primarily a mixed-signal circuit with
several analog as well as digital blocks to perform different functions.

Fig: The SerDes Link

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Advantage: Fast signaling, robust, high signal integrity.
• Low cost: Due to lesser number of pins and lower board space usage. The extra
space can be reused for other components.
• Less Crosstalk: Fewer conductors in proximity, thus serial links minimize cross-talk
• Clock skew issues: Parallel links face clock skew issues between parallel channels.
This becomes redundant for serial links as they usually use asynchronous and
unclocked data transmission.

Clock and Data Recovery (CDR)

Sometimes the data is sent over the channel without an accompanying clock signal.
The CDR block performs the role of generating a clock from the received data. It
receives the data at an approximately known frequency and then uses phase
alignment to align the generated clock to the transitions in the data. This clock and
retimed data is then used by the deserializer to recover the data. The aligned clock
now allows the data to be sampled at the middle of the eye and hence supports the
accurate recovery of data. The middle of the eye is also the most optimum point to
take a data sample as it has the least jitter usually.

Phase Locked Loop (PLL)

The Phase-locked-loop forms an essential part of the SerDes circuitry as it generates
the high frequency reference clock used to drive the serial transmitter. The reference
clock inputs are often required to meet tight electrical and jitter requirements as the
quality of the clock can have a significant impact on the links performance. The PLL is
primarily used as a frequency synthesizer and is responsible for stepping up the clock
frequency by using a divider in the feedback loop.

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A PLL in the most basic of terms is a feedback system. It constitutes of a Phase
Detector, charge pump loop filter and a voltage controlled oscillator. Figure 3.2 shows
a basic phase locked loop.

Fig: A Basic Phase Locked Loop

The PLL is said to achieve lock when the phase difference between the two input
signals becomes constant and the corresponding frequencies become equal. The
phase frequency detector (PFD) generates an error pulse for a phase difference
between the two signals. This error signal is often amplified and converted into an
analog signal by a charge pump. The analog output of the pump is passed onto the
loop filter which suppresses the high frequencies, enabling the DC component called
control voltage. This control voltage is the controlling input of the VCO which
determines the oscillation frequency of the VCO. The VCO changes its frequency to
accumulate enough phase for the PLL to achieve lock. The VCO output is fed back into
the PD for comparison.

SerDes TX
A Serializer/Deserializer (SerDes) transmitter (TX) is a component that
converts parallel data into a high-speed serial data stream for transmission
over a serial link. It is a crucial part of high-speed communication systems
and is commonly used in applications such as data transmission,
networking, and high-speed serial protocols.

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The SerDes TX performs the following key functions:

1. Parallel-to-Serial Conversion: The SerDes TX takes parallel data inputs,

typically in the form of multiple bits transmitted simultaneously, and
converts them into a serialized data stream, where the bits are
transmitted one after another.

2. Encoding: The parallel data is encoded using specific encoding schemes,

such as 8b/10b or 64b/66b encoding, to ensure reliable transmission,
provide error detection, and facilitate clock recovery at the receiver
end. Encoding schemes help maintain data integrity, improve signal
quality, and enable efficient data synchronization.

3. Clock Generation: The SerDes TX generates a high-speed clock signal

synchronized with the transmitted serial data stream. This clock signal
is crucial for the receiver to properly sample and decode the received
data. The clock generation circuitry ensures that the transmitted data is
synchronized and aligned with the receiver's clock.

4. Data Serialization: The parallel data is serialized by the SerDes TX,

meaning that the bits are transmitted sequentially over the serial link.
The serialization process may involve multiplexing techniques to
combine multiple parallel data streams into a single serial stream.

5. Output Driver: The SerDes TX includes an output driver that provides

the necessary voltage swing and current drive to transmit the serial
data stream over the serial link. The output driver ensures that the
transmitted signal meets the required signal amplitude and impedance
characteristics.

6. Signal Conditioning: In high-speed communication systems, the SerDes

TX may incorporate signal conditioning techniques to compensate for
signal impairments caused by transmission medium characteristics,
such as attenuation and inter-symbol interference. Techniques like pre-
emphasis and equalization may be employed to improve signal quality
and mitigate transmission errors.

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 SerDes RX
A Serializer/Deserializer (SerDes) receiver (RX) is a component that receives a high-speed
serial data stream over a serial link and converts it back into parallel data. It is a crucial
part of high-speed communication systems and is commonly used in applications such as
data transmission, networking, and high-speed serial protocols.

The SerDes RX performs the following key functions:

1. Serial-to-Parallel Conversion: The SerDes RX takes the incoming high-speed serial

data stream and converts it back into parallel data. The serialized bits are
deserialized, and multiple bits are simultaneously processed to reconstruct the
original parallel data format.
2. Decoding: The parallel data received from the SerDes RX is decoded using the
specific encoding scheme used by the SerDes TX during transmission. This decoding
process ensures the recovery of the original data and facilitates error detection and
correction.
3. Clock Recovery: The SerDes RX extracts the clock signal from the incoming serial
data stream to synchronize its operations with the transmitted data. Clock recovery
is crucial for proper sampling and synchronization of the received data.
4. Deserialization: The SerDes RX deserializes the received serial data stream,
converting it back into parallel data format. This process involves separating the
bits and distributing them to their respective parallel data lines.
5. Input Equalization: High-speed serial links are susceptible to signal degradation due
to channel attenuation, noise, and inter-symbol interference. The SerDes RX may
incorporate equalization techniques to compensate for signal distortions and
improve signal integrity. Equalization techniques help recover the original data by
mitigating the effects of channel impairments.
6. Error Detection and Correction: The SerDes RX may include error detection and
correction mechanisms to identify and correct transmission errors. Techniques such
as forward error correction (FEC) or cyclic redundancy check (CRC) may be
employed to ensure reliable data reception.

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 7. Output Buffers: The SerDes RX includes output buffers that provide the necessary
voltage swing and current drive to transmit the parallel data to subsequent stages
or processing units.

SerDes channel
A SerDes channel refers to the communication channel over which the serialized data is
transmitted between a Serializer/Deserializer (SerDes) transmitter (TX) and receiver (RX).
It represents the physical medium or link through which the high-speed serial data is
transmitted.

The SerDes channel can take various forms depending on the application and
communication requirements. It may include different types of transmission media, such
as copper cables, backplanes, printed circuit board (PCB) traces, or fiber optic cables. The
characteristics of the channel, including its length, impedance, bandwidth, and noise
characteristics, have a significant impact on the overall performance and reliability of the
SerDes link.

The channel can introduce various types of impairments or distortions to the transmitted
signal, which can affect the quality of the received data. Some common impairments in a
SerDes channel include:

1. Attenuation: Attenuation refers to the loss of signal strength as it travels through

the channel. It is typically dependent on the length and characteristics of the
transmission medium. Attenuation can degrade the signal quality and reduce the
effective communication distance.
2. Inter-symbol Interference (ISI): ISI occurs when the transmitted symbols interfere
with each other due to channel characteristics such as dispersion or multi-path
effects. ISI can distort the shape and timing of the received signal, leading to errors
in data recovery.
3. Noise: Noise in the channel can be introduced by various sources, including
electromagnetic interference (EMI) and crosstalk from neighboring signals. Noise
can corrupt the signal and increase the bit error rate (BER) in the received data.

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 4. Jitter: Jitter refers to the variation in the timing of signal transitions. It can be
caused by various factors, including clock mismatches, signal reflections, and noise.
Excessive jitter can lead to timing errors and impact the reliability of the data
transmission.

To ensure reliable data transmission over the SerDes channel, several techniques and
design considerations are employed, including:

1. Equalization: Equalization techniques, such as pre-emphasis and adaptive

equalization, are used to compensate for the effects of channel impairments.
Equalization helps to improve the signal integrity and mitigate the impact of
attenuation and ISI.
2. Clock and Data Recovery: The SerDes receiver incorporates clock recovery circuits
to extract the clock signal from the received serial data stream. The recovered clock
is then used for data sampling and synchronization.
3. Forward Error Correction (FEC): FEC techniques are employed to detect and correct
errors introduced during transmission. Additional redundant data is added to the
transmitted data, allowing the receiver to detect and correct certain types of
errors.
4. Channel Modeling and Simulation: Advanced design techniques involve channel
modeling and simulation to analyze the channel characteristics and optimize the
system performance. This helps in understanding and mitigating the effects of
channel impairments.

SerDes channels are designed and optimized based on the specific requirements of the
communication system, including the desired data rate, distance, noise immunity, and
available transmission media. By carefully considering channel characteristics and
implementing appropriate techniques, reliable and high-speed data transmission can be
achieved in SerDes-based communication systems.

Video link:
1.Serdes: https://youtu.be/608TPRam3G8

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29. Buffer chips / Data buffer
Buffer chips, also known as data buffers or buffer amplifiers, are electronic
components used to improve the driving capability, signal integrity, and overall
performance of digital communication or data transfer systems. They are commonly
used in various applications, including data buses, memory interfaces, high-speed
communication interfaces, and digital systems with multiple devices.

The primary function of a buffer chip is to isolate the driving capability of a signal
source from the load it is driving. It provides a low-impedance output that can drive
capacitive loads or multiple inputs without significantly degrading the signal quality. By
providing a high-current, low-impedance output, buffer chips ensure that the
transmitted signals can reach their destination with minimal distortion, reduced
propagation delay, and improved noise immunity.

Key features and benefits of buffer chips include:

1. Signal Amplification: Buffer chips can amplify weak or low-voltage signals to ensure
reliable transmission over long distances or through high-capacitance loads. They
provide a higher voltage swing, helping to overcome the voltage drop and ensuring
that the received signals are within acceptable voltage levels.

2. High-Speed Data Handling: Buffer chips are designed to operate at high speeds,
allowing them to handle fast data rates without introducing signal degradation. They
minimize signal reflections, signal distortion, and inter-symbol interference, ensuring
accurate data transmission.

3. Fan-out Capability: Buffer chips have the ability to drive multiple loads
simultaneously without significant degradation in signal quality. They provide a low-
impedance output that can supply sufficient current to multiple devices or inputs,
enabling effective signal distribution across the system.

4. Voltage Level Translation: Buffer chips can perform voltage level translation,
allowing for interfacing between devices with different voltage requirements. They can

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convert signals from one voltage level to another, ensuring compatibility and proper
signal communication between different parts of a system.

5. Signal Conditioning: Buffer chips may incorporate signal conditioning features such
as slew rate control, edge sharpening, and input/output impedance matching. These
features help improve signal integrity, reduce signal reflections, and minimize signal
distortion.

6. ESD Protection: Many buffer chips include built-in electrostatic discharge (ESD)
protection circuits to safeguard the components and the overall system against ESD
events, preventing damage from electrostatic discharge.

Buffer chips come in various types, such as single-ended buffers, differential buffers,
and bidirectional buffers, depending on the specific application requirements. They
are available in different package types, such as through-hole packages and surface-
mount packages, to accommodate different system designs and assembly processes.

When selecting a buffer chip, it is important to consider parameters such as voltage

compatibility, speed requirements, current drive capability, input/output voltage
levels, and package options to ensure proper integration and functionality within the
target system.

Overall, buffer chips play a crucial role in enhancing signal quality, enabling effective
data transmission, and improving the overall performance of digital communication
systems.

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30. Temperature sensor
A temperature sensor chip, also known as a temperature sensor integrated circuit (IC)
or temperature sensor module, is an electronic component designed to measure and
monitor temperature variations in a wide range of applications. These chips provide
accurate and reliable temperature readings, enabling temperature control,
monitoring, and thermal management in various systems and devices.

Temperature sensor chips are available in different types, each employing different
sensing principles. Here are a few commonly used temperature sensor chip types:

1. Thermocouples: Thermocouple-based temperature sensor chips utilize the principle

of the Seebeck effect, where temperature variations generate a voltage across the
junction of two dissimilar metals. Thermocouples are known for their wide
temperature range, durability, and compatibility with high-temperature environments.

2. Resistance Temperature Detectors (RTDs): RTD-based temperature sensor chips

utilize the change in electrical resistance of certain metals or alloys with temperature.
The most common RTD material is platinum (Pt), known for its high accuracy and
linearity. RTDs offer excellent stability and are suitable for precise temperature
measurements.

3. Thermistors: Thermistor-based temperature sensor chips use the temperature-

dependent resistance of semiconductor materials. Thermistors are classified into two
types: Negative Temperature Coefficient (NTC) thermistors, where resistance
decreases with increasing temperature, and Positive Temperature Coefficient (PTC)
thermistors, where resistance increases with temperature. Thermistors provide high
sensitivity and are commonly used in applications where cost-effectiveness is
important.

4. Integrated Circuit Temperature Sensors: These temperature sensor chips

incorporate a temperature sensor element along with signal conditioning and
calibration circuitry on a single IC. They are often based on semiconductor diodes or
transistors with temperature-dependent characteristics. Integrated circuit

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temperature sensors are compact, low-power, and offer digital outputs, making them
suitable for integration into various electronic systems.

Temperature sensor chips can provide analog or digital output, depending on the
specific chip and application requirements. Analog output sensors generate a voltage
or current proportional to the measured temperature, while digital output sensors
typically utilize communication protocols such as I2C or SPI to provide temperature
readings directly in a digital format.

When selecting a temperature sensor chip, important considerations include

temperature range, accuracy, response time, power consumption, calibration
requirements, output format, package type, and compatibility with the target system's
voltage levels and communication interfaces.

Temperature sensor chips find widespread use in industries such as automotive,

consumer electronics, industrial automation, healthcare, environmental monitoring,
and HVAC (heating, ventilation, and air conditioning) systems. They enable precise
temperature control, thermal protection, process monitoring, and overall system
reliability.

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31. Example of analog circuits
• DAC: This includes constant current source, amplifier using external Rset to
adjust full rang current and bias circuit.
• ADC: this includes comparator, amplifier, sample/hold switch, switching
capacitor and reference voltage resistor ladder.
• PLL: this includes VCO (delay stage) and charge pump (current mirror and
buffer/opamp)
• Bandgap: BJT, current mirror, bias circuit, differential amplifier and ratioed
resistor
• Operational Amplifier (Op-Amp) Circuit: Op-amps are widely used in analog
circuits for various applications, such as amplification, filtering, signal
conditioning, and mathematical operations. A basic op-amp circuit
configuration includes an inverting or non-inverting amplifier, summing
amplifier, difference amplifier, or integrator.
• Voltage Follower Circuit: A voltage follower, also known as a unity-gain
amplifier, produces an output voltage that is equal to the input voltage. It is
commonly used to provide impedance matching and buffering between
different stages of a circuit.
• Low-Pass Filter Circuit: A low-pass filter allows low-frequency signals to pass
through while attenuating high-frequency signals. It is used to remove noise or
unwanted high-frequency components from a signal.
• High-Pass Filter Circuit: A high-pass filter allows high-frequency signals to
pass through while attenuating low-frequency signals. It is commonly used to
eliminate DC offset or remove low-frequency interference from a signal.
• Band-Pass Filter Circuit: A band-pass filter allows a specific range of
frequencies, known as the passband, to pass through while attenuating
frequencies outside the passband. It is used to select or isolate a specific
frequency range from a signal.

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 32. Wafer Level Packaging (WLP)
Wafer-level packaging (WLP) is an advanced semiconductor packaging technology that
aims to integrate the packaging process with the wafer fabrication process. It involves
packaging multiple semiconductor devices or integrated circuits (ICs) at the wafer level,
before they are separated into individual chips.

Traditionally, ICs were packaged in a process called "chip-level packaging," where

individual die (chips) were packaged after they were separated from the wafer. However,
with the increasing complexity and miniaturization of semiconductor devices, WLP has
gained popularity due to its potential for cost reduction, improved performance, and
increased functionality.

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What is System in Package?

Components of SIP - Interconnections

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Security for Sip

Types

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Wire Bond

Bonding Techniques

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Flip Chip

Manufacturing Process

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What is a Silicon Interposer

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Interposer

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Advantages of the Silicon Interposer

Interconnection Types

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Overview

RDL- Redistribution Layer

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 Shubham Kumar
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UBM – Under Bump Metallization

Package Materials

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Summary

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 Shubham Kumar
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Future

Video link:
1. https://youtu.be/WMQtD4hDHak
2. https://youtu.be/igIm17Odkms

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 33. INDUSTRY EXAMPLE
Block diagram:

Example of Cell level:

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Example of a chip level layout:

Fig: Final Layout view of the test chip

Fig: Layout view of six-stacked RF power switch

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Fig: chip level Layout view

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Fig: chip level Layout view

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Fig: chip level Layout view

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Fig: Bond-wire diagram of RF power switch

Fig: Test PCB for the RF power switch

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Fig: Test PCB with mounted chip and other components

Fig: Measurement setup of the RF Switch

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LinkedIn profile link: - https://www.linkedin.com/in/shubham-kumar-4354b7135/

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 3D view links of devices

1. Planar: https://skfb.ly/oGOKI
2. FinFET: https://skfb.ly/oGOLU
3. FDSOI: https://skfb.ly/oGOMr
4. GAAFET: https://skfb.ly/oGOMz
5. MBCFET: https://skfb.ly/oIPSz

3D view of Inverter
1. FinFET tech Inverter :- https://skfb.ly/oGOLU
2. planar tech Inverter :- https://skfb.ly/oGOLC

3D view of Deep NWell : https://skfb.ly/oGTIz

3D view of Device Capacitor:

1. N-type device cap : https://skfb.ly/oGTII
2. P-type device cap : https://skfb.ly/oGTJy

LinkedIn profile link: - https://www.linkedin.com/in/shubham-kumar-4354b7135/

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 Let’s have a cup of coffee

"If you have found my work to be valuable and have gained

significant knowledge from this document, leading to success in
Real-world projects, effortlessly cracking interviews, triumphant
collage study and more, then I kindly request
the delightful gesture of a cup of coffee.
It would be a small appreciation is a symbol of the shared
enjoyment, treat, and happiness that comes with
professional growth."

“THANK YOU”
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 SHUBHAM KUMAR

Scan this code to pay a cup of coffee

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