COMPUTER ORGANIZATION AND DESIGN

RISC-V
Edition
The Hardware/Software Interface

Week 5
Instructions: Language of
the Computer (Chap. 2)
Contents
◼ Instruction formats
◼ R-format / S-format / I-format

◼ Operations
◼ Arithmetic / Logical / Conditional

◼ Operands
◼ Immediate / Register / Memory

Chapter 2 — Instructions: Language of the Computer — 2

Datapath With Control

Chapter 4 — The Processor — 3

RISC-V Encoding Summary

Chapter 2 — Instructions: Language of the Computer — 4

 §2.1 Introduction
Instruction Set
◼ The repertoire of instructions of a
computer
◼ Different computers have different
instruction sets
◼ But with many aspects in common
◼ Early computers had very simple
instruction sets
◼ Simplified implementation
◼ Many modern computers also have simple
instruction sets

Chapter 2 — Instructions: Language of the Computer — 5

The RISC-V Instruction Set
◼ Used as the example throughout the book
◼ Developed at UC Berkeley as open ISA
◼ Now managed by the RISC-V Foundation
(riscv.org)
◼ Typical of many modern ISAs
◼ See RISC-V Reference Data tear-out card
◼ Similar ISAs have a large share of embedded
core market
◼ Applications in consumer electronics, network/storage
equipment, cameras, printers, …

Chapter 2 — Instructions: Language of the Computer — 6

 §2.5 Representing Instructions in the Computer
Representing Instructions
◼ Instructions are encoded in binary
◼ Called machine code

◼ RISC-V instructions
◼ Encoded as 32-bit instruction words
◼ Small number of formats encoding operation code
(opcode), register numbers, …
◼ Regularity!

Chapter 2 — Instructions: Language of the Computer — 7

 §2.2 Operations of the Computer Hardware
Arithmetic Operations
◼ Add and subtract, three operands
◼ Two sources and one destination
add a, b, c // a gets b + c
◼ All arithmetic operations have this form
◼ Design Principle 1: Simplicity favours
regularity
◼ Regularity makes implementation simpler
◼ Simplicity enables higher performance at
lower cost

Chapter 2 — Instructions: Language of the Computer — 8

Arithmetic Example
◼ C code:
f = (g + h) - (i + j);
◼ Compiled RISC-V code:
add t0, g, h // temp t0 = g + h
add t1, i, j // temp t1 = i + j
sub f, t0, t1 // f = t0 - t1

Chapter 2 — Instructions: Language of the Computer — 9

 §2.3 Operands of the Computer Hardware
Register Operands
◼ Arithmetic instructions use register
operands

◼ RISC-V has a 32 × 64-bit register file

◼ Use for frequently accessed data
◼ 64-bit data is called a “doubleword”
◼ 32 x 64-bit general purpose registers x0 to x30
◼ 32-bit data is called a “word”

◼ Design Principle 2: Smaller is faster

◼ c.f. main memory: millions of locations

Chapter 2 — Instructions: Language of the Computer — 10

RISC-V Registers
◼ x0: the constant value 0
◼ x1: return address
◼ x2: stack pointer
◼ x3: global pointer
◼ x4: thread pointer
◼ x5 – x7, x28 – x31: temporaries
◼ x8: frame pointer
◼ x9, x18 – x27: saved registers
◼ x10 – x11: function arguments/results
◼ x12 – x17: function arguments

Chapter 2 — Instructions: Language of the Computer — 11

Register Operand Example
◼ C code:
f = (g + h) - (i + j);
◼ f, …, j in x19, x20, …, x23

◼ Compiled RISC-V code:

add x5, x20, x21
add x6, x22, x23
sub x19, x5, x6

Chapter 2 — Instructions: Language of the Computer — 12

Memory Operands
◼ Main memory used for composite data
◼ Arrays, structures, dynamic data
◼ To apply arithmetic operations
◼ Load values from memory into registers
◼ Store result from register to memory
◼ Memory is byte addressed
◼ Each address identifies an 8-bit byte
◼ RISC-V is Little Endian
◼ Least-significant byte at least address of a word
◼ c.f. Big Endian: most-significant byte at least address
◼ RISC-V does not require words to be aligned in
memory
◼ Unlike some other ISAs
Chapter 2 — Instructions: Language of the Computer — 13
Memory Operand Example
◼ C code:
A[12] = h + A[8];
◼ h in x21, base address of A in x22

◼ Compiled RISC-V code:

◼ Index 8 requires offset of 64
8 bytes per doubleword
◼

ld x9, 64(x22)
add x9, x21, x9
sd x9, 96(x22)

Chapter 2 — Instructions: Language of the Computer — 14

Registers vs. Memory
◼ Registers are faster to access than
memory
◼ Operating on memory data requires loads
and stores
◼ More instructions to be executed
◼ Compiler must use registers for variables
as much as possible
◼ Only spill to memory for less frequently used
variables
◼ Register optimization is important!

Chapter 2 — Instructions: Language of the Computer — 15

Immediate Operands
◼ Constant data specified in an instruction
addi x22, x22, 4

◼ Make the common case fast

◼ Small constants are common
◼ Immediate operand avoids a load instruction

Chapter 2 — Instructions: Language of the Computer — 16

RISC-V R-format Instructions
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

◼ Instruction fields
◼ opcode: operation code
◼ rd: destination register number
◼ funct3: 3-bit function code (additional opcode)
◼ rs1: the first source register number
◼ rs2: the second source register number
◼ funct7: 7-bit function code (additional opcode)

Chapter 2 — Instructions: Language of the Computer — 17

R-format Example
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

add x9,x20,x21
0 21 20 0 9 51

0000000 10101 10100 000 01001 0110011

0000 0001 0101 1010 0000 0100 1011 0011two =

015A04B316

Chapter 2 — Instructions: Language of the Computer — 18

RISC-V I-format Instructions
immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits

◼ Immediate arithmetic and load instructions

◼ rs1: source or base address register number
◼ immediate: constant operand, or offset added to base address
◼ 2s-complement, sign extended
◼ Design Principle 3: Good design demands good
compromises
◼ Different formats complicate decoding, but allow 32-bit
instructions uniformly
◼ Keep formats as similar as possible

Chapter 2 — Instructions: Language of the Computer — 19

RISC-V S-format Instructions
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

◼ Different immediate format for store instructions

◼ rs1: base address register number
◼ rs2: source operand register number
◼ immediate: offset added to base address
◼ Split so that rs1 and rs2 fields always in the same place

Chapter 2 — Instructions: Language of the Computer — 20

 §2.6 Logical Operations
Logical Operations
◼ Instructions for bitwise manipulation
Operation C Java RISC-V
Shift left << << slli
Shift right >> >>> srli
Bit-by-bit AND & & and, andi
Bit-by-bit OR | | or, ori
Bit-by-bit XOR ^ ^ xor, xori
Bit-by-bit NOT ~ ~

◼ Useful for extracting and inserting

groups of bits in a word
Chapter 2 — Instructions: Language of the Computer — 21
Shift Operations
funct6 immed rs1 funct3 rd opcode
6 bits 6 bits 5 bits 3 bits 5 bits 7 bits

◼ immed: how many positions to shift

◼ Shift left logical
◼ Shift left and fill with 0 bits
◼ slli by i bits multiplies by 2i
◼ Shift right logical
◼ Shift right and fill with 0 bits
◼ srli by i bits divides by 2i (unsigned only)

Chapter 2 — Instructions: Language of the Computer — 22

 AND Operations
◼ Useful to mask bits in a word
◼ Select some bits, clear others to 0
and x9,x10,x11

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000

x9 00000000 00000000 00000000 00000000 00000000 00000000 00001100 00000000

Chapter 2 — Instructions: Language of the Computer — 23

 OR Operations
◼ Useful to include bits in a word
◼ Set some bits to 1, leave others unchanged
or x9,x10,x11

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x11 00000000 00000000 00000000 00000000 00000000 00000000 00111100 00000000

x9 00000000 00000000 00000000 00000000 00000000 00000000 00111101 11000000

Chapter 2 — Instructions: Language of the Computer — 24

 XOR Operations
◼ Differencing operation
◼ Set some bits to 1, leave others unchanged
xor x9,x10,x12 // NOT operation

x10 00000000 00000000 00000000 00000000 00000000 00000000 00001101 11000000

x12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

x9 11111111 11111111 11111111 11111111 11111111 11111111 11110010 00111111

Chapter 2 — Instructions: Language of the Computer — 25

 §2.7 Instructions for Making Decisions
Conditional Operations
◼ Branch to a labeled instruction if a condition is
true
◼ Otherwise, continue sequentially

◼ beq rs1, rs2, L1

◼ if (rs1 == rs2) branch to instruction labeled L1

◼ bne rs1, rs2, L1

◼ if (rs1 != rs2) branch to instruction labeled L1

Chapter 2 — Instructions: Language of the Computer — 26

Compiling If Statements
◼ C code:
if (i==j) f = g+h;
else f = g-h;
◼ f, g, … in x19, x20, …
◼ Compiled RISC-V code:
bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit // unconditional
Else: sub x19, x20, x21
Exit: …
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer — 27
Compiling Loop Statements
◼ C code:
while (save[i] == k) i += 1;
◼ i in x22, k in x24, address of save in x25
◼ Compiled RISC-V code:
Loop: slli x10, x22, 3
add x10, x10, x25
ld x9, 0(x10)
bne x9, x24, Exit
addi x22, x22, 1
beq x0, x0, Loop
Exit: …

Chapter 2 — Instructions: Language of the Computer — 28

More Conditional Operations
◼ blt rs1, rs2, L1
◼ if (rs1 < rs2) branch to instruction labeled L1
◼ bge rs1, rs2, L1
◼ if (rs1 >= rs2) branch to instruction labeled L1
◼ Example
◼ if (a > b) a += 1;
◼ a in x22, b in x23
bge x23, x22, Exit // branch if b >= a
addi x22, x22, 1
Exit:

Chapter 2 — Instructions: Language of the Computer — 29

Branch Addressing
◼ Branch instructions specify
◼ Opcode, two registers, target address
◼ Most branch targets are near branch
◼ Forward or backward
◼ SB format:
imm imm
[10:5] rs2 rs1 funct3 [4:1] opcode

imm[12] imm[11]

◼ PC-relative addressing
◼ Target address = PC + immediate × 2

Chapter 2 — Instructions: Language of the Computer — 30

RISC-V Addressing Summary

Chapter 2 — Instructions: Language of the Computer — 31

RISC-V Encoding Summary

Chapter 2 — Instructions: Language of the Computer — 32

 §2.19 Fallacies and Pitfalls
Fallacies
◼ Powerful instruction  higher performance
◼ Fewer instructions required
◼ But complex instructions are hard to implement
◼ May slow down all instructions, including simple ones
◼ Compilers are good at making fast code from simple
instructions
◼ Use assembly code for high performance
◼ But modern compilers are better at dealing with
modern processors
◼ More lines of code  more errors and less
productivity

Chapter 2 — Instructions: Language of the Computer — 33

Fallacies
◼ Backward compatibility  instruction set
doesn’t change
◼ But they do accrete more instructions

x86 instruction set

Chapter 2 — Instructions: Language of the Computer — 34

 §2.20 Concluding Remarks
Concluding Remarks
◼ Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Good design demands good compromises
◼ Make the common case fast
◼ Layers of software/hardware
◼ Compiler, assembler, hardware
◼ RISC-V: typical of RISC ISAs
◼ c.f. x86

Chapter 2 — Instructions: Language of the Computer — 35