CTL (Synopsys Format) For Core Based Test
CTL (Synopsys Format) For Core Based Test
Abstract
As part of an industry wide effort IEEE is in the
process of standardizing the elements of test
technology such that plug & play can be achieved
when testing SoC designs. This standard under
development is a language namely, Core Test
Language (CTL), which is introduced in this paper.
CTL describes all necessary information for test
pattern reuse and the needs of test during system
integration. CTL syntax and its link to STIL are
explained with examples.
1 Introduction
Design Reuse Methodologies [11 have allowed for the
partitioning of effort needed to create a complete
design at the expense of communication between the
teams creating the design. Tasks when partitioned
across teams that are in close proximity to each other,
the teams can get together with frequent formal
meetings, Share C ~ - U K J ~dOctumWation Or discuss Figure 1: Usage of the CTL representation of the
problems informally in coffee breaks. This is a core in the creation of a generic test access
normal business process for any company that has a architecture.
reasonably sized project under way. This breaks
down when the design teams are separated in time
and space. To avoid Figure 1 shows a usage of CTL where the information
problems the process needs to be formalized and the about the core is represented in CTL. Using the CTL
interface between the partition (or core) providers and Of the ‘Ore a wrapper can be constmcted7 and the
the integrators needs to be standardized.This is where appropriate Test Access Mechanism (TAM) can be
indus&y-wide standards step in. A Core Test determined based upon the test constraints in the CTL
L~~~~~~~(CTL) is being developed to address the of the core [61[71[81. Once all the structures are in
interoperability needs of SoC test [2]. IEEE P1500 place the test patterns that are a part Of CTL can
[3][4] is proposing a standard wrapper with a CTL be re-targeted to the boundary Of the In this
interface to isolate the cores from the embedded example the core described by the CTL did not have a
environment. As a precursor to this, the VSI Alliance wrapper inside the ‘Ore.
[5] is defining a similar hardware architecture to be
replaced by the p15OO hardware when it becomes an CTL is the language to support the information
IEEE Standard. that the core provider needs to give the system
integrator such that the integrator can successfully
This paper is focusses on the Core Test Language test the WdXdded core and any user-defined logic
(CTL). Through this mechanism all test aspects of around the core. This language is broad enough to
cores can be described such that a system integrator describe p15009
and even IEEE 1149.1 L91
can integrate a core as a black box into a SoC and hardware as described in BSDL [101* The language
perform all the usual test tasks as though the core was constructs being defined in CTL with
a white box with test patterns to be reused. As shown Of digital their different test
in ~i~~~~1, CTL describes d l the information about methodologies and the different ways in which they
the core needed by the system integrator. The are integrated in the
language is designed to be manually written and
created and/or consumed by test automation tools. Since CTL is the formal means by which a core
provider supplies test information to the system
ITC INTERNATIONAL TEST CONFERENCE Paper 5.3
69-0/01$1 0.00 0 2001 IEEE
0-7803-71 131
integrator, it is important for this mechanism to not
restrict the way cores are designed. CTL is designed
to work with cores that come with any type of DfT
methodology. Furthermore, CTL also works with any
type of test methodology (structural tests that use the
stuck-at or delay fault model, Iddq tests and
functional tests).
2.1 Signals
The U 0 signals of a core define the boundary to
which test patterns are written. STIL defines a block Figure 3: Example pattern of an ATPG generated
of statements named Signals, within which the single test where the scan-in and scan-out operation
interface of the design is specified. are not overlapped.
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CLK 1
I
Figure 4: Example of a single ATPG test pattern
A0
where the protocol information is separated from the
data portion of the test.
AI
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These allow for complete representation of the There are numerous other blocks of statements in
information needed to test the core within an SOC. CTL that are not covered, since the complete syntax
of CTL is not the focus of this paper.
The Language: The primary task of CTL is to
describe information that allows for the reuse of test While every syntax description of STIL is part of
patterns. This brings a natural affinity for Test CTL, there is a distinct difference in the way the
Patterns to CTL. IEEE has standardized a format pieces of the CTL information are represented
called STIL to represent test patterns. The standard is relative to the origin of the syntax itself. Figure 6,
known as IEEE 1450 [ll]. It became the natural depicts the relationship between the STIL portion of
choice for the syntax for CTL information. CTL the CTL syntax and the syntax that is not part of
builds on STIL by leveraging off pattern information STIL.
available in STIL whenever appropriate without
replicating or creating any new syntax for the same.
Since CTL describes a number of concepts that a test 4 CTL for Design Configurations
pattern language is not intended to describe, new A typical SoC’s design for testability (DFT) would
syntax is created for CTL in a STIL-friendly way. follow a methodology where individual cores are
isolated from other logic during test of the SOC. This
CTL can be viewed as a superset of STIL in terms of isolation can be accomplished by using a boundary-
the syntax. Furthermore, some constructs in CTL can
scan like wrapper added to the periphery of the core.
also be viewed as a meta-language of STIL when it
comes to describing the patterns since it defines how Once bounded, the new wrapped core would support
the test data described in STIL should be interpreted. multiple modes (configurations) to allow for internal
testing of the original core embedded in its wrapper
STIL and the test of the logic external to the wrapped core.
STIL (Note: Although a wrapper is used in the example,
Independent Dependent CTL is not limited to describing wrapped cores.)
information information
Info Da
Test BSE Y z
-i--l-----
.................I.......i......................................
1 Bist Structures]
A B
SI so
Protocols ~~
. ~.
BCK CLK SE
SE Y=O Z=O n;
2; 1 SO Out { ScanOut 2; }
n 2; } BSO Out { ScanOut 2; }
A B
SI
I I
BCK CLK SE
A
pose EstablishMode
s1
I
I
! i
SI
BCK CLK SE
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The three modes are defined in the Environment (1) for a scan operation. This scan chain is described in
block of statements to be myN (2), myE (6) and myl the CTL of Figure 11.
(11). Using a TestMode statement, these modes are
identified to be the configurations for the following. BSE Y z
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Figure 12: Partial CTL code to describe test patterns
Figure 11: Partial CTL code to describe information that come with a core, for internal testing of the core.
for the wrapper scan chain of the example.
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STIL is the preferred format for the patterns that for a very controlled environment that is mostly
come with a core. However, test patterns in STIL available in a single company. CTL [2] is a new
come in many flavors and CTL requires that the data language that is created to allow for a general SoC
and protocol portion of the patterns be separated [12]. strategy that goes beyond controlled environments.
Figure 12 shows example patterns for the (wrapped)
core that has been used in the previous sections. The In this paper, the basic capabilities of the Core Test
patterns are defined in a PatternExec topPat. The Language are described. Examples are used to
PatternInformation block (4) identifies this top level describe
pattern to be used for Production test (5, 6). The 0 Design ConfigurationInformation.
actual patterns of the PatternExec exist in 0 Structural Information.
PatternBursts and are referenced in the 0 Test Pattern Information.
PatternInformation block of statements (7, 8). The This paper should not be interpreted to be an
PatternBurst in this example contains patterns that exhaustive description of CTL. There are numerous
are applied through Scan (8, 9). The fault coverage of syntax items of CTL that were not introduced. The
the patterns is described by CTL to be 96% of the CTL used reflects the latest syntax of the
StuckAt fault model (10, 11, 12, 13). standardization effort upon the time of writing this
paper and is subject to changes before it is finalized.
As mentioned earlier, the sequence information is
separated from the Patterns in CTL. As a result of this 9 Acknowlegements
separation the Macro which represents the sequence
is the entity that gets modified to reflect the The authors would like to thank Erik Jan Marinissen,
embedded environment. The macro that needs to Greg Maston and Ben Bennetts for their constructive
change is identified in this example as a DoTest criticism of this paper.
macro, implying that the sequence represented by the
macro is the application of a single test (14). In this References
case, the sequence is called non-overlapping, as the Michael Keating, Pierre Bricaud, Reuse
scan-in and scan-out operation of consecutive tests do Methodology Manual for System-on-a-Chip
not overlap. Designs, Kluwer Academic Publishers, Norwell,
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7 Beyond the Example CTL Web Site, http://grouper.ieee.org/groups/ctll
The example used describes the basic constructs for
CTL needed to describe information that comes with IEEE P1500 Web Site,
a core. The keywords used here are a limited subset http://grouper.ieee.ordgroups/l5OO/
of the keywords available in the language. Erik Jan Marinissen, Yervant Zorian, Rohit
Kapur, Tony Taylor, and Lee Whetsel, “Towards
CTL relies on protocols (Macros) to describe the a Standard for Embedded Core Test: An
needs for every configuration of the core. The Example,” in Proceedings ZEEE Znternational
protocols differ from design to design and can be of Test Conference (ZTC), 1999, pages 616-627.
any length. This is the fundamental mechanism
behind CTL’s design independence. VSI Alliance Web Site, httv://www.vsi.org/
Erik Jan Marinissen and Maurice Lousberg,
There are numerous other aspects to SoC designs that “Macro Test: A Liberal Test Approach for
have not been covered in this document. Most of Embedded Reusable Cores,” in Digest of Papers
these aspects deal with different design and test of ZEEE International Workshop on Testing
methodologies, such as Logic BIST, or diagnostic Embedded Core Based Systems (TECS), 1997,
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special mention here. CTL is designed to allow for
system integration activities to be performed within Erik Jan Marinissen, Rohit Kapur and Yervant
the realm of CTL itself. The conversion of test Zorian, “On Using IEEE P1500 SECT for Test
patterns that come with a core to the SoC level can be Plug-n-Play,” in Proceedings of the Zntemational
done by changing the Macros associated with the Test Conference (ZTC),2000, pages 770-777.
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details on this subject. Clemens Wouters, “A Structured And Scalable
Mechanism for Test Access to Embedded
8 Conclusions Reusable Cores,” in Proceedings IEEE
SoC test itself has been performed in numerous ways Znternational Test Conference (ZTC), 1998, pages
in the past. The problems encountered are well known 284-293.
and solutions have existed in the industry that work
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