ENGINEERING NOTES

ON
VLSI DESIGN
(18EC72)

MODULE 05
SEMICONDUCTOR MEMORIES
TESTING & VERIFICATION

by
MOHAMED ANEES
Assistant Professor
Department of Electronics & Communication
Vidyavardhaka College of Engineering, Mysore
https://vvce.ac.in/

Note: In case of mistakes, please inform @9620195073

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TABLE OF CONTENTS

1.0 SEMICONDUCTOR MEMORIES ................................................................................................... 3

1.1 INTRODUCTION ........................................................................................................................................... 3
1.2 EQUIVALENT CIRCUITS OF MEMORY CELLS ...................................................................................... 4
1.2.1 DRAM......................................................................................................................................................................... 4
1.2.2 SRAM ......................................................................................................................................................................... 4
1.3 CONCEPTUAL RAM ARRAY ORGANIZATION ...................................................................................... 5
1.4 DYNAMIC RANDOM ACCESS MEMORY (DRAM) ................................................................................. 6
1.4.1 CONFIGURATIONS OF DRAM CELL .................................................................................................................... 6
1.4.2 OPERATION OF THREE TRANSISTOR DRAM CELL ......................................................................................... 8
1.5 STATIC RANDOM ACCESS MEMORY (SRAM) .................................................................................... 11
1.5.1 FULL CMOS SRAM CELL ..................................................................................................................................... 11

2.0 TESTING AND VERIFICATION ................................................................................................... 12

2.1 INTRODUCTION ......................................................................................................................................... 12
2.1.1 TYPES OF TESTS.................................................................................................................................................... 12
2.1.2 FAULT ...................................................................................................................................................................... 12
2.1.3 TESTING A DIE ...................................................................................................................................................... 12
2.1.4 COST OF FAULT .................................................................................................................................................... 13
2.1.5 LOGIC VERIFICATION.......................................................................................................................................... 13
2.1.6 DEBUGGING ........................................................................................................................................................... 14
2.1.6.1 LAB RUN TESTS .............................................................................................................................. 14
2.1.6.2 POINTERS FOR REASONABLE DEBUGGING ............................................................................. 15
2.1.7 MANUFACTURING TESTS ................................................................................................................................... 16
2.2 LOGIC VERIFICATION PRINCIPLES ....................................................................................................... 17
2.2.1 TEST VECTORS ...................................................................................................................................................... 17
2.2.2 TESTBENCHES OR HARNESSES ......................................................................................................................... 17
2.2.3 REGRESSION TESTING ........................................................................................................................................ 18
2.2.4 VERSION CONTROL ............................................................................................................................................. 18
2.2.5 BUG TRACKING..................................................................................................................................................... 18
2.3 MANUFACTURING TEST PRINCIPLES .................................................................................................. 18
2.3.1 FAULT MODELS .................................................................................................................................................... 18
2.3.1.1 STUCK-AT FAULTS ........................................................................................................................ 18
2.3.1.2 SHORT-CIRCUIT (STUCK SHORT) AND OPEN-CIRCUIT (STUCK OPEN) FAULTS................ 19
2.3.2 OBSERVABILITY ................................................................................................................................................... 19
2.3.3 CONTROLLABILITY ............................................................................................................................................. 20
2.3.4 REPEATABILITY.................................................................................................................................................... 20
2.3.5 SURVIVABILITY .................................................................................................................................................... 20
2.3.6 FAULT COVERAGE ............................................................................................................................................... 20
2.3.7 AUTOMATIC TEST PATTERN GENERATION (ATPG) ..................................................................................... 21
2.3.8 DELAY FAULT TESTING ...................................................................................................................................... 21
2.4 DESIGN FOR TESTABILITY ..................................................................................................................... 22
2.4.1 AD HOC TESTING .................................................................................................................................................. 22
2.4.2 SCAN DESIGN ........................................................................................................................................................ 22
2.4.2.1 SERIAL SCAN .................................................................................................................................. 23
2.4.2.2 PARALLEL SCAN ............................................................................................................................ 23
2.4.3 BUILT-IN SELF-TEST (BIST) ................................................................................................................................ 24
2.4.3.1 PSEUDO-RANDOM SEQUENCE GENERATOR (PRSG) .............................................................. 24
2.4.3.2 BIST .................................................................................................................................................. 26
VTU QUESTIONS ......................................................................................................................................... 27

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1.0 SEMICONDUCTOR MEMORIES

1.1 INTRODUCTION
• Semiconductor memory arrays capable of storing large quantities of digital information are
essential to all digital systems. The amount of memory required in a particular system depends on
the type of application, but, in general, the number of transistors utilized for the information (data)
storage function is much larger than the number of transistors used in logic operations and for
other purposes.
• There are three key design criteria’s:
o Area efficiency – It refers to the number of stored data bits per unit area and defines cost per
area.
o Access time – the time required to store and/or retrieve a particular data bit in the memory
array. The access time determines the memory speed.
o Power consumption – low power consumption.
• Random Access Memory (RAM)
o Read/write (R/W) memory must permit the modification (writing) of data bits stored in
the memory array, as well as their retrieval (reading) on demand. The read/write memory
is commonly called Random Access Memory (RAM).
o The stored data is volatile; i.e., the stored data is lost when the power supply voltage is
turned off.
o Based on the operation type of individual data storage cells, RAMs are classified into two
main categories.
a) Dynamic RAMs (DRAM)
- The DRAM cell consists of a capacitor to store binary information, 1 (high voltage) or
0 (low voltage), and a transistor to access the capacitor.
- Cell information (voltage) is degraded mostly due to a junction leakage current at the
storage node. Therefore, the cell data must be read and rewritten periodically (refresh
operation) even when memory arrays are not accessed.
- Due to the advantage of low cost and high density, DRAM is widely used for the main
memory in personal and mainframe computers.
b) Static RAMs (SRAM)
- SRAM cell consists of a latch, therefore, the cell data is kept as long as the power is
turned on and refresh operation is not required.
- SRAM is mainly used for the cache memory in microprocessor, mainframe computers
and hand-held devices due to high speed and low power consumption.

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1.2 EQUIVALENT CIRCUITS OF MEMORY CELLS
1.2.1 DRAM
• The DRAM cell consists of a capacitor
and a switch transistor.
• The data are stored in the capacitors as
presence and absence of charge. The
presence of charge in the capacitor is
considered as data ‘1’ while the absence
of charge in the capacitor as data ‘0’.
• The stored charge is subject to gradual
Fig.: DRAM – Equivalent Memory Cell decay due to leakage current, thus
refresh operation is required.

1.2.2 SRAM

Fig.: SRAM – Equivalent Memory Cell

• The SRAM cell has a six-transistor latch structure to hold the state of each cell node.
• Since the cell data can be held indefinitely at one of the two possible states of the bistable latch
as long as power supply is provided, the refresh operation is not needed in SRAMs.

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1.3 CONCEPTUAL RAM ARRAY ORGANIZATION
A conceptual memory array organization is as shown in figure.

Fig.: Conceptual RAM Array Organization

• The data storage structure consists of individual memory cells arranged in an array of horizontal
rows and vertical columns.
• Each cell is capable of storing one bit of binary information.
• In this structure, there are 𝟐𝐍 rows, also called 𝒘𝒐𝒓𝒅 𝒍𝒊𝒏𝒆𝒔, and 𝟐𝐌 columns, also called bit
lines. Thus, the total number of memory cells in this array is 𝟐𝑵 𝐱 𝟐𝑴 .
• To access a particular memory cell, the corresponding word line and the corresponding bit line
must be selected according to the addresses coming from outside of the memory array. These
addresses are provided by the memory controller or the processor directly.
• The row and column selection operations are accomplished by row and column decoders,
respectively.

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• The row decoder circuit selects one out of 2𝑁 word lines according to an N-bit row address,
while the column decoder circuit selects one out of 2𝑀 bit lines according to an 𝑀 − 𝑏𝑖𝑡 column
address.
• Once a memory cell is selected, a data read or write operation is performed on the selected single
or multiple bits on a particular row.
• Other chip control signals, e.g., 𝐶ℎ𝑖𝑝 𝑆𝑒𝑙𝑒𝑐𝑡 (𝐶𝑆), 𝑊𝑟𝑖𝑡𝑒 𝐸𝑛𝑎𝑏𝑙𝑒 (𝑊𝐸), are also provided to
activate the read or write operation of the particular memory chip out.

1.4 DYNAMIC RANDOM ACCESS MEMORY (DRAM)

1.4.1 CONFIGURATIONS OF DRAM CELL
FOUR TRANSISTOR DRAM CELL

Fig.: Four transistor DRAM cell with two storage nodes

• The four-transistor cell shown in the figure is one of the earliest dynamic cells from the 1970’s.
• Its “write” and “read” operations are similar to those of the SRAM cell.
• Write Operation
In the “write” operation, a word line is enabled and complementary data are written from a pair
of bit lines. Charge is stored at the parasitic and gate capacitances of a node connected with a
high voltage bit line. Since no current path if provided to the storage nodes for restoring the
charge lost due to leakage, the cell must be refreshed periodically.
• Read Operation
In the “read” operation, the voltage of a bit line is discharged to the ground through the
transistor where the gate is charged with the high voltage. The read operation is non-
destructive since the voltage stored at the node is maintained during the read operation.
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THREE TRANSISTOR DRAM CELL

Fig.: Three transistor DRAM cell with two-bit lines and two-word lines

• The three-transistor DRAM cell utilizes a single transistor (M3) as the storage device and one
transistor each for “read” and “write” access switches.
• Write Operation
During the “write” operation, the “write” word line is enable and the voltage of the “Write” bit
line is passed onto the gate of storage device through the M1 transistor
• Read Operation
During the “read” operation, the voltage of the “read” bit line is discharged to the ground the
M2 and M3 transistors when the gate voltage of the storage device is high. The read operation
of the three-transistor DRAM cell is also non-destructive and relatively fast.

TWO AND ONE TRANSISTOR DRAM CELL

Fig.: Two-transistor DRAM cell Fig.: One-transistor DRAM cell

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• The two-transistor and one-transistor DRAM cells have explicit storge capacitors. This means
that a separate capacitors(s) must be manufactured for each storage cell, instead of relying on
the gate and diffusion capacitances of the transistors for data storage.
• The one-transistor DRAM cell has become the industry-standard dynamic RAM cell in high-
density DRAM arrays.
• In the “write” operation after the word line is enabled, the data are written into the cell through
M1(or M2) transistor and stored at the storage capacitor.
• The read operation is destructive. When the charge stored in the storage cell is shared with the
bit line, its charge cab changed significantly (destructed).
• Also, since the capacitance of the bit line is larger than that of the storage cell by about 10
times, only a small voltage difference is produced at the bit line depending on the voltage level
(data) of the storage cell. Therefore, an amplifier to sense the signal difference and rewrite the
data into the cell (charge restoring operation) is required for the successful “read” operation.

1.4.2 OPERATION OF THREE TRANSISTOR DRAM CELL

The circuit diagram of a typical three-transistor dynamic DRAM cell is shown in figure.

Fig.: Three Transistor DRAM Cell

Here, the binary information is stored in the form of charge in the parasitic node capacitance 𝐶1 . The
storage transistor M2 is turned on or off depending on the charge stored in 𝐶1 , and the pass
transistors M1 and M3 act as access switches for data read and write operations. The cell has two
separate bit lines for “data read” and “data write” and two separate word lines to control the access
transistors.
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Precharge Events
- The precharge events are driven by ∅1 , whereas the
“read” and “write” events are driven by ∅2 .
- Every “data read” and “data write” operation is
preceded by a precharge cycle, which is initiated with
the precharge signal PC going high.
- During the precharge cycle, the column pull-up
transistors are activated, and the corresponding column
capacitances C2 and C3 are charged up to logic-high
level.
- All “data read” and “data write” operations are
Fig.: Column capacitances C2 and performed during the active ∅2 phase, i.e., when PC is
C3 are being charged-up through low.
MP1 and MP2 during the precharge
Cycle.

Figure depicts the typical voltage waveforms associated with the 3-T DRAM cell during a sequence
of four consecutive operations: write “1”, read “1”, write “0”, and read “0”.

Fig.: Typical voltage waveforms associated with the 3-T DRAM cell during four consecutive
operations: : write “1”, read “1”, write “0”, and read “0”.

Write “1” and Read “1” operations

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Write “0” and Read “0” operations

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1.5 STATIC RANDOM ACCESS MEMORY (SRAM)

1.5.1 FULL CMOS SRAM CELL
Q) Explain full CMOS SRAM cell with necessary circuit topology. [Mar 2022, 08 M]
Answer:
The circuit structure of the full CMOS static RAM cell is shown in the figure along with the pMOS
column pull-up transistors on the complementary bit lines.

Fig.: Circuit topology of the CMOS SRAM cell

• The memory cell consists of a simple CMOS latch (two inverters connected back-to-back), and
two complementary access transistors (M3 and M4).
• The cell will preserve the state as long as the power supply is available.
• The access transistors are turned on whenever a word line (row) is activated for read or write
operation, connecting the cell to the complementary bit-line columns.
• Advantages
- Very small static power dissipation (limited to leakage current).
- High noise immunity (large noise margin).
- Ability to operate at lower supply.
• Disadvantages
- Cell area slightly larger, latch-up phenomena.

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2.0 TESTING AND VERIFICATION
2.1 INTRODUCTION
2.1.1 TYPES OF TESTS
Tests fall into three main categories.
a) Functionality tests or logic verification
This test verifies that the chip performs its intended function. These tests are run before tapeout to
verify the functionality of the circuit. The second set of tests are run on the first batch of chips that
return from fabrication. These tests confirm that the chip operates as it was intended and help
debug any discrepancies. For example, a new microprocessor can be placed in a prototype
motherboard to try to boot the operating system.

b) Silicon debug
This silicon debug requires creative detective work to locate the cause of failures because the
designer has much less visibility into the fabricated chip compared to during design verification.

c) Manufacturing tests
The third set of tests verify that every transistor, gate, and storage element in the chip functions
correctly. These tests are conducted on each manufactured chip before shipping to the customer to
verify that the silicon is completely intact.

2.1.2 FAULT
• The yield of a particular IC was the number of good die divided by the total number of die per
wafer.
• Because of the complexity of the manufacturing process, not all die on a wafer function
correctly.
• Dust particles and small imperfections in starting material or photomasking can result in bridged
connections or missing features. These imperfections result in what is termed a fault.

2.1.3 TESTING A DIE

Testing a die (chip) can occur at the following levels:
• Wafer level
• Packaged chip level
• Board level
• System level
• Field level

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2.1.4 COST OF FAULT
• By detecting a malfunctioning chip early, the manufacturing cost can be kept low.
• For instance, the approximate cost to a company of detecting a fault at the various levels is as
mentioned in the table. if faults can be detected at the wafer level, the cost of manufacturing is
lower.
Level Cost to the company
Wafer $0.01–$0.10
Packaged chip $0.10–$1
Board $1–$10
System $10–$100
Field $100–$1000

• In an extreme example, Intel failed to correct a logic bug in the Pentium floating point divider
until more than 4 million units had shipped in 1994. IBM halted sales of Pentium-based
computers and Intel was forced to recall the flawed chips. The mistake and lack of prompt
response cost the company an estimated $450 million.

2.1.5 LOGIC VERIFICATION

• A designer first conducts Logic Verification tests as part of the design process. For example,
does this adder add? does this counter count?
• Figure shows functional equivalence at various levels of abstraction.

Fig.: Functional equivalence at various levels of abstraction

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• The behavioural specification might be a high-level computer language such as C, or a hardware
description language such as VHDL or Verilog, or simply a table of inputs and required outputs.

• Functional equivalence involves running a simulator at gate level and functional level of the chip.
Outputs are checked at for all the inputs applied at convenient check points. This is most
conveniently done in an HDL by employing a test bench.

• RTL level description - the behaviour at a system level may be able to be fully verified. For
instance, in the case of a microprocessor, one can boot the operating system and run key programs
for the behavioural description. However, this might be impractical due to long simulation times for
a gate-level model and even harder for a transistor-level model.

• Functional tests should be written to simulate as closely as possible the way in which the chip or
system will be used in the real world. Often, this is impractical due to slow simulation times and
extremely long verification sequences.

• One approach is to move up the simulation hierarchy as modules become verified at lower levels.
Verification at the top chip level using an FPGA emulator offers several advantages over
simulation and close to real time.

2.1.6 DEBUGGING
2.1.6.1 LAB RUN TESTS
When a chip returns from fabrication, several tests are run in a lab environment.
• Construct a circuit board that provides the following attributes:
o Power for the IC with ability to vary VDD and measure power dissipation
o Real-world signal connections (i.e., analog and digital inputs and outputs as
required)
o Clock inputs as required (it is helpful to have a stable variable-frequency clock
o generator)
o A digital interface to a PC (either serial or parallel ports for slow data or PCI bus for fast
data interchanges)
• Writing software routines
o Software routines can be written to interface with the chip through serial or parallel port
or the bus interface.
o The lowest level of the software should provide for peeking (reading) and poking
(writing) registers in the chip.

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• Another approach is to provide interfaces for a logic analyzer. These interfaces can be added
during PCB design.

• Smoke Test
This involves ramping the supply voltages from zero to VDD while monitoring the current
without any clocks running. For a fully static circuit, the current should remain at zero. Analog
circuits will draw their quiescent current.

• PC based peek and poke software can be used to examine the health of various registers.

• Built-in self-test (BIST)

If the chip has built-in self-test provision, one can run the commercial software that provides for
this functionality over a boundary scan interface. This type of system automatically runs a set of
tests on the chip that completely verify the correct operation of all gates and registers as defined
by the original RTL description.

2.1.6.2 POINTERS FOR REASONABLE DEBUGGING

• Keep an annotated and dated logbook for all tests done.
• When postulating a cause for the bug and a test, do one change at a time and observe the result:
Changing many things and then seeing if they work will not logically lead you to the bug and is
commonly called the “shotgun approach.
• Check everything two or three times; never assume anything unless it is measured and logged
in a notebook. Have someone independently check critical measurements.
• Check signals and supply voltages at the pins of the IC; frequently, new test boards have errors.
• Double-check the specified chip I/O and perform a continuity check from the IC pins to
expected places (i.e., test pins, supplies) on the board.
• Never disregard a possible reason for a bug, however crazy, unless you can prove it isn’t the
cause.
• Use freeze spray or a heat gun to cool down or heat up a circuit to check for temperature
problems.
• Check the state of any internal registers against that noted in the documentation.
• Evaluate the timing of any inputs and outputs with respect to the clock; often setup or hold
times can be violated in a new test setup.
• When a bug is discovered and corrected, hunt for other portions of the design that might have a
similar bug that hasn’t been detected yet.

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2.1.7 MANUFACTURING TESTS
• Manufacturing tests are used to verify that every gate operates as expected. The need to do this
arises from a number of manufacturing defects that might occur during either chip fabrication or
accelerated life testing (where the chip is stressed by over-voltage and over-temperature
operation).

• Typical defects include the following:

o Layer-to-layer shorts (e.g., metal-to-metal)
o Discontinuous wires (e.g., metal thins when crossing vertical topology jumps)
o Missing or damaged vias
o Shorts through the thin gate oxide to the substrate or well

• These in turn lead to particular circuit maladies, including the following:

o Nodes shorted to power or ground
o Nodes shorted to each other
o Inputs floating/outputs disconnected

• Tests are required to verify that each gate and register is operational and has not been
compromised by a manufacturing defect.

• Tests can be carried out at the wafer level to discard bad dies, or can be left until the parts are
packaged. This decision would normally be determined by the yield and package cost.

• If the yield is high and the package cost low (i.e., a plastic package), then the part can be tested
only once after packaging. However, if the wafer yield was lower and the package cost high (i.e.,
an expensive ceramic package), it is more economical to first screen bad dice at the wafer level.

• Apart from the verification of internal gates, I/O integrity is also tested, with the following
tests being completed:
o I/O levels (i.e., checking noise margin for TTL, ECL, or CMOS I/O pads)
o Speed test

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2.2 LOGIC VERIFICATION PRINCIPLES
2.2.1 TEST VECTORS
• Test vectors are a set of patterns applied to inputs and a set of expected outputs. Both logic
verification and manufacturing tests require a good set of test vectors.
• The set should be large enough to catch all the logic errors and manufacturing defects, yet small
enough to keep test time (and cost) reasonable. Directed and random vectors are the most
common types.
• Directed vectors are selected by an engineer who is knowledgeable about the system. Their
purpose is to cover the corner cases where the system might be most likely to malfunction.
For example, in a 32-bit Datapath, likely corner cases include the following:

0x00000000 All zeros

0xFFFFFFFF All ones
0x00000001 One in the LSB
0x80000000 One in the MSB
0x55555555 Alternating 0’s and 1’s
0xAAAAAAAA Alternating 1’s and 0’s
0x7A39D281 A random value

The circuit could be tested by applying all combinations of these directed vectors to the various
inputs. Directed vectors are an efficient way to catch the most obvious design errors and a good
logic designer will always run a set of directed tests on a new piece of RTL to ensure a minimum
level of quality.

• Applying a large number of random or semirandom vectors is a good way to detect more
refined errors. The effectiveness of the set of vectors is measured by the fault coverage. Automatic
test pattern generation tools are good at producing high fault coverage for manufacturing test.

2.2.2 TESTBENCHES OR HARNESSES

• Test benches or harness is a piece of HDL code that is placed as a wrapper around a core piece
of HDL to apply and check test vectors.
• In the simplest test bench, input vectors are applied to the module under test and at each cycle, the
outputs are examined to determine whether they comply with a predefined expected data set. The
expected outputs can be derived from the golden model and saved as a file or the value can be
computed on the fly.
• Simulators usually provide break points and single or multiple stepping abilities to allow the
designer to step through a test sequence while debugging discrepancies.

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2.2.3 REGRESSION TESTING
• High-level language scripts are frequently used when running large testbenches, especially for
regression testing.
• Regression testing involves performing a suite of simulations to automatically verify that no
functionality has inadvertently changed in a module or set of modules.
• During a design, it is common practice to run a regression script every night after design
activities have concluded to check that bug fixes or feature enhancements have not broken
completed modules.

2.2.4 VERSION CONTROL

• Combined with regression testing is the use of versioning, that is, the orderly management of
different design iterations.
• Unix/Linux tools such as CVS or Subversion are useful for this.

2.2.5 BUG TRACKING

• Another important tool to use during verification is a bug-tracking system.
• Bug-tracking systems such as the Unix/Linux based GNATS allow the management of a wide
variety of bugs.
• In these systems, each bug is entered and the location, nature, and severity of the bug noted.
• The bug discoverer is noted, along with the perceived person responsible for fixing the bug.

2.3 MANUFACTURING TEST PRINCIPLES

2.3.1 FAULT MODELS
2.3.1.1 STUCK-AT FAULTS
• In the Stuck-At model, a faulty gate input is stuck at logic 0 (Stuck-At-0, S-A0) or stuck at
logic 1 (Stuck-At-1, S-A1). Hence it has no dependency on input and output.
• These faults most frequently occur due to gate oxide shorts (the nMOS gate to GND or the
pMOS gate to VDD) or metal-to-metal shorts.
• Fig shows how an S-A-0 or S-A-1 fault might occur in basic gates.

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2.3.1.2 SHORT-CIRCUIT (STUCK SHORT) AND OPEN-CIRCUIT (STUCK OPEN) FAULTS
MOS transistor is considered as ideal switch and two types of faults are modelled.
a) Stuck Open – a single transistor is permanently stuck in the open state.
b) Stuck Short – a single transistor is permanently shorted irrespective of its gate voltage.

Two bridging or shorted faults are shown in Figure a. The short S1 results in an S-A-0 fault at input
A, while short S2 modifies the function of the gate.

Fig a: CMOS bridging faults

• Considering the case of a 2-input NOR gate in which one of the transistors is rendered ineffective.
̅̅̅̅ ) +
If nMOS transistor A is stuck open, then the function displayed by the gate will be 𝑍 = (𝐴+𝐵
𝐵𝑍̅, where 𝑍̅ is the previous state of the gate.

• Stuck - closed states can be detected by observing the static VDD current (IDD) while applying
test vectors.

2.3.2 OBSERVABILITY
• The observability of a particular internal circuit node is the degree to which one can observe that
node at the outputs of an IC.
• This metric is relevant when one wants to measure the output of a gate within a larger circuit to
check that it operates correctly.
• Given the limited number of nodes that can be directly observed, it is the aim of good chip
designers to have easily observed gate outputs.
• Ideally, one should be able to observe directly or with moderate indirection every gate output
within an integrated circuit. This involves expense of extra test circuitry and a lack of design
methodology, current processes and design practices allow you to approach this ideal.
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2.3.3 CONTROLLABILITY
• The controllability of an internal circuit node within a chip is a measure of the ease of setting the
node to a 1 or 0 state.
• This metric is of importance when assessing the degree of difficulty of testing a particular signal
within a circuit.
• An easily controllable node would be directly settable via an input pad. A node with little
controllability might require many hundreds or thousands of cycles to get it to the right state.
• It should be the aim of good chip designers to make all nodes easily controllable. Making all flip-
flops resettable via a global reset signal is one step toward good controllability.

2.3.4 REPEATABILITY
• The repeatability of a system is the ability to produce the same outputs given the same inputs.
• Combinational logic and synchronous sequential logic are always repeatable when it is
functioning correctly.
• However, certain asynchronous sequential circuits are nondeterministic. For example, an arbiter
may select either input when both arrive at nearly the same time.
• Testing is much easier when the system is repeatable. Some systems with asynchronous interfaces
have a lock-step mode to facilitate repeatable testing.

2.3.5 SURVIVABILITY
• The survivability of a system is the ability to continue function after a fault.
• For example, error-correcting codes provide survivability in the event of soft errors. Redundant
rows and columns in memories and spare cores provide survivability in the event of
manufacturing defects. Adaptive techniques provide survivability in the event of process
variation.
• Some survivability features are invoked automatically by the hardware, while others are activated
by blowing fuses after manufacturing test.

2.3.6 FAULT COVERAGE

• This determines what percent of the chip’s internal nodes are checked when the test vectors are
applied. The fault coverage of a set of test vectors is the percentage of the total nodes that can be
detected as faulty when the vectors are applied.
• The way in which the fault coverage is calculated is as follows:
o Each circuit node is taken in sequence and held to 0 (S-A-0), and the circuit is simulated with
the test vectors and then comparing the chip outputs with a known good machine––a circuit
with no nodes artificially set to 0 (or 1).
o If any discrepancy is detected between the faulty machine and the good machine, the fault is
marked as detected and the simulation is stopped.

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o This is repeated for setting the node to 1 (S-A-1). In turn, every node is stuck (artificially) at 1
and 0 sequentially.
o To achieve world-class quality levels, circuits are required to have in excess of 98.5% fault
coverage.

2.3.7 AUTOMATIC TEST PATTERN GENERATION (ATPG)

• In the IC industry, logic and circuit designers implements the functions at the RTL or schematic
level, mask designers complete the layout, and test engineers write the tests.
• The test engineers took the assistance of designers to include extra circuitry to ease the burden of
test generation. With increased complexity and density, the inclusion of test circuitry has
become less of an overhead for both the designer.
• In addition, as tools have improved, more of the burden for generating tests has fallen on the
designer. To deal with this burden, Automatic Test Pattern Generation (ATPG) methods have
been invented.
• Commercial ATPG tools can achieve excellent fault coverage. However, they are computation-
intensive and often must be run on servers or compute farms with many parallel processors.
• Some tools use statistical algorithms to predict the fault coverage of a set of vectors without
performing as much simulation. Adding scan and built-in self-test improves the observability of
a system and can reduce the number of test vectors required to achieve a desired fault coverage.

2.3.8 DELAY FAULT TESTING

• The fault models dealt with until this point have neglected timing. Failures that occur in CMOS
could leave the functionality of the circuit untouched but affect the timing.

Fig: An example of a delay fault

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• For instance, consider the layout shown in Figure for an inverter gate composed of paralleled
nMOS and pMOS transistors.
• If an open circuit occurs in one of the nMOS transistor source connections to GND, then the gate
would still function but with increased tpdf. In addition, the fault now becomes sequential as the
detection of the fault depends on the previous state of the gate.
• Delay faults may be caused by crosstalk. Delay faults can also occur more often in SOI logic
through the history effect. Software has been developed to model the effect of delay faults and is
becoming more important as a failure mode as processes scale.

2.4 DESIGN FOR TESTABILITY

2.4.1 AD HOC TESTING
• Testability can be increased by making nodes more accessible by physically inserting more access
circuits to the original design.
• Some of the ad hoc testable design techniques are:
o Partitioning large sequential circuits
o Adding test points
o Adding multiplexers
o Providing for easy state reset
• Ad hoc techniques typically use test point insertion to access internal nodes directly. An example
of a test point is a multiplexer inserted to control or observe an internal node.
• One of the techniques is use of the bus in a bus-oriented system for test purposes. Here, the
internal logic values that exist on a data bus are enabled onto the bus for testing purposes.
• Multiplexers can be used to provide alternative signal paths during testing. In CMOS,
transmission gate multiplexers provide low area and delay overhead.
• Any design should always have a method of resetting the internal state of the chip within a single
cycle or at most a few cycles. Apart from making testing easier, this also makes simulation faster
as a few cycles are required to initialize the chip.
2.4.2 SCAN DESIGN
• The scan-design strategy for testing has evolved to provide observability and controllability at
each register.
• In designs with scan, the registers operate in one of two modes.
o In normal mode, they behave as expected.
o In scan mode, they are connected to form a giant shift register called a scan chain
spanning the whole chip. By applying N clock pulses in scan mode, all N bits of state in
the system can be shifted out and new N bits of state can be shifted in. Therefore, scan
mode gives easy observability and controllability of every register in the system.

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2.4.2.1 SERIAL SCAN
• Modern scan is based on the use of scan registers, as shown in Figure. The scan register is a D
flip-flop preceded by a multiplexer.
• When the SCAN signal is de-asserted, the register behaves as a conventional register, storing
data on the D input.
• When SCAN is asserted, the data is loaded from the SI pin, which is connected in shift register
fashion to the previous register Q output in the scan chain.

Fig: Scan – Based Testing

• To load the scan chain, SCAN is asserted and 8 CLK pulses are given to load the first two
ranks of 4-bit registers with data. Then SCAN is deasserted and CLK is asserted for one cycle
to operate the circuit normally with predefined inputs. SCAN is then reasserted and CLK
asserted eight times to read the stored data out. At the same time, the new register contents can
be shifted in for the next test.
• Testing proceeds in this manner of serially clocking the data through the scan register to the
right point in the circuit, running a single system clock cycle and serially clocking the data out
for observation. In this scheme, every input to the combinational block can be controlled and
every output can be observed.

2.4.2.2 PARALLEL SCAN

• Serial scan chains can become quite long, and the loading and unloading can dominate testing
time. A simple idea is to split the chains into smaller segments.
• The basic idea is shown in Figure.

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Fig.: Parallel Scan

• The figure shows a two-by-two register section.
• Each register receives a column (column<m>) and row (row<n>) access signal along with a
row data line (data<n>).
• A global write signal (write) is connected to all registers.
• By asserting the row and column access signals in conjunction with the write signal, any
register can be read or written in the same method as a conventional RAM.
• The notional logic is shown to the right of the four registers. Implementing the logic required
at the transistor level can reduce the overhead for each register.

2.4.3 BUILT-IN SELF-TEST (BIST)

• Built-in test techniques, as their names suggest, rely on augmenting (additional) circuits to allow
them to perform operations upon themselves that prove correct operation.
• These techniques add area to the chip for the test logic but reduce the test time required and thus
can lower the overall system cost.

2.4.3.1 PSEUDO-RANDOM SEQUENCE GENERATOR (PRSG)

• One method of testing a module is to use signature analysis or cyclic redundancy checking.
This involves using a pseudo-random sequence generator (PRSG) to produce the input signals
for a section of combinational circuitry and a signature analyzer to observe the output signals.
• A PRSG of length n is constructed from a linear feedback shift register (LFSR), which in turn
is made of n flip-flops connected in a serial fashion, as shown in Figure.

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(a) Linear feedback shift register (LFSR)

o The XOR of particular outputs are fed back to the input of the LFSR.
o An n-bit LFSR will cycle through 2n – 1 states before repeating the sequence.

• A complete feedback shift register (CFSR), shown in Figure, includes the zero state that may be
required in some test situations.

• An n-bit LFSR is converted to an n-bit CFSR by adding an n – 1 input NOR gate connected to
all but the last bit.

(b) Complete feedback shift register (CFSR)

• A signature analyzer receives successive outputs of a combinational logic block and produces a
syndrome that is a function of these outputs.

• The syndrome is reset to 0, and then XORed with the output on each cycle. The syndrome is
swizzled each cycle so that a fault in one bit is unlikely to cancel itself out.

• At the end of a test sequence, the LFSR contains the syndrome that is a function of all previous
outputs. This can be compared with the correct syndrome (derived by running a test program on
the good logic) to determine whether the circuit is good or bad. If the syndrome contains enough
bits, it is improbable that a defective circuit will produce the correct syndrome.

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2.4.3.2 BIST
• The combination of signature analysis and the scan technique creates a structure known as
BIST—for Built-In Self-Test or BILBO—for Built-In Logic Block Observation.

(a)

(b)
Fig.: BIST (a) 3-bit register, (b) use in a system

• The 3-bit BIST register shown in Figure is a scannable, resettable register that also can serve as
a pattern generator and signature analyzer.
• C[1:0] specifies the mode of operation.
• In the reset mode (10), all the flip-flops are synchronously initialized to 0.
• In normal mode (11), the flip-flops behave normally with their D input and Q output.
• In scan mode (00), the flip-flops are configured as a 3-bit shift register between SI and SO. Note
that there is an inversion between each stage.
• In test mode (01), the register behaves as a pseudo-random sequence generator or signature
analyzer.
• If all the D inputs are held low, the Q outputs loop through a pseudo-random bit sequence, which
can serve as the input to the combinational logic. If the D inputs are taken from the
combinational logic output, they are swizzled with the existing state to produce the syndrome.
• In summary, BIST is performed by first resetting the syndrome in the output register. Then both
registers are placed in the test mode to produce the pseudo-random inputs and calculate the
syndrome. Finally, the syndrome is shifted out through the scan chain.

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VTU QUESTIONS

2018 Scheme (18EC72)

1) Explain the terms:
i) Observability
ii) Controllability
iii) Fault coverage [Mar 2022, 04 M]

2) What is fault model? Explain stuck-at model with examples [Mar 2022, 07 M]

3) Mention the approaches used in design for testability. Explain scan-based testing using necessary
diagrams. [Mar 2022, 07 M]

4) Draw the circuit of 3-bit BIST register and explain. [Mar 2022, 06 M]

5) With necessary circuit diagram, explain the operation of three transistor DRAM cell.
[Mar 2022, 08 M]

6) Explain full CMOS SRAM cell with necessary circuit topology. [Mar 2022, 08 M]

VTU Other Schemes

1) Write a note on automatic test pattern generation. [Jul 2019, 04 M]
2) Write short notes on
a. Observability and controllability
b. Built In Self-Test (BIST) [Jul 2019, 08 M]
3) Explain any two fault models in combinational circuits. [Jul 2019, 06 M]
4) Explain logic verification principle. [Jan 2019, 08 M]
5) What is design manufacturability. [Jan 2019, 10 M]
6) Explain logic verification process with its functional equivalence diagram. [July 2018, 06 M]
7) Discuss the design for manufacturability. [July 2018, 06 M]
8) Discuss the Ad-hoc testing. [July 2018, 04 M]

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