THE PROCESSING

UNIT

SCHOOL OF COMPUTING MITCH M. ANDAYA

BASIC OPERATIONAL CONCEPTS

• The processing unit

executes machine
instructions and
coordinates the
activities of other
units.

• This unit is often

called the Instruction
Set Processor (ISP), or
simply the Processor.

The Processing Unit

BASIC OPERATIONAL CONCEPTS

• The processing unit

used to be called the
Central Processing Unit
(CPU).

• The term "central" is

less appropriate today
because many modern
computer systems
include several
processing units (e.g.
GPU).
The Processing Unit
BASIC OPERATIONAL CONCEPTS

• The instructions constituting a 11101001 0000...0000

program to be executed by a 10101111 0000...0001
computer are loaded in sequential
locations in the main memory. 00001111 0000...0010
.
• To execute this program, the
processor fetches one instruction .
at a time and performs the .
functions specified.
01010101 1111...1110
• Instructions are fetched from
successive memory locations until 10101010 1111...1111
a branch or a jump instruction is
executed (altering the sequential
flow of instruction execution). Program Addresses
Instructions or in binary
Data in Binary

The Processing Unit

BASIC OPERATIONAL CONCEPTS

11101001 0000...0000
• The processor keeps track of
the address of the memory 10101111 0000...0001
location containing the next 00001111 0000...0010
instruction by using a
dedicated register, referred to .
as the program counter (PC). .
.
• So if the PC is currently equal 01010101 1111...1110
to 0000. . . .0001, then the
next instruction to be fetched 10101010 1111...1111
and executed is found at that
memory address.
0000….0001
PC

The Processing Unit

BASIC OPERATIONAL CONCEPTS

11101001 0000...0000
• After fetching an
10101111 0000...0001
instruction, the contents
of the PC are updated 00001111 0000...0010
(incremented) to point to .
the next instruction in the .
sequence. .
01010101 1111...1110
next instruction to
10101010 1111...1111
be fetched and
executed
0000….0010
0000….0001
PC

The Processing Unit

BASIC OPERATIONAL CONCEPTS

• Example of a typical
assembly language
instruction:
R0
ADD R0, LOCA
LOCA
+
Add the operand at
memory location LOCA to
the operand in a register
in the processor, R0, and CPU Main Memory
place the result into
register R0.

The Processing Unit

BASIC OPERATIONAL CONCEPTS

• Example of a typical • The execution of this instruction

assembly language requires several steps:
instruction:
1. The instruction must be fetched
ADD R0, LOCA or transferred from the MM into
the CPU.

2. The instruction is decoded.

Add the operand at
memory location LOCA to 3. The operand at LOCA must be
the operand in a register fetched and added to the
contents of R0.
in the processor, R0, and
place the result into 4. The resultant sum is stored in
register R0. register R0.

The Processing Unit

BASIC OPERATIONAL CONCEPTS

• In order to fetch/read an instruction address of memory

or data from main memory: location to be read

Read signal

1. The CPU first sends the address

of the memory location to be
read. CPU

2. The CPU then issues or sends the

Read signal to the memory. requested data

3. The word is then read out of

Primary or Main Memory
memory and is loaded into a CPU
internal register.

The Processing Unit

BASIC OPERATIONAL CONCEPTS

• In order to store/write data address of memory

into main memory: location to be written

1. The CPU first sends the

address of the memory CPU

location to be written.

2. The CPU then sends the Write signal and data

to be written
Write signal together Primary or Main Memory
with the data or word to
be written to memory.

The Processing Unit

INSIDE THE PROCESSOR

Main Memory
connections between
the processor and the
main memory

MAR MDR controls the entire

Control activity of the CPU
PC
R0
IR R1 performs all arithmetic
ALU and logic operations
.
.
CPU .
Rn-1
n General Purpose for general processing
requirements of
Registers programs

The Processing Unit

INSIDE THE PROCESSOR

Main Memory
– The PC (Program
Counter) contains
the memory address
MAR MDR of the instruction to
Control
be executed.
PC
R0
IR R1
.
ALU During execution,
. the contents of the
CPU . PC are updated to
Rn-1 point to the next
n General Purpose instruction.
Registers

The Processing Unit

INSIDE THE PROCESSOR

Main Memory
– The MAR (Memory
Address Register)
holds the address of
MAR MDR the location to or
Control
from which data are
PC
R0 to be transferred.
IR R1
ALU
.
. The MAR is used by
CPU . the CPU to send
Rn-1 addresses to the
n General Purpose MM.
Registers

The Processing Unit

INSIDE THE PROCESSOR

Main Memory
– The MDR (Memory
Data Register)
contains the data to
MAR MDR
Control
be written or read
PC out of the addressed
R0 location.
IR R1
ALU
.
. The MDR is used by
CPU .
Rn-1
the CPU to send or
receive data to/from
n General Purpose
Registers
the MM.

The Processing Unit

INSIDE THE PROCESSOR

Main Memory

– The IR (Instruction
Register) contains
MAR MDR the instruction that
Control
is being executed.
PC
R0
IR R1
.
ALU After an instruction
. is fetched from the
CPU . MM, it is sent to the
Rn-1 IR for decoding
n General Purpose
Registers

The Processing Unit

INSIDE THE PROCESSOR

• Operating Steps:
Recall that whenever a user
wants to execute a particular
program, the operating
system will:
1 2
1. copy the program from
secondary to primary
memory
fetch
decode
2. and the CPU will then execute
fetch these instructions
(one by one) from main
memory for execution.

The Processing Unit

INSIDE THE PROCESSOR

• Operating Steps:
Main Memory
1. The PC is set to point
to the first
instruction of the
MAR MDR
program Control
address of1st
PC
instruction R0
The operating IR R1
ALU
system is the one .
that loads the .
memory address of CPU .
Rn-1
the first instruction n General Purpose
of the program into Registers
the PC.

The Processing Unit

INSIDE THE PROCESSOR

• Operating Steps:
Main Memory
2. The contents of the
Read signal
PC are transferred to
the MAR.
address of 1st MAR MDR
instruction Control
This address is then PC
R0
automatically IR R1
transmitted to the .
ALU
MM. .
CPU .
Rn-1
A Read signal is sent n General Purpose
to the MM (by the Registers
Control Unit).
The Processing Unit
INSIDE THE PROCESSOR

• Operating Steps:
Main Memory
3. The addressed word instruction
(which is the instruction to be executed

to be executed) is read
out of MM and loaded MAR MDR
into the MDR. Control
PC
R0
4. The contents of MDR IR R1
ALU
are transferred to the .
IR. .
CPU .
Rn-1
The instruction is ready
n General Purpose
to be decoded and then Registers
executed.

The Processing Unit

INSIDE THE PROCESSOR

• Operating Steps:
Main Memory

5. While the current

instruction is being MAR MDR
Control
executed, the PC
R0
contents of the PC
IR R1
are incremented or ALU
.
updated to point to .
the next instruction. CPU .
Rn-1
n General Purpose
PC = PC + 1 Registers

The Processing Unit

INSIDE THE PROCESSOR

• Operating Steps:
Main Memory
If operand or data needed by requested
the instruction resides in operand Read signal
MM:
MAR MDR
a. It will have to be fetched Control
by sending its address to PC
R0
the MAR and initiating a IR R1
read cycle. .
ALU
b. When the operand has .
been read from MM into
the MDR, it may be
CPU .
Rn-1
transferred from the address of n General Purpose
MDR to the ALU or to a operand Registers
internal register

The Processing Unit

INSIDE THE PROCESSOR

• Operating Steps:
Main Memory
If result is to be stored result Write signal
in MM:
MAR MDR
Control
a. The address of the
PC
location where the R0
result is to be stored IR R1
ALU
is sent to the MAR. .
.
CPU .
b. The result is sent to address of
Rn-1
result
the MDR and a write location where
result will be
n General Purpose
cycle is initiated Registers
stored

The Processing Unit

INSIDE THE PROCESSOR

• Instruction execution in a CPU can now be summarized by the

following steps:

1. Fetching the instruction from the memory into the instruction

register.

2. Incrementing the PC to point to the next instruction to be

executed.

3. Determining the type of instruction fetched (instruction

decoding).

4. Determining the location of data in the memory if the

instruction uses data which is in MM.

The Processing Unit

INSIDE THE PROCESSOR

5. Fetching the required data into internal CPU registers.

6. Executing the instruction.

7. Storing the results in the designated locations.

8. Return to Step 1 and start again for the next instruction.

This is the complete description of the fetch-decode-

execute cycle.

The Processing Unit

BUS STRUCTURES

• A bus is a collection of wires that connect several devices within a

computer system.

• When a word of data is transferred between units, all its bits are
transferred in parallel.

• A computer must have some lines for addressing and control

purposes.

Main or
Secondary I/O
CPU Primary
Memory Devices
Memory

Interconnecting Bus

The Processing Unit

BUS STRUCTURES

• Three main groupings of lines: Main Memory

2 1 3
1. Data Bus. This is for the
transmission of data.
MAR MDR
Control
2. Address Bus. This specifies PC
the location of data in MM. R0
IR R1
ALU
.
3. Control Bus. This indicates .
the direction of data CPU .
transfer and coordinates Rn-1
the timing of events during n General Purpose
the transfer. Registers

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

• Types of Instructions:

1. Data transfers between MM and processor

registers (MM to register, register to MM, or
register to register).

2. Arithmetic and logic operations on data.

3. Program sequencing and control.

4. I/O operations or transfers.

The Processing Unit
INSTRUCTION EXECUTION IN THE CPU
• Sample Notations
[ ] - "the contents of"
R1 [LOC]

The contents of memory location LOC are transferred

(copied) into register R1.

R1
LOC

CPU Main Memory

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU
• Sample Notations
B [R2] + [A]

The contents of register R2 and the contents of

memory location A are added and the resulting sum
is stored into memory location B.

R2

A
+
B

CPU Main Memory

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

• The number of bits per instruction varies from 8 bits to as high as

32 bits.

• An instruction usually contains two parts:

1. the part that specifies the operation to be performed (op-code

field).

2. the part that may be used to specify operand addresses

(address field).

For example: 8 bits 24 bits

op-code address field

field

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

• Steps in instruction execution:

1. Fetch the contents of the memory location pointed to by the

PC. The contents of this location are interpreted as an
instruction to be executed. Hence, they are loaded into the IR.

IR [ [PC] ]

2. Increment the contents of the PC by 1.

PC [PC] + 1

3. Carry out the actions specified by the instruction in the IR.

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

IR [ [PC] ]
0 MOV R1, LOC1
PC 2
1 MOV R2, LOC2

[PC] = 22 2 ADD R1, R2

[[PC]] = [2] 3 MOV LOC, R1

4 SUB R2, R1

IR ADD R1, R2

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

• Steps in instruction execution:

1. Fetch the contents of the memory location pointed to by the

PC. The contents of this location are interpreted as an
instruction to be executed. Hence, they are loaded into the IR.

IR [ [PC] ]

2. Increment the contents of the PC by 1.

PC [PC] + 1

3. Carry out the actions specified by the instruction in the IR.

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

• Take note that if the instruction occupies

more than one word, steps 1 and 2 are
repeated as many times as necessary to
fetch the complete instruction.

• Steps 1 and 2 are usually referred to as

the fetch phase; step 3 constitutes the
execution phase.

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

Instruction
Decoder Internal
Processor
Main Memory IR
Bus

PC
Address Lines
MAR
Memory
Bus Data Lines
MAR MDR MDR
Control
R0
PC
R0 R1
.
IR R1 .
ALU .
.
Rn-1
.
CPU .
Rn-1
1 Y

Select MUX
n General Purpose
Registers
Add A B
ALU Sub
Control : ALU
Lines XOR Carry-in

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

Instruction
Decoder Internal
Processor • This is the single-bus organization of the
IR
Bus
data paths inside the processing unit.
PC
Address Lines
MAR
• In this organization, the arithmetic and
Memory
Bus Data Lines
logic unit (ALU) and all the registers are
MDR
interconnected via a single common bus
R0 (internal processor bus).
R1

external
.
. • This bus is internal to the processor and
bus
.
should not be confused with the external
Rn-1
bus that connects the processor to the
1 Y memory and I/O devices.
Select MUX
• The data and address lines of the external
ALU
Add
Sub
A B memory bus are connected to the internal
Control
Lines XOR
: ALU
Carry-in
processor via the MDR and the MAR
Z
respectively

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

Instruction
Decoder Internal
Processor
Bus
• Two registers (Y and Z) have not
IR
been mentioned before.
PC
Address Lines
MAR
Memory
Bus Data Lines
MDR
These registers are transparent to
R0
the programmer; that is, the
programmer need not be
R1
.
concerned with them, because
.
. they are never referenced directly
Rn-1
by any instruction.
1 Y

Select MUX They are used only by the

Add
processor for temporary storage
ALU
Control
Lines
Sub
XOR
:
A
ALU
B
during execution of some
Z
Carry-in
instructions.

The Processing Unit

 INSTRUCTION EXECUTION IN THE CPU

Instruction
Decoder Internal
Processor

•
Bus
IR
The ALU performs all
Address Lines
PC
arithmetic (ADD, SUB, MULT,
Memory
Bus Data Lines
MAR
DIV, etc.) and logic (AND, OR,
MDR
NOT, XOR, etc.) operations.
R0

R1
.
ALU control .
.
lines Rn-1
• The ALU control lines
1 Y determine the exact
Select MUX operation the ALU will
Add
perform.
ALU A B
Sub ALU
Control :
Lines XOR Carry-in

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

Yin

For example, if the Add

control line is activated 1
Y

(Add = 1) then the ALU

will perform an Select MUX

addition operation. 1 Add A B

0 Sub
: ALU
0 XOR

The data at input A Zin

is added to the data
at input B and the Z

result is stored at
register Z. Zout

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

Instruction
Decoder Internal
Processor
Bus
IR

PC
• The Instruction Decoder unit is
Address Lines
MAR
responsible for implementing
Memory
Bus Data Lines
MDR
the actions specified by the
R0 instruction loaded in the IR
R1
register.
.
.
.
Rn-1
• The decoder generates the
1 Y
control signals needed to
Select MUX select the registers involved
ALU
Add
Sub
A B
and direct the transfer of data.
Control : ALU
Lines XOR Carry-in

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

Instruction
Decoder Internal
Processor
Bus
IR

PC
Address Lines
MAR
Memory
Bus Data Lines

• The registers, the ALU, and

MDR

R0

R1
.
the interconnecting bus
.
. are collectively referred to
Rn-1
as the data path.
1 Y

Select MUX

Add A B
ALU Sub
Control : ALU
Lines XOR Carry-in

The Processing Unit

INSTRUCTION EXECUTION IN THE CPU

• With a few exceptions, an instruction can be executed by

performing one or more of the following operations in some
specified sequence:

1. Transfer a word of data from one processor register to another

or to the ALU.

2. Perform an arithmetic or logic operation and store the result in

a processor register.

3. Fetch the contents of a given memory location and load them

into a processor register.

4. Store a word of data from a processor register into a given

memory location.

The Processing Unit

REGISTER TRANSFERS

Instruction
Decoder Internal
Input
Processor Gate of Ri
Bus
IR

PC
Address Lines
MAR
Memory
Bus Data Lines Riin
MDR

R0
Internal
R1 Ri Processor
.
.
Bus
.
Rn-1
Riout
1 Y

Select MUX

Add A B
ALU
Control
Sub
: ALU Output
Lines XOR Carry-in Gate of Ri
Z

The Processing Unit

REGISTER TRANSFERS

• To enable data transfers

between various blocks in a
common data bus, input and
output gating must be
provided. Riin

Internal
• The input and output gates Ri Processor
Bus
for register Ri are controlled
by the signals Riin and Riout, Riout

respectively.

• If Riin = 1, the data available • If Riout = 1, the

on the common bus is contents of register Ri
loaded into Ri. are placed on the bus.

The Processing Unit

REGISTER TRANSFERS

• Example: R4 [R1] R1in

R1
Enable the output gate of
register R1 by setting R1out to
1. This places the contents R1out 1
of R1 on the processor bus. Internal
Processor
R4 in Bus
1
Enable the input gate of
register R4 by setting R4in to R4
1. This loads data from the
processor bus into register
R4. R4 out

The Processing Unit

REGISTER TRANSFERS

• Example: R4 [R1] R1in

The sequence of control R1

signals will therefore be:
R1out 1
R1out = 1
1,, R4in = 1 Internal
Processor
R4 in Bus
1
After the transfer operation,
both R1out and R4in will be
deactivated (reset to 0) to R4

close all the gates in

preparation for the next R4 out
instruction to be executed.

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

Yin

• The ALU is a
combinational circuit 1
Y

that has no internal

storage. Select MUX

A B
ALU
It performs arithmetic
and logic operations Zin
on the two operands
applied to its A and B Z

inputs.
Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

A multiplexer (or MUX) is Yin

a device that selects
between several input
signals and forwards it to a 1
Y

single output line.

Select MUX

It has a Select line which is A B

used to select which input ALU

line to send to the output.

Zin

In this set-up, the inputs to Z

the MUX are the constant
1 and the output of
register Y. Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

Yin

If Select = 0, then 1
Y

the signal 0
Select MUX

representing the A B
constant 1 passes ALU

through the MUX

and is sent to Zin

input A of the ALU. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

Yin

If Select = 1, then 1
1

the contents of Select MUX

register Y pass A
ALU
B

through the MUX

and is sent to Zin

input A of the ALU. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

So one of the operands of Yin

the ALU (input A) is the

output of the multiplexer Y
MUX (which is either the 1

constant 1 or the contents Select MUX

of register Y)
A B
ALU
While the other operand 1 or Y

(input B) is obtained
Zin
directly from the bus.
Z

The result is stored

temporarily in register Z. Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2

This instruction means add R3

the contents of registers R1 Yin

and R2 and store the results

to register R3. 1
Y

Select MUX

To accomplish this, both the Add A B

contents of R1 and R2 must Sub .
.
.
ALU

be brought to the ALU in XOR

order for the ALU to add Zin

the two operands. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2

The first step requires the R3

contents of R1 be stored in Yin

register Y of the ALU.

Y
1

So this means the output of Select MUX

register R1 and the input of Add A B

register Y are enabled, Sub .
.
.
ALU

causing the contents of R1 XOR

to be transferred over the Zin

bus to Y. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2

1. R1 out =
R1out = 1,
1, Yin = 1 R3

Yin

or simply write: Y
1

Select MUX
1. R1out, Yin
Add A B
Sub .
.
ALU
.

to indicate which lines are XOR

activated during the 1st Zin

step. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2
Before proceeding to the next
step in the sequence (step 2), all R3

lines that were activated (R1out same as the

contents of R1
Yin

and Yin) will now be deactivated.

Y
1
So at this point, register Y has the
same contents as register R1. Select MUX

Add A B
Sub .
ALU
Take note that Y does not have
.
.
XOR

an output gate. It's contents are Zin

automatically gated to the one of
the inputs of the MUX. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2
In step 2, the contents of register R2
are gated onto the bus and, hence to R3

input B. same as the Yin

contents of R1

At the same time, the multiplexer's Y

Select signal is set to SelectY, causing 1
the multiplexer to gate the contents of
register Y to input A of the ALU. Select MUX

Add A B
Sub
At this point, both operands are in the .
.
.
ALU

ALU. XOR

Zin

2. R2out, SelectY Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2

The function of the ALU depends on R3

the signals applied to its control lines. same as the Yin
contents of R1
In this case, the Add line is set to 1
(activated), causing the output of the 1
Y

ALU to be the sum of the two

numbers at inputs A and B. Select MUX

1 Add A B
This sum is loaded into register Z by Sub .
ALU
activating Zin. 
.
.
XOR

Zin

2. R2out, SelectY, Add, Zin Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2

So the sequence of control R3

signals so far would be: Yin

1. R1out, Yin Y
1

Select MUX
2. R2out, SelectY, Add, Zin
Add A B
Sub .
.
ALU

Before proceeding to the next XOR

.

step (3rd step), all lines that Zin

were activated in the 2nd step
will be deactivated. Z

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

In step 3, the contents of R2

register Z are transferred to the R3

destination register R3. Yin

This last transfer cannot be Y

carried out during step 2, 1

because only one register Select MUX

output can be connected to the Add

bus during the step. Sub .
.
A
ALU
B

.
XOR

2. R2out, SelectY, Add, Zin, Zout Zin data

collision
Z

will conflict with R2out

Zout

The Processing Unit

PERFORMING AN ARITHMETIC OR LOGIC OPERATION

• Example: R3 [R1] + [R2]

R1

R2

So the sequence of control R3

signals for the specified Yin

operation:
Y

1. R1out, Yin 1

2. R2out, SelectY, Add, Zin Select MUX

3. Zout, R3
R3inin Add
Sub
A B
.
.
ALU
.
XOR

Each step in the sequence takes Zin

one clock cycle of the
processor internal clock. Z

Zout

The Processing Unit

SYSTEM CLOCK

• The system clock is needed to synchronize all

components in a computer system.

clock cycle Clock

Generator CPU
or clock pulse

A cycle is the part of a repetitive

signal that repeats itself.

The Processing Unit

SYSTEM CLOCK

• Clock speed is measured in terms of its frequency which measures

the number of clock cycles per second. Its unit of measurement is
hertz (Hz).

So if the frequency of the computer system clock is 2 GHz which is

2,000,000,000 Hz, then it has 2,000,000,000 cycles per second.

• The time for one cycle (which is called the period) is just the
reciprocal of the frequency.

period =  == 1/f
1/f = 1/2,000,000,000 = 0.5 ns/cycle

The Processing Unit

FETCHING A WORD FROM MEMORY

• To fetch a word from

main memory, the
processor has to specify
the address of the
memory location where
it is stored and request a
Read operation.

• This applies whether the

information to be fetched
represents an instruction
in a program or an
operand specified by an
instruction.

The Processing Unit

 FETCHING A WORD FROM MEMORY

Instruction
Decoder
MDRoutE MDRin
Internal
Processor
Bus
IR

PC Memory-bus Internal
MDR Processor
Address Lines Data Lines
Memory
MAR Bus
Bus Data Lines
MDR

R0 MDRinE MDRout
R1
.
.
.
Rn-1 • Register MDR has four control signals:
1 Y

Select MUX
‒ MDRin and MDRout control the
connection to the internal bus, and
Add A B
ALU Sub
Control : ALU
Lines XOR Carry-in
‒ MDRinE and MDRoutE control the
Z
connection to the external bus.

The Processing Unit

FETCHING A WORD FROM MEMORY
• During a memory Read and Write operation, the timing of internal
processor operations must be coordinated with the response of the
addressed device on the memory bus.

• The processor completes one internal data transfer (such as

register to register transfer) in one clock cycle.

R4out, R1in

• The processor completes one internal add operation in three clock

cycles.

1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in

The Processing Unit

FETCHING A WORD FROM MEMORY

• The speed of operation of the addressed device

(such as the external main memory), on the other
hand, varies with the device.

For example, if the memory has an average access

time of 70 ns and one clock cycle is equal to 0.5 ns,
then a memory access will take:

70/0.5 = 140 clock cycles.

The Processing Unit

FETCHING A WORD FROM MEMORY

• To accommodate the variability in

response time, the processor waits address of memory
until it receives an indication that the location to be read
requested Read operation has been Read signal
completed.

• There is a control signal called CPU

Memory-Function-Complete (MFC)
that is used for this purpose.
requested data
• The addressed device (in this case, the MFC = 1
memory) sets this signal to 1 to
indicate that the contents of the Primary or Main Memory
specified location have been read and
are available on the data lines of the
memory bus.

The Processing Unit

 FETCHING A WORD FROM MEMORY
• Example:

Assume that the address of the memory location to be accessed is in R1 and the
memory data in that location is to be loaded into R2.

R1 12 The actions needed to execute this instruction

are:

11 87 1. MAR [R1]
12 15
2. Start a Read operation on the memory bus
13 30
14 46 3. Wait for the MFC response from the
memory
15 92
number to be
loaded to R2 4. Load MDR from the memory bus

5. R2 [MDR]

The Processing Unit

FETCHING A WORD FROM MEMORY

1. MAR [R1]
• The actions may be carried
out as separate steps, but
2. Start a Read operation on some can be combined into
the memory bus
a single step.
3. Wait for the MFC
response from the • Each action can be
memory completed in one clock cycle,
except action 3 which
4. Load MDR from the requires one or more clock
memory bus cycles, depending on the
speed of the addressed
5. R2 [MDR] device.

The Processing Unit

FETCHING A WORD FROM MEMORY

• When a new address is loaded into

MAR, MARoutE must be activated so R1
that the address is loaded on the
R2
memory bus.
MDRoutE MDRin
• A Read signal is activated at the same
time this is done. This signal will cause
the bus interface circuit to send a
Read command on the bus. Data Bus MDR

• With this arrangement, actions 1 and

2 above are combined into a single MDRinE MDRout
control step.
MARoutE MARin

out, MARin , MARoutE, Read

1. R1out Address Bus MAR

Internal Processor Bus

The Processing Unit

FETCHING A WORD FROM MEMORY

• Actions 3 and 4 can also be combined

by activating control signal MDRinE R1
while waiting for a response from
memory. R2

2. MDRinE , WMFC MDRoutE MDRin

where WMFC is the control signal that

causes the processor's control Data Bus MDR
circuitry to wait for the arrival of the
MFC signal.
MDRinE MDRout
• Thus, the data received from the
memory are loaded into MDR at the MARoutE MARin
end of the clock in which the MFC
signal is received. Address Bus MAR

Internal Processor Bus

The Processing Unit

FETCHING A WORD FROM MEMORY

• In the next clock cycle, MDRout

is activated to transfer the data R1
to register R2.
R2

3. MDRout
out, R2in MDRoutE MDRin

• This means that the memory Data Bus MDR

read operation requires three
steps:
MDRinE MDRout

1. R1out, MARin, MARoutE, Read MARoutE MARin

2. MDRinE, WMFC
Address Bus MAR
3. MDRout, R2in
Internal Processor Bus

The Processing Unit

STORING A WORD INTO MEMORY

• In order to store/write
data into main memory: • So to store a word into
main memory:
1. The CPU first sends the
address of the memory 1. Load the address
location to be written. into the MAR.

2. The CPU then sends 2. Then, the data to be

the Write signal written to memory is
together with the data loaded into MDR and
or word to be written a Write command is
to memory. issued.

The Processing Unit

STORING A WORD INTO MEMORY

• Example:
R1
Assume that the data word to
be stored in memory is in R2 R2

and the memory address is in

MDRoutE MDRin
R1.

1. R1
R1out
out,, MAR
MARinin, MARoutE
outE Data Bus MDR

2. R2out, MDRin, MDRoutE,, Write

Write
3. WMFC MDRinE MDRout

MARoutE MARin
However, for future
discussions, assume all external Address Bus MAR

gates are always activated.

Internal Processor Bus

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

[ [R2] ]
• Assume the following
instruction:
R2 12
R1 [R1] + [[R2]]

[R2] ==1212 11 87
The contents of register
R1 are added to the 12 15
contents of a memory [[R2]] = [12] = 12
location (the address of 13 30
which is in register R2) 14 46
and store the results in number to be
15 92
register R1. added to the
contents of R1

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Assume the following • Executing this instruction

instruction: requires the following
actions:
R1 [R1] + [[R2]]
1. Fetch and decode the
instruction.
The contents of register 2. Fetch the operand in
R1 are added to the memory (the contents
contents of a memory of the memory
location (the address of location pointed to by
which is in register R2) R2).
and store the results in 3. Perform the addition.
register R1. 4. Load the result into
R1.

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

Step 1. The instruction fetch PC

operation is initiated by loading Memory

Address Lines
MAR

the contents of the PC into the Bus Data Lines

MDR

MAR and sending a Read R0

request to the memory. R1

.
.
.

1. PC
PCout
out,, MAR
MARinin,, Read
Read Rn-1

1 Y

Select MUX
Since the Read operation will
take several clock cycles, the ALU
Control
Add
Sub
:
A
ALU
B

PC may be updated at this Lines XOR Carry-in

step. Z

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

The select signal is set to Select1, PC

which causes the multiplexer MUX Address Lines
MAR
to select the constant 1 to be gated Memory
Bus Data Lines

to input A of the ALU. MDR

R0

R1

This value is added to the operand .

.

at input B, which is the contents of .

Rn-1
the PC, and the result is stored in
register Z (the PC is incremented by 1 Y

1). Select MUX

1
Add A B
ALU Sub
1. PCout, MARin, Read,, Select1, Add, Zin Control
Lines XOR
: ALU
Carry-in

Z
PC + 1

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

Step 2. The updated value of PC

the PC (which is in register Z) is Address Lines

MAR

moved back to the PC. Memory

Bus Data Lines
MDR

R0

Note that step 2 begins R1

.

immediately after the memory .

.

Read is requested, without Rn-1

waiting for the memory 1 Y

function to be completed. Select MUX

Add A B
ALU Sub
Control : ALU

2. ZZout
out, ,PC
PCinin, ,WMFC
WMFC Lines XOR Carry-in

Z
updated PC

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

Step 3. The word fetched from the PC

memory is now in the MDR. It is Address Lines
MAR
then loaded into the IR. Memory
Bus Data Lines
MDR

3. MDR out, ,IR

MDRout IRinin R0

R1
MDR now contains the
.
instruction that was
.
The instruction decoding circuit fetched .

interprets the contents of the IR at Rn-1

the beginning of step 4. 1 Y

Select MUX

This enables the control circuitry to ALU

Add
Sub
A B

choose the appropriate signals for Control

Lines XOR
: ALU
Carry-in

the remainder of the control Z

sequence.

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

1. PCout, MARin, Read, Select1, PC

Add, Zin Address Lines
MAR
Memory
2. Zout, PCin, WMFC Bus Data Lines
MDR

3. MDRout, IRin R0

R1
.
.
.
Steps 1 through 3 constitute the Rn-1

instruction fetch and decode 1 Y

phases, which is the same for all
instructions. Select MUX

Add A B
ALU Sub
Control : ALU

The succeeding steps constitutes Lines XOR Carry-in

the execution phase. Z

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

Step 4. The contents of R2 is PC

the address of the operand to Memory

Address Lines
MAR

be added to the contents of R1. Bus Data Lines

MDR

It will have to fetched from R0

memory. R1

R2

Rn-1
The contents of register R2 are
transferred to the MAR and a 1 Y

memory Read is initiated. Select MUX

Add A B
ALU Sub
Control : ALU
Lines XOR Carry-in
4. R2out
out, MARin
in,, Read
Read Z

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus

Step 5. Take note that the IR

WMFC signal is not yet Address Lines

PC

activated in step 4 since there Memory

Bus Data Lines
MAR

is still something the processor MDR

R0
can do. R1

R2

Specifically, the contents of R1 Rn-1

are transferred to register Y to 1 Y

prepare for the addition Select MUX

operation. Add
ALU A B
Sub ALU
Control :
Lines XOR Carry-in
5. R1out, Yin, WMFC Z

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR
Step 6. When the Read operation is
completed, the memory operand is Address Lines
PC

available in register MDR. Memory

Bus Data Lines
MAR

MDR

R0
The contents of the MDR are gated
to the bus, and thus also to the B MDR now contains the
R1

input of the ALU, and register Y is second operand R2

selected as the second input to the Rn-1

ALU by choosing SelectY. 1 Y

Select MUX

The addition is performed and the ALU

Add
1
A B
sum is stored in register Z. Control
Lines
Sub
XOR
: ALU
Carry-in

Z
6. MDRout, SelectY,
SelectY, Add, Zinin

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

PC

Step 7. The sum is then Memory

Address Lines
MAR

transferred to R1. Bus Data Lines

MDR

R0

R1
The End signal causes a new R2
instruction fetch cycle to begin Rn-1

by returning to step 1.
1 Y

Select MUX

R1inin,, End
7. Zout, R1 ALU
Control
Add
Sub
A
ALU
B
:
Lines XOR Carry-in

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [[R2]] Instruction

Decoder Internal
Processor
Bus
IR

So the control sequence for the Address Lines

PC

given instruction is: Memory

Bus Data Lines
MAR

MDR

R0
1. PCout, MARin, Read, Select1,
Add, Zin R1

R2
2. Zout, PCin, WMFC Rn-1

3. MDRout, IRin
1 Y
4. R2out, MARin, Read
Select MUX
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin ALU
Control
Add
Sub
:
A
ALU
B

Lines XOR Carry-in

7. Zout, R1in, End Z

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Assume the following • Executing this instruction

requires the following
instruction: actions:

1. Fetch and decode the

R1 [R1] + [LOC] instruction.
2. Fetch the operand in
memory (the contents
The contents of of the memory
register R1 are added location pointed to
to the contents of LOC which is in the
memory location LOC address field of the
instruction).
and store the results 3. Perform the addition.
in R1. 4. Load the result into
R1.
The Processing Unit
INSTRUCTION EXECUTION IN THE CPU

• Recall that an instruction is composed of two fields:

LOC
op-code address field
field

used to specify the operation used to specify addresses

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [LOC] Instruction

Decoder Internal
Processor
Bus
IR

1. PCout, MARin, Read, Select1, Address Lines

PC

Add, Zin Memory

Bus Data Lines
MAR

MDR

2. Zout, PCin, WMFC R0

3. MDRout, IRin R1
.
.
.
Rn-1
As discussed earlier, steps 1
through 3 constitute the 1 Y

instruction fetch and decode Select MUX

phases, which is the same for ALU

Add
Sub
A
ALU
B

all instructions. Control

Lines XOR
:
Carry-in

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [LOC] Instruction

Decoder Internal
Processor
Bus
IR

PC
LOC is the address of the Address Lines
MAR

operand to be added to the Memory

Bus Data Lines
MDR

contents of R1. This operand R0

will have to fetched from R1

memory. .
.
.
Rn-1

So to fetch the contents of LOC, 1 Y

the address LOC must be Select MUX

loaded to the MAR and a ALU

Add A B
memory Read is initiated. Control
Lines
Sub
XOR
: ALU
Carry-in

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [LOC] Instruction

Decoder Internal
Processor
Bus
IR

LOC is in the address field of Address Lines

PC

the instruction (which is Memory

Bus Data Lines
MAR

currently inside the IR). MDR

R0

R1
.
4. Address-Field-of-IRout
out,
.
.

MAR in, Read Rn-1

5. R1out, Yin,, WMFC

WMFC 1 Y

6. MDRout, SelectY, Add, Zin Select MUX

7. Zout, R1in, End ALU

Control
Add
Sub
:
A
ALU
B

Lines XOR Carry-in

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: R1 [R1] + [LOC] Instruction

Decoder Internal
Processor
Bus
IR

So the control sequence for the PC

given instruction is: Address Lines
MAR
Memory
Bus Data Lines
MDR

1. PCout, MARin, Read, Select1, R0

Add, Zin R1

2. Zout, PCin, WMFC .

.
.

3. MDRout, IRin Rn-1

4. Address-Field-of-IRout, MARin, 1 Y

Read Select MUX

5. R1out, Yin, WMFC

Add A B
6. MDRout, SelectY, Add, Zin ALU
Control
Lines
Sub
XOR
: ALU
Carry-in

7. Zout, R1in, End Z

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Assume the following

instruction: • Executing this
instruction requires the
following actions:
[R3] [R1] + [R2]
1. Fetch and decode
The contents of the instruction.
register R1 are added 2. Perform the
to the contents of addition.
register R2 and store 3. Store the result in
the results in memory memory whose
location is pointed
whose address is to by R3.
stored in R3.

The Processing Unit

EXECUTION OF A COMPLETE INSTRUCTION

• Example: [R3] [R1] + [R2] Instruction

Decoder Internal
Processor
Bus
IR

1. PCout, MARin, Read, Select1, PC

Add, Zin Memory

Address Lines
MAR
Bus Data Lines
2. Zout, PCin, WMFC MDR

R0
3. MDRout, IRin R1

R2

4. R1out , Yin Rn-1

5. R2out , SelectY, Add, Zin 1 Y

6. R3out
out, MARin
Select MUX

7. Zout, MDRin,, Write

Write ALU
Control
Add
Sub
:
A
ALU
B

Lines XOR

8. WMFC, End Z
Carry-in

The Processing Unit

BRANCH INSTRUCTIONS
• A branch is an instruction in a computer
program that can cause a computer to
0 MOV R1, LOC1
begin executing a different instruction 1 MOV R2, LOC2
sequence and thus deviate from its
default behavior of executing instructions 2  ADD R1, R2
in order. 3  JUMP 200
4 XOR R3, R1
• It is is accomplished by replacing the
current contents of the PC by the branch .
address, that is, the address of the .
instruction to which branching is required.
.
• This branch address is usually obtained by
adding an offset X, which is given in the 200 MOV LOC, R1
branch instruction (in the address field of 201 SUB R2, R1
the instruction), to the updated value of
the PC. Main Memory
The Processing Unit
BRANCH INSTRUCTIONS
• Control Sequence for Instruction
Decoder

Unconditional Branching IR
Internal
Processor
Bus

PC
Address Lines
1. PCout, MARin, Read, Select1, Memory
Bus Data Lines
MAR

Add, Zin MDR

R0

2. Zout, PCin, WMFC R1

3. MDRout, IRin .
.
.
Rn-1

4. PCout,, YYinin 1 Y

5. Address-Field-of-IRout, Select MUX

SelectY, Add, Zin ALU

Control
Add
Sub
:
A
ALU
B

6. Zout, PCin, End Lines XOR

Z
Carry-in

The Processing Unit

EXERCISES

1. Write the sequence of control steps required for the following

instruction:

[R1] [[R2]] + [LOC]

2. Assume that each instruction consists of two words and that each
word occupies one address location.

The first word of an instruction specifies the first part of the

operation code and the second word specifies the second part of
the operation code plus the address LOC.

Write the sequence of control signals that will add the contents of
LOC to register R1 and store the results in register R1.

The Processing Unit

SEQUENCING OF CONTROL SIGNALS

• To execute instructions, the processor must

have some means of generating the control
signals (R1in, MDRout, Read, WMFC, etc.).

• Computer designers have used a wide

variety of techniques to solve this problem.

• Most of these techniques, however, fall into

one of two categories: hardwired control
and microprogrammed control.

The Processing Unit

HARDWIRED CONTROL UNIT
Instruction 1 Instruction 2 Instruction 3
R1 [R1] + [[R2]] R1 [R1] + [LOC] Branch

1. PCout, MARin, Read, 1. PCout, MARin, Read, 1. PCout, MARin, Read,

Select1, Add, Zin Select1, Add, Zin Select1, Add, Zin
2. Zout, PCin, WMFC 2. Zout, PCin, WMFC 2. Zout, PCin, WMFC
3. MDRout, IRin 3. MDRout, IRin 3. MDRout, IRin
4. R2out, MARin, Read 4. Address-Field-of- 4. Address-Field-of-
5. R1out, Yin, WMFC IRout, MARin, Read IRout, SelectY, Add,
6. MDRout, SelectY, 5. R1out, Yin, WMFC Zin
Add, Zin 6. MDRout, SelectY, 5. Zout, PCin, End
7. Zout, R1in, End Add, Zin
7. Zout, R1in, End

• To execute instructions, the CPU must be able to generate the right control
signals at the right time.

The Processing Unit

HARDWIRED CONTROL UNIT
Instruction 1 Instruction 2 Instruction 3
R1 [R1] + [[R2]] R1 [R1] + [LOC] Branch

1. PCout, MARin, Read, 1. PCout, MARin, Read, 1. PCout, MARin, Read,

Select1, Add, Zin Select1, Add, Zin Select1, Add, Zin
2. Zout, PCin, WMFC 2. Zout, PCin, WMFC 2. Zout, PCin, WMFC
3. MDRout, IRin 3. MDRout, IRin 3. MDRout, IRin
4. R2out, MARin, Read 4. Address-Field-of- 4. Address-Field-of-
5. R1out, Yin, WMFC IRout, MARin, Read IRout, SelectY, Add,
6. MDRout, SelectY, 5. R1out, Yin, WMFC Zin
Add, Zin 6. MDRout, SelectY, 5. Zout, PCin, End
7. Zout, R1in, End Add, Zin
7. Zout, R1in, End

• The required control signals are uniquely determined by following information:

1. what the instruction being executed is

2. what the current step is

The Processing Unit

HARDWIRED CONTROL UNIT

• The required CLK

indicates what the
current step is
Control Step
control unit is Clock
Counter
based on the use of . . .
a counter (control Status Flags
step counter) driven .
by a clock signal IR .
Decoder/
Encoder
.
(CLK). Condition Codes

. . .
• Each state or count
of this counter indicates what the
Control Signals
corresponds to one current instruction is
step in the
execution of an • The contents of the IR
instruction. represent the current
instruction being executed
The Processing Unit
HARDWIRED CONTROL UNIT

• For example, if IR is indicates what the

CLK current step is
equal to 0000000000, Clock
Control Step
Counter
then Instruction 1 is . . .
being executed.
Status Flags
.
Assume that IR .
Decoder/
Encoder
Instruction 1 is the .
instruction: Condition Codes

. . .

R1 [R1] + [[R2]
Control Signals
indicates what the
• If control step counter current instruction is

is 000000000001, • This means that the control

then it is currently in signals Zout, PCin, and WMFC
the 2nd step. should be activated while the
rest are deactivated.
The Processing Unit
HARDWIRED CONTROL UNIT

CLK
Clock Control Step Reset
CLK Control Step Counter
Clock
Counter . . .
. . .
Step Decoder
Status Flags T1 T2 . . . Tn
. INS1
Decoder/
IR . INS2
Encoder Status Flags
.
. .
Condition Codes Instruction
IR . . Encoder
Decoder
. .
. . .
INSm Condition Codes

Control Signals PCout . . . END

The Processing Unit

HARDWIRED CONTROL UNIT
• The decoder-encoder block is a combinational circuit that
generates the required control outputs depending on the state of
all its inputs.

CLK
Clock Control Step Reset
Counter
. . .

Step Decoder

T1 T2 . . . Tn
INS1
INS2 Status Flags
. .
Instruction
IR . . Encoder
Decoder
. .
INSm Condition Codes

PCout . . . END

The Processing Unit

HARDWIRED CONTROL UNIT

• The step decoder provides a separate signal line for each step, or
time slot, in the control sequence.
T2 = 1 while the 000000000001
rest will be 0 CLK (step 2)
Clock Control Step Reset
Counter
. . .

Step Decoder

T1 T2 . . . Tn
INS1
INS2 Status Flags
. .
Instruction
IR . . Encoder
Decoder
. .
INSm Condition Codes

PCout . . . END

The Processing Unit

HARDWIRED CONTROL UNIT
• The output of the instruction decoder consists of a separate line
for each machine instruction. That is, for any instruction loaded in
the IR, one of the output lines INS1 through INSm is set to 1, and
all other lines are set to 0.
CLK
Clock Control Step Reset
Counter
0000000000 . . . INS1 = 1 while the
(instruction 1) rest will be 0
Step Decoder

T1 T2 . . . Tn
INS1
INS2 Status Flags
. .
Instruction
IR . . Encoder
Decoder
. .
INSm Condition Codes

PCout . . . END

The Processing Unit

HARDWIRED CONTROL UNIT

• All input signals to the encoder block should be combined to

generate the individual control signals Yin, PCout, ADD, END, and
so on.
CLK
Clock Control Step Reset
Counter
. . .

Step Decoder

T1 T2 . . . Tn
INS1
INS2 Status Flags
. .
Instruction
IR . . Encoder
Decoder
. .
INSm Condition Codes

PCout . . . END

The Processing Unit

HARDWIRED CONTROL UNIT

• The control signal Zin, which enables the input to register Z, is

turned on (active) during the following instances: T1 of INS 1 , T6 of
INS1,
1 , T1 of INS2,
INS1,
INS INS2 , T6 of INS2,
INS2 , T11 of INS3,
INS3 , and T44 of INS3.
INS3.

INS1 INS2 INS3

1. PCout, MARin, Read, 1. PCout, MARin, Read, 1. PCout, MARin, Read,

Select1, Add, Zin Select1, Add, Zin Select1, Add, Zin
2. Zout, PCin, WMFC 2. Zout, PCin, WMFC 2. Zout, PCin, WMFC
3. MDRout, IRin 3. MDRout, IRin 3. MDRout, IRin
4. R2out, MARin, Read 4. Address-Field-of- 4. Address-Field-of-
5. R1out, Yin, WMFC IRout, MARin, Read IRout, SelectY, Add,
6. MDRout, SelectY, 5. R1out, Yin, WMFC Zin
Add, Zin 6. MDRout, SelectY, 5. Zout, PCin, End
7. Zout, R1in, End Add, Zin
7. Zout, R1in, End

The Processing Unit

HARDWIRED CONTROL UNIT

• The control signal Zin, which enables the input to register Z, is

turned on (active) during the following instances: T1 of INS 1 , T6 of
INS1,
1 , T1 of INS2,
INS1,
INS INS2 , T6 of INS2,
INS2 , T11 of INS3,
INS3 , and T44 of INS3.
INS3.

• This means that Zin = 1 if:

• The logic equation
for Zin is therefore:
1. (T1 = 1 and INS1 = 1) or
2. (T6 = 1 and INS1 = 1) or Zin = (T1 and INS1) or
3. (T1 = 1 and INS2 = 1) or (T6 and INS1) or (T1
4. (T6 = 1 and INS2 = 1) or and INS2) or (T6 and
5. (T1 = 1 and INS3 = 1) or INS2) or (T1 and INS3)
6. (T4 = 1 and INS3 = 1) or (T4 and INS3)

The Processing Unit

 HARDWIRED CONTROL UNIT
• The logic circuit for Zin is therefore:

Zin = (T1 and INS1) or (T6 and INS1) or (T1 and INS2) or (T6 and INS2) or (T1 and INS3) or
(T4 and INS3)

T1
INS1

T6
INS1

T1
INS2
Zin
T6
INS2

T1
INS3

T4
INS3

The Processing Unit

HARDWIRED CONTROL UNIT

• Simplification:
Therefore, the circuit can be
Since Zin is active at simplified as:
T1 for all
T1
instructions, it can
be concluded that
Zin is active at T1 no T6
matter what INS1
instruction is being Zin
executed. T6
INS2

In other words, if T1 T4
= 1, then Zin = 1. INS3

The Processing Unit

EXERCISE

• Give the simplified logic circuit needed for

the generation of the following control
signals:

1. PCout
2. WMFC

The Processing Unit

HARDWIRED CONTROL UNIT

• Advantages:

‒ Speed.

• Disadvantages:

‒ Requires change in wiring if the design has to be

modified.
‒ Error-prone during design phase.
‒ It requires a more chip area, therefore, it is a
costlier control unit.

The Processing Unit