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A New Triswitching Double Duty High Voltage Gain Boost Converter for DC
Nanogrid Application

Conference Paper · September 2021

DOI: 10.1109/GUCON50781.2021.9573921

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 2021 IEEE 4th International Conference on Computing, Power and Communication Technologies (GUCON)
University of Malaya, Kuala Lumpur, Malaysia. Sep 24-26, 2021

A New Triswitching Double Duty High Voltage

Gain Boost Converter for DC Nanogrid Application
2021 IEEE 4th International Conference on Computing, Power and Communication Technologies (GUCON) | 978-1-7281-9951-1/21/$31.00 ©2021 IEEE | DOI: 10.1109/GUCON50781.2021.9573921

Atif Iqbal Sheetal Gore Pandav Kiran Maroti

Dept. of Electrical Engg. Dept. of Electrical Engg. Dept. of Electrical Engg.
Qatar University Qatar University Qatar University
Doha, Qatar Doha, Qatar Doha, Qatar
[email protected] [email protected] [email protected]

Mohammed Meraj Dr. Mousa Marzband.

Dept. of Electrical Engg. Dept. of Electrical Engg
Qatar University Northumbria University
Doha, Qatar Newcastle upon Tyne, UK
[email protected] [email protected]

Abstract—The Tri-switching Double Duty Converter (TSDDC) enhanced through the isolated converters topologies like fly-
is a new non-isolated high gain DC-DC boost converter topology back and pushpull. In this configuration high gain is obtained
presented in this paper for 400V PV based DC Nanogrid through changing the turns ratio of the transformer, that also
application. The drawback of conventional DC-nanogrid system
is that it uses two dc-dc converter one for stepping up the voltage provides isolation. The disadvantage is that the whole system
the other for maximum power point tracking mechanism(MPPT). becomes bulky, leakage inductance and circulating currents are
This issue was overcome by single TSDCC that performs both high [8]. Voltage Multiplier, Switched Inductor (SI), Voltage
functions(Step-up and MPPT). The proposed converter has three Lift Switched Inductor (VLSI), X-Y converter, and Cascading
switches that are operated by two distinct duty ratio (δ1 and Converters are some of the investigated approaches to enhance
δ2 ). Features of the TSDCC converter that are beneficial are
i) Work on two different duty cycles ii) High voltage gain at gain. In voltage multiplier method the gain is increased by
low duty ratio iii) Lower voltage stress on switches and diode. adding the number of multiplier levels and the duty cycle. In
The TSDDC is simulated for 500 W power with 400V. The this technique the unique arrangement of diodes and capacitors
working of the converter is explained in detail for continuous was built to improve the voltage gain. The shortcoming in this
conduction mode (CCM).The mathematical analysis of voltage method is that number of components required are more as
gain is derived considering the voltage drop of the diode and
neglecting it. The proposed TSDDC converter’s operating concept level rise [9], [10].
and controllability are verified by the simulation results.
Index Terms—High DC-DC converter, Boost converter, Electric
Vehicle Application, Non-Isolated Boost Converter  



I. I NTRODUCTION
 

In recent years there is extensive use of renewable energy
resources in order to preserve the fossil fuels for longer
time and to avoid global warming.Renewable energy sources
include photovoltaic (PV) cells, fuel cells, and wind turbines.

This renewable sources are called clean sources they are ample
in nature,cost-less [1]–[4]. In order to obtain energy from these  
sources it is required to incorporate power electronics devices

like high gain dc-dc converters between the renewable source 
and load. Some of the applications of non-isolated high gain
converter are electric vehicles,UPS and DC Nanogrid. Through 
the conventional isolated boost converter high gain can be


produced only at very maximal duty cycle. The advantage of

this conventional converter is that its design is lucid [5]–[7].

But it has negative impact leading high voltage stress across
switches,increases the switching losses. They are typically Fig. 1: Typical structure of PV based DC-Nanogrid (a) Stan-
used for low and medium voltage range. The gain can be dard Approach (b) New Approach

978-1-7281-9951-1/21/$31.00 ©2021 IEEE 1

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 Another method to have high gain is by adding SI and VLSI CCM (Continuous Conduction Mode) is the mode of oper-
structure. In SI and VLSI [11]–[13] capacitors and inductors ation for the converter, with all components assuming to be
are arranged such that the storage elements gets energized in in ideal.In addition inductors and capacitors are considered to
parallel and discharges in series. In [14], [15] the gain of X-Y be identical for mathematical analysis purpose. The converter
converter is increased by cascading with buck-boost converter. operation is divided in three modes in mode 1 S1 and S2 are
While in SEPIC and CUK converters are cascaded with boost in ON state and S3 is OFF state. In mode 2 S1 and S2 are in
converter, this lowers efficiency of the converter,requires more OFF state and S3 is ON state.In mode 3 all switches S1 , S2
elements and circuit becomes complex. In the last technique and S3 in OFF state.
structure of VLSI and SI are added in X-Y [16], [17] con- • Mode I (0 to δ1 TS )
verter that helps to amplify the gain. In [18]–[20] proposes a • Mode II (δ1 TS to δ2 TS )
topology that operates on single switch with high gain [20]– • Mode III (δ2 TS to TS )
[23]. The usual arrangement of a PV-based DC nanogrid is
depicted in the Fig 1. To obtain maximum power from a PV
source and step up the dc voltage two dc-dc converters are
typically needed as shown in Fig.1a. As per the Fig.1a the first
function of a dc-dc converter is to implement the maximum
power point tracking mechanism (MPPT), while the other dc-
dc converter function is to boost the output voltage. This two
stage power conversion issue is settled by proposing a single
dc-dc converter that will perform the work of boosting the
input voltage and also maximum power point tracking(MPPT)
implementation as shown in Fig.1b. As a result this will save
space and cost of the entire system. The proposed triswitching
double duty converter (TSDDC) converter has some unique
feature are outlined as
• Work on two dissimilar duty cycles
• Voltage gain is high.
• Switches and diodes have lower voltage stress
• Switches S1 ,S2 for MPPT and switch S3 for stepping up
the voltage
The following is the layout of the paper The section II explains
working mechanism of the converter while section III is
about the mathematical derivation. The section IV presents
simulation results and followed by conclusions.

II. W ORKING M ECHANISM OF TSDDC CONVERTER

The TSDDC is as shown in Fig 2.The three MOSFETS are
S1 , S2 and S3 . The switches are driven by two distinct duty
cycles δ1 ,δ2 . The duty cycle for MOSFET S1 and S2 will be
the same δ1 while for MOSFET S3 operates with second duty
cycle δ2 that is given at the end of the first duty cycle. There
are four inductors L1 ,L2 L3 L4 ten didoes D0 to D9 and three
capacitors C0 to C2 .

Fig. 3: Working Mechanisms of TSDDC (a) Mode I (b) Mode

II and (c) Mode III

A. Mode I
In mode 1 MOSFETS S1 and S2 are turned-on while S3 is
turned-off as depicted in Fig 3a. During this time the upper SI
module inductors L1 L2 are in parallel to supply voltage. They
Fig. 2: Proposed Topology are charged through the current path is (Vin -L1 -D3 -S1 -Vin ),as

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diode D1 is forward biased the other current path is(Vin - As per the volt second balance method for the inductors from
D1 -L2 -S1 -Vin ). In the lower part of SI module inductors (2) to(8)
L3 ,L4 are also in parallel to input supply. They are charged {(Vin − Vd )(δ1 ) + ( 2Vin2−4Vd )(δ2 ) + ( 3Vin −V40 −5Vd )(1 − δ1 −
and the current path is (Vin -S2 -L3 -D4 -Vin ),as diode D6 is δ2 )} = 0
forward biased the other current path is (Vin -S2 -D6 -L4 -Vin ).
The capacitor C1 is energized along the path (Vin -D7 -C1 -S1 - (3 + δ1 + δ2 ) (5 − δ1 + 3δ2 )Vd
Vin ) and C2 are charged along the path (Vin -S2 -C2 -D8 -Vin ). V0 = Vin − (10)
(1 − δ1 − δ2 ) (1 − δ1 − δ2 )
The load receives energy from the capacitor C0 . In this mode
D2 ,D5 D9 D0 are reversed biased.Here capacitors C1 and C2
are charging.
B. Mode II
Switches S1 ,S2 are in the OFF state for this mode, whereas
S3 is in the ON state as in above Fig 3b. The each inductor
of upper SI module is in series with each inductor of another
module. However, series combination one inductor from each
module is in parallel with input voltage supply. They are
energised upto the maximum Vin .Just before the cycle end the
current path in this mode (Vin -L1 -D2 -L2 -C1 -D9 -S3 -C2 -L3 -
D5 -L4 -Vin ). The output capacitors C0 discharges its energy
to the load. Here D7 ,D8 ,D0 are reversed biased.
C. Mode III Fig. 4: Voltage Gain curve

Switches S1 ,S2 and S3 is in OFF state as shown above

Fig 3c. From the upper SI module of mode III inductors
L1 ,L2 and L3 ,L4 from lower SI module discharges.In addition
capacitor C1 also discharges to charge the output capacitor
C0 . The current path is (Vin -L1 -D2 -L2 -C1 -D0 -C0 -C2 −L3 -
D5 -L4 -Vin ). Here D7 ,D8 ,D9 are reversed biased.
III. M ATHEMATICAL A NALYSIS OF THE TSDDC
The mathematical analysis is done considering the internal
forward voltage drop of diodes D0 to D9 as (Vd ).Here the
internal resistance of diode,inductors, capacitors and switches
are neglected. Both inductors and capacitors are presumed to
have the same value. In Mode I inductors L1 ,L2 ,L3 and L4
and capacitor C1 , C2 is charged equal to input supply.
VL = Vin − Vd (1)
VC1 = Vin − Vd (2)
VC2 = Vin − Vd (3)
VC0 = V0 (4)
In Mode II- the inductors L1 ,L2 ,L3 and L4 continue charging
as they come in series and capacitor C1 ,C2 discharge
VL = Vin − 3Vd + Vin + Vd (5)
2Vin − 4Vd
VL = (6)
2
VC0 = V0 (7)
In Mode III the output capacitor C0 is charged with the help
of L1 ,L2 ,L3 and L4 , C1 Fig. 5: Characteristics waveform

VL = Vin − 3Vd + Vin + Vd − V0 + Vin − Vd (8) By substituting in (10) Vd =0 the voltage gain is derived as
3Vin − V0 − 5Vd (11). The proposed TSDDC converter’s voltage and current
VL = (9)
4 gain are provided in (11) and (12) with δ1 and δ2 as the

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duty cycle.The constraint on duty selection is such that (δ1
+ δ2 )≤ 1. The graph of the voltage gain curve for the TSDDC
converter with varied duty cycles is illustrated in Fig 4. The
characteristics waveform for this suggested converter can be
seen here in Fig 5. When δ1 =0.85 and δ2 =0.10, the highest
gain attained for this is 79.

V0 (3 + δ1 + δ2 )
= (11)
Vin (1 − δ1 − δ2 )

and current gain is

Iin (3 + δ1 + δ2 )
= (12)
I0 (1 − δ1 − δ2 )

IV. S IMULATION R ESULTS

To confirm the TSDDC converter’s working, it is simulated

in MATLAB 2016B using the design specifications described
in Table I. The gate pulses for the MOSFETS S1 ,S2 and
S3 is presented in below Fig 6. Considering the constraint
on duty cycle they are selected as δ1 =0.5,δ2 =0.3. Switch
S3 is triggered on only after the switch S1 ,S2 are triggered
off. The converter’s voltage gain is determined using the
internal forward voltage drop of the diode as Vd and also
neglecting it. The TSDDC is simulated with the input voltage
as Vin =21V and δ1 =0.5,δ2 =0.3. The corresponding results of
output current, voltage and power waveforms are displayed in
Fig 7a, Fig 7b and Fig 7c respectively.
Fig. 7: (a) Output current (b) Output voltage (c) Output power
TABLE I: Design Specification.

Parameters Value
Input voltage (Vin ) 21V
Input power (Pin ) 500W
Duty cycle (δ1 ,δ2 ) 0.5,0.3
Switching Frequency (Fs ) 50 KHz
Output voltage (V0 ) 400V
Load (R) 320 ohm

Fig. 8: Current and voltage stress across switches S1 ,S2

The output current value Io reaches 1.19A reaches steady

value after 3sec as displayed in Fig 7a. It has been noticed
in Fig 7b the output voltage is around V0 =378V. From Fig 7c
output power is equal to 446W. In Fig 8 it shows the current
and voltages stress across switches S1 and S2 . The maximum
voltage stress across switch S1 and S2 was observed to be
170V during mode II and mode III. The drain to source current
Fig. 6: Gate pulses(a) For switches S1 ,S2 (b) For switch S3 for both switches S1 and S2 is 30A.

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 Fig. 9: Current and voltage stress across switch S3

The current stress and voltage stress are seen in Fig 9 is for
switch S3 . During mode III switch S3 drain to source voltage
is around 349V. This voltage is the addition of voltage across
diode D2 and switch S3 . However it was observed that drain
to source current IDS value is 22A across switch S3 . The
peak inverse voltage across diodes are shown in Fig 10 it can
been seen that across diodes D1 ,D3 ,D4 and D6 the voltage
stress is 85V that is non-conducting in mode-II and mode III
as shown in while the PIV of diodes D2 and D5 is 20V they Fig. 11: Voltage stress across diodes D7 , D8 , D9 and D0
are non conducting in mode I and mode II as shown in Fig 11.
As per the characteristic waveform the voltage stress across
diode D7 and D8 should be half of output voltage. It can be Gate pulses for switches are generated with the help of
seen that in PIV of diode D7 and D8 is 190V that occurs FPGA board of duty cycle δ1 =0.5,δ2 =0.3. It is confirmed that
in mode II and mode III. The diode D7 and D8 is reverse the proposed configuration generates 400V with 22 V of input
biased in mode II and mode III in Fig 11. The voltage stress voltage supply. A 18 V drop is observed in the output voltage
of Switch S3 and diode D9 is 390V that is equal to the output due to the circuit components. The average input and output
voltage. The voltage stress across diode D0 is 390V. Fig. 12 current, drawn by the proposed converter are nearly equal to
indicates the experimental result of input-output voltage and the 21.8 A and 1.27A respectively.
current waveform of the proposed configuration.

Fig. 12: Input-output voltage and current waveform of the

proposed configuration

The three operating modes can be seen from the input

current waveform, which includes a slight peak current at the
start of mode-I. As discussed in theoretical analysis inductor
current is rising with the positive slope in mode I. For mode
II and mode III the inductor current is decreasing with the
negative slope can be seen in Fig. 12. With these current and
voltage value, it can be concluded that the TSDDC converter
Fig. 10: Voltage stress across diodes work with 94% efficiency at the 500W power load.

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 V. C ONCLUSION [11] P. K. Maroti, S. Padmanaban, F. Blaabjerg, L. Martirano, and P. Siano,
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