Ideas

Volume 1

for Design

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 Ideas
forDesign

WILLIAM WONG | SENIIOR CONTENT DIRECTOR, Electronic Design

Welcome to Electronic Design’s

Ideas for Design
In 2012, Electronic Design
celebrated its 60th anniversary. One of
the articles was Reader Submissions
Drive Our Most Popular Department.
It highlighted one of the most popu-
lar sections of the magazine, Ideas for
Design (IFD). These are short articles
that usually have one or two circuit
diagrams, figures or listings that are
examples of useful designs.
Actually, IFD’s first showed up in
Electronic Design in 1968. Walt Jung’s
article, A Look Back At 40 Years Of
Ideas For Design, highlights this event.
His article, “Gated Amplifier Uses FET
in Feedback Loop,” was in the Jan 4,
1968 issue.
Unfortunately, we don’t have a PDF
copy of Walt’s article but we do have
quite a few and we are collecting them
here where you can read and download
them. It takes some time to generate
the PDFs and clean up articles on our
site since many of the older ones are
missing some figures. These were mis-
placed during are many website migra-
tions. But fear not, we are updating
both the online and the PDF versions
so you can examine, dissect and utilize
some of our newer IFDs.
We will have IFDs in our print
archive (see the figure) but there have
been one to four IFDs in every issue of
Electronic Design since they started.
If you would like to add your ideas
to our collection you can contribute
articles to Electronic Design. This will
let you share your ideas with the Elec-
tronic Design community and maybe
even get into the print edition of the
magazine. Yes, we still have a print and
digital edition of the magazine in addi- 1. This Idea for Design appeared in 1970 in a print edition of Electronic Design.
tion to our website. You can access the
Electronic Design Digital Archive by
getting an account on our site. If you
want the latest and greatest you can
subscribe to our newsletters that high-
light all the articles on our site.

02.10.11 ELECTRONIC DESIGN

 Vol. 1, No. 1

Welcome to Electronic Design’s Ideas for Design

Electronic Design opens its archives to bring you Ideas for Design. These short
articles present useful circuits and designs and have been very popular over
the years.

Contestant Controller Is Simple

and Easy to Expand
Game-show “contestant-selection” controllers aren’t new. But the designs are
complicated, especially as the number of inputs grows. This contestant controller is
simple and expands easily. The idea is to keep arbitration to a minimum. The design
has a window of opportunity so small (nanoseconds) that if two or more signals get
through, you can call it a tie.

Simple Circuit Turns PWM Into a Digitally

Adjustable Precision Reference
Designs frequently require the conversion of a microprocessor’s pulse-width-
modulation (PWM) signal into an analog voltage. This circuit uses the ubiquitous
LM431 shunt regulator to implement a second-order Sallen-Key low-pass filter
together with a level shifter.

Simple Circuit Offers Single-Adjustment

Tone Control
Early radio receivers and record players nearly always had a knob marked “tone,”
which was usually a crude low-pass filter with some form of severity adjustment.
At best, these controls could partially compensate for bass loss caused by poor
speaker baffling. A single-adjustment tone control often can be useful for fine
balance adjustment or where multiple controls are impractical or unnecessary.

Click
these Vol. 1, No. 2
other volumes
to
view their Vol. 1, No. 3

contents. Vol. 1, No. 4
Vol. 1, No. 5

Do you have Electronic Design is always on the lookout for new ideas. Do
an Idea for you have one? Our Ideas for Design articles are short and to
the point, often with a single figure or program listing to help
Design for
explain the idea. If you would like to submit one, you can
Electronic
check out the details at
Design?
https://www.electronicdesign.com/contribute.
We look forward to seeing your ideas.
 Vol. 1, No. 2

Circuit Monitors and Protects Against Power

Supply Overvoltage
Systems incorporating microprocessors, FPGA, ASICs and other
expensive devices can sustain costly damage if the power supply voltages
exceed the nominal values. Rather than hoping for the best, good design
practice says you should add circuitry that will indicate an overvoltage
(OV) condition, take corrective action, take protective action, or perform a
combination of all of these functions.

Electronic Load Achieves 0 Ω

The general approach to an electronic load is to use a transistor across
the input terminals so the current flows from drain (collector) to source
(emitter). A resistance is affected by causing a current flow in proportion
to the applied voltage in the manner of a resistor, I = V/R. A controller
monitors the applied voltage and adjusts the current in response. To
achieve 0 Ω, the terminal voltage must be 0 in the presence of a current.

Determine MOSFET Junction Temperature and

Switching Losses for Various Package Types
The junction temperature of power MOSFETs is one of the major criteria
used to obtain temperature derating curves for power converters. This
article describes an improved technique for determining MOSFET
junction temperature and switching losses more accurately based on
the given thermal resistances and lead and case (package) temperature
measurements.

Do you have Electronic Design is always on the lookout for new

an Idea for ideas. Do you have one? Our Ideas for Design
Design for articles are short and to the point, often with a single
Electronic figure or program listing to help explain the idea. If
Design? you would like to submit one, you can check out the
details at
https://www.electronicdesign.com/contribute.
We look forward to seeing your ideas.

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 Vol. 1, No. 3

Single-Chip Circuit Delivers Direction

Information in Encoders
Incremental-rotation or linear encoders are very common, but normally
they don’t provide a direction signal. This design shows an easy way to
detect forward or reverse direction.

Excel Formula Calculates Standard 5% Resistor Value

When using a spreadsheet to calculate circuit values, determining
“standard” component values for use in subsequent calculations can
produce more accurate results. This approach will also result in real-life
solutions to your circuit designs. When 5% resistors will suffice, this Excel
solution provides values that can directly be used for a material list.

Automotive Power-Conditioning
Circuit Eliminates Power-Hold Relay
Automotive electronic control applications require robust input power
conditioning. Circuitry must absorb 100-V transients on the one
hand, while providing a stable dc bus for a few hundred milliseconds
after the ignition is switched off on the other. The use of high-energy
transient absorbers usually meets the former requirement, while an
electromechanical relay handles the latter. This circuit offers novel
solutions for both requirements.

Simple Strategy Safely Connects

Transformerless-Supply Circuits
Low-power circuits commonly use transformerless power supplies.
However, using earth grounds in many of these circuits creates a serious
problem that’s often ignored. This design safely connects transformerless-
supply circuits.

Do you have Electronic Design is always on the lookout for new

an Idea for ideas. Do you have one? Our Ideas for Design
Design for articles are short and to the point, often with a single
Electronic figure or program listing to help explain the idea. If
Design? you would like to submit one, you can check out the
details at
https://www.electronicdesign.com/contribute.
We look forward to seeing your ideas.

Click here to go back to main table of contents

 Vol. 1, No. 4

JFET Follower Amplifier Cancels Distortion

Many improvements to the follower circuit have been proposed over the
years. The White cathode follower doubles the output current and makes
the transfer function more linear. Adding a common-base amplifying stage
(current follower) significantly improved the White follower’s power-supply
rejection ratio.

Synthesized Inductor Delivers Maximum Power Transfer

To transfer maximum power from a circuit to a load, the load’s resistance,
RL, must match the source resistance. In the case of a complex load, ZL,
and a resistive source, this transfer can require the use of a bulky inductor.
This idea shows how to replace the physical inductor with a smaller
synthesized inductor.

Improved Power-Factor Corrector Further Minimizes

Miller Effect
Adding a discharge path to the upper MOSFET of a cascode circuit
significantly reduces the unavoidable Miller effect and thus the PFC
performance of a power supply’s front end can be improved.

LM555 Makes Inexpensive Power Driver

The venerable 555-type timer makes an effective driver for power
MOSFETs, but you have to understand the drive situation when selecting
the correct variation of the basic timer. This idea shows how the wrong
choice led to unreliable operation and failure, and the basic analysis that
points to the correct choice.

Do you have Electronic Design is always on the lookout for new

an Idea for ideas. Do you have one? Our Ideas for Design
Design for articles are short and to the point, often with a single
Electronic figure or program listing to help explain the idea. If
Design? you would like to submit one, you can check out the
details at
https://www.electronicdesign.com/contribute.
We look forward to seeing your ideas.

Click here to go back to main table of contents

 Vol. 1, No. 5

Inexpensive Solution Protects Sensitive

Devices From Surges
A Zener diode and small resistor can create an inexpensive and effective
voltage surge protector for sensitive devices. The tricky part is choosing
the right suppressor and value for the resistor.

Stabilize SMPS With Slope Compensation Resistance

This idea describes how to compute the value of the slope resistor,
Rsl, that will create the desired voltage pulse slope needed to maintain
reliability and robustness of a current-control SMPS at pulse duty cycles
above 0.5.

Best IFDs Demonstrate Engineering Elegance

The Ideas for Design department is one of the most popular and widely
followed sections of Electronic Design, and with good reason: It embodies
the essence of engineering. How so? In an IFD, an engineer takes
standard parts and connects them in a clever, innovative configuration to
solve a specific problem simply and crisply, and usually at lower cost than
alternative approaches. Furthermore, since in most cases it’s a circuit
alone without needing any software to function, anyone can look at the
schematic and description to study, follow, and grasp the design’s intent
and execution.
This year’s Best Idea for Design, “Simple Circuit Turns PWM Into a
Digitally Adjustable Precision Reference” by Rick Mally, tackles a common
design dilemma of needing a function that is both precise and adjustable,
preferably via digital control.

Do you have Electronic Design is always on the lookout for new

an Idea for ideas. Do you have one? Our Ideas for Design
Design for articles are short and to the point, often with a single
Electronic figure or program listing to help explain the idea. If
Design? you would like to submit one, you can check out the
details at
https://www.electronicdesign.com/contribute.
We look forward to seeing your ideas.

Click here to go back to main table of contents

 for Design
Ideas
RICHARD BEDELL | GEORGIA INSTITUTE OF TECHNOLOGY

Contestant Controller
[email protected]

Is Simple And Easy To Expand

GAME-SHOW “CONTESTANT-SELECTION” CONTROLLERS aren’t new. Each contestant’s input contains a D flip-flop (U1) with the
But the designs are complicated, especially as the number contestant button connected to the positive-edge clock input.
of inputs grows. This contestant controller is simple and Once the button is pressed, the high on the D input is clocked to
expands easily. the output and any further pressing of the button does nothing,
The idea is to keep arbitration to a minimum. In other words, effectively disconnecting
_ the button.
minimize the possibility of two or more contestants getting The Q and Q outputs of the D flip-flop go to the J-K flip-flop
through the circuit and then having to arbitrate which contes- (U2), with the Q output passing through an inverter (U3). The
tant is selected. The key is to minimize the “window of oppor- table shows the J-K input logic. The CLK input is a negative-
tunity” during which two or more signals can pass through the edge triggered input. Because the K input is tied to ground,
circuit. The smaller the window, the less likely arbitration will there are only two
be needed. states the flip-flop can
This design has a window of opportunity so small (nanosec- transition to when the J-K FLIP-FLOP TRUTH TABLE
onds) that if two or more signals get through, you can call it a clock signal occurs:
tie. If arbitration is still desired, a microcontroller or scanning “no change” or “set.” J K Qnext Result
multiplexer could continuously scan the output and stop on the The inverter 0 0 No change No change
first signal it detects. between the D
0 1 0 Reset
The circuit uses J-K flip-flops to allow one signal through and J-K flip-flops
and block the rest, with the J and K inputs allowing the flip- sets the window of 1 0 1 Set
flop to toggle or not (see the figure). The starting state of all opportunity. As an 1 1
–
Q prev Toggle
flip-flops is CLR. (All Q outputs equal 0.) open-drain device, it

+3.3 V

Reset R9
+3.3 V
10k R15 +3.3 V
+3.3 V
CLR +3.3 V 100
+3.3 V
+3.3 V +3.3 V R12
SW5 Q1
R1 14 4.7k U2a 16 R14
R2 U1a D1
14 100
10k +3.3 V 2 1 2 3 5
Contestant 1 100 14 D VCC Q 5 J VCC Q
1 2 3 6 U3a 2
CLK K 6
1 Q 7 74LVC06 Q
SW1 1
C1 U4a 7 CLR CLR CLK
4 15
4.7 µF 74LVC04 PRE CLR
+3.3 V GND CLR
4
PRE
74LVC74 7 +3.3 V GND
8 74LVC112 R17 +3.3 V
+3.3 V
100
Q2
R3 U2b 74LVC112 R16
R4 U1b 74LVC74 D2
10k 12 3 4 100
100 U4b +3.3 V D 9 11 9
Contestant 2 3 4 Q J Q
11 8 12 7
CLK Q K
13 U3b Q
SW2 CLR CLR 13
C2 74LVC04 10 74LVC06 CLK
PRE 14
4.7 µF +3.3 V CLR CLR
10
PRE
+3.3 V
+3.3 V

Start timeout R10 To additional input circuits

10k
This two-input version of the con-
Start Timeout circuit 11 10
SW6 A high output blocks all inputs.
testant-selection circuit can easily be
CLR Reset A low output allows inputs to pass. expanded by adding additional input
U3c
74LVC06 sections connected in a similar fashion.
IdeasForDesign

allows logical ORing with inverters from other contestant ORing with the output of the open-drain inverters or using an
inputs and connects to all J inputs of the J-K flip-flops. unused contestant input. The timeout circuit can be anything
U3 inverts the Q output_from the D flip-flop and delays it from a button to an RC circuit or some other timing circuit.
long enough to allow the Q output of the D flip-flop to clock Because flip-flops generally come packaged in pairs, the
the J-K flip-flop while the J input is still low. Once the delayed number of inputs would be even. Additionally, the design
Q output passes through the inverter, all the J inputs are taken scales up linearly. Simply add contestant sections connected
to 0. At this point, any clock signals on any of the J-K flip- as the first two are connected. The circuit was built using stan-
flops will not change the output. dard 5-V transistor-transistor logic (TTL) and open-collector
The outputs of the J-K flip-flops can then drive indicators inverters. The CMOS version of TTL was not tested but should
directly or be used as inputs to a microcontroller to ensure one function similarly.
output is selected in the unlikely event that two signals get through.
As noted, you could also use a multiplexer (several to one) to count RicHaRD BeDell is an electrical engineer with the Georgia
through the outputs, stopping on the first output that is detected institute of Technology chemistry Department, where he
high. The count would then reflect the winning contestant. maintains research equipment and designs for research and
Resetting the circuit is simply a matter of clearing the flip- support applications. He has a BS in electrical engineering
flops. A timeout signal can be implemented in two ways: from the Georgia institute of Technology.

rick Mally | Independent desIgns, denver, Colo. [email protected]

Simple Circuit Turns PWM Into

A Digitally Adjustable Precision Reference
Designs frequently require the conversion of a microproces- The value of VOut is equal to (5 V × dc) – 2.5 V, where dc is the
sor’s pulse width modulation (PWM) signal into an analog PWM duty from 0.0 to 1.0 (0% to 100%).
voltage. Often a passive single-pole RC filter will satisfy The component values depicted provide a flat response with
design requirements, but this approach typically suffers from a cutoff frequency around 2300 Hz, a –12-dB/octave roll-off,
several drawbacks including slow response time, noisy results, and drive capability of about 3 mA. You can easily change
and having an unbuffered output. the cutoff frequency by adjusting R1 and R2 or C1 and C2,
The circuit described here uses the ubiquitous LM431 shunt although it is important to keep R1 equal to R2 and C2 at about
regulator to implement a second-order Sallen-Key low pass half the value of C1.
filter together with a level shifter (see the figure). Compared to Doubling the resistor or capacitor values will cut the fre-
the traditional approach, it provides a far sharper roll-off along quency in half. Halving either set of values will double the cut-
with a low-impedance output, bipolar output. It will produce off frequency. You can adjust R3 to provide more output cur-
a –2.5- to +2.5-V output with a 0- to 5-V PWM signal input. rent or to reduce power consumption. The 5-V rails depicted
do not have to be precise and can be a higher voltage. Only the
+5 V
R1 R2 PWM input signal needs to be precisely 5 V.
10k 10k
PWM signal in IC1 Because it uses only six components, this circuit can be very
0/+5 V LM431 cost effective. The LM431 can be purchased for as low as 10
C2
C1 0.0047 µF cents in single-unit quantities, well below that of any op amp.
0.01 µF
R1 = R2
C2 ~
– 0.5 × C1 DC voltage out Editor’s Note: See Texas Instruments Application Report
±2.5 V
SLOA024B, “Analysis of the Sallen-Key Architecture,” for
R3 additional information on Sallen-Key filters.
499

–5 V Rick Mally is the sole proprietor of independent

Designs, a small-scale custom electronic design and
A shunt regulator acts as the feedback element in a low-pass Sallen-Key light manufacturing firm for clients with a low budget.
filter, converting a 5-V PWM signal to a dc value between –2.5 V and 2.5 He was home-schooled and self-educated in many
V based on duty cycle. disciplines, primarily in the electronics field.

ElEctronic DEsign Go To www.elecTronicdesiGn.com

IdeasForDesign

dErEk F. BowErs | AnAlog Devices, sAn Jose, cAlif. [email protected]

Simple Circuit Offers

Single-Adjustment Tone Control
0
R1 C1 R2
200 47 nF 3.6k

Amplitude response (dB)

–5
Treble boost/bass cut
0% (center)
VIN VR1 VOUT –10
50k 20%
Bass boost/treble cut
(Linear) 40%
60%
–15
R3 C2 80%
R4
3.6k 47 nF
200 100%
–20
20 100 1.0k 10k
(a) Frequency (Hz)

0
1. This simple circuit allows single-adjustment tone control for fine bal-
ance adjustment or applications where multiple controls are impractical.
Amplitude response (dB)

–5
Early radio rEcEivErs and record players nearly always had a
0% (center)
knob marked “tone,” which was usually a crude low-pass filter –10 20%
with some form of severity adjustment. At best, these con- 40%
trols could partially compensate for bass loss caused by poor 60%
speaker baffling. More sophisticated controls were developed –15
80%
for more modern equipment, including the bass/treble (Baxan- 100%
dall) controls, parametric equalizers, and graphic equalizers. –20
20 100 1.0k 10k
Nevertheless, a single-adjustment tone control often can be (b) Frequency (Hz)
useful for fine balance adjustment or where multiple controls
are impractical or unnecessary. A simple version of such a 2. The tone-control circuit delivers good response characteristics in both
control provides a symmetric response that is flat at the center the lower half (a) and upper half (b) of the control range.
of the adjustment range (Fig. 1).
Moving the control in one direction simultaneously boosts Naturally, for stereo, the circuit would be duplicated and
the treble and cuts the bass until about 5.5 dB of boost and VR1 substituted with a dual, ganged component. Since the
23 dB of cut are obtained. Moving the control in the other circuit is purely passive, it is easy to insert in the signal chain.
direction boosts the bass and cuts the treble in an identical However, it must be preceded by a low impedance (below 100
fashion. Figure 2 shows the typical curves obtained from 20 Ω) and followed by a high impedance (more than 250 kΩ) for
Hz to 20 kHz with a 1-kHz center frequency, for the lower half best results. Under these circumstances, insertion loss (at cen-
and upper half of the control range, respectively. ter) approaches 6 dB.
Since this is a purely passive circuit, all component val-
ues may be scaled without affecting the ac transfer function.
With lower resistor values (and higher capacitor values), the
signal-to-noise ratio improves, but the circuit requires a lower
Send us yor Ideas For Design. We’ll pay you $150 for every Idea For
impedance to drive it. The values shown represent a good com-
Design that we publish. In addition, this year’s top design as selected by promise. Overall signal-to-noise ratio in a 20-kHz bandwidth
our readers will earn an additional $500, with two runners up each is about –113 dB referenced to 1 V rms with the control in the
receiving $250. You can submit your Ideas For Design via:
center position.
• E-mail: [email protected]

Or bY
• Postal mail to: Derek F. Bowers is a Fellow at Analog Devices, where
Ideas For Design he designs monolithic amplifiers, non-linear circuits, and
Electronic Design digital-to-analog converters. He has been with the com-
249 W. 17th Street,
New York, NY 10011 pany since its acquisition of Precision Monolithics in 1990,
Go to www.electronicdesign.com for our submission guidelines. which he had previously joined in 1978.

ElEctronic DEsign
 for Design
BRAD ALBING | INTERSIL CORP.

Circuit Monitors And Protects

[email protected]
Ideas
Against Power Supply Overvoltage
SYSTEMS INCORPORATING MICROPROCES- VIn VIn The divider resistors are R1 and R2
SORS, FPGAs, ASICs, and other expen- (3.40 V) (3.60 V) (upper and lower resistors, respectively),
sive devices can sustain costly damage which set the overvoltage trip-point for
if the power supply voltages exceed the R1 R3 the ISL6132’s OVMON_1 input, and
nominal values. Rather than hoping for 8.66k 9.38k R3 and R4, which set the overvoltage
the best, good design practice says you OVMON_1 OVMON_2 trip-point for OVMON_2 (Fig. 1). For
should add circuitry that will indicate an (633 mV) (633 mV) example, assume the system operates
overvoltage (OV) condition, take cor- R2 R4 with a 3.30-V dc bus. Then assume we
rective action, take protective action, or 2.00k 2.00k want an alarm indication to occur if the
perform a combination of all of these supply bus voltage rises to 3.40 V dc,
functions. and we want to take protective action if
The OV indicator can be an audible 1. The overvoltage protection circuit employs two the voltage rises to 3.60 V dc.
or visual alarm. Correction can take the voltage divider circuits that set the overvoltage The voltage dividers reduce the
form of additional active circuitry that trip points for the voltage monitoring/supervising applied voltage to match the ISL6132’s
adjusts or clamps the higher-than-nor- IC, inputs OVMON_1 and OVMON_2. internal reference voltage. The internal
mal voltage. Protection usually involves comparators act when the applied volt-
forcibly shutting down the power supply. age just exceeds the reference voltage. Assuming that the input
To decide if an OV condition exists, you will probably want current to the comparator is negligible, and the reference volt-
to use a separate, standalone detection circuit with an accurate age is typically 633 mV, the standard voltage divider formula
trip-point. The advantage of a standalone detector compared provides the resistor values:
to a power supply that detects its own overvoltage condition
becomes clear if a failure mode effects analysis is performed. VOut = VIn – R2/(R1 + R2)
With separate circuitry, a single-point failure can be prevented
from causing an overvoltage condition. where VOut is 633 mV, and VIn is 3.40 V or 3.60 V. If you select
To get an accurate trip-point, avoid using Zener diodes. R2 as some standard value, e.g., 2.00 kΩ, you can calculate R1.
They generally have poor initial accuracy, an undesirable For the 3.40-V detection circuitry, R1 is 8.74 kΩ. For the
temperature coefficient, and an undesirable voltage versus cur- 3.60-V detector, R1 is 9.38 kΩ. For practical purposes, pick the
rent characteristic (a soft knee). A voltage reference diode/IC nearest 1% values. To add some adjustment range in the trip-
or a voltage monitoring IC will provide better results. These points, insert a trimmer potentiometer between the upper and
devices usually feature an accurate, sta- lower resistors (Fig. 2).
VIn VIn
ble comparator and an accurate voltage For example, use a 500-Ω trim-pot
(3.40 V) (3.60 V)
reference, and they may include on-chip and subtract 250 Ω from each of the
voltage divider resistors. Designers can R1 R3
upper and lower resistor values. Then,
also add voltage divider resistors exter- 8.45k 9.09k pick the nearest standard value. The
nal to the IC. If so, they should be accu- result is 8.45 kΩ, 500 Ω, and 1.74 kΩ for
R5 OVMON_1 R6 OVMON_2
rate (1% tolerance or better) resistors 500 (633 mV) 500 (633 mV) the 3.40-V divider and 9.09 kΩ, 500 Ω,
with a low temperature coefficient. and 1.74 kΩ for the 3.60-V divider.
The Intersil ISL6132 is an easy to use, R2 R4 Those who would prefer to avoid
flexible voltage monitoring/supervising 1.74k 1.74k algebraic manipulation can use an alter-
IC. It has two comparators intended for native method for calculating the divider
undervoltage detection, two comparators resistor values. As before, assume you
for overvoltage detection, and an accu- 2. The addition of trimmer potentiometers to the want to get a specific output voltage,
rate reference voltage. This application divider circuits provides the ability to make makes VOut, from the divider with a specific
uses the two OV detectors to implement adjustments to the trip points. The divider resis- input voltage, V In, and that the input
two of the three previously described tors’ values should be modified to account for the current to the comparator is negligible
functions: indication and protection. potentiometers’ values. (Fig. 3).

ELECTRONIC DESIGN GO TO WWW.ELECTRONICDESIGN.COM

IdeasForDesign

Select the lower resistor, R1, as some and the circuit’s common ground (Fig. (OVSTATUS_2) can be used to shut off
convenient value—1.0 kΩ, 10 kΩ, or 4). Typically, 1 nF to 0.1 µF is suf- the monitored power supply.
such. Using Ohm’s law, calculate the ficient. Since the circuit does not use The preferred implementation (which
current through that resistor: V In/R1. the ISL6132’s undervoltage detection is usually called a crowbar circuit) con-
This is also the current through the upper inputs (UVMON_1 and UVMON_2), sists of a silicon controlled rectifier
resistor, R2. The voltage across R2 is they should be connected to the circuit’s (SCR) that’s connected across the pow-
VIn less VOut. R2 can then be calculated common ground. er supply bus being protected. OVSTA-
using Ohm’s law. The device’s overvoltage 1 output TUS_2 triggers the SCR’s gate. The
If you want to minimize the response (OVSTATUS_1) can be used to light gate should be bypassed with a 0.1-µF
to very narrow voltage transients, you an LED, energize an audible alarm, or capacitor so the SCR isn’t triggered
can add small capacitors (C1 and C2) provide an input to an FPGA or micro- by the rapid dv/dt of the supply bus at
between the potentiometers’ wipers processor. The overvoltage 2 output power-up.

VIn To LED, audible alarm, FPGA, or microprocessor

From output
of regulator
being
monitored
OVSTATUS_1

OVSTATUS_2
R2 R1
UVSTATUS_1

UVSTATUS_2
8.45k
Alternate
VOut R5 connection:
500 raw dc
VDD input to
R1 regulator
R2 1.0k
UVMON_1 1.74k SCR1
GND
UVMON_2

OVMON_1
3. An alternative method of determining the PGOOD1 OVMON_2 1.0k 0.1 µF
voltage divider resistors involves using the PGOOD2 R3
9.09k
known voltages, VIn and VOut, and simple
Ohm’s law calculations. C1 R6
500

R4
C2
Brad alBing is a senior field 1.74k

applications engineer at intersil,

with almost 30 years experience
in electronic design. He holds a 4. The complete circuit includes two capacitors, C1 and C2, that minimize its response to very narrow
BSE from the University of akron. voltage transients. The IC’s OVSTATUS_2 output triggers the SCR connected across the power supply.

henry SanTana | [email protected]

Electronic Load Achieves 0 Ω

The general approach to an electronic load is to use a transis- ≥ IIn(max) × RS + VDS@I(max), is sufficient to maintain forward
tor across the input terminals so the current flows from drain conduction with VIn = 0 and 0 < IIn ≤ IIn(max). This condition
(collector) to source (emitter). A resistance is effected by caus- corresponds to an effective zero input resistance.
ing a current flow in proportion to the applied voltage in the It can be shown that RIn = α × k × RS for 0 ≤ α ≤ 1 and
manner of a resistor, I = V/R. A controller monitors the applied where k multiplies RS so it can be made small to reduce power
voltage and adjusts the current in response (Fig. 1). loss. If, for example, RS = 1.0 Ω, k = 100, then 0 ≤ RIn ≤ 100
To achieve 0 Ω, the terminal voltage must be 0 in the pres- Ω for 0 ≤ α ≤ 1. If IIn(max) = 1 A and VDS@I(max) = 2 V, then VB
ence of a current. Under this condition the pass transistor suf- ≥ 3 V.
fers a loss of operating voltage and cannot conduct a current. In virtually all applications, the pass transistor must be
To maintain conduction of the pass transistor, an auxiliary heatsinked as the power dissipated is IIn(max) × (VIn(max) +
power supply is connected (Fig. 2). The required voltage, VB VB) – IIn(max)2 × RS. If in this example VIn(max) = 15 V, the pass

ElEctronic DEsign
IdeasForDesign

transistor would have a maximum dissipation of 17 W. This Furthermore, even with a low RDS(on), a MOSFET will not
would appear as a 15-W resistor adjustable over 0 to 100 Ω. conduct at 0 V (VDS). At high currents, a MOSFET requires
You may be wondering why an additional power source was non-zero voltage (see note A) to sustain conduction. This cir-
introduced between the source of the MOSFET and the current cuit will maintain VDS right into a virtual short circuit.
sense resistor to achieve a “0-Ω load” condition (essentially a Finally, a hard switch such as a relay does not permit a
short across input voltage) in Figure 2. After all, why would smooth transition of resistance. The circuit described here
you need an electronic load that can go down to 0 V (i.e., short acts more like a rheostat but with the ability to be voltage con-
circuit) condition? trolled (see note B) from a remote point. The controller does
If you wanted to short an electronic load, you could always not have to carry the load current. It would require multiple
use a relay directly across the input voltage. Or if you wanted relays to apply a range of loading. This circuit can provide
it to be all solid state, you could place another MOSFET that smooth (stepless) effective resistive loading over a large range
has much higher current capacity (and very low RDS(on) that including 0 Ω.
approaches a few milliohms) directly across the input and turn The circuit can be scaled up to higher voltages and currents.
it on using a switch. This approach would be much simpler Figure 3 shows an application. For a derivation of the equa-
(and cost effective) than adding a second power supply in tions, e-mail the author at [email protected].
series with sense resistor. So, why would you use the addi-
tional power source? Note A: For example, an RFP30N06 MOSFET has a specified RDS(on)
Here’s the answer. This electronic load can check low- of 0.047 Ω. At 30 A this device requires at least 2 V VDS. This would
voltage power supplies (i.e., 3.3 V and lower) where a voltage not be an effective short circuit on a 3.3-V, 30-A power supply. On a
burden (i.e., 1 V) would not permit testing under short-circuit 1.8-V supply, it would not conduct this current.
condition. This is useful in testing the short-circuit response of Note B: The effective resistance can be controlled with a voltage-
power supplies, current trip level, and effectiveness of over- controlled amplifier (see “Op Amp And Two JFETs Form A Voltage-
load protection. Controlled Amplifier” at electronicdesign.com).

IIn RIn = ȼ × k × RS
IIn
VIn
VIn
Q D A1 15 V max
0 < RIn ≤ a × k × RS +15 V
+ Q1 RFP12N10L LT1006 1.0 A max
Aż∞ 1.0 µF
A 7 3 C2
+
– G
I In 6 2 0 ≤ RIn ≤ 100
4 –
S
CW 3 RS –15 V
2 –
k
2.5 V
a 1 C1 0.1 µF
+
A2 +24 V R4
CW 10k
LT1006
1. An electronic load typically employs a transistor across the input termi- R1 RV1 3 7
+
nals so the current flows from drain (collector) to source (emitter). 1.0 100k 6
K = 100
2
– 4
5 R3
1 –15 V
VIn 10k
0≤a≤1
Adjust RV1 for required RIn
IIn
Q CW
0 < RIn ≤ a × k × RS 3
+ R2
2 RV2
Aż∞ A –5 V 100
10k
– 1
IIn
Maximum power
– VB
dissipated in Q1= 16.5 W Adjust RV2 for 0 VIn at IIn(max) and a = 0

+ Auxiliary power supply 3. An application circuit like this one achieves a zero-load condition for
CW 3 RS testing low-voltage power supplies.
2
k
a 1

Henry Santana is a former senior electronic engi-

2. To maintain conduction of the pass transistor for a zero-load condition, neer with CSt Corp. He has a BSee from Colorado State
the circuit uses an auxiliary power supply. University, Fort Collins.

ElEctronic DEsign Go To www.elecTronicdesiGn.com

 for Design
Ideas
ALEXANDER ASINOVSKI | MURATA POWER SOLUTIONS INC., MANSFIELD, MASS.

Determine MOSFET Junction Temperature And

[email protected]

Switching Losses For Various Package Types

THE JUNCTION TEMPERATURE of power MOSFETs is one of the Using Equation 1 implies that Pj can be determined under
major criteria used to obtain temperature derating curves for any operational condition and that the total power generated
power converters. This article describes an improved technique inside the package is dissipated to ambient through the drain
for determining MOSFET junction temperature and switching leads. In reality, the accuracy of the Pj calculation is relatively
losses more accurately based on the given thermal resistances low because switching losses in the MOSFET cannot be calcu-
and lead and case (package) temperature measurements. lated accurately enough. Also, since a portion of Pj is dissipat-
To keep the junction temperature (Tj) within specifications, ed to ambient through the MOSFET package, the actual heat
allowable drain (leads) temperature (TD) is often calculated as: flow through the drain leads is smaller than Pj, which presents
another source of error.
TD = Tj – (Pj ñ ĤJD) (1) The more accurate technique starts by considering the MOS-
FET thermal model in the figure, which is a modification of the
where Pj is the total heat power generated inside the package model used in “Estimating TJ of SO-8 Power MOSFETs” at
(including conduction, switching, and gate losses), and ĤJD www.irf.com/technical-info/designtp/dt99-2.pdf.
is the junction-to-drain (leads) thermal resistance, which is a According to this model, the total heat generated in the
package-related parameter provided in the MOSFET’s data package, represented by current source Pj, flows to ambient
sheet. The table shows typical values of ĤJD for some standard through two parallel branches. The first is the junction-drain
power MOSFET packages. (leads)-to-PCB-to-ambient route (the “drain” or “lead” branch,
For example, if a MOSFET in an SO8 package (Ĥ JD = labeled P jD) with junction-to-drain thermal resistance ĤjD,
15°C/W) dissipates a Pj of 1 W and must maintain a junction drain-to-PCB thermal resistance ĤDB, and PCB-to-ambient
temperature below 125°C, then the measured drain tempera- thermal resistance ĤBA.
ture must not exceed 110°C according to Equation 1: The second is junction-to-case (package)-to-ambient (the
“case” or “package” branch, labeled PjC) with junction-to-case
TD = 125°C – (1 W ñ 15°C/W) = 110°C (2) thermal resistance ĤjC and case-to-ambient thermal resistance
ĤCA. The model represents the case temperature as TC and the
ambient temperature TA by a voltage source.
PjD ȏjD ȏDB Applying conventional electrical circuit analysis and Ohm’s
(+)
law to the model, we obtain the following equations for the
heat (PjD and PjC) flowing through the respective drain and
case branches:
ȏBA
(+)
PjD = Pj/(1 + ĤD/ĤC) (3)
PjC ȏjC ȏCA
PjC = Pj/(1 + ĤC/ĤD) (4)
(+)

where ĤD = ĤJD + ĤDB + ĤBA (total drain-branch thermal resis-

Tj
Pj + tance) and ĤC = ĤjC + ĤCA (total case branch thermal resis-
TD TC TA
tance). So, total heat flow Pj is:
–
Pj = PjD + PjC (5)

(–) (–) (–) Applying Ohm’s law to the combinations of thermal resis-
tances in each branch of the diagram in the figure, we get two
This modified thermal model of a MOSFET illustrates how the total heat equations for junction temperature:
Pj generated in the device is dissipated to ambient through two parallel
branches: junction-to-drain (leads)-to-PCB-to-ambient and junction-to-case Tj = TD + [(TD – TA) ñ ĤjD]/(ĤDB + ĤBA) =
(6)
(package)-to-ambient. TD + [(TD – TA) ñ
ĤjD/ĤDA]

ELECTRONIC DESIGN
IdeasForDesign

TYPICAL VALUES OF THERMAL RESISTANCE

Thermal
Package type
resistance
ºC/W DirectFET PowerPAKSO8 DPAK D2PAK LFPAK SO8
1 1.5 1.5 1.5 2 15

Tj = TC + [(TC – TA) ñ ĤjC]/ĤCA (7) For a more accurate Tj calculation based on Equation 6,
ĤDA, which is not available from MOSFET datasheets, can
Neither of these equations contains the troublesome heat pow- be determined. According to the model, junction-to-ambient
er term, Pj, and either one can be used to calculate the junction thermal resistance, ĤjA, which is provided in datasheets, is a
temperature, Tj, as long as the case, drain, and ambient tempera- parallel combination of ĤD and ĤC resistances and ĤDA = ĤD –
tures and the thermal resistances of the package are known. ĤjD. Applying this to the model, we can get:
Consider a typical SO8 power MOSFET with thermal resis-
tances ĤCA = 380°C/W, ĤJC = 18°C/W, ĤJD = 15°C/W, and ĤDA ĤDA = ĤjA/(1 – ĤjA/ĤC) – ĤjD (12)
= 20°C/W (given in “Estimating TJ of SO-8 Power MOSFETs,”
again). Substituting these values into Equations 3 and 4, we Taking into account that ĤC is approximately an order of
obtain: magnitude greater than ĤjA, Equation 12 can be simplified as:

PjD/Pj = 1/[1 + (15 + 20)/(18 + 380)] = 0.92 (8) ĤDA ≈ (1.1 ñ ĤjA) – ĤjD (13)

PjC/Pj = 0.08 (9) Substituting Equation 13 into Equation 6, we get:

In other words, 92% of the total power generated in the sili- Tj ≈ TD + [(TD – TA) ñ ĤjD]/[(1.1 ñ ĤjA) – ĤjD] (14)
con is dissipated to ambient through the drain, and the remain-
ing 8% is dissipated through the case. where all the thermal resistance values are available from the
Another important observation is that ĤCA is much greater datasheets.
than any other thermal resistance in the system, which makes We calculated the junction temperature based on parameters
the second term in Equation 7 relatively small. Assuming TC specified on a MOSFET’s datasheet and temperature mea-
= 125°C and TA = 85°C for the set of parameters given above, surements taken from the component under test conditions. A
Equation 7 gives a junction temperature of: conventional measurement technique for the drain (lead) and
case (package) temperature uses thermocouples placed on the
Tj = 125 + [(125 – 85) ñ 18]/380 = 126.9°C (10) package and on the lead areas.
This technique results in measured temperatures that are
This is only 1.9°C greater than the case temperature. Using lower than actual temperatures for two reasons. First, the
Equation 6, the drain temperature is: thermocouple itself works as a heatsink, cooling the device
down. Second, its physical placement is critical when trying
TD = {Tj + [(TA ñĤjD)/ĤDA)]}/(1+ ĤJD/ĤDA) = to determine the device’s hottest temperature. A more accurate
(11)
{126.9 + [(85 ñ 15)/20)]}/(1 + 15/20) = 108.9°C temperature measurement method uses an infrared camera to
determine the hottest temperature in the areas of interest (case
So, the drain temperature is 16.1°C lower than the case tem- and lead) without interfering with the heat flow.
perature. This implies that for an SO8 power MOSFET with Once the junction temperature is determined, the total power
a ĤjD on the same order as ĤDA and with a ĤCA much greater generated in the silicon, Pj, can be calculated:
than ĤJC, the drain temperature tends to be lower than the case
temperature. Also, the plastic case temperature is an accurate Pj = (Tj – TA)/ĤjA (15)
representation of the junction temperature.
According to the measured results in “Estimating TJ of SO-8 where ĤjA is the junction-to-ambient thermal resistance avail-
Power MOSFETs,” the difference between Tj and TC for SO8 able from the MOSFET’s datasheet. Pj also can be calculated
packages is typically 1°C to 3°C. If we use the same equations based on Equation 3 and the junction-to-drain thermal resis-
for other MOSFET packages, like PPAKSO8, D2PAK, DPAK, tance, which is also available from the datasheets:
and LFPAK with low junction-to-drain thermal resistances
(see the table, again), both the drain and case temperatures are Pj = [(1 + ĤD/ĤC) ñ (Tj – TD)]/ĤjD (16)
close to the junction temperature. For DirectFET type MOS-
FETs with metal cases, ĤJD is even lower and, according to Although ĤD and ĤC are not available from the datasheets, ĤC
Equation 6, the drain temperature is an accurate representation is approximately one order greater than ĤD, so Equation 16 can
of the junction temperature. be simplified as:

ELECTRONIC DESIGN GO TO WWW.ELECTRONICDESIGN.COM

IdeasForDesign

Pj ≈ [1.1 ñ
(Tj – TD)]/ĤjD (17) ALEXANDER ASINOVSKI, principal

engineer of Murata Power Solutions Inc.,
After Pj is determined, switching losses, PSW can be calcu- Manfield, Mass., holds BSEE and MSEE degrees
lated in the conventional way: from State Technical University, St. Peteresburg,
Russia, and a PhD from the University of
PSW = Pj – Pdc – Pg = Telecommunications, St. Petersburg.
(18)
Pj – [Irms2 ñ RDS(on)] – [Q ñ Vg ñ FSW]
where Pdc = conduction (dc) losses, Pg = gate drive losses, Irms
= the rms value of the drain current, RDS(on) = the MOSFET on
resistance, Q = total gate charge, Vg = peak gate voltage, and IDEAS FOR DESIGN WANTED
FSW = switching frequency. For a square-wave drain current Send us your Ideas For Design. We’ll pay you $150 for every Idea For
with peak current of Ipk and duty cycle D, Irms2 = Ipk2 ñ D. Design that we publish. In addition, this year’s top design as selected by
This analysis of the modified thermal model of the MOS- our readers will earn an additional $500, with two runners up each
receiving $250. You can submit your Ideas For Design via:
FET demonstrates that the hottest spot on the lead and package
areas of a power MOSFET is typically a couple of degrees t
&NBJM
KPFEFTQPTJUP!QFOUPODPN
Celsius less than the junction temperature. This hot-spot tem-
OR BY
perature can be accurately measured by an infrared camera t

1PTUBM
NBJM
UP
without affecting the device’s heat flow, and the result can be Ideas For Design
&MFDUSPOJD
%FTJHO
used with the thermal resistance values found in the datasheet 249 W. 17th Street,
to calculate the MOSFET’s junction temperature. Finally, the New York, NY 10011
total power generated inside the silicon and the switching Go to www.electronicdesign.com for our submission guidelines.
losses can be calculated.

ELECTRONIC DESIGN
 for Design
Ideas
GUIDO NOPPER | ERNST REINER GMBH & CO. KG, FURTWANGEN, GERMANY

Single-Chip Circuit Delivers

[email protected]

Direction Information In Encoders

I N C R E M E N TA L - R OTAT I O N O R L I N E A R
U1a encoders are very common, but nor-
4
In Channel A A 6
5 Q Out Forward mally they do not provide a direction
B ≥1
signal. This design shows an easy way
3
2
R
7 to detect forward or reverse direction.
VCC 5 V RX/CX Q
1 Incremental encoders normally pro-
R1 CX
16k vide two output signals, usually named
C1 4538
2.2 nF
Channel A and Channel B. These sig-
nals deliver both clock information,
depending on resolution, and rotating
speed. They differ only in phase margin
(for example, –90° for clockwise and
U1b +90° for counter clockwise).
12
11
A
Q
10
Out Reverse
The circuit in Figure 1 uses these
B ≥1 signals as inputs to a 4538 single-
13
In Channel B R
9
chip, dual monostable multivibrator.
14
VCC 5 V RX/CX Q Depending on the speed required for
15
R2 CX
the application, the IC could be a metal-
16k C2 4538 gate device, a 74HC, or a 74HCT type.
2.2 nF
The feedback from one of the out-
puts to an input is used to avoid re-trig-
gering. This isn’t strictly necessary but
1. The direction discriminator circuit is based on a dual monostable multivibrator, which can be a helps to keep the pulse duration con-
metal-gate, 74HC, or 74HCT type depending on the speed required by the application. stant. On the other hand, an important
function is to trigger forward pulses
from one edge of the input signal and reverse pulses from the
other edge of that signal (Fig. 2).
This is why the same mechanical position, or slot edge of the
encoding wheel, delivers, for instance, a positive edge in the
forward direction and a negative edge in reverse. So if a design
uses the same electrical edge for triggering, the result will be a
hysteresis in changing the direction of one encoder slot width,
which is normally one half of the rated encoder resolution (Fig.
3). This can create accuracy problems that get even worse if
the encoder is mechanically jittering (vibrating) around the
clocking edge.
The designer should use care in determining the output pulse
duration of the monostables. If medium scale integrated (MSI)
logic counters like the ’193 are used, 200 ns will be enough, but
sometimes a microprocessor using its interrupt inputs counts
the forward and reverse signals. This requires a pulse length of
at least the maximum MCU interrupt response time.
2. This scope printout shows the behavior of the circuit when the encoder In many cases, this may be pulse lengths of some tens of
shaft is moved a little between clockwise and counter-clockwise. Channel 1 microseconds as in the circuit of Figure 1, where the pulse
is In Channel A (U1 pin 4). Channel 2 is In Channel B (pin 13). Channel 3 width, tPLS ≈ 50 µs. Once the pulse length is known, the maxi-
is Out Forward (pin 6). Channel 4 is Out Reverse (pin 10). mum speed is determined by:

ELECTRONIC DESIGN
IdeasForDesign

VCC VCC

fMax = 1/(tPLS × 4)

So, the maximum speed or encoder

frequency in this example is approxi- Channel A
4.7k
mately 5 kHz (Fig. 4). The circuit won’t OPB 822
AOut
totally stop working if overdriven in fre-
VCC
quency, but beyond the maximum fre-
4.7k
quency the duration of the output pulse
will be cut to a length from the trigger- SN7414
170 Q1 VCC
ing edge (Channel A) to the falling edge 130
2N2222
(Channel B).
This leads to a possible simplifica- 14k
tion of the circuit in Figure 1. If you
PR CLR
eliminate resistors R1 and R2, the output
pulse would always be the time from the Clk
triggering edge of Channel A to the fall- D Q
Q2
2N3906
ing edge of Channel B (Fig. 5). VCC

SN7474

DIROut
GUIDO NOPPER is Channel B
OPB 822
responsible for all 4.7k
hardware design in
paper-processing
4.7k
business machines, SN7414 BOut
especially check print- 170 Q1
ers and scanners, at 2N2222 “0” = clockwise
Ernst Reiner GmbH “1” = counter clockwise

& Co. KG, Furtwangen, Germany. He 14k

also has worked as an LSI-MOS design
engineer with experience in analog-to-
digital converters and digital filters. He
received his Dipl. Ing. (FH) degree from
the Hochschule Furtwangen University. 3. This circuit using a D flip-flop can cause inaccuracies at the point of reversing the direction, espe-
cially when the encoder is jittering (vibrating) around the clocking edge.

4. These scope traces show the circuit’s response when the encoder’s 5. Resistors R1 and R2 in the direction discriminator circuit can be
shaft turns clockwise at near maximum speed. The channels are the same removed with only minor changes to the circuit’s response. Again, the
as in Figure 2. scope’s traces are the same as those in Figure 2.

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IdeasForDesign

andreW ToTh | [email protected]

Excel Formula Calculates

Standard 5% Resistor Value
When using a spreadsheet to calculate circuit values, deter- Preliminary calculation in cell B1:
mining “standard” component values to be used in subsequent
calculations can produce more accurate results. This approach =10^INT(LOG(A1))
will also result in real-life solutions to your circuit designs.
When 5% resistors will suffice, the Excel solution below will Final calculation in any cell:
provide values that can directly be used for a material list.
The general formula to calculate standard resistor values is
given below. The results are then rounded to the proper num- =IF(A1=0,0,
ber of significant figures (3 for 1% and 2%, 2 for 5%): IF((A1/B1)<1.05,1*B1,
IF((A1/B1)<1.15,1.1*B1,
r = d*10 i/N | i = 0, 1, 2, to N-1 IF((A1/B1)<1.25,1.2*B1,
IF((A1/B1)<1.4,1.3*B1,
where d = decade multiplier (0.1, 1, 10, etc.) and N = number IF((A1/B1)<1.55,1.5*B1,
of values per decade. For the 1% resistor, the value of N = 96, IF((A1/B1)<1.7,1.6*B1,0)))))))+
for 2% N = 48, and for 5% N = 24. IF((A1/B1)<1.7,0,
This formula is true for 1% and 2% standard resistors, but IF((A1/B1)<1.9,1.8*B1,
the 5% resistors do not track exactly. In fact, a full one-third IF((A1/B1)<2.1,2*B1,
of the 5% “preferred” values deviate from the formula. There- IF((A1/B1)<2.3,2.2*B1,
fore, the solution to this problem is not elegant like the Excel IF((A1/B1)<2.55,2.4*B1,
solution for the 1% resistor described in “Excel Formula Cal- IF((A1/B1)<2.85,2.7*B1,
culates Standard 1% Resistor Values” (see http://electron- IF((A1/B1)<3.15,3*B1,0)))))))+
icdesign.com/article/components/excel-formula-calculates- IF((A1/B1)<3.15,0,
standard-1-resistor-value.aspx). IF((A1/B1)<3.45,3.3*B1,
The simple Excel formula below determines the nearest 5% IF((A1/B1)<3.75,3.6*B1,
standard resistor value by comparison without using a lookup IF((A1/B1)<4.1,3.9*B1,
table or a macro. A preliminary calculation is needed to deter- IF((A1/B1)<4.5,4.3*B1,
mine the decade multiplier. IF((A1/B1)<4.9,4.7*B1,
Type the preliminary calculation formula below into cell IF((A1/B1)<5.35,5.1*B1,0)))))))+
B1, then type the final calculation formula into any cell other IF((A1/B1)<5.35,0,
than A1. The formula will calculate the nearest 5% resistor IF((A1/B1)<5.9,5.6*B1,
for the value in cell A1. Be sure when copying the formula IF((A1/B1)<6.5,6.2*B1,
to other cells that both preliminary and final calculations are IF((A1/B1)<7.15,6.8*B1,
replicated. The preliminary calculations can be hidden by col- IF((A1/B1)<7.85,7.5*B1,
lapsing the column. IF((A1/B1)<8.65,8.2*B1,
IF((A1/B1)<9.55,9.1*B1,10*B1)))))))

ideas for design wanted Note: Type this formula into the spreadsheet cell as a con-
Send us your Ideas For Design. We’ll pay you $150 for every Idea For
tinuous entry without carriage returns.
Design that we publish. In addition, this year’s top design as selected by
our readers will earn an additional $500, with two runners up each
receiving $250. You can submit your Ideas For Design via:

• E-mail: [email protected]
Andrew ToTh retired as a senior systems engineer in
Or bY
• Postal mail to: 1999, having spent 30 years with the former GTe hawaiian
Ideas For Design Telephone Company. he earned his BSee from the
Electronic Design
University of hawaii in 1969 and obtained his Pe license
249 W. 17th Street,
New York, NY 10011 from the State of hawaii in 1975.
Go to www.electronicdesign.com for our submission guidelines.

78 ElEctronic DEsign
 for Design
Ideas
VISHWAS VAIDYA | TATA MOTORS, INDIA

Automotive Power-Conditioning Circuit

[email protected]

Eliminates Power-Hold Relay

AUTOMOTIVE ELECTRONIC CONTROL applications require robust the breather provided to it by the R5-C2-R6 delay circuitry.
input power conditioning. The circuitry must absorb 100-V This clever scheme obviates the need for the electromechanical
transients on one hand, while providing a stable dc bus for a relay that’s usually used, reducing cost and eliminating cum-
few hundred milliseconds after the ignition is switched off, bersome wiring.
so the CPU has the time to write logged data into EEPROM During an overvoltage/bus transient condition exceeding 33
before going off. The use of high-energy transient absorb- V dc, Q1 turns on due to the 32-V dc zener in its base circuit. It
ers usually meets the former requirement, while an electro- switches off Q2, protecting the load-circuit from high voltages.
mechanical relay handles the latter. A tricky situation arises when a transient arrives while the
The circuit described here offers novel solutions for both CPU is logging its data in RAM under normal operation. Q2
requirements. It replaces the costly and bulky transient absorb- will switch off and power to CPU will disappear, requiring a
ers with an electronic switch and the electromechanical relay power-on reset when the transient goes away and Q2 restores
with a simple RC timer that sustains the dc bus for a preset the power. This is highly undesirable since it would interfere
amount of time after the ignition is switched off. with the integrity of the data being written in RAM.
The 12-V dc battery bus enters the power-conditioning stage This problem can be addressed by putting the CPU to sleep
through the reverse-polarity protection diode, D1 (see the figure). during the transient period (usually a few hundred millisec-
Electronic switch Q2 is the heart of the circuit block responsible onds) and waking it up when the transient goes away. Doing
for bus-transient protection. Transistors Q1 and Q3 form a logic this avoids a hard reset under such situations.
block that switches Q1 on and off under different conditions. Capacitor C8 keeps the CPU alive during the sleep mode. An
Under normal conditions, when the ignition switch is kept on, extremely low CPU current avoids draining C8 during the tran-
Q3 stays on and also maintains Q2 on. Q1 is usually off and turns sient period, avoiding a CPU power-reset. The CPU can also
on only when the bus voltage exceeds 33 V dc, governed by the turn off output power drivers during the transients to protect
32-V zener, Z1 (under transient and other overvoltage situations). them from high current spikes.
When the ignition key is turned off, Q3 stays on for a time
governed by R5, C2, and R6 to hold Q2 on. Since Q2 is directly
connected to the battery through D1, the circuit remains pow- VISHWAS VAIDYA is an assistant general manager of the
ered as long as Q3 and, hence, Q2 is on. electronics division at Tata Motors Ltd. He is based in Pune,
However, the CPU senses the ignition off condition through India. He holds a master’s degree in control engineering from
one of its inputs and starts performing “cleanup” operations, the Indian Institute of Technology, New Delhi, India.
such as storing the data logged in RAM to EEPROM during

D1 L1 L2
VR1
VBatt
C1 R3 Z2 C8 C13 C7 C9
R1 Q2
Q1 Load 1 Load n
R2 Logic supply
R4
Z1
R8
Gnd D2 R5
Q3
Ignition CPU Driver
R7 Z3
C2 R6

This power-conditioning circuit for an automotive electronic control unit replaces bulky transient absorbers with an electronic switch, Q1, and an electro-
mechanical relay with an RC timer circuit, R5-C2-R6.

ELECTRONIC DESIGN
IdeasForDesign

ramkumar ramaswamy | AuDesIne [email protected]

Simple Strategy Safely Connects

Transformerless-Supply Circuits
Low-power circuits commonLy use R2
100k
transformerless power supplies. How-
ever, the use of earth grounds in many of R1
100k V+
these circuits creates a serious problem
–
that is often ignored. A
The very popular Microchip Applica- + B
R3
tion Note AN954 shows a circuit ground V–
100k R4
(0 V), but the reference is silent about G1 G1 100k
G2
whether it can be connected to the main
power supply’s earth ground.1 Similarly,
G2 G2
Apex Technology’s Application Note 35
describes circuits that cannot be inter- A simple op-amp circuit placed between a transformerless circuit with a ground tied to neutral and a
faced safely and legitimately with any circuit with an earth ground will eliminate the safety and noise problems associated with such connec-
external test equipment.2
The reasons for these problems are not difficult to see. In the G2) cancels out completely and does not appear at the input of
former (AN954), the transformerless power supply’s circuit B. Effectively, the circuit allows for the safe use of both neutral
ground has high voltages with reference to neutral, and con- and earth terminals by making the neutral-earth noise voltage
necting it to earth would cause a dangerous situation. There- appear as a common-mode signal at the op-amp input. This
fore, connecting any external equipment whose circuit ground simple strategy overcomes the two problems described above.
is connected to earth would be downright dangerous. Any general-purpose, unity-gain stable JFET-input op amp
In the latter (Note 35), the transformerless power supply’s with a low offset voltage will work.
circuit ground is connected to neutral, so connecting any exter-
nal equipment to the circuit (such as an oscilloscope to trou- RefeRences
bleshoot the circuit) would violate wiring regulations in most 1. condit, Reston; “Transformerless Power supplies: Resistive and
countries and usually cause the circuit breaker to trip if the capacitive,” Application note An954, Microchip Technology Inc., 2004.
external equipment has its circuit ground connected to earth. 2. “Ac-Dc Power supply Design,” Application note 35, Apex
One solution might be to try to insert a small resistor Technology, Dec. 1999.
between the circuit ground in question and the earth ground of
the external equipment. This prevents the mains circuit breaker For more on this Idea for Design, see Anoop’s Analysis by
from tripping and technically avoids violating wiring regula- Anoop Hegde with the online version of this article at www.
tions, but it causes a new problem—noise between the earth electronicdesign.com.
and neutral lines. This noise gets into the circuit, defeating the
purpose of the earth connection. Usually, the result is that the
earth ground is, quite simply, rendered unusable. RamkumaR Ramaswamy is chief scientist at audesine,
A simple workaround to this problem assumes that the Bangalore, India.
transformerless circuit’s ground is tied to neutral, which is the
much more popular and preferred strategy for transformer-
less power supplies (see the figure). The circuit is nothing
fancy. It’s a simple differential amplifier, but its use in this ideas for design wanted
specific context is innovative. It illustrates how a signal from
Send us your Ideas For Design. We’ll pay you $150 for every Idea For
equipment A can safely and reliably be fed into equipment B Design that we publish. In addition, this year’s top design as selected by
irrespective of which one has the problematic circuit ground. our readers will earn an additional $500, with two runners up each
For example, A could be a signal generator feeding into a receiving $250. You can submit your Ideas For Design via:
transformerless circuit, B, in which case G1 is earth, and G2 • E-mail: [email protected]
is neutral. If B is an oscilloscope being used to troubleshoot
Or bY
a transformerless circuit, A, G1 is neutral, and G2 is earth. • Postal mail to:
Either way, G1 is A’s circuit ground and G2 is B’s circuit Ideas For Design
ground, as well as the op-amp circuit’s ground. Electronic Design
249 W. 17th Street,
The gain at both op-amp inputs is equal and opposite, so the New York, NY 10011
earth-neutral noise (which is the noise at G1 with respect to Go to www.electronicdesign.com for our submission guidelines.

ElEctronic DEsign Go To www.elecTronicdesiGn.com

 for Design
Ideas
DIMITRI DANYUK |

JFET Follower Amplifier Cancels Distortion

[email protected]

MANY IMPROVEMENTS TO the follower cir- will modulate its base-emitter voltage. Figure 2 shows the measured total har-
cuit have been proposed over the years. The gate-source voltage of Q1 can be monic distortion plus noise (THD+N)
The White cathode follower doubles the modulated in the same way by adding for this circuit for three values of RL as
output current and makes the transfer resistor RS to the SLC. At a certain value RS is varied. The improvement is quite
function more linear. 1 Adding a com- of R S, modulation in V BE will be can- remarkable, with distortion for 1 V rms
mon-base amplifying stage (current fol- celled by the same modulation in VGS. below 103 dB.
lower) significantly improved the White A similar distortion-cancellation mecha- Another way to control the circuit’s
follower’s power-supply rejection ratio.2 nism occurs in a single-FET, common- balance condition is to change the cur-
Engineers at Pioneer Electronic Corp. source amplifying stage.4 rent mirror’s transfer ratio. Figure 3 illus-
took the next step by applying the White
follower to a pair of followers connected +15 V
in series. The premise of the Pioneer +
Super Linear Circuit (SLC) is that the C2 C3
RL 10 µF 33 nF
nonlinear transfer function of the first
transistor is canceled by the inverse
nonlinearity of the second transistor in R1
D
51
series.3 Input
G Q1 Output
Figure 1 presents another improve- BF862 R5
S 200 R6
ment, a JFET follower with distortion Q3
BC850 100k
compensation. Transistor Q1’s source R2
voltage reproduces the input voltage and 1M

then drives Q3’s base. Both Q1 and Q3 RS C1

supply current in the load, RL. Because 100 pF
of the current mirror (Q2-Q4), Q1’s Q2 Q4
source current is equal to Q3’s collector BC860 BC860

current. The sum of Q1’s source current

and Q4’s collector current is: +
R3 R4 C4 C5
100 100 10 µF 33 nF

(VIn – VGS + VBE)/RL –15 V

Because Q3 has a finite transconduc- 1. A JFET follower circuit with a current mirror made up of Q2 and Q4 provides distortion cancella-
tance, its emitter current (or load current) tion based on the value selected for RS.

–60 –60

R3 = 100
R3 = R4 = 100
R4 = 33

–80 –80
THD+N (dB)

THD+N (dB)

–100 –100
RL = 6.81 kΩ RL = 6.81 kΩ
RL = 2.2 kΩ RL = 2.2 kΩ
RL = 1.2 kΩ RL = 1.2 kΩ
–120 –120
1 10 100 1000 1 10 100 1000
RS (kΩ) RS (kΩ)

2. For the three loads used in these measurements and at 1 V rms, 3. If the ratio of R3/R4 is changed, the required value of RS additionally
THD+N is below 103 dB at the optimum RS. changes.

ELECTRONIC DESIGN
IdeasForDesign

trates how the THD+N versus R S curves are shifted for a quiescent current is determined by other design objectives—
different ratio of R3/R4. In this case, Q1’s source current is a for example, noise performance.
portion of Q3’s emitter current. This can be helpful when Q1’s Because of regenerative feedback, the capacitive load of
Q3’s emitter will lead to high-frequency peaking inside the
+ loop. So the load capacitance is isolated with R5, and some
kind of frequency compensation (C1) might be needed. R6 =
RFB
100 kΩ represents the system input resistance.
The linear relationship between the voltage across RL and
FB
the input means there is a linear relationship between the
R1 Input output current and input signal. So, the circuit of Figure 1 can
Input Q1
be rearranged in the form of an amplifier with a linear transfer
function (Fig. 4).
R2
Q3
The author would like to thank Louis Vlemincq and Scott
Wurcer for their discussions.
Adjust
C1 rEfErENcEs
1. White, E.l.c., “Thermionic Valve amplifier circuit arrangements,”
RS
U.s. patent 2358428, sept. 19, 1944.
2. Taylor, P.l., “audio Power amplifier,” Wireless World, June 1973,
Q2 Q4 p. 301.
3. Ozawa, O., and ishikawa, K., “super linear circuit,” 60th aEs
4. Because of the linear R3 R4 convention, May 1980, Preprint No. 1660, pp 1-38.
relationship of the out- 4. Designing With field-Effect Transistors, edited by a.D. Evans,
put current and input Load
McGraw-Hill, New york, 1981, chapters 3-11, “Distortion in fET
signal created by the amplifiers.”
Output
circuit, it can be rear-
ranged in the form of
RL
an amplifier with a lin- Dimitri Danyuk is a consultant. He received his training in
ear transfer function. – electrical engineering at kiev Polytechnic institute, ukraine.

michael Gambuzza | GE ENErGy, BillErica, Mass. [email protected]

Synthesized Inductor Delivers

Maximum Power Transfer
To Transfer maximum power from a cir- a resistive source, this transfer can require To match Ro to RL, L must be chosen
cuit to a load, the load’s resistance, RL, the use of a bulky inductor. This idea to “resonate out” Co:
must match the source resistance, Ro (Fig. shows how to replace the physical induc-
1). In the case of a complex load, ZL, and tor with a smaller synthesized inductor. –XCo = XL
A good example of a complex load is
a piezoelectric transducer represented – {–j[1/(ωCo)]} = jωL
RO by the Butterworth-Van Dyke model
as Co, RL, Cs, and L (Fig. 2a). At series Therefore:
resonance, the load impedance reduces
VS to the equivalent circuit shown in Figure L = 1/(ω2 × Co)
+ RL
2b. The load is still complex, with RL
– in parallel with Co. This makes match- where:
ing to Ro impossible without a complex
conjugate match of –Co at the source— ω = 2πf
that is, an inductor in parallel with C o
1. The simplest matching circuit consists of a resis- and having the same magnitude of reac- To replace the physical inductor, L,
tive load, RL, equal to the source resistance, Ro. tance (Fig. 2c). with a synthesized inductor, consider

ElEctronic DEsign Go To elecTronicdesiGn.com

IdeasForDesign

RO RO RO

VS RL VS VS L
CO RL CO RL

CO CS

(a) (b) (c)

2. An example of a complex load is a Butterworth-Van Dyke model of a piezoelectric transducer (a), which can be reduced to an equivalent circuit (b).
To match the load to the source, an appropriate inductor, L, must be added (c).

R1
R1
–
L
+

C
R

3. Instead of a bulky physical inductor, the designer can use this gyrator
circuit, which provides a simulated inductance equal to (R1)(R)(C).

RO
5. In these simulation results, the voltage across the load (top trace)
shows a minima at the resonant frequency. The phase of the voltage
across the load (bottom trace) is 0° at resonance. These results indicate
the selected inductance created a successful match.

RL
+ the gyrator circuit, which Bernard Tellegen invented in 1948
–
R1 (Fig. 3). The circuit is basically a differentiator in which the
–
CO CS operation of capacitor C is reversed. The simulated inductance
+ becomes:
C
L
R
L = (R1)(R)(C) Henries

Typically, R1 is kept to 100 Ω or less so the circuit’s Q

can be at least 10. (Details of the gyrator circuit are avail-
able on the Internet. For example, see www.beigebag.com/
4. In a typical implementation of the gyrator matching circuit, dynamically case_gyrator.htm.) Figure 4 shows the final implementation
varying R can change the tuning of the circuit for different complex loads, pro- of the matched circuit. With this circuit, R can be dynamically
vided that the voltage across the load is measured to ensure optimum tuning. varied to change the tuning on the fly for different complex
loads, provided that the voltage across the load is measured so
optimum tuning can be achieved.
Figure 5 shows the simulation results of a tuned circuit
MICHAEL GAMBUZZA is senior using the described gyrator circuit. The top trace is the volt-
engineer in measurement and age across the load, which shows a minima at the resonant
control at GE Energy. He is a grad- frequency. The bottom trace shows the phase of the voltage
uate of SUNY Farmingdale with a across the load, which is 0° at resonance. These results indi-
degree in engineering science. cate that the selected synthesized inductance successfully
matches the load to the source.

ELECTRONIC DESIGN
 for Design
GREGORY MIRSKY | ATLAS MATERIALS TESTING TECHNOLOGY

Improved Power-Factor Corrector

Ideas
[email protected]

Further Minimizes Miller Effect

L1
200 µH
D4
D3
D5 R10
V1 C15 DSEE29-12CC
+ 1M D2
D6 R11 0.1 µF M2
–
0.06 STW88N65M5 R12
D7 C14 C7 R1
1M 560 pF 470 80
C1 C2 µF
C8 100 pF V3 + R7 1k
100 pF
4.7 nF R3 R13
R5 R6 12 – 1k
200 200 D1 19.1k
C13 VCC1 M3
In1
10 µF MOut IAC Si5515_P
D2 1N4148
VAOut C10 G3
– + VCC GND1 U1 Out1 C3 C4 3 nF
0.047
U2 C9 µF R8 470 R9 470 LTC1693-1 220 µF
M1
V4
LT1249 VSense 0.47 R16
In2 VCC2 G1 IPB230N06L3
18 µF D1
100 V2
CAOut GND2 Out2 R2
GTDR R4
1N4148 1 1k
GND
R14 R17 C5 C6
330k 620 300 pF 300 pF
C11 C12
100 pF 1000 pF

R15 D8
10k 1N5819

1. This improved design adds a discharge path for the upper-cascode MOSFET’s input capacitance to improve PFC performance.

IN “CASCODE CONFIGURATION Removes Miller 13 V

Effect, Boosts PFC Performance” (September 28, 12 V
2006) , a cascode connection of two MOSFETs 11 V
helped eliminate the Miller effect and improve
10 V
power-factor correction (PFC) performance.
Recall that the Miller effect is a very large 9 V
increase in a transistor’s apparent input capaci- 8 V
tance due to negative feedback from the transis- 7 V
tor’s output to input, when the transistor compris-
6V
es a high-gain amplifier. A unity-gain amplifier
has no Miller effect, although it may have a huge 5 V
input capacitance and cause subsequent effects 4 V
such as leading-edge and trailing-edge distor- 3 V
tion associated with this input capacitance, and a
2V
charge-versus-voltage characteristic plateau.
However, the tested and published schematic 1 V
was less than perfect for an important reason: 0 V
the upper-cascode MOSFET input capacitance, Ð1 V V(g3) V(g1)
Cgs, did not have a reliable discharge path. The Ð2 V
improved design described here removes that
s
s

m
m

6
6

32

downside and presents a viable cascode PFC

30

30

31

31

31

31

31

32

32

32

3.
3.

3.

3.

3.

3.

3.

3.

3.

3.

3.

schematic layout. Values and models of compo-

nents used are just for demonstration and may 2. The gate-drive waveforms for M1 (blue) and M3 (green) show the relative timing needed to
differ depending on the purpose of the design. ensure proper, reliable operation of the circuit (horizontal: time; vertical: gate-drive voltage).

ELECTRONIC DESIGN GO TO ELECTRONICDESIGN.COM

IdeasForDesign

The cascode PFC design is built around MOSFETs M1, M2, resistors R5 and R6, capacitors C1 and C2, and diode D2 as
and M3 (Fig. 1). The previous schematic does not have M3, well as symmetric counterparts R8, R9, C5, C6, and D1. A
which serves as the M2 Cgs discharge switch. This MOSFET MOSFET driver with Schmitt triggers at the inputs is best.
significantly improves the PFC characteristics, expanding the Integrated circuit U2 is an example of an available PFC
upper operating frequency if driven properly. chip. The supply line is replaced with power source V1, and
P-channel MOSFET M3 should be controlled in-phase with diodes D4 through D7 form a line rectifier. Almost any ade-
the M1. An inexpensive low-voltage moderate RDS(on) transis- quate power diodes can be used here.
tor can be used here. Voltage source V3 represents a 12-V dc IC U2 creates a pulse-width modulated control signal across
gate offset for M2, and it should be bypassed with a 10-μF resistor R17, which splits into two delay lines. When passed
ceramic capacitor. Both M1 and M3 work best if driven from a through the delay lines, it undergoes different delays of the
two-channel MOSFET driver such as the LTC1693-1 (Linear leading and trailing edges due to the delay lines in both chan-
Technology Corp.) or similar. nels. This is how the gate-drive voltages of MOSFETs M1 and
It is important to create proper gate-drive signals for M1 and M3 are generated (Fig. 2, again).
M3 (Fig. 2). Transistor M3 should turn off earlier and turn on
later than M1 to prevent a shoot-through current from the volt- GReGoRy MiRsky is the principal electrical engineer at
age source V3 through closed M3 and M1. atlas Materials Testing Technology, an ametek company.
Two delay lines, whose parameters depend on the MOS- He holds an Ms from the leningrad Mechanical institute (now
FETs used, create the control voltage for M1 and M3. These known as st. Petersburg Baltic Technical University), Russia,
delay lines are built on similar low-pass filters comprising and a PhD from the Moscow Pedagogical University, Russia.

RICk MALLy | Independent desIgns LLC [email protected]

LM555 Makes Inexpensive Power Driver

VARIOUS DIGITAL CIRCUITS require push-pull power drivers, par- could be used as an active-high enable line with the same tran-
ticularly for gate and line driver applications. Many special- sition levels, including the 1.8-V logic level, as stated above.
purpose devices are available for these issues, but they are With its 200-mA sink/source capability, an LM555 powered
typically expensive and single-sourced, with a short product by 12 or 15 V can drive most MOSFET/IGBT gates at frequen-
lifecycle that forces a costly redesign when they are discon- cies exceeding 250 kHz without clamping diodes on the gate,
tinued. Fortunately, the ubiquitous LM555 timer (non-CMOS minimizing cost. When driving gates, you should place a 5- or
versions) can serve as a very inexpensive and capable driver. 10-Ω resistor in series with the output to minimize ringing
With its powerful totem-pole output and a 4.5- to 16-V and transient currents. In addition, the circuit should include
supply range, the LM555 can be used as either a buffer or an a ceramic or tantalum bypass capacitor or at least 1 µF to pro-
inverter. If more than one driver is required, designers can use vide the surge currents required.
the dual LM556 to reduce cost and footprint. The rare 558, a Both of the circuits also provide an additional open-collec-
quad version, can also be applied as a quad inverting driver. tor output on the discharge pin (pin 7) that could be set to any
To implement a buffer function, configure the timer’s reset voltage level, up to 18 V. You can let the control voltage pin
line (pin 4) as the input (Fig. 1). This provides a transition (pin 5) float, or you could use it to change the internal com-
level of 0.5 to 1 V, allowing the device to be driven directly by parator threshold levels.
standard 5-, 3.3-, and even 1.8-V logic regardless
VCC VCC
of the VCC level. Alternatively, the trigger line
(pin 2) may serve as an active-low enable line,
although this line does not have the same compat- In 4 8
4 8 R VCC
ibility as the reset pin in terms of levels.
7 7
In the inverting configuration, the trigger line D R VCC D
LM555 LM555
is used as the input, with a transition threshold of 3 0 3
6 0 Out 6 TH Out
0.334 × VCC (Fig. 2). Additionally, the reset line 2
TH
2 TR
TR In
CV VSS
CV VSS
5 1
Rick Mally is the sole proprietor of 5 1
independent Designs, a small-scale custom elec-
tronic design and light manufacturing firm for cli-
ents with a low budget. He was home-schooled 1. By using the LM555’s reset pin as the input, 2. Designers can also employ the LM555
and self-educated in many disciplines, primarily the timer can serve as a buffer circuit driven by as an inverting driver by configuring the
in the electronics field. standard logic levels from 1.8 to 5 V. trigger line as the input.

ElEctronic DEsign
 for Design
Ideas
GIRISH CHOUDANKAR | EMPHATEC INC., MARKHAM, ONT., CANADA

Inexpensive Solution Protects

[email protected]

Sensitive Devices From Surges

AS TODAY’S HIGH-TECH electronic devices become smaller and tion would be a costly solution. Alternatively, you can add a
faster while running at lower voltages, they also become more small resistor in series with the source impedance, effectively
vulnerable to surges. Making matters worse, they often operate reducing the surge current and along with it the overall size,
in harsh environments that expose them to extreme surges, par- power dissipation, and cost of the circuit (Fig. 2).
ticularly in industrial applications where sensors are interfaced Assuming a small load, 10 mA, the voltage drop across the
to microcontrollers or logic devices. This idea shows engineers 20-Ω would be:
how to design their circuits to withstand these surges.
The key to surge protection is adding a transient voltage V20Ω = 10 mA × 20 Ω = 0.2 V (2)
suppressor at the input to the sensitive devices. The simple cir-
cuitry includes a resistor and a transient suppressor that handle Therefore, the surge current I would be:
the voltage surge and regulate the input voltage. The tricky part
is choosing the right value for the suppressor. Ip = (150 V – 36 V)/22 Ω = 5.2 A (3)
Properly designed, the transient suppressor appears invisible
to the protected device until a surge hits. That is, during normal The added resistor reduces the surge current to less than 1/10
conditions the suppressor’s breakdown voltage, current, and of the surge current without the resistor. The low-power sup-
capacitance will have no effect on operation and performance. pressor can handle this current. Also, the clamping current is
When a surge strikes, the suppressor immediately clamps to a less than the rated current. The clamping voltage is:
safe voltage level (the clamping voltage), conducting away the
,S
surge current.
In the example circuit, the load, which can be the input of
9& = (9
& 0D[ ² 9%5 ) ,SS 0D[
+ 9%5 
a logic device, is fed by a 24-V dc input, which can be from a
sensor, transducer, or other device (Fig. 1). The source resis- From the SMBJ26A datasheet, the maximum clamping
tance is 2 Ω and the failure threshold is 36 V. The circuit uses an voltage, V C(max) = 42.1 V; the maximum breakdown volt-
SMBJ26A 600-W transient voltage suppressor. If a malfunc- age, VBR(max) = 31.9 V; and the maximum peak pulse current,
tion causes a peak surge of 150 V with a duration of 10 ns at the Ipp(max) = 14.3 A. Using these values and the result of Equation
input terminal, the suppressor must clamp that surge at 36 V or 3 for Ip, Equation 4 yields VC = 35.5 V.
less. The current delivered by this transient is: Thus, the clamping voltage is a little below the threshold
voltage at 25°C. For higher temperatures, de-rating parameters
Ip = (150 V – 36 V)/2 Ω = 57 A (1) must be considered. The steady state power dissipated by the
20-Ω resistor is:
The suppressor causes the surge voltage to be divided
between the source impedance and itself. Equation 1 shows P20Ω = (20 mA)2 × 20 Ω = 8 mW (5)
that the higher the clamping voltage is, the lower the surge cur-
rent in the circuit. Unfortunately, the resulting current in this Consequently, a 1/8-W carbon composition resistor can be
example would fry the circuit. used for the suppressor circuit for the given pulse condition.
A higher-wattage suppressor could be used, but that is not This small series resistor drastically improves the suppressor
advisable because the high power capacity and power dissipa- performance with little cost impact.
2 2 20

GIRISH CHOUDANKAR works at

24 V dc SMBJ26A Load 24 V dc SMBJ26A Load Emphatec Inc., a Toronto-based design
house for industrial control interfaces
and switch-mode power supplies. He
1. Using only the suppressor diode in this cir- 2. The addition of an inexpensive 20-Ω resistor holds a bachelor’s degree in elec-
cuit that has a 2-Ω source resistance creates to the input greatly reduces the surge current tronics engineering from Mumbai
too high a peak transient current. and power dissipated. University, India.

ELECTRONIC DESIGN
GREGORY MIRSKY | ATLAS MATERIAL TESTING TECHNOLOGY, AN AMETEK COMPANY [email protected]

Stabilize SMPS With Slope

Compensation Resistance
CURRENT-CONTROL SWITCHING-MODE POWER supplies (SMPS) lated full-bridge controller with an internal current-ramping
are gaining in popularity because they allow pulse-by-pulse source whose peak current reaches 74 µA. This internally
current control and monitoring, making them more reliable generated current creates the compensation slope that adds to
and robust than their voltage-controlled counterparts. Current the slope of a pulse that is developed across the current sens-
control also eliminates a positive zero in some transfer func- ing resistor, Rcs, making the current feedback loop stable at
tions, which makes the supplies more stable. However, at pulse any duty cycle.
duty cycles above 0.5, current-control SMPS become unstable, The computation starts with the known factors: the SMPS
oscillating at half of the switching frequency.1 output power, voltage, switching frequency, and other param-
To stabilize the circuit, the designer must change the slope eters that are obtained during the power supply analysis.
of the pulses going to the pulse-width modulation (PWM) Assuming that the pulses across the secondary winding of
comparator.2 This can be done by adding a sawtooth voltage transformer TR have an amplitude of Vsec, and neglecting the
derived from the voltage across the timing capacitor to the volt- voltage drop across rectifier D2, which may be a synchronous
age developed across the current-sensing resistor. Or, you can low-dropout type:
add a high-enough current slope to the slope-shaping resistor
before summing the voltage across the slope-shaping resistor Vload = Vsec × D (1)
and the current-sensing resistor in the current-sensing trans-
former’s output circuit. where D is the duty cycle of the rectified pulses. Note that Vload
This idea describes how to compute the value of the slope is not the rms value of Vsec. Then, the current ripple in the filter
compensation resistor, Rsl, that will create the desired volt- inductor, ∆iL, is:
age pulse slope. The analysis uses Figure 1, which is part of 9 ² 9ORDG
ΔL/ = VHF ×τ 
a bridge converter that is a component of a current-control / ILOWHU
SMPS. Although the figure is a simplified schematic that
denotes rectifiers as diodes and does not show the full bridge, it where Lfilter is the value of the filter inductance and τ is the
is suitable for this analysis. duration of the output pulse. Substituting Equation 1 into
The voltage pulse slope is sent to the current-sensing input Equation 2:
of U1, an LTC3722-1 synchronous dual-mode phase-modu- 9VHF ² 9VHF '
Δ L/ = ×τ
Bridge / ILOWHU

TR 9VHF ( ² ' )
Δ L/ = ×τ
UVLO VCC
Vfilter
/ ILOWHU
PDLY OutA Vload
Vsec D2
ADLY OutB
with a switching frequency of fsw and τ = D/fsw:
M1
SBUS CS 9VHF ( ² ' ) '
U1 Δ L = × 
Vref OutD Rsl D1
TC Cfilter Rload / ILOWHU I6:
LTC3722-1
SPRG OutC
1 turn with a transformation coefficient or windings turn
DPRG OutE Rcs
ratio of Ntr for TR of:
RLEB OutF

Ct Comp
Ntr = w2/wl
SS FB
Gnd PGnd
GREGORY MIRSKY, principal electrical engineer, holds an
1. This simplified schematic of part of a bridge converter that is a compo- MS from the Leningrad Mechanical Institute, Russia (now
nent of a current-control SMPS illustrates how designers can compute the known as St. Petersburg Baltic Technical University) and a
value of a slope-compensation resistor to ensure stable operation. PhD from the Moscow Pedagogical University, Russia.

ELECTRONIC DESIGN GO TO ELECTRONICDESIGN.COM

IdeasForDesign

and a MOSFET source current of: ∆ics = ∆il/wct (6)

∆il = ∆iL/Ntr Substituting Equation 5 into Equation 6:

Equation 4 becomes: 9VHF ' ( ² ' )

ΔLFV = 
1 WU / ILOWHU IVZ Z FW
9VHF ' ( ² ' )
ΔL = 
1 WU / ILOWHU I6: Then, the voltage across Rcs is:

9VHF ' ( ² ' ) 9 ( ² ' ) 5 FV

Assuming that the current transformer, TC, has one turn 9FV = ΔLFV 5 FV = × 5 FV = ORDG 
on the primary side and wct turns on the secondary, and the 1 WU / ILOWHU IVZ Z FW 1 WU / ILOWHU IVZ Z FW
current-sensing resistor current is ∆ics:
From Figure 2, Slopecs = Vcs/τ:
Vsec
Iout 9FV 9 9 I 9 ( ² ' ) 5 FV
6ORSH FV = = FV = FV VZ = ORDG 
τ '7VZ ' '1 WU Z FW / ILOWHU
ΔiL
Iout
The voltage slope, Slopesl, created by U1’s internal current
Time
τ generator, Isl, or by an external component is:
Duty cycle = τ/T
,VO 5 VO I
T T = 1/fsw 6ORSHVO = = ,VO 5 VO VZ 
τ '
2. The SMPS stabilization technique uses a sawtooth wave that changes Equation 10 ignores the value of Rcs, which is much smaller
the slope of pulses coming into the controller, U1. than Rsl. Slopesl should be equal to or greater than 0.5 Slopecs.

ElEctronic DEsign
IdeasForDesign

So: Now you can calculate the Rcs value Controllers,” http://cds.linear.com/docs/
I 9 ( ² ' ) 5 FV that will ensure smooth operation of the Datasheet/372212fa.pdf
,VO 5 VO VZ ≥ ORDG 
' '1 WU Z FW / ILOWHU power supply in the normal mode: 3. “Modelling, Analysis And Compensation
Of The Current-Mode Converter,” www.
Then: I 1 Z / 9 ti.com/lit/an/slua101/slua101.pdf
5 FV < VZ WU FW ILOWHU WK 
9 ( ² ' ) 5 FV 9ORDG ( ² ' )
5 VO ≥ ORDG 
,VO IVZ 1 WU Z FW / ILOWHU
After making this calculation and
and: selecting a standard value, you can use
9ORDG ( ² ' ) 5 FV that value in Equation 12 to compute Rsl.
9VO ≥  
IVZ 1 WU Z FW / ILOWHU If the controller IC that you employ
does not provide the required current
The value of Rcs is obtained by using sawtooth waveform, you can derive
the ratio of U1’s sensing voltage to the it from the voltage across the tim-
operating current, scaled by the current ing capacitor. Just add a simple power
transformer. amplifier based on two complementary
Sometimes, however, the IC’s current- bipolar transistors.
sensing input has a current-limiting
threshold, Vth. If needed to avoid reach- REFERENCES
ing the current-limiting mode, Rcs may 1. “Average Current Mode Control of Switching
be calculated using: Power Supplies,” Lloyd Dixon, http://ecee.
colorado.edu/~ecen5807/course_mate-
9 ( ² ' ) 5 FV rial/papers/cpm/Dixon_1990.pdf
9WK > ORDG 
IVZ 1 WU Z FW / ILOWHU 2. “LTC3722-1/LTC3722-2 Synchronous
Dual Mode Phase Modulated Full Bridge
IDEASFOR DESIGN

Best IFDs Demonstrate Engineering Elegance

T
he Ideas for Design department is one of the most popular This “small” circuit tackles a much larger challenge with clar-
and widely followed sections of Electronic Design, and ity and directness.
with good reason: it embodies the essence of engineer- Runner-up “Electronic Load Achieves 0 Ω” by Henry San-
ing. How so? In an IFD, an engineer takes standard parts and tana packs a one-two punch. First, it shows how to build an
connects them in a clever, innovative configuration to solve a electronic load, which is an increasingly common, more versa-
specific problem simply and crisply, and usually at lower cost tile replacement for a resistor-based load when doing test and
than alterative approaches. Further, since in most cases it’s a evaluation. But it also shows you how adding just a little more
circuit alone without needing any software to function, anyone circuit complexity lets you take this load down to 0 Ω.
can look at the schematic and description to study, follow, and Although that seems unnecessary—after all, you could just
grasp the design’s intent and execution. hard-short the load using an electromechanical relay—the
This year’s Best Idea for Design, “Simple Circuit Turns author explains why being able to electronically transition
PWM Into a Digitally Adjustable Precision Reference” by down to 0 Ω smoothly actually results in more meaningful and
Rick Mally, tackles a common design dilemma of needing insightful data, especially with low-voltage supplies. That’s
a function that is both precise and adjustable, preferably via representative of true engineering insight, when incurring a
digital control. small additional burden in component count avoids a potential
The circuit uses just six passive components, including a problem and also enables better results.
common, low-cost LM431 shunt regulator, to configure a
Sallen-Key filter that, in turn, transforms a digital pulse-width BILL SCHWEBER is an electronics engineer who has written three
modulated output into a fully controlled dc voltage. The 0% textbooks and hundreds of articles, opinion columns, and product fea-
to 100% duty cycle of the PWM signal maps to an output tures. He also has designed for industrial controls at Instron Corp. and
between –2.5 and +2.5 V (based on a 0- to +5-V PWM signal). done applications and product marketing at Analog Devices.

ELECTRONIC DESIGN GO TO ELECTRONICDESIGN.COM

iDeasfor Design
Rick Mally | Independent desIgns, denver, Colo. [email protected]

Simple Circuit Turns PWM Into

A Digitally Adjustable Precision Reference
Designs frequenTly require the conversion of a micropro- +5 V
R1 R2
cessor’s pulse width modulation (PWM) signal into an ana- PWM signal in
10k 10k
IC1
log voltage. Often a passive single-pole RC filter will satisfy 0/+5 V LM431
design requirements, but this approach typically suffers from C2
C1 0.0047 µF
several drawbacks including slow response time, noisy results, 0.01 µF
R1 = R2
and having an unbuffered output. C2 ~
– 0.5 × C1 DC voltage out
The circuit described here uses the ubiquitous LM431 shunt ±2.5 V
regulator to implement a second-order Sallen-Key low pass R3
filter together with a level shifter (see the figure). Compared to 499

the traditional approach, it provides a far sharper roll-off along

with a low-impedance output, bipolar output. It will produce –5 V
a –2.5- to +2.5-V output with a 0- to 5-V PWM signal input.
The value of VOut is equal to (5 V × dc) – 2.5 V, where dc is the A shunt regulator acts as the feedback element in a low-pass Sallen-Key
PWM duty from 0.0 to 1.0 (0% to 100%). filter, converting a 5-V PWM signal to a dc value between –2.5 V and 2.5
The component values depicted provide a flat response with V based on duty cycle.
a cutoff frequency around 2300 Hz, a –12-dB/octave roll-off,
and drive capability of about 3 mA. You can easily change LM431 can be purchased for as low as 10 cents in single-unit
the cutoff frequency by adjusting R1 and R2 or C1 and C2, quantities, well below that of any op amp.
although it is important to keep R1 equal to R2 and C2 at about
half the value of C1. Editor’s Note: See Texas Instruments Application Report
Doubling the resistor or capacitor values will cut the fre- SLOA024B, “Analysis of the Sallen-Key Architecture,” for
quency in half. Halving either set of values will double the additional information on Sallen-Key filters.
cutoff frequency. You can adjust R3 to provide more output
current or to reduce power consumption. The 5-V rails depict- Rick Mally is the sole proprietor of independent Designs, a
ed do not have to be precise and can be a higher voltage. Only small-scale custom electronic design and light manufacturing firm
the PWM input signal needs to be precisely 5 V. Because it uses for clients with a low budget. He was home-schooled and self-edu-
only six components, this circuit can be very cost effective. The cated in many disciplines, primarily in the electronics field.

HenRy Santana | [email protected]

Electronic Load Achieves 0 Ω

The general approach to an electronic conduction of the pass transistor, an aux- In virtually all applications, the pass
load is to use a transistor across the input iliary power supply is connected (Fig. transistor must be heatsinked as the
terminals so the current flows from drain 2). The required voltage, VB ≥ IIn(max) × power dissipated is I In(max) × (VIn(max)
(collector) to source (emitter). A resis- RS + VDS@I(max), is sufficient to maintain + VB) – IIn(max)2 × RS. If in this example
tance is effected by causing a current flow forward conduction with VIn = 0 and 0 < VIn(max) = 15 V, the pass transistor would
in proportion to the applied voltage in the IIn ≤ IIn(max). This condition corresponds have a maximum dissipation of 17 W.
manner of a resistor, I = V/R. A controller to an effective zero input resistance. This would appear as a 15-W resistor
monitors the applied voltage and adjusts It can be shown that RIn = α × k × RS adjustable over 0 to 100 Ω.
the current in response (Fig. 1). for 0 ≤ α ≤ 1 and where k multiplies RS You may be wondering why an addi-
To achieve 0 Ω, the terminal voltage so it can be made small to reduce pow- tional power source was introduced
must be 0 in the presence of a current. er loss. If, for example, RS = 1.0 Ω, k = between the source of the MOSFET and
Under this condition the pass transistor 100, then 0 ≤ RIn ≤ 100 Ω for 0 ≤ α ≤ 1. If the current sense resistor to achieve a
suffers a loss of operating voltage and IIn(max) = 1 A and VDS@I(max) = 2 V, then “0-Ω load” condition (essentially a short
cannot conduct a current. To maintain VB ≥ 3 V. across input voltage) in Figure 2. After

ElEctronic DEsign
Ideasfor desIgn

all, why would you need an electronic permit testing under short-circuit condi- can provide smooth (stepless) effec-
load that can go down to 0 V (i.e., short tion. This is useful in testing the short- tive resistive loading over a large range
circuit) condition? circuit response of power supplies, including 0 Ω.
If you wanted to short an electronic current trip level, and effectiveness of The circuit can be scaled up to higher
load, you could always use a relay overload protection. voltages and currents. Figure 3 shows an
directly across the input voltage. Or if Furthermore, even with a low RDS(on), application. For a derivation of the equa-
you wanted it to be all solid state, you a MOSFET will not conduct at 0 V (VDS). tions, e-mail the author at hsantana@
could place another MOSFET that has At high currents, a MOSFET requires pacbell.net.
much higher current capacity (and very non-zero voltage (see note A) to sustain
low R DS(on) that approaches a few mil- conduction. This circuit will maintain Note A: For example, an RFP30N06 MOSFET
liohms) directly across the input and turn VDS right into a virtual short circuit. has a specified RDS(on) of 0.047 Ω. At 30 A
it on using a switch. This approach would Finally, a hard switch such as a relay this device requires at least 2 V VDS. This
be much simpler (and cost effective) than does not permit a smooth transition of would not be an effective short circuit on a
adding a second power supply in series resistance. The circuit described here 3.3-V, 30-A power supply. On a 1.8-V supply,
with sense resistor. So, why would you acts more like a rheostat but with the it would not conduct this current.
use the additional power source? ability to be voltage controlled (see note Note B: The effective resistance can be
Here’s the answer. This electron- B) from a remote point. The control- controlled with a voltage-controlled ampli-
ic load can check low-voltage power ler does not have to carry the load cur- fier (see “Op Amp And Two JFETs Form A
supplies (i.e., 3.3 V and lower) where rent. It would require multiple relays to Voltage-Controlled Amplifier” at electron-
a voltage burden (i.e., 1 V) would not apply a range of loading. This circuit icdesign.com).

RIn = α × k × RS
IIn IIn
VIn VIn

D A1 15 V max
+15 V
Q Q1 RFP12N10L LT1006 1.0 A max
0 < RIn ≤ a × k × RS 1.0 µF
+ 7 3 C2
A→∞ +
A G
6 2 0 ≤ RIn ≤ 100
– –
4
I In S
–15 V

CW 3 RS
–
2
k
2.5 V C1 0.1 µF
a 1
+ R4
10k
CW A2 +24 V
LT1006
R1 RV1 3 7
1. An electronic load typically employs a transistor across the input termi- +
1.0 100k 6
nals so the current flows from drain (collector) to source (emitter). K = 100
2
– 4
5
1 –15 V
VIn R3
0≤a≤1 10k
Adjust RV1 for required RIn
IIn
Q 0 < RIn ≤ a × k × RS
+
A→ ∞ A CW
– 3
2 RV2 R2
IIn –5 V 10k 100
1
– VB

+ Auxiliary power supply Maximum power

dissipated in Q1= 16.5 W Adjust RV2 for 0 VIn at IIn(max) and a = 0

CW 3 RS
3. An application circuit like this one achieves a zero-load condition for
2 testing low-voltage power supplies.
k
a 1

Henry Santana is a former senior electronic engi-

2. To maintain conduction of the pass transistor for a zero-load condition, neer with CSt Corp. He has a BSee from Colorado State
the circuit uses an auxiliary power supply. University, Fort Collins.

ElEctronic DEsign