Version 2.

3, 19 Nov 2012

C o o l S E T ®- F 3

ICE3A1065ELJ

Off-Line SMPS Current Mode

Controller with integrated 650V
CoolMOS® and Startup Cell
(Latched and frequency jitter
Mode)

Power Management & Supply

N e v e r s t o p t h i n k i n g .
CoolSET®-F3
ICE3A1065ELJ
Revision History: 2012-11-19 Datasheet
Previous Version: V2.2
Page Subjects (major changes since last revision)
25 revised outline dimension for PG-DIP-8 package

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com

CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.

Edition 2012-11-19
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2008 Infineon Technologies AG.
All Rights Reserved.

Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).

Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
 CoolSET®-F3
ICE3A1065ELJ
Off-Line SMPS Current Mode Controller with
integrated 650V CoolMOS® and Startup Cell
(Latched and frequency jitter Mode)
Product Highlights
• Active Burst Mode to reach the lowest Standby Power Requirements
< 100mW
• Built-in latched off mode and external latch enable function to PG-DIP-8
test
increase robustness of the system
• Built-in and extendable blanking window for high load jumps to
increase system reliability
• Built-in soft start
• Frequency jitter for low EMI
• Robustness to system noise
• Pb-free lead plating; RoHS compliant
Features Description
• 650V avalanche rugged CoolMOS® with built-in The CoolSET®F3 ELJ version is the enhanced LJ version
Startup Cell for system noise. It retains all the features of LJ series
• Active Burst Mode for lowest Standby Power such as BiCMOS technologies, active burst mode,
• Fast load jump response in Active Burst Mode frequency jitter, propagation delay compensation, built-in
• 100kHz internally fixed switching frequency soft start, auto-restart protection for over load and open
• Built-in latched Off Mode for Overtemperature, loop, latch off protection for over voltage, over
Overvoltage & Short Winding Detection temperature and short winding, external latch off enable,
• Auto Restart Mode for Overload, Open Loop & built-in and extendable blanking time for short period of
VCC Undervoltage over power, etc. It is target for low power SMPS
• Built-in Soft Start application such as Off-Line Battery Adapters, DVD player
• Built-in and extendable blanking Window for short and recorder, set-top box, auxiliary power supply, etc. The
duration high current ELJ version has implemented some noise resist
• External latch enable function techniques to the IC such that it is more robust to the
• Max Duty Cycle 75% system noise which is generated during system ESD test,
• Overall tolerance of Current Limiting < ±5% lightning surge test, transient test, etc.
• Internal PWM Leading Edge Blanking
• BiCMOS technology provide wide VCC range
• Frequency jitter and soft driving for low EMI
• Robustness to system noise such as ESD,
lightning surge, etc.

Typical Application
+

Snubber Converter
CBulk DC Output
85 ... 270 VAC
-

CVCC
VCC Drain
Startup Cell
Power Management

PWM Controller
Current Mode
CS
Precise Low Tolerance Peak Depl. CoolMOS™
Current Limitation
RSense

FB
Active Burst Mode
GND Control
Latched Off Mode
Unit BL
Auto Restart Mode
CoolSET®-F3
( Latch & Jitter )

Type Package Marking VDS FOSC RDSon1) 230VAC ±15%2) 85-265 VAC2)
ICE3A1065ELJ PG-DIP-8 3A1065ELJ 650V 100kHz 2.95 32W 16W
1)
typ @ T=25°C
2)
Calculated maximum input power rating at Ta=75°C, Tj=125°C and without copper area as heat sink.

Version 2.3 3 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ

Table of Contents Page

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7.3.1 Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7.3.2 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3.7 CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Version 2.3 4 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ

6 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
8 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .27

Version 2.3 5 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Pin Configuration and Functionality

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-8 1.2 Pin Functionality
BL (Blanking and Latch)
The BL pin combines the functions of extendable
Pin Symbol Function blanking time for entering the Auto Restart Mode and
the external latch enable. The extendable blanking time
1 BL Blanking and Latch function is to extend the built-in 20ms blanking time by
2 FB Feedback adding an external capacitor at BL to ground. The
external latch enable function is an external access to
3 CS Current Sense/ latch off the IC. It is triggered by pulling down the BL pin
650V1) CoolMOS® Source to less than 0.1V.
4 Drain 650V1) CoolMOS® Drain
FB (Feedback)
5 Drain 650V1) CoolMOS® Drain The information about the regulation is provided by the
6 n.c. Not Connected FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FB-
7 VCC Controller Supply Voltage Signal controls in case of light load the Active Burst
8 GND Controller Ground Mode of the controller.

1)
at Tj = 110°C CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
integrated CoolMOS®. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
Package PG-DIP-8 output is immediately switched off. Furthermore the
current information is provided for the PWM-
Comparator to realize the Current Mode.

BL 1 8 GND Drain (Drain of integrated CoolMOS®)

Pin Drain is the connection to the Drain of the internal
CoolMOS®.

FB 2 7 VCC
VCC (Power supply)
The VCC pin is the positive supply of the IC. The
operating range is between 10.5V and 26V.
CS 3 6 n.c.
GND (Ground)
The GND pin is the ground of the controller.
Drain 4 5 Drain

Figure 1 Pin Configuration PG-DIP-8(top view)

Note: Pin 4 and 5 are shorted within the DIP 8
package.

Version 2.3 6 19 Nov 2012

 2

Figure 2

Version 2.3
+
Conv
CBulk Snubber DC O
85 ... 270 VAC VO
-

CVCC

VCC Drain
5.0V Power Management CoolMOS®
3.25kΩ Startup Cell
Internal Bias Voltage 5.0V
Reference
IBK Latched Off
Latch T2
Mode Reset
Enable
BL T3 0.6V VVCC < 6.23V GND
Signal #2 #1 CBK Undervoltage Lockout
Power-Down 18V
T1
Reset 0.72 PWM
TLE

Representative Blockdiagram
10.5V
Oscillator Section
Duty Cycle
VCC Spike max
0.9V C1 & 1
Blanking G3 Latched Off
24V G1 Clock
8.0us Mode Soft Start Soft-Start
1 ms Comparator
counter Freq. jitter
Thermal Shutdown Soft
& Gate
Tj >140°C
Start FF1
C7 G7 Driver
0.1V Block
S

7
C2 8us Blanking Time 1
R Q &
S1 G8
1 G9
C3 G2 PWM
4.0V Comparator
5.0V Spike 1.66V
& C8 Blanking C11
Spike
Representative Blockdiagram

4.5V Auto 190ns

G5 Blanking
RFB C4 20ms Restart
8.0us Propagation-Delay
Blanking Mode
Time Compensation
25kΩ
Active Burst Vcsth Leading 10kΩ CS
C5 20ms Blanking & 0.6V
FB Mode C10 Edge
1.35V Time
2pF G6 Blanking 1pF D1
x3.2 220ns RSense
C6a PWM OP &
3.61V G10 C12
& 0.31V
Current Limiting
C6b G11 Current Mode
3.0V
Control Unit
ICE3Axx65ELJ / CoolSET®-F3 ( Latch & Jitter Mode )

# : optional external components;

#1 : CBK is used to extand the Blanking Time
#2 : TLE is used to enable the external Latch function
CoolSET®-F3

19 Nov 2012
Representative Blockdiagram
ICE3A1065ELJ
 CoolSET®-F3
ICE3A1065ELJ
Functional Description

3 Functional Description
All values which are used in the functional description the BL pin is pulled down to less than 0.1V, the Latch
are typical values. For calculating the worst cases the Off Mode is triggered.
min/max values which can be found in section 4 The Auto Restart Mode reduces the average power
Electrical Characteristics have to be considered. conversion to a minimum under unsafe operating
conditions. This is necessary for a prolonged fault
3.1 Introduction condition which could otherwise lead to a destruction of
the SMPS over time. Once the malfunction is removed,
CoolSET®-F3 ELJ series is the enhanced version of the normal operation is automatically retained after the
LJ series. Not only retains all the features of LJ series next Start Up Phase.
but it also implements with special technique to make The internal precise peak current limitation reduces the
the IC more robust to the system noise which is costs for the transformer and the secondary diode. The
generated during transient test, system ESD test, influence of the change in the input voltage on the
lightning surge test, etc. power limitation can be avoided together with the
In order to obtain the best-in class low standby power, integrated Propagation Delay Compensation.
a new fully integrated Standby Power concept is Therefore the maximum power is nearly independent
implemented into the IC. An intelligent Active Burst on the input voltage which is required for wide range
Mode is used for this Standby Mode. After entering this SMPS. There is no need for an extra over-sizing of the
mode there is still a full control of the power conversion SMPS, e.g. the transformer or the secondary diode.
by the secondary side via the same optocoupler that is Furthermore, this ELJ version implements the
used for the normal PWM control. The response on frequency jitter mode to the switching clock such that
load jumps is optimized. The voltage ripple on Vout is the EMI noise will be effectively reduced.
minimized. Vout is on well controlled in this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
3.2 Power Management
IC to reduce the external part count. Drain VCC
Furthermore a high voltage Startup Cell is integrated
into the IC which is switched off once the Undervoltage Startup Cell
Lockout on-threshold of 18V is exceeded. This Startup
Cell is part of the integrated CoolMOS®. The external
startup resistor is no longer necessary as this Startup CoolMOS ®
Cell is connected to the Drain. Power losses are
therefore reduced. This increases the efficiency under
light load conditions drastically. Power M anagem ent
This version is adopting the BiCMOS technology and it
Undervoltage Lockout
can increase design flexibility as the Vcc voltage range Internal Bias
18V
is increased to 26V. Latched Off M ode 10.5V
For this ELJ version, the soft start is a built-in function. Reset
V VC C < 6.23V
It is set at 20ms. Then it can save external component
counts. Power-Down Reset Voltage 5.0V
Reference
There are 2 modes of blanking time for high load
jumps; the basic mode and the extendable mode. The
blanking time for the basic mode is set at 20ms while Auto Restart
the extendable mode will increase the blanking time M ode

from basic mode by adding external capacitor at the BL Soft Start block Active Burst
M ode
pin. During this time window the overload detection is
disabled. Latched Off
M ode
In order to increase the robustness and safety of the
system, the IC provides 2 levels of protection modes:
Latched Off Mode and Auto Restart Mode. The
Latched Off Mode is only entered under dangerous Figure 3 Power Management
conditions which can damage the SMPS if not switched
off immediately. A restart of the system can only be The Undervoltage Lockout monitors the external
done by recycling the AC line. In addition, for this ELJ supply voltage VVCC. When the SMPS is plugged to the
version, there is an external Latch Enable function main line the internal Startup Cell is biased and starts
provided to increase the flexibility in protection. When to charge the external capacitor CVCC which is

Version 2.3 8 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

connected to the VCC pin. This VCC charge current is Current Mode means the duty cycle is controlled by the
controlled to 0.9mA by the Startup Cell. When the VVCC slope of the primary current. This is done by comparing
exceeds the on-threshold VCCon=18V, the bias circuit the FB signal with the amplified current sense signal.
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
losses present due to the connection of the Startup Cell Amplified Current Signal
to the Drain voltage. To avoid uncontrolled ringing at
switch-on a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place after FB
Active Mode was entered and VVCC falls below 10.5V.
The maximum current consumption before the
controller is activated is about 250μA. 0.6V
When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit switched off and the soft start counter is Driver
reset. Thus it is ensured that at every startup cycle the t
soft start starts at zero.
The internal bias circuit is switched off if Latched Off
Mode or Auto Restart Mode is entered. The current
consumption is then reduced to 250μA.
Ton
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line. In case
Latched Off Mode is entered, VCC needs to be lowered t
below 6.23V to reset the Latched Off Mode. This is
done usually by re-cycling the AC line. Figure 5 Pulse Width Modulation
When Active Burst Mode is entered, the internal Bias is In case the amplified current sense signal exceeds the
switched off most of the time but the Voltage Reference FB signal the on-time Ton of the driver is finished by
is kept alive in order to reduce the current consumption resetting the PWM-Latch (see Figure 5).
below 450μA. The primary current is sensed by the external series
resistor RSense inserted in the source of the integrated
CoolMOS®. By means of Current Mode regulation, the
3.3 Improved Current Mode secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
Soft-Start Comparator the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS®.
PWM-Latch
FB To improve the Current Mode during light load
C8 R Q conditions the amplified current ramp of the PWM-OP
Driver is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
S Q
maximum duty cycle limitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
0.6V T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
PWM OP small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
x3.2 comparison with the FB-signal. The duty cycle is then
CS controlled by the slope of the Voltage Ramp.
Improved By means of the time delay circuit which is triggered by
the inverted VOSC signal, the Gate Driver is switched-off
Current Mode until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
Figure 4 Current Mode continuously till 0% by decreasing VFB below that
threshold.

Version 2.3 9 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
Soft-Start Comparator leading edge blanking to the external sense resistor
PWM Comparator RSense connected to pin CS. RSense converts the source
current into a sense voltage. The sense voltage is
FB amplified with a gain of 3.2 by PWM OP. The output of
C8 the PWM-OP is connected to the voltage source V1.
PWM-Latch The voltage ramp with the superimposed amplified
Oscillator current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
VOSC Figure 6).
time delay
circuit (156ns) 3.3.2 PWM-Comparator
Gate Driver
The PWM-Comparator compares the sensed current
0.6V signal of the integrated CoolMOS® with the feedback
10kΩ signal VFB (see Figure 8). VFB is created by an external
X3.2 optocoupler or external transistor in combination with
the internal pull-up resistor RFB and provides the load
T2 R1 information of the feedback circuitry. When the
V1
PWM OP amplified current signal of the integrated CoolMOS®
C1 exceeds the signal VFB the PWM-Comparator switches
off the Gate Driver.

Voltage Ramp
5V
Figure 6 Improved Current Mode
RFB Soft-Start Comparator

FB
VOSC PWM-Latch
C8
max.
Duty Cycle
PWM Comparator

0.6V
Voltage Ramp t
Optocoupler
PWM OP
CS
0.6V
X3.2
FB

Improved
Gate Driver t Current Mode
156ns time delay

Figure 8 PWM Controlling

t
Figure 7 Light Load Conditions

Version 2.3 10 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

3.4 Startup Phase

Soft Start counter

SoftS
Soft Start finish

Soft Start

Soft Start
V SoftS
Soft-Start
Comparator
Gate Driver V SoftS2
C7 & V SoftS1

G7

Figure 10 Soft Start Phase

0.6V

5V
x3.2 CS
PWM OP R SoftS
SoftS

Figure 9 Soft Start

In the Startup Phase, the IC provides a Soft Start
period to control the maximum primary current by
means of a duty cycle limitation. The Soft Start function Soft Start 32I 8I 4I 2I I
is a built-in function and it is controlled by an internal Counter
counter.
When the VVCC exceeds the on-threshold voltage, the
IC starts the Soft Start mode. The function is realized
by an internal Soft Start resistor, a current sink and a
counter. And the amplitude of the current sink is
controlled by the counter. Figure 11 Soft Start Circuit
After the IC is switched on, the VSoftS voltage is
controlled such that the voltage is increased step-
wisely (32 steps) with the increase of the counts. The
Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
decrease gradually and the duty ratio of the gate drive
increase gradually. The Soft Start will be finished in
20ms after the IC is switched on. At the end of the Soft
Start period, the current sink is switched off.

Version 2.3 11 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

The Start-Up time tStart-Up before the converter output

voltage VOUT is settled, must be shorter than the Soft-
Start Phase tSoft-Start (see Figure 13).
VSoftS
By means of Soft-Start there is an effective
tSoft-Start minimization of current and voltage stresses on the
VSOFTS32 integrated CoolMOS®, the clamp circuit and the output
overshoot and it helps to prevent saturation of the
transformer during Start-Up.

3.5 PWM Section

t 0.75
Gate PWM Section
Driver Oscillator

Duty Cycle
max

Clock
t Frequency
Jitter
Figure 12 Gate drive signal under Soft-Start Phase
Within the soft start period, the duty cycle is increasing
from zero to maximum gradually (see Figure 12).
Soft Start
In addition to Start-Up, Soft-Start is also activated at Block FF1
each restart attempt during Auto Restart. Gate Driver
Soft Start 1 S
Comparator R &
G8 Q
VSoftS PWM G9
Comparator
tSoft-Start
Current
VSOFTS32 Limiting
CoolMOS®
Gate

VFB t Figure 14 PWM Section Block

3.5.1 Oscillator
4.0V The oscillator generates a fixed frequency of 100KHz
with frequency jittering of ±4% (which is ±4KHz) at a
jittering period of 4ms.
A capacitor, a current source and a current sink which
VOUT t determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
VOUT very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
tStart-Up reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
t into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Figure 13 Start Up Phase Start block. Then the switching frequency is varied in
range of 100KHz ± 4KHz at period of 4ms.

Version 2.3 12 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

3.5.2 PWM-Latch FF1 is set to low in order to disable power transfer to the
The output of the oscillator block provides continuous secondary side.
pulse to the PWM-Latch which turns on/off the internal
CoolMOS® After the PWM-Latch is set, it is reset by the 3.6 Current Limiting
PWM comparator, the Soft Start comparator or the
Current -Limit comparator. When it is in reset mode, the
output of the driver is shut down immediately. PWM Latch Latched Off
FF1 Mode
Current Limiting
3.5.3 Gate Driver
Spike 1.66V
Blanking C11
190ns
VCC
Propagation-Delay
Compensation
PWM-Latch
1
Vcsth
C10 Leading
Edge
Gate Blanking
PWM-OP 220ns
CoolMOS® &
G10 C12
0.31V

Gate Driver
10k 1pF
Active Burst
Figure 15 Gate Driver Mode D1

The driver-stage is optimized to minimize EMI and to

provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the internal CS
CoolMOS® threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see Figure 17 Current Limiting Block
Figure 16).
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS® is sensed
(internal) via an external sense resistor RSense. By means of
VGate RSense the source current is transformed to a sense
voltage VSense which is fed into the pin CS. If the voltage
VSense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately turns off the gate drive by
ca. t = 130ns resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
5V support the immediate shut down of the integrated
CoolMOS® with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
t In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Figure 16 Gate Rising Slope Blanking is integrated in the current sense path for the
Thus the leading switch on spike is minimized. comparators C10, C12 and the PWM-OP.
Furthermore the driver circuit is designed to eliminate The output of comparator C12 is activated by the Gate
cross conduction of the output stage. G10 if Active Burst Mode is entered. When it is
During power up, when VCC is below the undervoltage activated, the current limiting is reduced to 0.31V. This
lockout threshold VVCCoff, the output of the Gate Driver

Version 2.3 13 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

voltage level determines the maximum power level in The overshoot of Signal2 is larger than of Signal1 due
Active Burst Mode. to the steeper rising waveform. This change in the
Furthermore, the comparator C11 is implemented to slope is depending on the AC input voltage.
detect dangerous current levels which could occur if Propagation Delay Compensation is integrated to
there is a short winding in the transformer or the reduce the overshoot due to dI/dt of the rising primary
secondary diode is shorten. To ensure that there is no current. Thus the propagation delay time between
accidentally entering of the Latched Mode by the exceeding the current sense threshold Vcsth and the
comparator C11, a 190ns spike blanking time is switching off of the integrated internal CoolMOS® is
integrated in the output path of comparator C11. compensated over temperature within a wide range.
Current Limiting is then very accurate.
3.6.1 Leading Edge Blanking For example, Ipeak = 0.5A with RSense = 2. The current
sense threshold is set to a static voltage level Vcsth=1V
without Propagation Delay Compensation. A current
VSense
ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a
propagation delay time of tPropagation Delay =180ns leads
Vcsth to an Ipeak overshoot of 14.4%. With the propagation
tLEB = 220ns
delay compensation, the overshoot is only around 2%
(see Figure 20).

with compensation without compensation

V
1,3

t 1,25

1,2

Figure 18 Leading Edge Blanking

VSense

1,15

1,1
Whenever the internal CoolMOS® is switched on, a
1,05
leading edge spike is generated due to the primary-
1
side capacitances and reverse recovery time of the
0,95
secondary-side rectifier. This spike can cause the gate
drive to switch off unintentionally. In order to avoid a 0,9
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 V
premature termination of the switching pulse, this spike
dVSense μs
is blanked out with a time constant of tLEB = 220ns.
dt

3.6.2 Propagation Delay Compensation Figure 20 Overcurrent Shutdown

In case of overcurrent detection, there is always The Propagation Delay Compensation is realized by
propagation delay to switch off the internal CoolMOS®. means of a dynamic threshold voltage Vcsth (see Figure
An overshoot of the peak current Ipeak is induced to the 21). In case of a steeper slope the switch off of the
delay, which depends on the ratio of dI/dt of the peak driver is earlier to compensate the delay.
current (see Figure 19).
V OSC m ax. D uty C ycle

Signal2 Signal1
ISense tPropagation Delay
Ipeak2 IOvershoot2 off tim e

Ipeak1
ILimit V S e n se P ro pa gatio n D e lay t

IOvershoot1 V csth

t
S ig n a l1 S ig n a l2
Figure 19 Current Limiting t

Figure 21 Dynamic Voltage Threshold Vcsth

Version 2.3 14 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

3.7 Control Unit the 8.0us spike blanking time, the Auto Restart Mode is
activated.
The Control Unit contains the functions for Active Burst For example, if CBK = 0.22uF, IBK = 8.4uA
Mode, Auto Restart Mode and Latched Off Mode. The
Active Burst Mode and the Auto Restart Mode both Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 100ms
have 20ms internal Blanking Time. For the Auto The 20ms blanking time circuit after C4 is disabled by
Restart Mode, a further extendable Blanking Time is the soft stat block such that the controller can start up
achieved by adding external capacitor at BL pin. By properly.
means of this Blanking Time, the IC avoids entering The Active Burst Mode has basic blanking mode only
into these two modes accidentally. Furthermore those while the Auto Restart Mode has both the basic and the
buffer time for the overload detection is very useful for extendable blanking mode.
the application that works in low current but requires a
short duration of high current occasionally. 3.7.2 Active Burst Mode
The IC enters Active Burst Mode under low load
3.7.1 Basic and Extendable Blanking Mode conditions. With the Active Burst Mode, the efficiency
increases significantly at light load conditions while still
maintaining a low ripple on VOUT and a fast response on
BL load jumps. During Active Burst Mode, the IC is
5.0V controlled by the FB signal. Since the IC is always
# CBK IBK active, it can be a very fast response to the quick
change at the FB signal. The Start up Cell is kept OFF
in order to minimize the power loss.
0.9V Soft Start
block
1
S1
G2

Internal Bias
C3
Spike
4.0V
Blanking
Current
8.0us 20 ms Blanking Limiting
Time &
& G10

4.5V 20ms G5 Auto 4.5V

C4 Blanking Restart
Time Mode C4

Active
FB Burst
FB & C5 & Mode
20ms Active
C5 Blanking G6 Burst 1.35V G6
1.35V Time Mode

Control Unit C6a

3.61V

Figure 22 Basic and Extendable Blanking Mode &

C6b G11
There are 2 kinds of Blanking mode; basic mode and
3.0V
the extendable mode. The basic mode has an internal Control Unit
pre-set 20ms blanking time while the extendable mode
has extended blanking time to basic mode by Figure 23 Active Burst Mode
connecting an external capacitor to the BL pin. For the
extendable mode, the gate G5 is blocked even though
the 20ms blanking time is reached if an external The Active Burst Mode is located in the Control Unit.
capacitor CBK is added to BL pin. While the 20ms Figure 23 shows the related components.
blanking time is passed, the switch S1 is opened by
G2. Then the 0.9V clamped voltage at BL pin is 3.7.2.1 Entering Active Burst Mode
charged to 4.0V through the internal IBK constant The FB signal is kept monitoring by the comparator C4.
current. Then G5 is enabled by comparator C3. After
During normal operation, the internal blanking time
counter is reset to 0. When FB signal falls below 1.35V,

Version 2.3 15 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

it starts to count. When the counter reach 20ms and FB

signal is still below 1.35V, the system enters the Active
Burst Mode. This time window prevents a sudden VFB Entering Leaving
entering into the Active Burst Mode due to large load Active Burst Active Burst
jumps. Mode Mode
4.5V
After entering Active Burst Mode, a burst flag is set and 3.61V
the internal bias is switched off in order to reduce the 3.0V
current consumption of the IC to approx. 450uA.
It needs the application to enforce the VCC voltage 1.35V
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on Blanking Timer t
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst 20ms Blanking Time
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.

3.7.2.2 Working in Active Burst Mode

After entering the Active Burst Mode, the FB voltage
rises as VOUT starts to decrease, which is due to the VCS t
inactive PWM section. The comparator C6a monitors
the FB signal. If the voltage level is larger than 3.61V,
the internal circuit will be activated; the Internal Bias Current limit level
circuit resumes and starts to provide switching pulse. In 1.06V
during Active Burst
Active Burst Mode the gate G10 is released and the Mode
current limit is reduced to 0.31V. In one hand, it can
0.31V
reduce the conduction loss and the other hand, it can
reduce the audible noise. If the load at VOUT is still kept
unchanged, the FB signal will drop to 3.0V. At this level VVCC t
the C6b deactivates the internal circuit again by
switching off the internal Bias. The gate G11 is active
again as the burst flag is set after entering Active Burst
Mode. In Active Burst Mode, the FB voltage is changing
like a saw tooth between 3.0V and 3.61V (see Figure
24). 10.5V

3.7.2.3 Leaving Active Burst Mode

IVCC t
The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4.
As the current limit is ca. 31% during Active Burst 2.5mA
Mode, a certain load jump is needed so that the FB
signal can exceed 4.5V. At that time the comparator C4
resets the Active Burst Mode control which in turn
blocks the comparator C12 by the gate G10. The 450uA
maximum current can then be resumed to stabilize
VOUT. VOUT t

Figure 24 Signals in Active Burst Mode

Version 2.3 16 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

3.7.3 Protection Modes The VCC voltage is observed by comparator C1 while

The IC provides several protection features which are the FB voltage is monitored by the comparator C4. If
separated into two categories. Some enter Latched Off the VCC voltage is > 24V and the FB is > 4.5V, the
Mode and the others enter Auto Restart Mode. Besides overvoltage detection is activated. That means the
the pre-defined protection feature for the Latch off overvoltage detection is only activated if the FB signal
mode, there is also an external Latch off Enable pin for is outside the operating range > 4.5V, e.g. when Open
customer defined Latch off protection features. The Loop happens. The logic can eliminate the possible of
Latched Off Mode can only be reset if VCC falls below entering Latch off mode if there is a small voltage
6.23V. Both modes prevent the SMPS from destructive overshoots of VVCC during normal operating.
states.The following table shows the relationship The internal Voltage Reference is switched off most of
between possible system failures and the chosen the time once Latched Off Mode is entered in order to
protection modes. minimize the current consumption of the IC. This
Latched Off Mode can only be reset if the VVCC < 6.23V.
VCC Overvoltage Latched Off Mode In this mode, only the UVLO is working which controls
Overtemperature Latched Off Mode the Startup Cell by switching on/off at VVCCon/VVCCoff.
During this phase, the average current consumption is
Short Winding/Short Diode Latched Off Mode only 250μA. As there is no longer a self-supply by the
External latch enable Latched Off Mode auxiliary winding, the VCC drops. The Undervoltage
Lockout switches on the integrated Startup Cell when
Overload Auto Restart Mode VCC falls below 10.5V. The Startup Cell is switched off
again when VCC has exceeded 18V. Once the Latched
Open Loop Auto Restart Mode
Off Mode was entered, there is no Start Up Phase
VCC Undervoltage Auto Restart Mode whenever the VCC exceeds the switch-on level of the
Undervoltage Lockout. Therefore the VCC voltage
Short Optocoupler Auto Restart Mode
changes between the switch-on and switch-off levels of
the Undervoltage Lockout with a saw tooth shape (see
3.7.3.1 Latched Off Mode Figure 26).

VVCC
CS Spike Latched Off
1.66V C11 Blanking Mode Reset
190ns VVCC < 6.23V
18V

UVLO
1
Latched 10.5V
1ms G3 Off Mode
counter
BL IVCCStart t
8us
TLE C2 Blanking
# Time 0.9mA
0.1V
Latch
Enable
signal
VCC
& Spike
C1 Blanking
24V G1 8.0us VOUT t

4.5V Figure 26 Signals in Latched Off Mode

C4 The Thermal Shutdown block monitors the junction
Voltage
FB Thermal Shutdown Reference temperature of the IC. After detecting a junction
temperature higher than latched thermal shutdown
Tj >140°C
temperature; TjSD, the Latched Off Mode is entered.
The signals coming from the temperature detection and
Control Unit
VCC overvoltage detection are fed into a spike
blanking with a time constant of 8.0μs in order to
ensure the system reliability.
Figure 25 Latched Off Mode

Version 2.3 17 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Functional Description

Furthermore, a short winding or short diode on the to charge the capacitor CBK from 0.9V to 4.0V after the
secondary side can be detected by the comparator C11 switch S1 is released. The charging time from 0.9V to
which is in parallel to the propagation delay 4.0V are the extendable blanking time. If CBK is 0.22uF
compensated current limit comparator C10. In normal and IBK is 8.4uA, the extendable blanking time is
operating mode, comparator C10 controls the around 80ms and the total blanking time is 100ms. In
maximum level of the CS signal at 1.06V. If there is a combining the FB and blanking time, there is a blanking
failure such as short winding or short diode, C10 is no window generated which prevents the system to enter
longer able to limit the CS signal at 1.06V. Instead the Auto Restart Mode due to large load jumps.
comparator C11 detects the peak current voltage > In case of VCC undervoltage, the IC enters into the
1.66V and enters the Latched Off Mode immediately in Auto Restart Mode and starts a new startup cycle.
order to keep the SMPS in a safe stage.
Short Optocoupler also leads to VCC undervoltage as
In case the pre-defined Latch Off features are not there is no self supply after activating the internal
sufficient, there is a customer defined external Latch reference and bias.
Enable feature. The Latch Off Mode can be triggered
In contrast to the Latched Off Mode, there is always a
by pulling down the BL pin to < 0.1V. It can simply add
Startup Phase with switching cycles in Auto Restart
a trigger signal to the base of the externally added
Mode. After this Start Up Phase, the conditions are
transistor, TLE at the BL pin. To ensure this latch
again checked whether the failure mode is still present.
function will not be mis-triggered during start up, a 1ms
Normal operation is resumed once the failure mode is
delay time is implemented to blank the unstable signal.
removed that had caused the Auto Restart Mode.
3.7.3.2 Auto Restart Mode

BL
5.0V
# CBK IBK

0.9V
1
S1
G2

C3
Spike
4.0V
Blanking
8.0us

&

4.5V 20ms G5 Auto

C4 Blanking Restart
FB Time Mode

Control Unit

Figure 27 Auto Restart Mode

In case of Overload or Open Loop, the FB exceeds
4.5V which will be observed by comparator C4. Then
the internal blanking counter starts to count. When it
reaches 20ms, the switch S1 is released. Then the
clamped voltage 0.9V at VBL can increase. When there
is no external capacitor CBK connected, the VBL will
reach 4.0V immediately. When both the input signals at
AND gate G5 is positive, the Auto-Restart Mode will be
activated after the extra spike blanking time of 8.0us is
elapsed. However, when an extra blanking time is
needed, it can be achieved by adding an external
capacitor, CBK. A constant current source of IBK will start

Version 2.3 18 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Electrical Characteristics

4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.Ta=25°C unless otherwise specified.

Parameter Symbol Limit Values Unit Remarks

min. max.
Drain Source Voltage VDS - 650 V Tj=110°C
Pulse drain current, tp limited by max. ID_Puls - 3.4 A
Tj=150°C
Avalanche energy, repetitive tAR limited EAR - 0.07 mJ
by max. Tj=150°C1)
Avalanche current, repetitive tAR limited IAR - 1.0 A
by max. Tj=150°C
VCC Supply Voltage VVCC -0.3 27 V
FB Voltage VFB -0.3 5.5 V
BL Voltage VFB -0.3 5.5 V
CS Voltage VCS -0.3 5.5 V
Junction Temperature Tj -40 150 °C Controller & CoolMOS®
Storage Temperature TS -55 150 °C
Thermal Resistance RthJA - 90 K/W PG-DIP-8
Junction -Ambient
Soldering temperature, wavesoldering Tsold - 260 °C 1.6mm (0.063in.) from case
only allowed at leads for 10s
ESD Capability (incl. Drain Pin) VESD - 22) kV Human body model3)
1)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2)
2KV is for all pin combinations except VCC to GND is 1KV
3)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

Version 2.3 19 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Electrical Characteristics

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.
VCC Supply Voltage VVCC VVCCoff 26 V
Junction Temperature of TjCon -25 130 °C Max value limited due to thermal
Controller shut down of controller
Junction Temperature of TjCoolMOS -25 150 °C
CoolMOS®

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from – 25 °C to 130 °C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Start Up Current IVCCstart - 150 250 μA VVCC =17V

VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

IVCCcharge2 0.55 0.90 1.60 mA VVCC = 1V
IVCCcharge3 - 0.7 - mA VVCC =17V
Leakage Current of IStartLeak - 0.2 50 μA VDrain = 450V
Start Up Cell and CoolMOS® at Tj=100°C
Supply Current with IVCCsup1 - 1.5 2.5 mA
Inactive Gate
Supply Current with Active Gate IVCCsup2 - 2.5 4.2 mA IFB = 0A
Supply Current in Latched Off IVCClatch - 250 - μA IFB = 0A
Mode
Supply Current in IVCCrestart - 250 - μA IFB = 0A
Auto Restart Mode with Inactive
Gate
Supply Current in Active Burst IVCCburst1 - 450 950 μA VFB = 2.5V
Mode with Inactive Gate
IVCCburst2 - 450 950 μA VVCC = 11.5V,VFB = 2.5V
VCC Turn-On Threshold VVCCon 17.0 18.0 19.0 V
VCC Turn-Off Threshold VVCCoff 9.8 10.5 11.2 V
VCC Turn-On/Off Hysteresis VVCChys - 7.5 - V

Version 2.3 20 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Electrical Characteristics

4.3.2 Internal Voltage Reference

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FB
IFB = 0

4.3.3 PWM Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Fixed Oscillator Frequency fOSC1 87 100 113 kHz
fOSC2 92 100 108 kHz Tj = 25°C
Frequency Jittering Range fjitter - ±4.0 - kHz Tj = 25°C
Max. Duty Cycle Dmax 0.70 0.75 0.80

Min. Duty Cycle Dmin 0 - - VFB < 0.3V

PWM-OP Gain AV 3.0 3.2 3.4

Voltage Ramp Offset VOffset-Ramp - 0.6 - V

VFB Operating Range Min Level VFBmin - 0.5 - V

VFB Operating Range Max level VFBmax - - 4.3 V CS=1V, limited by

Comparator C41)
FB Pull-Up Resistor RFB 9 15.4 22 kΩ

1)
The parameter is not subjected to production test - verified by design/characterization

4.3.4 Soft Start time

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Soft Start time tSS - 20.0 - ms

Version 2.3 21 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Electrical Characteristics

4.3.5 Control Unit

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Clamped VBL voltage during VBLclmp 0.85 0.90 0.95 V VFB = 4V
Normal Operating Mode
Blanking time voltage limit for VBKC3 3.85 4.00 4.15 V
Comparator C3
Over Load & Open Loop Detection VFBC4 4.28 4.50 4.72 V
Limit for Comparator C4
Active Burst Mode Level for VFBC5 1.23 1.35 1.43 V
Comparator C5
Active Burst Mode Level for VFBC6a 3.48 3.61 3.76 V After Active Burst
Comparator C6a Mode is entered
Active Burst Mode Level for VFBC6b 2.88 3.00 3.12 V After Active Burst
Comparator C6b Mode is entered
Overvoltage Detection Limit VVCCOVP 23 24 25 V VFB = 5V

Latch Enable level at BL pin VLE 0.07 0.1 0.2 V > 30μs

Charging current at BL pin IBK 5.8 8.4 10.9 μA Charge starts after the
built-in 20ms blanking
time elapsed
Latched Thermal Shutdown1) TjSD 130 140 150 °C

Built-in Blanking Time for tBK - 20 - ms without external

Overload Protection or enter capacitor at BL pin
Active Burst Mode
Inhibit Time for Latch Enable tIHLE - 1.0 - ms Count when VCC >
function during Start up 18V
Spike Blanking Time before Latch off tSpike - 8.0 - μs
or Auto Restart Protection

Power Down Reset for VVCCPD 5.2 6.23 7.8 V After Latched Off Mode
Latched Mode is entered
1)
The parameter is not subjected to production test - verified by design/characterization. The thermal shut down
temperature refers to the junction temperature of the controller.

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP
and VVCCPD

Version 2.3 22 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Electrical Characteristics

4.3.6 Current Limiting

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Peak Current Limitation Vcsth 0.99 1.06 1.09 V dVsense / dt = 0.6V/μs
(incl. Propagation Delay) (see Figure 20)
Peak Current Limitation during VCS2 0.27 0.31 0.37 V
Active Burst Mode
Leading Edge Blanking tLEB - 220 - ns

CS Input Bias Current ICSbias -1.5 -0.2 - μA VCS =0V

Over Current Detection for VCS1 1.57 1.66 1.76 V
Latched Off Mode
CS Spike Blanking for tCSspike - 190 - ns
Comparator C11

4.3.7 CoolMOS® Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Drain Source Breakdown Voltage V(BR)DSS 600 - - V Tj = 25°C
650 - - V Tj = 110°C
Drain Source On-Resistance RDSon - 2.95 3.42 Ω Tj = 25°C
- 6.60 7.56 Ω Tj=125°C1)
at ID = 1.0A

Effective output capacitance, Co(er) - 7.0 - pF VDS = 0V to 480V

energy related
Rise Time trise - 302) - ns
Fall Time tfall - 302) - ns
1)
The parameter is not subjected to production test - verified by design/characterization
2)
Measured in a Typical Flyback Converter Application

Version 2.3 23 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Temperature derating curve

5 Temperature derating curve

Safe Operating Area for ICE3A(B)1065(ELJ)

ID = f ( VDS )
parameter : D = 0, TC = 25deg.C
10

1
ID [A]

0.1

tp = 0.1ms
0.01 tp = 1ms
tp = 10ms
tp = 100ms
tp = 1000ms
DC

0.001
1 10 100 1000
V DS [V]

Figure 28 Safe Operating area (SOA) curve

(p g p )
120

100
SOA temperature derating coefficient [%]

80

60

40

20

0
0 20 40 60 80 100 120 140

Figure 29 SOA temperature derating coefficient curve

Version 2.3 24 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Outline Dimension

6 Outline Dimension

PG-DIP-8
(Plastic Dual In-Line Outline)

Figure 30 PG-DIP-8 (PB-free Plating Plastic Dual In-Line Outline)

Version 2.3 25 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Marking

7 Marking

Marking

Figure 31 Marking

Version 2.3 26 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Schematic for recommended PCB layout

8 Schematic for recommended PCB layout

TR1

BR1 R11 C12

Spark Gap 3 D21
FUSE1 C11
X-CAP Vo
L bulk cap
L1 D11
Spark Gap 1 C1
C21
GND
Spark Gap 2 D11
Spark Gap 4 Z11
GND
N IC11
C2 C3 R12
C16
R21
CS DRAIN R13
Y-CAP Y-CAP C4 D13
R14
Y-CAP
F3
SOFTS VCC
CoolSET
R23 R22
GND FB NC
C22

C13 C15

C14 C23
R24

IC12 IC21

R25
F3 CoolSET schematic for recommended PCB layout

Figure 32 Schematic for recommended PCB layout

General guideline for PCB layout design using F3 CoolSET® (refer to Figure 32):
1. “Star Ground “at bulk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET® device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET® device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector
of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET® IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 32):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)

Version 2.3 27 19 Nov 2012

 CoolSET®-F3
ICE3A1065ELJ
Schematic for recommended PCB layout

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET® and
reduce the abnormal behavior of the CoolSET®. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the
sensitive components such as the primary controller, IC11.

Version 2.3 28 19 Nov 2012

Total Quality Management

Qualität hat für uns eine umfassende Quality takes on an allencompassing

Bedeutung. Wir wollen allen Ihren significance at Semiconductor Group.
Ansprüchen in der bestmöglichen For us it means living up to each and
Weise gerecht werden. Es geht uns also every one of your demands in the best
nicht nur um die Produktqualität – possible way. So we are not only
unsere Anstrengungen gelten concerned with product quality. We
gleichermaßen der Lieferqualität und direct our efforts equally at quality of
Logistik, dem Service und Support supply and logistics, service and
sowie allen sonstigen Beratungs- und support, as well as all the other ways in
Betreuungsleistungen. which we advise and attend to you.
Dazu gehört eine bestimmte Part of this is the very special attitude of
Geisteshaltung unserer Mitarbeiter. our staff. Total Quality in thought and
Total Quality im Denken und Handeln deed, towards co-workers, suppliers
gegenüber Kollegen, Lieferanten und and you, our customer. Our guideline is
Ihnen, unserem Kunden. Unsere “do everything with zero defects”, in an
Leitlinie ist jede Aufgabe mit „Null open manner that is demonstrated
Fehlern“ zu lösen – in offener beyond your immediate workplace, and
Sichtweise auch über den eigenen to constantly improve.
Arbeitsplatz hinaus – und uns ständig Throughout the corporation we also
zu verbessern. think in terms of Time Optimized
Unternehmensweit orientieren wir uns Processes (top), greater speed on our
dabei auch an „top“ (Time Optimized part to give you that decisive
Processes), um Ihnen durch größere competitive edge.
Schnelligkeit den entscheidenden Give us the chance to prove the best of
Wettbewerbsvorsprung zu verschaffen. performance through the best of quality
Geben Sie uns die Chance, hohe – you will be convinced.
Leistung durch umfassende Qualität zu
beweisen.
Wir werden Sie überzeugen.

http://www.infineon.com

Published by Infineon Technologies AG