Điện Tử Tương Tự

Ôn tập

5/2023
Lecture #4: Multi-stage Transistor Amplifiers

Lecture #5: Op-Amp & Application Circuits

2
Lecture #4: Multi-stage Transistor Amplifiers
vo ii io
Voltage gain (hệ số kđ điện áp): Av =
vi +
io vi(t) RL vo(t)
Current gain (hệ số kđ dòng): Ai = _
ii

Power gain (hệ số kđ công suất): Ap = Av Ai

load power ( PL ) voio
Ap = =
input power ( PI ) vI iI

3
Lecture #4: Multi-stage Transistor Amplifiers
• Expressing Gain in Decibels
➢ Voltage gain in decibels = 20×log |Av| dB
➢ Current gain in decibels = 20×log |Ai| dB
➢ Power gain in decibels = 10×log |Ap| dB

4
Amplifier Configurations

5
Circuit Models for Amplifiers

Voltage gain: Overall voltage gain:

vo RL vo Rin Rin RL
Av  = Avo Gv  = Av = Avo
vi RL + Ro vsig Rin + Rsig Rin + Rsig RL + Ro

Ideal characteristic : Ri = , Ro = 0 6
Fig.: An npn transistor & an NMOS transistor operating in the active mode
7
 vCE = VCC − iC RC = VCC − RC I S e vBE /VT 1
vDS = VDD − iD RD = VDD − kn RD (vGS − Vt ) 2
2
IC 𝑣𝑏𝑒 𝛽 𝑉𝑇
gm = 𝑟𝜋  = = 2I D 2I W W
VT 𝑖𝑏 𝑔𝑚 𝐼𝐵 gm = = D = kn (VGS − Vt ) = 2kn I D
VGS − Vt VOV L L
𝑣𝑏𝑒 𝑉𝑇 𝛼 I C RC
𝑟𝑒 ≡ = = Av = − = − g m RC I D RD W
𝑖𝑒 𝐼𝐸 𝑔𝑚 VT Av = − = −kn VOV RD = − g m RD
VOV / 2 L
vbe = ib r = ie re  r = ( ie / ib ) re = (  + 1) re
1 VA
VA + VCE ro = =
ro = ID ID
IC 8
 Amplifier Circuit Analysis Steps
First we do a dc analysis to find the Q-point, and then we perform an ac analysis to determine the behavior
of the circuit as an amplifier. The Q-point values must be found first because they ultimately determine the ac
characteristics of the amplifier.
1) (a) Determine Q-point. The transistors must be biased into active mode (forward active for BJTs and
Saturation for MOSFET) and then, (b) calculate small signal parameters gm, r, ro etc…
2) Convert to the AC only model.
✓ DC Voltage sources are replaced with shorts to GND; DC Current sources are replaced with open
circuits
✓ Large capacitors are replaced with short circuits; Large inductors are replaced with open circuits
3) Use a Thevenin circuit where necessary on each leg of transistor.
4) Replace transistor with small signal model.
5) Simplify the circuit as much as necessary and solve for gain.
6) Solve for Input Resistance: With the load resistance attached… (a) Apply a test input voltage and measure
the input current, Rin= vt/it or (b) Apply a test input current and measure the input voltage R measure the
input voltage, Rin = vt/it
7) Solve for Output Resistance: With all input voltage sources shorted and all input current sources opened…
(a) Apply a test voltage to the output and measure the output current, Rout = vt/it or (b) Apply a test current to
the output and measure the output voltage, Rout= vt/it
9
 Transistor Equivalent-Circuit Models
BJT Hybrid- π

NPN transistor

10
 Transistor Equivalent-Circuit Models
BJT T-model

NPN transistor

11
BJT Hybrid- π

The small-signal hybrid-π equivalent circuit for the PNP transistor with
the (a) transconductance and (b) current gain parameters.

12
 Transistor Equivalent-Circuit Models
MOSFET: NMOS
Hybrid- π

ig = 0

13
MOSFET: PMOS
Hybrid- π

Figure: Small-signal equivalent

circuit of PMOS transistor

Figure: Small-signal equivalent circuit of

common-source amplifier with PMOS
Figure: (a) Common-source circuit with PMOS transistor model
transistor and (b) corresponding ac equivalent circuit
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15
Basic Amplifier Configurations

16
 Transistor Amplifier Configurations (review)
Single-Stage Amplifiers “Terminal Gain and I/O Resistances of BJT Amplifiers”
Rsig vin vo Rsig vin Rsig vin
+
vo
vs RL vs + vs RC
RB RE RC RB Ri RL RB
vo _
_ Ri
Ri Ro Ro
Ro Ro
(a) CE (b) CC (c) CB
−  RC − g m RC RL RL Av = g m RL
Avo = Av = =
r + (  + 1) R E 1 + g m RE 1 re + RL
+ RL  1
 R  gm Rin = re = ;
(1 +  ) RE  C + ro  gm gm
Ri = r +  (1 +  )  r + (  + 1) R E
Ri = r + (  + 1) RL
ro + RC + RE r + Rth 1 Rth Ro = RC
Ro =  +
Ro = RC || Ro = RC || 1 + g m ( r || RE )  ro + ( r || RE ) 1+  gm  AI 1
Ro 1 + g m RE  ro AIo =  + 1
AIo = 

Without degeneration RE: For the gain, Ri, Ro of the whole amplifier, you need to include
Simply set RE = 0 voltage/current dividers at input and output stages
17
Transistor Amplifier Configurations (review)
Single-Stage Amplifiers “Terminal Gain and I/O Resistances of BJT Amplifiers”

(C-C) (C-B)
(C-E)

18
 Transistor Amplifier Configurations (review)
Single-Stage Amplifiers “Terminal Gain and I/O Resistances of FET Amplifiers”

C-S C-G
C-D
g m RL g m RL AV ,t = g m RL
Av ,t = − AV ,t =
1 + g m RS 1 + g m RL Ri 1
gm
Ri =  Ri = 
Ro =  ro (1 + g m RS ) 
Ro =  ro (1 + g m RE )  Ro = 1
gm AI ,t 1
AI ,t = 
RI ,t = 
Without degeneration RS:
Simply set RS = 0
For the gain, Ri, Ro of the whole amplifier, you need to include voltage/current
dividers at input and output stages 19
Transistor Amplifier Configurations (review)
Inverting Amplifiers: C-E and C-S Amplifier Review

20
 Transistor Amplifier Configurations (review)
Follower Circuits - CC & CD
amplifiers Summary

(C-C) (C-D)

21
 Transistor Amplifier Configurations (review)
C-B and C-G Amplifiers
Summary

(C-B) (C-G)

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 • A Common-Source (CS) Amplifier vo
Rsig vi
RD RL
Draw the small signal equivalent circuit vsig
RG1 RG2

VDD Ro
Rin
RD
RG1 CC2 vo

Rsig CC1 v
i
RL G D
vsig CS
Rsig vO
RG2 RS vsig
RG1 RG2 ro RD RL
(a) gmvgs
Rin

S Ro

23
• A CE Amplifier with an RE vO1
Rsig vo
vin
Q1
RL
vs R2
R1 RC

CC2
Rin Ro

CC1

CC3
Then, the -model small signal circuit :

24
 4.2 Introduction Multistage Amplifiers
Cascade & Cascode Amplifiers
A multistage amplifier in a cascade: the first stage's output is
connected to the second stage's input, and the second stage's output is
connected to the third stage's input, and so on. A cascade amplifier is
a two-port network with amplifiers connected in series, with each
amplifier transmitting its output to the second amplifier's input.
Fig. 1: example of cascade amplifier,
Fig. 2: example of cascode amplifier: which consists of 2 CE amplifiers
a CE stage followed by a CB stage
The cascode is a two-stage amplifier that consists of a common-emitter stage
feeding into a common-base stage.
In modern circuits, the cascode is often constructed from two transistors (BJTs or
FETs), with one operating as a CE or CS and the other as a CB or CG. The
cascode improves input–output isolation (reduces reverse transmission), as there
is no direct coupling from the output to input. This eliminates the Miller effect
and thus contributes to a much higher bandwidth.
25
4.2 Introduction Multistage Amplifiers
• Figure shows a three-stage amplifier connected in cascade.

The basic functions of coupling blocks:

1.To move AC voltage from one stage output to the next stage input.
2.To block DC voltage and pass AC voltage from one stage to another.

Input & output

resistances 26
 4.2 Introduction Multistage Amplifiers
Open Circuit Overall Voltage Gain
Fig.: Three-stage amplifier cascade
In the cascade amplifier,
the overall voltage gain
is the product of the
open-circuit voltage
gains of the individual
stages.

Inverting amplifier using an operational amplifier Closed-loop feedback amplifier two-port model 27
 4.2 Introduction Multistage Amplifiers
Open Circuit Overall Voltage Gain

Fig.: Two-port representation for three-stage cascaded amplifier

 RinB   RinC 
vo = AvAvi   AvB   AvC Output resistances are small (zero in the ideal case)
 RoutA + RinB   RoutB + RinC 
𝑣0
The open circuit overall gain expression: 𝐴𝑣 = = 𝐴𝑣𝐴 ⋅ 𝐴𝑣𝐵 ⋅ 𝐴𝑣𝐶
𝑣𝑖 28
 4.2 Introduction Multistage Amplifiers
Closed Circuit Overall Voltage Gain
vo
Atotal = = A1  A2  ...  An
vin

Rin
Overall voltage gain: Av = Atotal (in dB) = 20log10|Av|
Rs + Rin
Pout
Power gain in decibels = 10log10 Ap = 10log10
Pin

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RC-coupled transistor amplifier

30
• Example: RC-Coupled Transistor Amplifier with 3 stages

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32
➢AC Analysis

Fig.: ac equivalent circuit for ac analysis of the three-stage

All capacitors have been replaced by short circuits. For Q2 & Q3, the base bias resistors
have been replaced by 𝑅𝐵2 = 𝑅1 ∥ 𝑅2 & 𝑅𝐵3 = 𝑅3 ∥ 𝑅4
33
➢AC Analysis

Simplified ac circuit of the three-stage

amplifier with 3 sets of parallel resistors

Rin2

RL1
Fig.: Small-signal equivalent (hybrid- equivalent) circuit for the three-stage amplifier.
To simplify calculations, let skip all ro1, ro2, and ro3 34
Example: Cascade small signal amplifier circuit
Vo  Ri 
Av = = g m1 g m 2 ( RC1 || r 2 )( RC 2 || RL )  
Vs  i
R + Rs 

Ri = R1 || R2 || r 1
Rout = RC 2

All the remain works (DC & AC analysis) must be

solved in detail at home by your own!

Fig.: Small-signal equivalent circuit 35

Darlington pair ❖ AC analysis: small signal

The output current: Io = gm1Vπ1 + gm2Vπ2 = β1Ii + β2(1 + β1)Ii where gm2rπ2 = β2.
The overall current gain is then
𝐼𝑜
𝐴𝑖 = = 𝛽1 + 𝛽2 (1 + 𝛽1 ) ≅ 𝛽1 𝛽2 , note: 𝛽1 𝛽2 >> 𝛽1 + 𝛽2
𝐼𝑖

36
 Differential Amplifier

The basic BJT differential-pair configuration

• Basic Characteristics
– 2 matched transistors with emitters shorted together and connected to a current source.
– Devices must always be in active mode.
– Amplifies the difference between the two input voltages, but there is also a common
mode amplification in the non-ideal case.
37
 Differential Amplifier

BJT differential amplifiers MOS differential amplifiers

Ideal, the differential amplifier is symmetric. The differential amplifier behaves as either an inverting or
noninverting amplifier for differential input signals but tends to reject signals common to both inputs.

38
 Differential Amplifier The BJT Differential Pair
Differential-mode gain

Fig.: Differential amplifier with a differential Fig.: Small-signal model for differential-mode inputs. The output
mode input signal. resistances are neglected in the calculations
39
 Differential Amplifier The BJT Differential Pair
Differential-mode gain

• Summing currents at the emitter node:

vid vid
v3 = − ve & v4 = − − ve → v3 + v4 = −2ve
2 2
Hence 𝑣𝑒 (𝐺𝐸𝐸 + 2𝑔𝜋 + 2𝑔𝑚 ) = 0 which requires 𝑣𝑒 = 0
v3 = vid /2 & v4 = – vid /2

• For a purely DM input voltage, the voltage at the emitter node is identically zero ➔ emitter node (ve)
represents a virtual ground for DM input signal. So this node causes the differential amplifier to
behave as a common-emitter (or common-source) amplifier.
40
Differential Amplifier The BJT Differential Pair
Differential-mode gain
vod
The differential-mode gain Ad for a balanced output, vod = vc1 − vc2, is Ad = = − g m RC
vid vic = 0

If vc1 or vc2 is used as the output, referred to as a single-ended (or ground-referenced) output, then

v g R A vc 2 g m RC A
Ad1 = c1 =− m C = d or Ad2 = =+ =− d
vid vic = 0
2 2 vid vic = 0
2 2

The virtual ground @ the emitter node causes the amplifier to behave as a single-stage C-E
amplifier. (The same as for C-S amplifier in case of CMOS).

common-mode output voltages voc = 0 since vc2 = −vc1, and therefore Adc is indeed zero.

41
 The BJT Differential Pair
4.6 Differential Amplifier
Common-mode gain

Purely CM input signals are applied to the

differential amplifier. For this case, both
sides of the amplifier are completely
symmetrical.
Thus, the two base currents, the emitter
currents, the collector currents, and the two
collector voltages must be equal.

42
 4.6 Differential Amplifier The BJT Differential Pair
Common-mode gain
voc  o RC R
The CM output voltage 𝑣𝑜𝑐 : Ac = =− − C (Because β𝑜 >> 1)
vic vid = 0
r + 2 (  o + 1) REE 2 REE
I C RC VCC / 2 VCC VCC
Ac = −    where it is assumed that F = 0
2 I C REE 2 I E REE 2 (VEE − VBE ) 2VEE and ICRC = VCC / 2.

The differential output voltage vod is identically zero because the

voltages are equal at two collectors: vod = vc1 – vc2 = 0.
So, the CM conversion gain for a differential output is also zero:
vod
Acd = =0
vic vid = 0

 1 1 
If ro is included Ac RC  − 

 oor 2 REE 

43
4.6 Differential Amplifier The BJT Differential Pair
Common-mode gain

Common-mode rejection ratio (CMRR), characterizes the ability of an amplifier to amplify

the desired differential-mode input signal and reject the undesired common mode input signal.

𝐴𝑑𝑚 𝐴𝑑 Τ 2 1 1
CMRR = = = 𝑔𝑚 𝑅𝐶 × = 𝑔𝑚 𝑅𝐸𝐸
𝐴𝑐𝑚 𝐴𝐶 2 𝑅𝐶 Τ2𝑅𝐸𝐸

By writing gm in terms of the collector current IC

CMRR = 40ICREE = 20(2IEREE) = 20(VEE − VBE)  20VEE

44
Power Amplifiers
➢ Power amplifiers are large-signal amplifiers.

Power amplifiers designed to amplify analog signals come under A, B, AB or C

category
• Class A power amplifiers
• Class B power amplifiers
• Class AB push-pull amplifiers
• Class C power amplifiers

45
4.9 Power Amplifiers Classification of Output Stages
Class A
❖ Class A: the transistor conducts
Class B
for the entire cycle of the input
signal
❖ Class B: the transistor conducts
for only half the cycle
❖ Class AB: conduction cycle is
greater than 180º and less than
360º
Class AB Class C – Used for opamp output stage and
audio power amplifiers
❖ Class C: conduction cycle is less
than 180º
– Used for radio-frequency (RF) power
amplifications (mobile phones, radio
Collector or Drain current waveforms and TV)
of different output stages 46
Class A power amplifiers
• Operating in linear region.
• Q-Point is centered on the AC load line
2
𝑃𝐿 𝑉𝐿2 𝑉𝑖𝑛
• Power Gain: 𝐴𝑝 = where 𝑃𝐿 = and 𝑃𝑖𝑛 =
𝑅𝑖𝑛
𝑃𝑖𝑛 𝑅𝐿
𝑉𝐿2 𝑅𝑖𝑛 𝑅𝑖𝑛
𝑅𝑖𝑛 = 𝑅1 ∥ 𝑅2 ∥ 𝑟𝜋
𝐴𝑝 = 2 𝐴𝑝 = 𝐴2𝑣 Where
𝑉𝑖𝑛 𝑅𝐿 𝑅𝐿

• Output Power: C-E Amplifiers with a centered Q-Point

✓𝑷𝒐𝒖𝒕 𝒎𝒂𝒙 = 0.707 𝑉𝑐 𝑚𝑎𝑥 ∗ 0.707 𝐼𝑐 𝑚𝑎𝑥 = 𝟎. 𝟓 𝑰𝑪𝑸 𝑽𝑪𝑬𝑸
• DC power: 𝑃𝐷𝐶 = 𝐼𝐶𝐶 𝑉𝐶𝐶 = 2𝐼𝐶𝑄 𝑉𝐶𝐸𝑄 (Supply voltage is at least 2VCEQ)
𝑃𝑜𝑢𝑡 0.5𝐼𝐶𝑄 𝑉𝐶𝐸𝑄
• Maximum efficiency: max = = = 0.25 In practice, is
𝑃𝐷𝐶 2𝐼𝐶𝑄 𝑉𝐶𝐸𝑄 less about 10%
47
Class A
power
amplifiers

1st stage (Q1) is a voltage-divider biased 2nd stage: The voltage gain of the
common-emitter with a resistor (RE1). Darlington emitter-follower: Av2  1

Rc1 2.29 103

Av1 = − =− −27.93
RE1 + re(Q1) 68 + 14
Pout 122 mW
➔ Efficiency of the amplifier = = 0.04 Only 4% !
PDC 3W
48
Op Amp
Terminals of primary interest:
• inverting input
• noninverting input
• output
• positive power supply (+Vcc)
• negative power supply (-Vcc)

Offset null terminals may be used to

compensate for a degradation in
The circuit symbol for an op amp performance because of aging and
imperfections.

A simplified circuit symbol for an op amp 49

 (+) (+)
Differential and Common-mode Signals

• vid : the differential input voltage:

vid  vP − vN
• vicm : the common-mode input voltage:
vP + v N
vicm  (-) (-)
2

• Rid : the input differential resistance

• R0 : the output resistance

50
 5.2. Ideal Operational Amplifier (used in circuit analysis)

Key Specifications

✓ Infinite voltage gain

✓ Infinite input impedance (does not load the
driving sources)
✓ Zero output impedance (drive any load)
✓ Infinite bandwidth (flat magnitude response,
zero phase shift)
✓ Zero input offset voltage.
Fig. Equivalent circuit of the ideal op amp.

✓ The output voltage depends only on the voltage difference vid and is
independent to source and load resistance.
𝑣
𝑣𝑜 = 𝐴𝑣𝑖𝑑 → 𝐴 = 𝑜 A is called the open-loop gain
𝑣𝑖𝑑

1. Input voltage difference is zero: vid = 0 → vP = vN

2. Input currents are zero: i+ = i- = 0
51
Practical Op-Amp

Real op-amps differ from the ideal model in various respects. In addition to
finite gain, bandwidth, and input impedance, they have other limitations.

▪ Finite open loop gain.

▪ Finite input impedance.
▪ Non-zero output impedance.
▪ Input current.
▪ Input offset voltage.
▪ Temperature effects

52
 Terminal Voltages and Currents

Terminal voltage variables Terminal current variables

All voltages are considered All current reference directions

as voltages rises from the are into the terminal of the op-
common node. amp.

53
 Internal Circuit of 741 Type Op Amp
Schematic:

A component level diagram of the common 741 op-amp. Dotted lines outline: current mirrors
(red); differential amplifier (blue); class A gain stage (magenta); voltage level shifter (green);
output stage (cyan). 54
Input Signal modes
The input signal can be applied to an op-amp in differential-mode or in
common-mode.

55
Signal modes
The input signal can be applied to an op-amp in differential-mode or in
common-mode.
Common-mode signals are applied
to both sides with the same phase on
both.

Usually, common-mode signals are

from unwanted sources, and affect
both inputs in the same way. The
result is that they are essentially
cancelled at the output.

56
 Transfer Characteristic
The graph that relates the output voltage to the input voltage is called the voltage transfer
curve and is fundamental in designing and understanding amplifier circuits.

The terminal behavior of the op amp as

linear circuit element is characterized by
constraints on the input voltages and input
currents.

−VCC A ( v p − vn )  − VCC


v0 =  A ( v p − vn ) − VCC  A ( v p − vn )  +VCC

+VCC
 A ( v p − vn )  +VCC
Fig.: Voltage transfer characteristic:

When the magnitude of the input voltage difference (|vp – vn|) is small, the op amp behaves as a linear
device, as the output voltage is a linear function of the input voltages (the output voltage is equal to
the difference in its input voltages times the gain, A.
57
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Inverting Configuration

𝑣𝑜
Closed-loop gain: G = = ?
𝑣𝐼
𝑣𝑜 𝑣𝑜
Open-loop gain: A = → 𝑣2 − 𝑣1 = = 0 (because 𝐴 → ∞)
𝑣2 −𝑣1 𝐴
Due to 𝑉𝑃 = 0 (grounded) → 𝑉𝑁 = 𝑉𝑃 = 0: The N point is called the virtual ground

vI − v1 vI
i1 = =
R1 R1 vo R
G= =− 2
R2 v1 R1
vo = v1 − i1 R2 = − vI
R1
58
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Inverting Configuration

(A is finite)
𝑣𝑜
Case of A is finite → 𝑉𝑁 = −
𝐴
vI − (−vo / A) vI + vo / A
i1 = =
R1 R1 vo − R2 / R1 non-ideal
G= =
vo vI 1 + (1 + R2 / R1 ) / A gain
vo = − − i1 R2
A
(If 𝐴 → ∞ then 𝐺 = −𝑅2 Τ𝑅1 )
59
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Inverting Configuration

Input Resistance:
vI vI
Ri = = = R1
i1 vI / R1

Output Resistance:
𝑣𝑥
𝑅𝑜𝑢𝑡 =
𝑖𝑥
𝑣𝑥 = 𝑖2 𝑅2 + 𝑖1 𝑅1 = 𝑅1 + 𝑅2 𝑖1
𝑖1 = 0 → 𝑣𝑥 = 0

𝑅𝑜𝑢𝑡 = 0
60
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Inverting Configuration

closed-loop gain
G = -R2/R1

Figure: Analysis of the inverting configuration. The circled numbers

indicate the order of the analysis steps. 61
Example.

62
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Non-inverting Configuration

𝑉𝑁 = 𝑉𝑃 = 𝑣𝑖

G= (closed-loop gain)

63
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Non-inverting Configuration

𝑣𝑜
A is finite → 𝑉𝑁 = 𝑣𝐼 −
𝐴

𝑣𝑖 − 𝑣𝑜 Τ𝐴
𝑖1 =
𝑅1
𝑣𝑜 𝑣𝑜 𝑣𝑖 − 𝑣𝑜 Τ𝐴
𝑣𝑜 = 𝑣𝑖 − + 𝑖1 𝑅2 = 𝑣𝑖 − + 𝑅2
𝐴 𝐴 𝑅1

vO 1 + ( R2 / R1 )
G =
vI 1 + ( R2 / R1 )
1+
A

64
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Non-inverting Configuration

65
 5.3. Two Configurations for Feedback Circuit Ideal op-amp

Non-inverting Configuration

Consider the effect of the finite op-amp

open-loop gain A on the gain of the
noninverting configuration.

vO 1 + ( R2 / R1 )
G =
vI 1 + ( R2 / R1 )
1+
A Voltage follower

𝐺≅1
What happens if 𝑹𝟏 =
∞ and 𝑹𝟐 = 𝟎?

66
 6.4. Some Application Circuits

Summing Amplifier (weighted summer )

 weighted summer - is a closed-loop amplifier

configuration which provides an output voltage
which is weighted sum of the inputs.

v1 v2 vn
i1 = , i2 = , ..., in = i = i1 + i2 + ... + in
R1 R2 Rn
 Rf Rf Rf 
vO = 0 − iR f = −iR f vO = −  v1 + v2 + ... + vn  A weighted summer
 R1 R2 Rn 

Rf
If R1 = R2 = ….= Rn  R then v0 = − ( v1 + v2 + ... + vn )
R

67
 6.4. Some Application Circuits

Summing Amplifier

A weighted summer capable of implementing summing coefficients of both

signs (summing signals with opposite signs).

 Ra   Rc   Ra   Rc   Rc   Rc 
vO = v1     + v2     − v3   − v4  
 R1   Rb   R2   Rb   R3   R4 

68
 Difference Amplifiers

❑ difference amplifier – is a closed-loop configuration which responds to the

difference between two signals applied at its input and ideally rejects
signals that are common to the two.
➢ Ideally, the amp will amplify only the differential signal (vId) and reject
completely the common-mode input signal (vIcm). However, a practical
circuit will behave as below…

common-mode gain common-mode input

differential input

differential gain

vOut = Ad vId + Acm vIcm

69
 Difference Amplifiers

vO = Ad vId + Acm vIcm

Fig.: Representing the input signals to a differential amplifier in

terms of their differential and common-mode components.

 Common-mode rejection ratio (CMRR) – is the degree to which a differential amplifier

“rejects” the common-mode input.
Ad
CMRR = 20 log
Acm
✓ Ideally, CMRR = infinity…
70
A Single Op-Amp Difference Amplifiers

𝑣𝐼2 = 0 Inverting amplifier

R2
vO1 = − vI 1
R1

𝑣𝐼1 = 0 Non inverting amplifier

R4  R2  Combining the 2 configurations
vO 2 = vI 2 1 + 
R4 + R3  R1 

We have to make the 2 gain magnitudes equal in order to reject common-mode signals
R4  R2  R2 R4 R2
𝑣𝐼1 ≠ 0 and 𝑣𝐼2 ≠ 0 1 +  =  =
R4 + R3  R1  R1 R4 + R3 R2 + R1
R4 R2
select: = (**)
R3 R1
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 A Single Op-Amp Difference Amplifiers
To find vO in terms of vI1 and vI2: assume the circuit is linear → can use superposition principle.
Consider Fig. (a):
R2
vO1 = − vI 1
R1
Next, Fig. (b): as the noninverting circuit with
an additional voltage divider, made up of R3
and R4, connected to the input vI2 (where we
have utilized Eq. (**))
R4  R2  R2
vO 2 = vI 2 1 +  = vI 2
R4 + R3  R1  R1
R2 R
The superposition principle gives: vO = ( vI 2 − vI 1 )  2 vId
R1 R1
R2
Thus, as expected, the circuit acts as a difference amplifier with a differential gain Ad of Ad =
R1

72
A Single Op-Amp Difference Amplifiers
Common – mode input signal
1 R4 
i1 =  vIcm − vIcm 
R1  R4 + R3 
R4
v0 = vIcm − i2 R2
R4 + R3

R4  R2 R3 
v0 = vIcm 1 −  (note: 𝑖2 = 𝑖1 )
R4 + R3  R1 R4 

R4 R2
Let = 𝑣𝑜 = 0 → 𝐴𝑐𝑚 = 0 However, any mismatch in the resistance
R3 R1 ratios can make 𝑨𝒄𝒎 nonzero, and hence
CMRR is finite.

73
A Single Op-Amp Difference Amplifiers

Differential Input Resistance 𝑅𝑖𝑑

vid
Rid =
i1
vid = i1 R1 + 0 + i1 R1 = 2i1 R1
Rid = 2 R1

74
 Instrumentation Amplifier (Khuếch đại đo lường / khuếch đại đo đạc )

Due to the input resistance of the difference amplifier is too low, the instrumentation
amplifier should be used. It is a combination between 2 non-invert amplifiers and a difference
amplifier so that this scheme becomes a high-qualified amplifier.
stage #1 Stage 1:
𝑣𝑜1 = 𝑅2
stage #2 𝑣𝑜1 = (1 + )𝑣𝐼1
𝑅1
𝑅2
𝑣𝑜2 = (1 + )𝑣𝐼2
𝑅1

𝑣𝑜2 =
75
Instrumentation Amplifier
Stage 2:
𝑣𝑜1 = 𝑅2
′
𝑣𝐼1 = (1 + )𝑣𝐼1
𝑅1
′
𝑅2
𝑣𝐼2 = (1 + )𝑣𝐼2
𝑅1
′ ′ ′ ′
𝑣𝐼1 𝑣𝑖𝑑 = 𝑣𝐼2 − 𝑣𝐼1

′
𝑣𝐼2 ′ 𝑅2
𝑣𝑖𝑑 = 1+ 𝑣𝐼2 − 𝑣𝐼1
𝑅1
′ 𝑅2
𝑣𝑖𝑑 = 1+ 𝑣𝑖𝑑
𝑅1
𝑣𝑜2 =

𝑅4 ′ R4  R2  R4  R2  Acm = 0
𝑣𝑜 = 𝑣𝑖𝑑 v0 = 1 +  vId Ad = 1 + 
𝑅3 R3  R1  R3  R1 
76
Instrumentation Amplifier

 2R  R4 R4  R2  R4  R2 
vO 2 − vO1 = 1 + 2  vId vo = ( vO 2 − vO1 ) = 1 +  vId Ad = 1 + 
 2 R1  R3 R3  R1  R3  R1 

77
 Integrators

Miller or Inverting Integrator vI (t )

i1 (t ) =
R
t
1
vC (t ) = VC +  i1 (t )dt
C0

initial voltage on C

Output voltage vO (t ) = −vC (t )

t
1
vO (t ) = − 
CR 0
vI (t )dt − VC

78
 Differentiator

𝑑𝑣𝐼 (𝑡)
𝑖(𝑡) = 𝐶
𝑑𝑡
𝑣𝑜 (𝑡) = 0 − 𝑖(𝑡)𝑅
𝑑𝑣𝐼 (𝑡)
→ 𝑣𝑜 (𝑡) = −𝑅𝐶
𝑑𝑡
1
𝑧1 𝑠 = 𝑎𝑛𝑑 𝑧2 𝑠 = 𝑅
𝑠𝐶
𝑉𝑜 (𝑠) 𝑧2 (𝑠)
= = −𝑠𝐶𝑅 Frequency response
𝑉𝑖 (𝑠) 𝑧1 (𝑠)
with a time-constant CR
The transfer function (in s-domain):
V0 ( j )
= − jCR
Vi ( j )
V0
= CR
Vi
 = −90
79