1MS22LVS03(B TEJAVARDHAN) ARM ASSIGNMENT DATE 1/9/2023

UNIT 2

2) Mention the data conversion operations available in ARM Cortex M4 for signed and
unsigned extensions. (8)

Data conversion operations (extend and reverse ordering) In the Cortex®-M3

and Cortex-M4 processors

 a number of instructions are available for handling signed and unsigned

extensions of data

 for example, to convert an 8-bit value to 32-bit, or from 16-bit to 32-bit.

The signed and unsigned instructions are available in both 16-bit and 32-
bit forms .

 The 16-bit form of the instructions can only access low registers (RO to
R7).

 The 32-bit form of these instructions can access high registers, and
optionally rotate the input data before the signed extension operations

 These instructions are useful for converting between different data types.

 Some- times the signed extend or unsigned extend operation can be

taking place on the fly when loading data from memory (e.g.. LDRB for
unsigned data and LDRSB for signed data).

 Another group of data conversion operations is used for reversing data

bytes in a register.

 These instructions are usually used for converting data between little
endian and big endian. The 16-bit form of these instructions can only
access low registers (RO to R7).

 REV reverses the byte order in a data word, and REVH reverses the byte
order

 inside a half-word. For example, if RO is Ox12345678, in executing the

following:

REV R1, RO

REVH R2, RO

R1 will become 0x78563412, and R2 will be 0x34127856.

  REVSH is similar to REVH except that it only processes the lower half-
word and then sign extends the result. For example, if RO is 0x33448899,
running:

REVSH R1, RD

R1 will become 0xFFFF9988.

UNIT3

Discuss the low power features of ARM Cortex M4 (10 – 12) Or Discuss in detail the
operation of sleep mode in ARM Cortex M4

Low power features

1. Sleep modes

 Sleep modes are common features in most microcontroller designs.

 In the Cortex®-M processors, the processors support two sleep modes:

Sleep and Deep Sleep. These sleep modes can be further extended using
device-specific power management features, and in some cases the Deep
Sleep mode can be used with advanced chip design technologies such as
State Retention Power Gating (SRPG) to further reduce the power.

 What exactly happens during sleep modes depends on the chip design.

 In most cases some of the clock signals can be stopped to reduce the
power consumption However, the chip can also be designed such that
part of it shuts down to further reduce power.

 In some cases it is also possible to power down the whole chip

completely, and the only way to wake up the system from such power
down mode is via a system reset.

2. System control register (SCR)

 The Cortex-M processor provides a register called the System Control

Register (SCR) to allow you to select between the Sleep mode and Deep
Sleep mode.
 This register is at address On5000ED10, and can be accessed in C
programming using the "SCB->SCR symbol.
  Just like most other registers in the System Control Block (SCB), the SCR
can only be accessed in privileged state.

 The SLEEPDEEP bit (bit 2) can be set to enable the Deep Sleep mode.
 This register can also be used to control other lower power features like
Sleep-On-Exit and SEV-On- Pend.

3. Entering sleep modes

 The processor provides two instructions for entering sleep modes: WFI
and WFE
 Both WFI sleep and WFE sleep can be woken up by interrupt requests
(depending on the priority of the interrupt, current priority level, and
interrupt mask settings)

 WFE can be woken up by events. This includes a pulse from an event

input signal (called RXEV on the processor), and events that happened in
the past. Inside the processor, there is a single bit event register that can
indicate that an event had occurred previously

4. Wake-up conditions

 In most cases, interrupts (including NMI and SysTick timer interrupts)

can be used to wake up the Cortex-M3 or Cortex-M4 microcontrollers
from sleep modes.
 However, you also need to check the microcontroller's reference manual
carefully because some of the sleep modes might turn off clock signals to
the NVIC or peripherals, which would then prevent the interrupts (or
some of them) from waking up the processor.

 If the sleep mode is entered using WFI or Sleep-On-Exit, the interrupt

request needs to be enabled, and have a higher priority level than the
current level for the wake-up to occur.
 For example, if the processor enters sleep mode while running an
exception handler, or if the BASEPRI register was set before entering
sleep mode, then the priority of the incoming interrupt will need to be
higher than the current level to wake-up the processor,The PRIMASK
wake-up condition is a special feature to allow software code to be used
to restore certain system resources between waking up and execution of
ISR For example, a microcontroller could allow its clocking of Phase
Locked Loops (PLL) to be turned off during sleep mode to reduce power,
and restore it before executing the ISRs:

1. Before entering sleep mode, the PRIMASK is set, the clock source
switched to crystal clock, and then the PLL is turned off.
2. The microcontroller enters sleep mode with the PLL turned off to save
power
3. An interrupt request arrives, wakes up the microcontroller, and
resumes pro- gram execution from the point after the WFI instruction.
 4. The software code re-enables the PLL and then switches back to using
the PLL clock, then clears the PRIMASK and services the interrupt
request.

5 Sleep-on-Exit feature

 The Sleep-on-Exit feature is very useful for interrupt-driven applications

where all operations (apart from the initialization) are carried out inside
interrupt handlers.
 This is a programmable feature, and can be enabled or disabled using bit
1 of the System Control Register (SCR). When enabled, the Cortex-M
processor automatically enters sleep mode (with WFI behavior) when
exiting from an exception handler and returning to Thread mode (i.e.,
when no other excep- tion request is waiting to be processed).

6. Send event on pend (SEVONPEND)

 One of the programmable control bits in the System Control Register

(SCR) is the SEVONPEND.
 This feature is used with the WFE sleep operation. When this bit is set to
1, a new interrupt pending status set triggers an event and can wake up
the processor.
 The interrupt does not have to be enabled, but the pending status before
entering WFE needs to be 0 to trigger the wake-up event.

7. Sleep extension/wake-up delay

 On some microcontrollers, some of the low power sleep modes might

reduce power consumption aggressively by, for example, reducing the
voltage supply to SRAM and turning off the power to the flash memory.
 In some cases, these hardware circuits might take a bit longer to get ready
to run again after an interrupt request arrives. The Cortex-M3 and Cortex-
M4 processors provide a set of handshaking signals to allow the waking
up to be delayed so that the rest of the system can get ready. This feature
is only visible to silicon designers and is completely transparent to
software. However, the microcontroller users might observe a longer
interrupt latency when this feature is used.

8. Wake-up interrupt controller (WIC)

 During Deep Sleep, when all the clock signals to the processor are
stopped, the NVIC cannot detect incoming interrupt requests. In order to
allow the microcontroller to be woken up by interrupt requests even
when clock signals are unavailable, a feature called the Wake-up Interrupt
Controller (WIC) was introduced in the Cortex- M3 revision 12p0.

 The WIC is a small, optional interrupt detection circuit that is coupled

with the NVIC in the Cortex-M processor via a special interface, and also
 linked to the device-specific power control system such as a Power
Management Unit (PMU) (Figure 9.6). The WIC does not contain any
programmable registers, and the interrupt masking information is
transferred from the NVIC to the WIC just before entering Deep Sleep
mode.

9. Event communication interface

 We mention that the WFE instruction can be woken up by an input signal

on the Cortex-M processor called RXEV (Receive Event). This signal is part
of the event communication interface feature. The processor also has an
output signal called TXEV (Transmit Event). The TXEV outputs a single
cycle pulse when executing the SEV (Send Event) instruction.
 The primary goal of the event communication interface is to allow the
processor to stay in sleep mode until a certain event has occurred. The
event communication interface can be used in a number of ways. For
example, it can:

 Allow event communication between a peripheral and the processor

Allow event communication between multiple processors
 Event communication is also important in multi-processor designs. For
example, if processor A is waiting for processor B to finish a task by
polling a variable in a shared memory space, then processor A might need
to wait for a long time and this wastes energy .

 In order to reduce power, we connect the event communication interface

of the two Cortex-M processors together . The connection arrange- ment
can be extended to support more processors.
 With this arrangement, we can use the SEV instruction to send an event
to another processor to wake up the other processor from WFE sleep. As a
result, the polling loop can be changed to include the sleep operation
Again, the polling loop is still required because the processor can be
woken by
 Another use for the event communication interface can be semaphores
and MUTEX (mutual exclusive, which is one type of semaphore
operation). For example, in semaphore operations which do not use the
event communication feature, a processor might have to use a polling
loop to detect when a locking var- able is free, which can waste a lot of
power:

UNIT4

Elaborate the four types of fault handlers that are available in ARM Cortex M4. (8-10)

Enabling fault handlers

 By default the configurable fault exceptions are disabled. You can enable
these exceptions by writing to System Handler Control and State Register
 (SCB->SHCSR). Be careful not to change the current status of system
exception active status, since this can cause a fault exception.

1. MemManage fault

You can enable the MemManage Fault exception handler using:

SCB→SHCSR |= SCB_SHCSR MEMFAULTENA Msk: //Set bit 16

The default name for MemManage Fault exception handler (as defined in CMSIS-
Core) is:

void MemManage_ Handler(void):

You can set up the priority of the MemManage Fault using:

NVIC_SetPriority (MemoryManagement IRQn, priority):

2 Bus fault

You can enable the Bus Fault exception handler using:

SCB→SHCSR |= SCB_SHCSR BUSFAULTENA MsK: //Set bit 17

The default name for the Bus Fault exception handler (as defined in

CMSIS-Core) is:

void BusFault_Handler(void);

You can set up the priority of the Bus Fault using:

NVIC_SetPriority(Bus Fault_IRQn. priority):

3 Usage fault

You can enable the Usage Fault exception handler using:

SCB->SHCSR |= SCB SHCSR USGFAULTENA_Msk: //Set bit 18

The default name for the Usage Fault exception handler (as defined in CMSIS-
Core) is:

vold UsageFault_Handler(void):

You can set up the priority of the Usage Fault using:

NVIC_SetPriority (Usage fault IRQn, priority):

4 HardFault

There is no need to enable the HardFault handler. This is always enabled and has
a fixed exception priority of -1. The default name for the Hard Fault exception
handler (as defined in CMSIS-Core) is:

void HardFault_Handler(void):