Digital(AKU) U:4

Principles of Logic Circuits II:

Sequential Circuits: The sequential circuit is a special type of circuit that has a series
of inputs and outputs. The outputs of the sequential circuits depend on both the
combination of present inputs and previous outputs. The previous output is treated as
the present state. So, the sequential circuit contains the combinational circuit and its
memory storage elements

Block diagram

Types of Sequential Circuits – There are two types of sequential circuit :

1. Asynchronous sequential circuit – These circuit do not use a clock signal but uses
the pulses of the inputs. These circuits are faster than synchronous sequential circuits.
Asynchronous circuits that can change the state immediately when enabled.
Asynchronous (fundamental mode) sequential circuit: The behavior is dependent on
the arrangement of the input signal that changes continuously over time, and the
output can be a change at any time (clockless).
We use asynchronous sequential circuits when speed of operation is important
and independent of internal clock pulse. The asynchronous sequential circuit is
similar to the combinational circuits with feedback.

But these circuits are more difficult to design and their output is uncertain.
2. Synchronous sequential circuit – These circuit uses clock signal and level inputs (or
pulsed) (with restrictions on pulse width and circuit propagation). The output pulse is
the same duration as the clock pulse for the clocked sequential circuits. Since they wait
 for the next clock pulse to arrive to perform the next operation, so these circuits are
bit slower compared to asynchronous. Level output changes state at the start of an input
pulse and remains in that until the next input or clock pulse.

We use synchronous sequential circuit in synchronous counters, flip flops.

Design Procedure of Sequential Logic Circuits

This procedure involves the following steps
1. First, derive the state diagram
2. Take as the state table or an equivalence representation, such as a state
diagram.
3. The number of states may be reduced by the state reduction technique
4. Verify the number of flip-flops needed
5. Choose the type of flip-flops to be used
6. Derive excitation equations
7. Using the map or some other simplification method, derive the output
function and the flip-flop input functions.
8. Draw a logic diagram or a list of Boolean functions from which a logic
diagram can be obtained.
.
Clock Signal and Triggering
Clock signal
A clock signal is a periodic signal in which ON time and OFF time need not be the same.
When ON time and OFF time of the clock signal are the same, a square wave is used to
represent the clock signal. Below is a diagram which represents the clock signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at logic,
either high 5V or low 0V, to an equal amount of time. It repeats with a certain time
period, which will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering
These are two types of triggering in sequential circuits:

Level triggering
The logic High and logic Low are the two levels in the clock signal. In level triggering,
when the clock pulse is at a particular level, only then the circuit is activated. There are
the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of positive level
triggering:
Negative level triggering
In negative level triggering, the signal with Logic Low occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of Negative level
triggering:

Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition either
from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge
triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive edge
triggering. So, in positive edge triggering, the circuit is operated with such type of clock
signal. The diagram of positive edge triggering is given below.

Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative edge
triggering. So, in negative edge triggering, the circuit is operated with such type of clock
signal. The diagram of negative edge triggering is given below.
Flip-Flops
A flip flop is an electronic circuit with two stable states that can be used to
store binary data. The stored data can be changed by applying varying
inputs.A
flip-flop is a circuit that maintains a state until directed by input to change the
state.
Flip flop is formed using logic gates, which are in turn made of transistors.
Flip flop are basic building blocks in the memory of electronic devices.
Each flip flop can store one bit of data.

These are also called as sequential logic circuits.

Flip – flops have two stable states and hence they are bistable
multivibrators. The two stable states are High (logic 1) and Low (logic 0).

The term flip – flop is used as they can switch between the states under
the influence of a control signal (clock or enable) i.e. they can ‘flip’ to one
state and ‘flop’ back to other state.

 Flip – flops are a binary storage device because they can store binary
data (0 or 1).
 Flip – flops are edge sensitive or edge triggered devices i.e. they are
sensitive to the transition rather than the duration or width of the
clock signal.
 They are also known as signal change sensitive devices which mean
that the change in the level of clock signal will bring change in
output of the flip flop.
 A Flip – flop works depending on clock pulses.
 Flip flops are also used to control the digital circuit’s
functionality. They can change the operation of a digital circuit
depending on the state.
Some of the most common flip – flops are SR Flip – flop (Set – Reset), D Flip
– flop (Data or Delay), JK Flip – flop and T Flip – flop.
Latches vs Flip-Flops
Latches and flip – flops are both 1 – bit binary data storage devices. The
main difference between a latch and a flip – flop is the triggering
mechanism. Latches are transparent when enabled ,whereas flip – flops
are dependent on the transition of the clock signal i.e. either positive edge
or negative edge.

The modern usage of the term flip – flop is reserved to clocked devices
and term latch is to describe much simpler devices. Some of the other
differences between latches and flip – flops are listed in below table.

Basic Flip-Flops
The Set-Reset SR Flip-flop
The most basic of all the bistable latches and bistable multivibrators is the
set-rest (SR) flip-flop. The basic SR flip-flop is an important bistable circuit
because all the other types of flip-flop are built from it. The SR flip-flop is
constructed using two cross-coupled digital NAND gates such as the TTL
74LS00, or two cross-coupled digital NOR gates such as the TTL 74LS02.
Generally SR bistables and flip-flops are said to be transparent because
their outputs change or respond immediately to changes in their inputs.
Also since they consist of digital logic gates along with feedback, SR flip-
flops are regarded as asynchronous sequential logic circuits.
The basic SR flip-flop has two inputs S (set) and R (reset) and two
outputs Q and Q’ with one of these outputs being the complement of the
other. Then the SR flip-flop is a two-input, two-output device. Consider the
circuits below.

Basic NAND and NOR SR Flip-flops

Above are the two basic configurations for the asynchronous SR bistable
flip-flop using either a negative input NAND gate, or a positive
input NOR gate. For the SR bistable latch using two cross-
coupled NAND gates operates with both inputs normally HIGH at logic level
“1”.
The application of a LOW at logic level “0” to the S input with R held HIGH
causes output Q to go HIGH, setting the latch. Likewise, a logic level “0” on
the R input with input S held HIGH causes the Q output to go LOW,
resetting the latch. For the SR NAND gate latch, the condition
of S = R = 0 is forbidden.
For the conversion of flip-flops using two cross-coupled NOR gates, when
the output Q = 1 and Q = 0, the bistable latch is said to be in the Set state.
When Q = 0 and Q’ = 1, the NOR gate latch is said to be in its Reset state.
Then we can see that the operation of the NOR and NAND gate flip-flops
are basically just the complements of each other.
The implementation of an SR flip-flop using two cross-coupled NAND gates
requires LOW inputs. However, we can convert the operation of
a NAND SR flip-flop to operate in the same manner as the NOR gate
implementation with active HIGH (positive logic) inputs by using inverters,
(NOT Gates) within the basic bistable design.

 S-R Flip Flop using NOR Gate

The design of such a flip flop includes two inputs, called the SET [S] and RESET
[R]. There are also two outputs, Q and Q’. The diagram and truth table is
shown below.

S-R Flip Flop using NOR Gate

From the diagram it is evident that the flip flop has mainly four states. They
are
S=1, R=0—Q=1, Q’=0
This state is also called the SET state.

S=0, R=1—Q=0, Q’=1

This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each
other and that the value of Q follows the value of S.

S=0, R=0—Q & Q’ = Remember

If both the values of S and R are switched to 0, then the circuit remembers the
value of S and R in their previous state.

S=1, R=1—Q=0, Q’=0 [Invalid]

This is an invalid state because the values of both Q and Q’ are 0. They are
supposed to be compliments of each other. Normally, this state must be
avoided.

 S-R Flip Flop using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown
below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

S=1, R=0—Q=0, Q’=1

This state is also called the SET state.

S=0, R=1—Q=1, Q’=0

This state is known as the RESET state.

In both the states you can see that the outputs are just compliments of each
other and that the value of Q follows the compliment value of S.
S=0, R=0—Q=1, & Q’ =1 [Invalid]
If both the values of S and R are switched to 0 it is an invalid state because the
values of both Q and Q’ are 1. They are supposed to be compliments of each
other. Normally, this state must be avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the
value of S and R in their previous state.

Types of Flip-Flops

 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

SR Flip-Flop
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, SR latch operates with enable signal. The circuit diagram of SR flip-flop
is shown in the following figure.

This circuit has two inputs S & R and two outputs Q t & Qt’. The operation of SR
flipflop is similar to SR Latch. But, this flip-flop affects the outputs only when positive
transition of the clock signal is applied instead of active enable.
The following table shows the state table of SR flip-flop.
 S R Qt+1

0 0 Qt

0 1 0

1 0 1

1 1 -

Here, Qt & Qt+1 are present state & next state respectively. So, SR flip-flop can be
used for one of these three functions such as Hold, Reset & Set based on the input
conditions, when positive transition of clock signal is applied. The following table
shows the characteristic table of SR flip-flop.
Present Inputs Present State Next State

S R Qt Qt+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 x

1 1 1 x

By using three variable K-Map, we can get the simplified expression for next state,
Qt+1. The three variable K-Map for next state, Qt+1 is shown in the following
figure.
The maximum possible groupings of adjacent ones are already shown in the figure.
Therefore, the simplified expression for next state Qt+1t+1 is
Q(t+1)=S+R′Q(t)
D Flip-Flop
D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas, D latch operates with enable signal. That means, the output of D flip-flop
is insensitive to the changes in the input, D except for active transition of the clock
signal. The circuit diagram of D flip-flop is shown in the following figure.

This circuit has single input D and two outputs Q t & Qt’. The operation of D flip-flop
is similar to D Latch. But, this flip-flop affects the outputs only when positive
transition of the clock signal is applied instead of active enable.
The following table shows the state table of D flip-flop.

D Qt + 1

0 0
 1 1

Therefore, D flip-flop always Hold the information, which is available on data input,
D of earlier positive transition of clock signal. From the above state table, we can
directly write the next state equation as
Qt+1=D
Next state of D flip-flop is always equal to data input, D for every positive transition
of the clock signal. Hence, D flip-flops can be used in registers, shift registers and
some of the counters.

JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions. The circuit diagram of JK flip-flop is shown
in the following figure.

This circuit has two inputs J & K and two outputs Q tt & Qtt’. The operation of JK flip-
flop is similar to SR flip-flop. Here, we considered the inputs of SR flip-flop as S = J
Qt’ and R = KQt in order to utilize the modified SR flip-flop for 4 combinations of
inputs.
The following table shows the state table of JK flip-flop.

J K Qt+1

0 0 Qt
 0 1 0

1 0 1

1 1 Qt'

Here, Qt & Qt+1 are present state & next state respectively. So, JK flip-flop can be
used for one of these four functions such as Hold, Reset, Set & Complement of
present state based on the input conditions, when positive transition of clock signal
is applied. The following table shows the characteristic table of JK flip-flop.
Present Inputs Present State Next State

J K Qt Qt+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

By using three variable K-Map, we can get the simplified expression for next state,
Qt+1. Three variable K-Map for next state, Qt+1 is shown in the following figure.
The maximum possible groupings of adjacent ones are already shown in the figure.
Therefore, the simplified expression for next state Qt+1 is
Q(t+1)=JQ(t)′+K′Q(t)

T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the
same input ‘T’ to both inputs of JK flip-flop. It operates with only positive clock
transitions or negative clock transitions. The circuit diagram of T flip-flop is shown
in the following figure.

This circuit has single input T and two outputs Q t & Qt’. The operation of T flip-flop
is same as that of JK flip-flop. Here, we considered the inputs of JK flip-flop as J =
T and K = T in order to utilize the modified JK flip-flop for 2 combinations of inputs.
So, we eliminated the other two combinations of J & K, for which those two values
are complement to each other in T flip-flop.
The following table shows the state table of T flip-flop.

D Qt+1
 0 Qt

1 Qt’

Here, Qt & Qt+1 are present state & next state respectively. So, T flip-flop can be
used for one of these two functions such as Hold, & Complement of present state
based on the input conditions, when positive transition of clock signal is applied.
The following table shows the characteristic table of T flip-flop.
Inputs Present State Next State

T Qt Qt+1

0 0 0

0 1 1

1 0 1

1 1 0

From the above characteristic table, we can directly write the next state
equation as
Q(t+1)=T′Q(t)+TQ(t)′
⇒Q(t+1)=T⊕Q(t).
The output of T flip-flop always toggles for every positive transition of the clock
signal, when input T remains at logic High 1. Hence, T flip-flop can be used
in counters.

Here we implemented various flip-flops by providing the cross coupling between

NOR gates. Similarly, you can implement these flip-flops by using NAND gates.

Design of Sequential Circuits

The design of a synchronous sequential circuit starts from a set of
specifications and culminates in a logic diagram or a list of Boolean
functions from which a logic diagram can be obtained. In contrast to a
combinational logic, which is fully specified by a truth table, a sequential
circuit requires a state table for its specification. The first step in the design
of sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram.

A synchronous sequential circuit is made up of flip-flops and combinational

gates. The design of the circuit consists of choosing the flip-flops and then
finding the combinational structure which, together with the flip-flops,
produces a circuit that fulfils the required specifications. The number of flip-
flops is determined from the number of states needed in the circuit.

The recommended steps for the design of sequential circuits are set out
below.
 Digital Registers

N flip flops are to be connected in an order to store n bits of data.

A Register is a device which is used to store such information. It is a group
of flip flops connected in series used to store multiple bits of data.

Register memory is the smallest and fastest memory in a computer. It is not a part
of the main memory and is located in the CPU in the form of registers, which are the
smallest data holding elements. A register temporarily holds frequently used data,
instructions, and memory address that are to be used by CPU. They hold instructions
that are currently processed by the CPU. All data is required to pass through
registers before it can be processed. So, they are used by CPU to process the data
entered by the users.

Registers hold a small amount of data around 32 bits to 64 bits. The speed of a CPU
depends on the number and size (no. of bits) of registers that are built into the CPU.
Registers can be of different types based on their uses. Some of the widely used
Registers include Accumulator or AC, Data Register or DR, the Address Register or
AR, Program Counter (PC), I/O Address Register, and more.

Types and Functions of Computer Registers:

o Data Register: It is a 16-bit register, which is used to store operands
(variables) to be operated by the processor. It temporarily stores data, which
is being transmitted to or received from a peripheral device.
o Program Counter (PC): It holds the address of the memory location of the
next instruction, which is to be fetched after the current instruction is
completed. So, it is used to maintain the path of execution of the different
programs and thus executes the programs one by one, when the previous
instruction gets completed.

o Instructor Register: It is a 16-bit register. It stores the instruction which is

fetched from the main memory. So, it is used to hold instruction codes, which
are to be executed. The Control Unit takes instruction from Instructor
Register, then decodes and executes it.

o Accumulator Register: It is a 16-bit register, which is used to store the

results produced by the system. For example, the results generated by CPU
after the processing are stored in the AC register.
o Address Register: It is a 12-bit register that stores the address of a
memory location where instructions or data is stored in the memory.
o I/O Address Register: Its job is to specify the address of a particular I/O
device.
o I/O Buffer Register: Its job is to exchange the data between an I/O module
and the CPU.

Register Symbol Number of bits Function

Data register DR 16 Holds mem

 Address register AR 12 Holds addre

Accumulator AC 16 Processor r

Instruction register IR 16 Holds instru

Program counter PC 12 Holds addre

Temporary register TR 16 Holds temp

Input register INPR 8 Carries inpu

Output register OUTR 8 Carries outp

The following image shows the register and memory configuration for a basic
computer.

o The Memory unit has a capacity of 4096 words, and each word contains 16
bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the
memory location.
 o The Memory Address Register (MAR) contains 12 bits which hold the address
for the memory location.

o The Program Counter (PC) also contains 12 bits which hold the address of the
next instruction to be read from memory after the current instruction is
executed.
o The Accumulator (AC) register is a general purpose processing register.

o The instruction read from memory is placed in the Instruction register (IR).

o The Temporary Register (TR) is used for holding the temporary data during
the processing.
o The Input Registers (IR) holds the input characters given by the user.

o The Output Registers (OR) holds the output after processing the input data.

Difference between Register and Memory :

S.NO. Register Memory

Registers hold the operands or Memory holds the instructions and

instruction that CPU is currently the data that the currently executing
1. processing. program in CPU requires.

Register holds the small amount of Memory of the computer can range
2. data around 32-bits to 64-bits. from some GB to TB.

CPU can operate on register

contents at the rate of more than one CPU accesses memory at the slower
3. operation in one clock cycle. rate than register.

Types are Accumulator register,

Program counter, Instruction
4. register, Address register, etc. Type of memory are RAM,etc.

5. Registers can be control i.e. you can Memory is almost not controllable.
store and retrieve information from
 S.NO. Register Memory

them.

6. Registers are faster than memory. RAM is much slower than registers.

Shift Registers
Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in such
registers can be made to move within the registers and in/out of the registers by applying clock
pulses. An n-bit shift register can be formed by connecting n flip-flops where each flip flop
stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register
Serial In − Serial Out SISO Shift Register
The shift register, which allows serial input and produces serial output is known as
Serial In – Serial Out SISO shift register. The block diagram of 3-bit SISO shift
register is shown in the following figure.

This block diagram consists of three D flip-flops, which are cascaded. That means,
output of one D flip-flop is connected as the input of next D flip-flop. All these flip-
flops are synchronous with each other since, the same clock signal is applied to
each one.
In this shift register, we can send the bits serially from the input of left most D flip-
flop. Hence, this input is also called as serial input. For every positive edge
triggering of clock signal, the data shifts from one stage to the next. So, we can
receive the bits serially from the output of right most D flip-flop. Hence, this output is
also called as serial output.
Example
Let us see the working of 3-bit SISO shift register by sending the binary
information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000.
We can understand the working of 3-bit SISO shift register from the following
table.
No of positive edge of Clock Serial Input Q2 Q1 Q0

0 - 0 0 0

1 1LSB 1 0 0

2 1 1 1 0

3 0MSB 0 1 1LSB

4 - - 0 1

5 - - - 0MSB

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000.
Here, the serial output is coming from Q0. So, the LSB 1 is received at 3rd positive
edge of clock and the MSB 0 is received at 5th positive edge of clock.
Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce
the valid output. Similarly, the N-bit SISO shift register requires 2N-1 clock pulses
in order to shift ‘N’ bit information.

Serial In - Parallel Out SIPO Shift Register

The shift register, which allows serial input and produces parallel output is known as
Serial In – Parallel Out SIPO shift register. The block diagram of 3-bit SIPO shift
register is shown in the following figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of
one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are
synchronous with each other since, the same clock signal is applied to each one.
In this shift register, we can send the bits serially from the input of left most D flip-
flop. Hence, this input is also called as serial input. For every positive edge
triggering of clock signal, the data shifts from one stage to the next. In this case, we
can access the outputs of each D flip-flop in parallel. So, we will get parallel
outputs from this shift register.
Example
Let us see the working of 3-bit SIPO shift register by sending the binary
information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000.
Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-
bit SIPO shift register from the following table.
No of positive edge of Clock Serial Input Q2MSBMSB Q1 Q0LSBLSB

0 - 0 0 0

1 1LSB 1 0 0

2 1 1 1 0

3 0MSB 0 1 1

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000.
The binary information “011” is obtained in parallel at the outputs of D flip-flops for
third positive edge of clock.
So, the 3-bit SIPO shift register requires three clock pulses in order to produce the
valid output. Similarly, the N-bit SIPO shift register requires N clock pulses in
order to shift ‘N’ bit information.
Parallel In − Serial Out PISO Shift Register
The shift register, which allows parallel input and produces serial output is known as
Parallel In − Serial Out PISO shift register. The block diagram of 3-bit PISO shift
register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of
one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are
synchronous with each other since, the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making
Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts
from one stage to the next. So, we will get the serial output from the right most D
flip-flop.
Example
Let us see the working of 3-bit PISO shift register by applying the binary
information “011” in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of
the D flip-flops from leftmost to rightmost will be Q2Q1Q0=011. We can understand
the working of 3-bit PISO shift register from the following table.
working of 3-bit PISO shift register from the following table.
 No of positive edge of Clock Q2 Q1 Q0

0 0 1 1LSB

1 - 0 1

2 - - 0LSB

Here, the serial output is coming from Q0. So, the LSB 1 is received before applying
positive edge of clock and the MSB 0 is received at 2nd positive edge of clock.
Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce
the valid output. Similarly, the N-bit PISO shift register requires N-1 clock pulses in
order to shift ‘N’ bit information.

Parallel In - Parallel Out PIPO Shift Register

The shift register, which allows parallel input and produces parallel output is known
as Parallel In − Parallel Out PIPO shift register. The block diagram of 3-bit PIPO
shift register is shown in the following figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of
one D flip-flop is connected as the input of next D flip-flop. All these flip-flops are
synchronous with each other since, the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making
Preset Enable to 1. We can apply the parallel inputs through preset or clear. These
two are asynchronous inputs. That means, the flip-flops produce the corresponding
outputs, based on the values of asynchronous inputs. In this case, the effect of
outputs is independent of clock transition. So, we will get the parallel outputs from
each D flip-flop.
Example
Let us see the working of 3-bit PIPO shift register by applying the binary
information “011” in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of
the D flip-flops from leftmost to rightmost will be Q2Q1Q0=011. So, the binary
information “011” is obtained in parallel at the outputs of D flip-flops before applying
positive edge of clock.
Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to
produce the valid output. Similarly, the N-bit PIPO shift register doesn’t require
any clock pulse in order to shift ‘N’ bit information.

Ring Counters(Shift Registers)

If the output of a shift register is fed back to the input. a ring counter
results. The data pattern contained within the shift register will recirculate
as long as clock pulses are applied.

For example, the data pattern will repeat every four clock pulses in the
figure below. However, we must load a data pattern.

All 0‘s or all 1‘s doesn’t count. Is a continuous logic level from such a
condition useful?

We make provisions for loading data into the parallel-in/ serial-out shift
register configured as a ring counter below.

Any random pattern may be loaded. The most generally useful pattern is a
single 1.
Loading binary 1000 into the ring counter, above, prior to shifting yields a
viewable pattern.
The data pattern for a single stage repeats every four clock pulses in our 4-
stage example.
The waveforms for all four stages look the same, except for the one clock
time delay from one stage to the next. See figure below.

The circuit above is a divide by 4 counter. Comparing the clock input to any
one of the outputs, shows a frequency ratio of 4:1.

Q: How may stages would we need for a divide by 10 ring counter?

A: Ten stages would recirculate the 1 every 10 clock pulses.

Johnson Counters
The switch-tail ring counter, also know as the Johnson counter, overcomes
some of the limitations of the ring counter.

Like a ring counter a Johnson counter is a shift register fed back on its’ self.
It requires half the stages of a comparable ring counter for a given division
ratio.
If the complement output of a ring counter is fed back to the input instead
of the true output, a Johnson counter results.
The difference between a ring counter and a Johnson counter is which
output of the last stage is fed back (Q or Q’).
Carefully compare the feedback connection below to the previous ring
counter.
This “reversed” feedback connection has a profound effect upon the
behavior of the otherwise similar circuits.

Recirculating a single 1 around a ring counter divides the input clock by a

factor equal to the number of stages.

Whereas, a Johnson counter divides by a factor equal to twice the number

of stages.

For example, a 4-stage ring counter divides by 4. A 4-stage Johnson

counter divides by 8.

Start a Johnson counter by clearing all stages to 0s before the first clock.
This is often done at power-up time.

Referring to the figure below, the first clock shifts three 0s from ( QA QB QC)
to the right into ( QB QC QD). The 1 at QD’ (the complement of Q) is shifted
back into QA.

Thus, we start shifting 1s to the right, replacing the 0s. Where a ring
counter recirculated a single 1, the 4-stage Johnson counter recirculates
four 0s then four 1s for an 8-bit pattern, then repeats.
The above waveforms illustrates that multi-phase square waves are
generated by a Johnson counter.
The 4-stage unit above generates four overlapping phases of 50% duty
cycle. How many stages would be required to generate a set of three phase
waveforms?

For example, a three stage Johnson counter, driven by a 360 Hertz clock
would generate three 120 o phased square waves at 60 Hertz.

The outputs of the flop-flops in a Johnson counter are easy to decode to a

single state.

Application Of Shift Registers

Follwing are the applications of shift registers.
 Shift register is used as Parallel to serial converter, which converts the
parallel data into serial data. It is utilized at the transmitter section after
Analog to Digital Converter ADC block.
 Shift register is used as Serial to parallel converter, which converts the
serial data into parallel data. It is utilized at the receiver section before Digital
to Analog Converter DAC block.
 Shift register along with some additional gate ss generate the sequence of
zeros and ones. Hence, it is used as sequence generator.
 Shift registers are also used as counters. There are two types of counters
based on the type of output from right most D flip-flop is connected to the
serial input. Those are Ring counter and Johnson Ring counter.

Counters
 According to Wikipedia, in digital logic and computing, a Counter is a
device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a
clock signal. Counters are used in digital electronics for counting
purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising
edge of clock. Not only counting, a counter can follow the certain
sequence based on our design like any random sequence
0,1,3,2… .They can also be designed with the help of flip flops.
Counters are formed by connecting flip-flops together and any number of
flip-flops can be connected or “cascaded” together to form a “divide-by-n”
binary counter where “n” is the number of counter stages used and which is
called the Modulus. The modulus or simply “MOD” of a counter is the
number of output states the counter goes through before returning itself
back to zero, i.e, one complete cycle.
Then a counter with three flip-flops like will count from 0 to 7 ie, 2n-1. It has
eight different output states representing the decimal numbers 0 to 7 and is
called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will
count from 0 to 15 and is therefore called a Modulo-16 counter and so on.
An example of this is given as.
 3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)
 4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
 8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)
 and so on..
The Modulo number can be increased by adding more flip-flops to the
counter and cascading is a method of achieving higher modulus counters.
Then the modulo or MOD number can simply be written as: MOD number =
2n
Counter Classification
Counters are broadly divided into two categories
1. Asynchronous counter(Ripple Counter)
2. Synchronous counter
2-bit ripple up counter

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-
flop are being used. But we can use the JK flip-flop also with J and K connected
permanently to logic 1. External clock is applied to the clock input of flip-flop A and
QA output is applied to the clock input of the next flip-flop i.e. FF-B.
Logical Diagram

Truth Table

Signal Diagram
Operation
1. Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip flop will change
from 0 to 1. The output of this flip flop will be taken by the clock input of the next flip
flop. This output will be taken as a positive edge clock by the second flip flop. This
input will not change the second flip flop's output state because it is the negative
edge triggered flip flop.
So, QA = 1 and QB = 0
3. Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 0 and QB = 1.
4. Condition 4: When the third negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 0 to 1. This output will be taken as a positive edge clock by the second
flip flop. This input will not change the second flip flop's output state because it is the
negative edge triggered flip flop.
So, QA = 1 and QB = 1
5. Condition 5: When the fourth negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop will
change from 1 to 0. This output will be taken as a negative edge clock by the second
flip flop. This input will change the output state of the second flip flop.
So, QA = 0 and QB = 0

A 3-bit Ripple counter using JK flip-flop –

In the circuit shown in above figure, Q0(LSB) will toggle for every clock pulse
because JK flip-flop works in toggle mode when both J and K are applied 1,
1 or high input. The following counter will toggle when the previous one
changes from 1 to 0
Truth Table –

The 3-bit ripple counter used in the circuit above has eight different states,
each one of which represents a count value. Similarly, a counter having n
flip-flops can have a maximum of 2 to the power n states. The number of
states that a counter owns is known as its mod (modulo) number. Hence a 3-
bit counter is a mod-8 counter.
A mod-n counter may also be described as a divide-by-n counter. This is
because the most significant flip-flop (the furthest flip-flop from the original
clock pulse) produces one pulse for every n pulses at the clock input of the
least significant flip-flop (the one triggers by the clock pulse). Thus, the
above counter is an example of a divide-by-4 counter.
Timing diagram – Let us assume that the clock is negative edge triggered
so above counter will act as an up counter because the clock is negative
edge triggered and output is taken from Q.

Asynchronous Decade Counter

If we take the modulo-16 asynchronous counter and modified it with
additional logic gates it can be made to give a decade (divide-by-10)
counter output for use in standard decimal counting and arithmetic circuits.
Such counters are generally referred to as Decade Counters. A decade
counter requires resetting to zero when the output count reaches the
decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed
this condition back to the reset input. A counter with a count sequence from
binary “0000” (BCD = “0”) through to “1001” (BCD = “9”) is generally
referred to as a BCD binary-coded-decimal counter because its ten state
sequence is that of a BCD code but binary decade counters are more
common.
Asynchronous Decade Counter

This type of asynchronous counter counts upwards on each trailing edge of

the input clock signal starting from 0000 until it reaches an output 1001
(decimal 9). Both outputs QA and QD are now equal to logic “1”. On the
application of the next clock pulse, the output from the 74LS10 NAND gate
changes state from logic “1” to a logic “0” level.
As the output of the NAND gate is connected to the CLEAR ( CLR ) inputs
of all the 74LS73 J-K Flip-flops, this signal causes all of the Q outputs to be
reset back to binary 0000 on the count of 10. As outputs QA and QD are
now both equal to logic “0” as the flip-flop’s have just been reset, the output
of the NAND gate returns back to a logic level “1” and the counter restarts
again from 0000. We now have a decade or Modulo-10 up-counter.

Decade Counter Truth Table

Output bit Pattern

Clock Decimal
Count Value

QD QC QB QA

1 0 0 0 0 0

2 0 0 0 1 1

3 0 0 1 0 2
4 0 0 1 1 3

5 0 1 0 0 4

6 0 1 0 1 5

7 0 1 1 0 6

8 0 1 1 1 7

9 1 0 0 0 8

10 1 0 0 1 9

11 Counter Resets its Outputs back to Zero

Decade Counter Timing Diagram

By using the same idea of truncating counter output sequences, the

above circuit could easily be adapted to other counting cycles be
simply changing the connections to the inputs of the NAND gate or
by using other logic gate combinations.

Asynchronous down counter

2 bit Ripple down counter

 As we know, when the output state (i.e. Q) of previous FF is feed as clock
to next FF then the counter will perform up counting .
 When the complemented output state (i.e. Q’) of previous FF is feed as
clock to next FF then the counter will perform down counting as you seen
below(i.e. 3 2 1 0).
After 4th -ve edge clock pulse the sequence will repeat.
 2 bit asynchronous down counter

Asynchronous Up/Down counter

Up/Down counter is the combination of both the counters in which we can
perform up or down counting by changing the Mode control input.
Design of 3 bit Asynchronous up/down counter :
It is used more than separate up or down counter.
1. In this a mode control input (say M) is used for selecting up and down
mode.
2. A combinational circuit is required between each pair of flip-flop to decide
whether to do up or do down counting.
For n = 3, i.e for 3 bit counter –
Maximum count = 2n -1 and number of states are 2n.
Step 1 : Decision for Mode control input –

When M = 0, then Y= Q, therefore it will perform Up counting (As

discussed above).
When M = 1, then Y= Q’ therefore it will perform Down counting (As
discussed above).
Combinational circuit is required for deciding mode control(i.e whether
counter will perform Up counting or Down counting).
Step 2 : Insertion of Combinational logic between every pair of FFs –
 Up/Down Counter

Timing diagram :
Initially Q3 = 0, Q2 = 0, Q1 = 0.

Timing diagram for 3 bit asynchronous up/down counter

Case 1 – When M=0, then M’ =1.
Put this in Y= M’Q + MQ’= Q So Q is acting as clock for next FFs.
Therefore, the counter will act as Up counter.
Explanation of Up counter –
 The 1st FF is connected to logic 1. Therefore, it will toggle for every falling
edge.
 The 2nd FF input is connected to Q 1.Therefore it changes its state when
Q1= 1 and there is falling edge of clock.
 Similarly, 3rd FF is connected to Q 2. Therefore, it changes its state when
Q2= 1 and there is falling edge of clock.
 By this we can generate counting states of Up counter.
 After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
Case 2 – When M=1, then M’ =0.
Put this in Y= M’Q + MQ’= Q’. So Q’ is acting as clock for next FFs.
Therefore, the counter will act as Down counter.
Explanation of Down counter –
 The 1st FF is connected to logic 1. Therefore, it will toggle for every falling
edge.
 The 2nd FF input is connected to Q’ 1.Therefore it changes its state when
Q’1= 1 and there is falling edge of clock.
 Similarly, 3rd FF is connected to Q’ 2. Therefore, it changes its state when
Q’2= 1 and there is falling edge of clock.
 By this we can generate counting states of down counter.
 After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.

Summarise some of the advantages of Asynchronous Counters:

 Asynchronous Counters can easily be made from Toggle or D-type flip-
flops.
 They are called “Asynchronous Counters” because the clock input of the
flip-flops are not all driven by the same clock signal.
 Each output in the chain depends on a change in state from the previous
flip-flops output.
 Asynchronous counters are sometimes called ripple counters because
the data appears to “ripple” from the output of one flip-flop to the input of
the next.
 They can be implemented using “divide-by-n” counter circuits.
 Truncated counters can produce any modulus number count.
Disadvantages of Asynchronous Counters:
 An extra “re-synchronizing” output flip-flop may be required.
 To count a truncated sequence not equal to 2n, extra feedback logic is
required.
 Counting a large number of bits, propagation delay by successive stages
may become undesirably large.
 This delay gives them the nickname of “Propagation Counters”.
 Counting errors occur at high clocking frequencies.
 Synchronous Counters are faster and more reliable as they use the
same clock signal for all flip-flops.

Synchronous counters
In the Asynchronous counter, the present counter's output passes to the input of
the next counter. So, the counters are connected like a chain. The drawback of this
system is that it creates the counting delay, and the propagation delay also occurs
during the counting stage. The synchronous counter is designed to remove this
drawback.

In the synchronous counter, the same clock pulse is passed to the clock input of all
the flip flops. The clock signals produced by all the flip flops are the same as each
other. Below is the diagram of a 2-bit synchronous counter in which the inputs of the
first flip flop, i.e., FF-A, are set to 1. So, the first flip flop will work as a toggle flip-flop.
The output of the first flip flop is passed to both the inputs of the next JK flip flop.

2.7M

51

Logical Diagram
3 bit synchronous up counter

Signal Diagram(3-bit)

Decade 4-bit Synchronous Counter

A 4-bit decade synchronous counter can also be built using synchronous
binary counters to produce a count sequence from 0 to 9. A standard
binary counter can be converted to a decade (decimal 10) counter with the
aid of some additional logic to implement the desired state sequence. After
reaching the count of “1001”, the counter recycles back to “0000”. We now
have a decade or Modulo-10 counter.
Truth Table of Decade Counter

Decade 4-bit Synchronous Counter

The additional AND gates detect when the counting sequence reaches
“1001”, (Binary 10) and causes flip-flop FF3 to toggle on the next clock
pulse. Flip-flop FF0 toggles on every clock pulse. Thus, the count is reset
and starts over again at “0000” producing a synchronous decade counter.
We could quite easily re-arrange the additional AND gates in the above
counter circuit to produce other count numbers such as a Mod-12 counter
which counts 12 states from”0000″ to “1011” (0 to 11) and then repeats
making them suitable for clocks, etc.

3 bit synchronous Down Counter

Down counter counts in descending order from 15 to 0 (4-bit counter). Down counter
can also be designed using T-flip flop and D-flip flop.
Consider 3-bit counter with each bit represented by Q 0, Q1, Q2as the outputs of flip-
flops FF0, FF1, FF2 respectively. The state table for down counter is given below:

Design Using T-Flip Flop

T-flip flop toggles its state when T-input = 1 & hold its state when T=0.
According to the state table of Down-counter
Q0 is continuously toggling so the input to the FF 0 will be permanent 1. i.e. T0 = 1.
Q1 toggles its state when the previous state is Q 0 = 0. So the input to FF 1 will be the
complemented output of FF0 i.e. T1 = Q̅0
Q2 toggles when both Q0 & Q1 are 0. So the input to FF 2 will be the AND of
complemented outputs of FF0 & FF1 i.e. T2 = Q̅0 & Q̅1.
The schematic for Down-counter using T-flip flops is given below
Synchronous Counter Summary
Then to summarise some of the main points about Synchronous Counters:
 Synchronous Counters can be made from Toggle or D-type flip-flops.
 Synchronous counters are easier to design than asynchronous counters.
 They are called synchronous counters because the clock input of the flip-
flops
are all clocked together at the same time with the same clock signal.
 Due to this common clock pulse all output states switch or change
simultaneously.
 With all clock inputs wired together there is no inherent propagation
delay.
 Synchronous counters are sometimes called parallel counters as the
clock is fed in parallel to all flip-flops.
 The inherent memory circuit keeps track of the counters present state.
 The count sequence is controlled using logic gates.
 Overall faster operation may be achieved compared to Asynchronous
counters.

Design of a sample counter

Example - A counter is first described by a state diagram, which is
shows the sequence of states through which the counter advances when it
is clocked. Figure 18 shows a state diagram of a 3-bit binary counter.
 State
diagram of a
3-bit binary
counter.

The circuit has no inputs other than the clock pulse and no outputs other
than its internal state (outputs are taken off each flip-flop in the counter).
The next state of the counter depends entirely on its present state, and the
state transition occurs every time the clock pulse occurs.

Clock Pulse used =8

Once the sequential circuit is defined by the state diagram, the next step is
to obtain the next-state table, which is derived from the state diagram
Table State table
Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

Since there are eight states, the number of flip-flops required would be
three. Now we want to implement the counter design using JK flip-flops.

Next step is to develop an excitation table from the state tableTable 16.
Excitation table
Now transfer the JK states of the flip-flop inputs from the excitation table to
Karnaugh maps to derive a simplified Boolean expression for each flip-flop
input. This is shown in Figure 20.

Figure 20.
Karnaugh
maps

The 1s in the Karnaugh maps of Figure 20 are grouped with "don't cares"
and the following expressions for the J and K inputs of each flip-flop are
obtained:

J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1 * Q0

The final step is to implement the combinational logic from the equations
and connect the flip-flops to form the sequential circuit. The complete logic
of a 3-bit binary counter is shown in Figure 21.
Figure 21.
Logic
diagram of a
3-bit binary
counter.
 Basic Computer Organisation: The Memory System

Memory Hierarchy
In the Computer System Design, Memory Hierarchy is an enhancement to
organize the memory such that it can minimize the access time. The Memory
Hierarchy was developed based on a program behavior known as locality of
references.The figure below clearly demonstrates the different levels of
memory hierarchy :

This Memory Hierarchy Design is divided into 2 main types:

1. External Memory or Secondary Memory –
Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e. peripheral
storage devices which are accessible by the processor via I/O Module.
2. Internal Memory or Primary Memory –
Comprising of Main Memory, Cache Memory & CPU registers. This is
directly accessible by the processor.
We can infer the following characteristics of Memory Hierarchy Design from
above figure:
1. Capacity:
It is the global volume of information the memory can store. As we move
from top to bottom in the Hierarchy, the capacity increases.

2. Access Time:
It is the time interval between the read/write request and the availability of
the data. As we move from top to bottom in the Hierarchy, the access
time increases.
3. Performance:
Earlier when the computer system was designed without Memory
Hierarchy design, the speed gap increases between the CPU registers
 and Main Memory due to large difference in access time. This results in
lower performance of the system and thus, enhancement was required.
This enhancement was made in the form of Memory Hierarchy Design
because of which the performance of the system increases. One of the
most significant ways to increase system performance is minimizing how
far down the memory hierarchy one has to go to manipulate data.
4. Cost per bit:
As we move from bottom to top in the Hierarchy, the cost per bit
increases i.e. Internal Memory is costlier than External Memory.

Random Access Memory (RAM) and

Read Only Memory (ROM)
Memory is the most essential element of a computing system because without it
computer can’t perform simple tasks. Computer memory is of two basic types –
Primary memory(RAM and ROM) and Secondary memory (hard drive, CD, etc).
Random Access Memory (RAM) is primary-volatile memory and Read Only Memory
(ROM) is primary-non-volatile memory.

1. Random Access Memory (RAM) –

 It is also called read-write memory or the main memory or the primary memory.
 The programs and data that the CPU requires during the execution of a program
are stored in this memory.
 It is a volatile memory as the data lost when the power is turned off.
 RAM is further classified into two types- SRAM (Static Random Access
Memory) and DRAM (Dynamic Random Access Memory).
. RAM is referred to as volatile memory and is lost when the power is
turned off whereas ROM in non-volatile and the contents are retained
even after the power is switched off.
Random-access memory, or RAM, is a form of data storage that can
be accessed randomly at any time, in any order and from any physical
location in contrast to other storage devices, such as hard drives, where
the physical location of the data determines the time taken to retrieve it.
RAM is measured in megabytes and the speed is measured in
nanoseconds and RAM chips can read data faster than ROM.

2. Read Only Memory (ROM) –

 Stores crucial information essential to operate the system, like the program
essential to boot the computer.
 It is not volatile.
 Always retains its data.
 Used in embedded systems or where the programming needs no change.
 Used in calculators and peripheral devices.
 ROM is further classified into 4 types- ROM, PROM, EPROM, and EEPROM.
 Read-only memory, or ROM, is a form of data storage in computers
and other electronic devices that can not be easily altered or
reprogrammed.

It provides instructions to the device to communicate and interact with other devices.

Block Diagram of ROM:

The block of ROM has 'n' input lines and 'm' output lines. Each bit combination of
the input variables is known as an address. Each bit combination that comes out
through output lines is called a word. The number of bits per word is equal to the
number of output lines, m.

The address of a binary number refers to one of the addresses of n variables. So, the
number of possible addresses with 'n' input variables is 2n. An output word has a
unique address, and as there are 2n distinct addresses in a ROM, there are 2n
separate words in the ROM. The words on the output lines at a given time depends
on the address value applied to the input lines.

Internal Structure of ROM:

The internal structure comprises two basic components: decoder and OR gates. A
decoder is a circuit that decodes an encoded form (such as binary coded decimal,
BCD) to a decimal form. So, the input is in binary form, and the output is its decimal
equivalent. All the OR gates present in the ROM will have outputs of the decoder as
their output. Let us take an example of 64 x 4 ROM. The structure is shown in the
following image.
This Read Only Memory consists of 64 words of 4 bits each. So, there would be four
output lines, and one of the 64 words available on the output lines is determined
from the six input lines as we have only six inputs because in this ROM we have 26 =
64, so we can specify 64 addresses or minterms. For each address input, there is a
unique selected word. For example, if the input address is 000000, word number 0
will be selected and applied to the output lines. If the input address is 111111, word
number 63 is selected and applied to the output lines.

Types of Read Only Memory (ROM) –

1. PROM (Programmable read-only memory) – It can be programmed by the user.

Once programmed, the data and instructions in it cannot be changed.

2. EPROM (Erasable Programmable read only memory) – It can be

reprogrammed. To erase data from it, expose it to ultraviolet light. To reprogram
it, erase all the previous data.
EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40
minutes.

3. EEPROM (Electrically erasable programmable read only memory) – The data

can be erased by applying an electric field, with no need for ultraviolet light. We
can erase only portions of the chip.
EEPROM is programmed and erased electrically. It can be erased and reprogrammed
about ten thousand times. Both erasing and programming take about 4 to 10 ms
(millisecond). In EEPROM, any location can be selectively erased and programmed.
 EEPROMs can be erased one byte at a time, rather than erasing the entire chip. Hence,
the process of reprogramming is flexible but slow.
Advantages of ROM
The advantages of ROM are as follows −

 Non-volatile in nature
 Cannot be accidentally changed
 Cheaper than RAMs
 Easy to test
 More reliable than RAMs
 Static and do not require refreshing
 Contents are always known and can be verified

Differences in use
RAM allows the computer to read data quickly and efficiently to be able to run
applications efficiently, whereas ROM stores the program required to initially
boot the computer and perform diagnostics. RAM is a common type of
memory found in computers and printers, and can go up to a few gigabytes.
ROM is usually only a few thousand bytes of storage in personal computers.
RAM is primary memory and volatile
Dynamic random-access
memory(DRAM)
Dynamic random-access memory (dynamic RAM or DRAM) is a type of random-
access semiconductor memory that stores each bit of data in a memory cell consisting of a
tiny capacitor and a transistor, both typically based on metal-oxide-semiconductor (MOS)
technology. The capacitor can either be charged or discharged; these two states are taken to
represent the two values of a bit, conventionally called 0 and 1.

Dynamic random access memory (DRAM) is a type of semiconductor memory that

is typically used for the data or program code needed by a computer processor to
function. DRAM is a common type of random access memory (RAM) that is used
in personal computers (PCs), workstations and servers.

How does DRAM work?

Memory is made of bits of data or program code that are arranged in a two-
dimensional grid. DRAM will store bits of data in what's called a storage, or
memory cell, consisting of a capacitor and a transistor. The storage cells are
typically organized in a rectangular configuration. When a charge is sent through a
column, the transistor at the column is activated. A DRAM storage cell is dynamic,
meaning that it needs to be refreshed or given a new electronic charge every few
milliseconds to compensate for charge leaks from the capacitor.

The memory cells will work with other circuits that can be used to identify rows
and columns, track the refresh process, instruct a cell whether or not to accept a
charge and read or restore data from a cell.

DRAM is one option of semiconductor memory that a system designer can use
when building a computer. Alternative memory choices include static RAM
(SRAM), electrically erasable programmable read-only memory (EEPROM), NOR
flash and NAND flash. Many systems use more than one type of memory.
Types of DRAM
There are many types of DRAM that can be used in a device. Some examples
include the following:

 Synchronous DRAM (SDRAM) syncs memory speeds with CPU clock speeds,
letting the memory controller know the CPU clock cycle. This allows the CPU to
perform more instructions at a time.

 Rambus DRAM (RDRAM) was more widely used in the early 2000s for graphics
cards.

 Double Data Rate SDRAM (DDR SDRAM) almost doubles the bandwidth in data
rate of SDRAM by using double pinning. This process allows for data to
transfer on rising and falling edges of a clock signal. It has been available in
different iterations over time, including DDR2 SDRAM, DDR3 SDRAM and DDR4
SDRAM.

 Fast Page Mode DRAM (FPM DRAM) gives higher performance than other
DRAM types through focusing on fast page access.

 Extended data out DRAM (EDO DRAM) improves the time to read from
memory on microprocessors, such as the Intel Pentium.

Major DRAM manufacturers include Samsung, Rambus, PNY Technologies and

SK Hynix.

Advantages
The main advantages of DRAM include the following:

 Its design is simple, only requiring one transistor.

 The cost is low in comparison to alternative types of memory such as SRAM.

 It provides higher density levels.

 More data can be stored using DRAM.

 Memory can be refreshed and deleted while a program is running.

Disadvantages
The main disadvantages of DRAM include the following:

 Memory is Volatile.

 Power consumption is high relative to other options.

 Manufacturing is complex.

 Data in storage cells needs to be refreshed.

 It is slower than SRAM.

DRAM vs. SRAM
DRAM is a successor to SRAM. Memory designers reduced the number of
elements per bit and eliminated differential bit lines to save chip area in order to
create DRAM. As a result, DRAM is less expensive to produce than SRAM.

But SRAM retains some advantages over DRAM. SRAM does not need to be
refreshed because it operates on the principle of switching the current flow in one
of two directions rather than holding a charge in place within a storage cell. SRAM
is generally used for cache memory, which can be accessed more quickly than
DRAM.

SRAM is capable of byte-level reads/writes, and is faster at reads/writes than

DRAM. DRAM writes data at the byte-level and reads at the multiple-byte page
level.

Power differences vary based on whether the system is in active or sleep mode.
DRAM requires less power than SRAM in an active state, but SRAM consumes
considerably less power than DRAM does while in sleep mode.

Flash memory
Definition
Flash memory is a solid-state chip that maintains stored data without any external
power source. It is commonly used in portable electronics and
removable storage devices, and to replace computer hard drives.
Alternatively referred to as flash storage, flash memory is non-
volatile computer memory. It was first invented by Fujio Masuoka in the
early 1980s while at Toshiba and introduced it to the market in 1984. It
was also later developed by Intel. Flash memory is
an integrated circuit that does not need continuous power to retain data,
but is a bit more expensive than magnetic storage. Today, flash memory is
very popular and solid-state drives are a practical replacement for
large hard drives
Flash memory is a long-life and non-volatile storage chip that is widely used in
embedded systems. It can keep stored data and information even when the power is
off. It can be electrically erased and reprogrammed. Flash memory was developed
from EEPROM (electronically erasable programmable read-only memory). It must be
erased before it can be rewritten with new data. The erase is based on a unit of a
block, which varies from 256 KB to 20 MB.
Flash memory is widely used with car radios, cell phones, digital
cameras, PDAs, solid-state drives, tablets, and printers.

Types of Flash Memory

Flash memory comes in two basic types: NOR and NAND. The names reflect the types of
logic gates each type utilizes. Logic gates are groups of transistors that work together to
carry out an “if-then” operation to produce the desired output. The logic gate’s structure
determines which output will result from any possible input.
1. NOR flash memory
2. - NAND flash memory

NOR flash memory

NOR flash allows quick random access to any location in the memory
array, 100% known good bits for the life of the part and code execution
directly from NOR flash. It is typically used for boot code storage and
execution as a replacement for the older EPROM and as an alternative
to certain kinds of ROM applications in embedded systems.

NAND flash memory

NAND flash requires a relatively long initial read access to the memory
array compared to that of NOR flash. It has 98% good bits when
shipped with additional bit failure over the life of the part (ECC is highly
recommended). NAND costs less per bit than NOR. It is usually used
for data storage such as memory cards, USB flash drives, solid-state
drives, and similar products, for general storage and transfer of data.

Example applications of both types of flash memory include personal

computers and all kinds of embedded systems such as digital audio
players, digital cameras, mobile phones, video games, scientific
instrumentation, industrial robotics, medical electronics and so on.
 Pros and Cons of Flash Memory
1. Disadvantage: Editing Ability. The main drawback of most EEPROM is that
editing memory byte by byte can take an unacceptably long amount of time. Flash
memory addresses this issue by grouping bytes into chunks, or “blocks,” which
cuts down the editing time significantly. Grouping the bytes into blocks speeds up
the process, but it also means you lose the ability to edit specific bytes. A
computer can read a specific byte from any address on the flash chip, but it can
only erase and rewrite in block units.
2. Disadvantage: Lifetime. Flash memory does not have an infinite lifetime. Applying
high voltage fields eventually degrades the transistors, which means the floating
gates will take longer to work. However, most types of flash don’t start to slow
down until at least 10,000 rewrites, and you can distribute those edits over the
entire chip to limit the functional impact of the wear and maintain utility for much
longer.
Biggest Advantages of Flash Memory
 Increased Durability. Unlike traditional hard-disk drives, flash drives lack moving
parts. ...
 Maximum Portability. ...
 Plenty of Storage Capacity. ...
 Fast Transfer Speeds. ...
 Compatibility with Many Devices. ...
 Use Flash Drives as Promotional Materials.

New developments in flash technology continue to decrease the cost per byte of flash
memory. Flash chips are also sturdier and more drop-resistant than their predecessors,
which makes them great for mobile devices, including digital cameras and camcorders,
cell phones, MP3 players, and notebook computers.

Application-Flash memory is used in computers, PDAs, digital audio players, digital

cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial
robotics, and medical electronics. Flash memory has fast read access time, but it is not as fast as
static RAM or ROM. In portable devices, it is preferred to hard disks because of its mechanical
shock resistance.

Secondary Memory
This type of memory is also known as external memory or non-volatile. It is slower
than the main memory. These are used for storing data/information permanently.
CPU directly does not access these memories, instead they are accessed via input-
output routines. The contents of secondary memories are first transferred to the
main memory, and then the CPU can access it. For example, disk, CD-ROM, DVD,
etc.
Characteristics of Secondary Memory

 These are magnetic and optical memories.

 It is known as the backup memory.
 It is a non-volatile memory.
 Data is permanently stored even if power is switched off.
 It is used for storage of data in a computer.
 Computer may run without the secondary memory.
 Slower than primary memories.
 High Capacity: Secondary storage devices like external hard drive can have
high memory capacity than the primary memory.
 Portable: Since secondary storage devices are external devices they are
portable and can be connected to different computer systems.
 Durable: highly durable in nature.
 Cost: The cost of the secondary storage devices is less than the primary
devices.

Types of Secondary memory

Mass storage devices:
The magnetic disk provides cheap storage and is used for both small and
large computer systems.

Two types of magnetic disks are:

 Floppy disks
 Hard disks

Flash/SSD
Solid State Drive provides a persistent flash memory. It's very fast
compared to Hard Drives. Frequently found in Mobile phones, its rapidly
being adopted in PC/Laptop/Mac.

Optical drives:
This secondary storage device is from which data is read and written with
the help of lasers. Optical disks can hold data up to 185TB.

Examples

 CD
  DVD
 Blue Ray

USB drives:
It is one of the most popular types of secondary storage device available in
the market. USB drives are removable, rewritable and are physically very
small. The capacity of USB drives is also increasing significantly as today
1TB pen drive is also available in the market.

Magnetic tape:
It is a serial access storage device which allows us to store a very high
volume of data. Usually used for backups.

Primary Memory Vs Secondary Memory

Difference between Main memory and Secondary memory

Parameter Primary memory Secondary memory

Hard Disk Drives(HDD)

 A hard disk consists of one or more circular disks called platters which
are mounted on a common spindle. Each surface of a platter is coated
with a magnetic material. Both surfaces of each disk are capable of
storing data except the top and bottom disk where only the inner surface
is used. The information is recorded on the surface of the rotating disk by
magnetic read/write heads. These heads are joined to a common arm
known as access arm.
Hard disk drive components:

Most of the basic types of hard drives contains a number of disk platters
that are placed around a spindle which is placed inside a sealed chamber.
The chamber also includes read/write head and motors. Data is stored on
each of these disks in the arrangement of concentric circles called tracks
which are divided further into sectors. Though internal Hard drives are not
very portable and used internally in a computer system, external hard
disks can be used as a substitute for portable storage. Hard disks can
store data upto several terabytes.
Data stores on the surface in circular rings are the tracks. Moreover, these tracks further divide
into divisions which are the sectors. They have a storage capacity of up to terabytes. Besides,
the hard disks are usually present internally on a system.

A hard drive fits inside a computer case and is firmly attached with the
use of braces and screws to prevent it from being jarred as it spins.
Typically it spins at 5,400 to 15,000 RPM. The disk moves at an
accelerated rate, allowing data to be accessed immediately. Most hard
drives operate on high speed interfaces using serial ATA (SATA) or serial
attached technology. When the platters rotate, an arm with a read/write
head extends across the platters. The arm writes new data to the platters
and reads new data from them. Most hard drives use enhanced integrated
drive electronics (EIDE) including cables and connectors to the
motherboard. All data is stored magnetically, allowing information to be
saved when power is shut off.

Hard drives need a read only memory (ROM) controller board to instruct
the read/write heads how, when and where to move across the platters.
Hard drives have disks stacked together and spin in unison. The
read/write heads are controlled by an actuator, which magnetically reads
from and writes to the platters. The read/write heads float on a film of air
above the platters. Both sides of the platters are used to store data. Each
side or surface of one disk is called a head, with each one divided into
sectors and tracks. All tracks are the same distance from the center of the
disk. Collectively they comprise one cylinder. Data is written to a disk
starting at the furthest track. The read/write heads move inward to the
next cylinder once the first cylinder is filled.
A hard drive is divided into one of more partitions, which can be further
divided into logical drives or volumes. Usually a master boot record (MBR)
is found at the beginning of the hard drive and contains a table of
partition information. Each logical drive contains a boot record, a file
allocation table (FAT) and a root directory for the FAT file system.

How is a hard drive connected to a computer?

An internal hard drive connects to the computer using two means: a
data cable (IDE, SATA, or SCSI) to the motherboard and a power
cable to the power supply.

 How to install a hard drive or SSD.

Where is the hard drive found in a computer?

All primary computer hard drives are found inside a computer case
and are attached to the computer motherboard using an ATA, SCSI,
or SATA cable. Hard drives are powered by a connection to the PSU
(power supply unit).

Note

Some portable and desktop computers may have newer flash drives
that connect directly to the PCIe interface or another interface and
not use a cable.

Optical memory

Optical memory was developed by Philips and Sony and released in 1982
in the fourth generation of computers. These memories use light beams for
its operations and require optical drives for its operations. These memories
are used for storing audio/video, backup as well as caring for data.
Read/write speed is slower compared to hard disk and flash memories.
Examples of optical memories are Compact Disk (CD), Digital Versatile Disk
(DVD), and Bluray Disk (BD).

Compact Disk (CD):

It stores data and it has circular plastic, single side of the plastic is coated by
aluminium alloy which stores data. It is protected by additional thin plastic
covering. CD requires a CD drive for its operation.

A CD could store much more data than a personal computer hard drive. The
CD has storage typically up to 700 MB (up to 80 minutes’ audio).

Types of Compact Disk (CD) :

These are various types of CD as follows below.
1. CD-R – It is a blank CD in which data can be stored once which is known
as CD-ROM after storing data on it.
2. CD-ROM – It became a ROM (read only memory), in which you can not
update or delete data. Only you can read data using a CD-drive.
3. CD-RW – You can update or delete data multiple times, if you want to do
so.

Mechanism of Compact Disk

How the digital data is imprinted on the compact disk?

The laser beam with high intensity is focused on the disk which imprints or
indents the series of microscopic pits on the surface of polycarbonate
plastic. These pits are arranged on a long circular track on the surface of
the disk spiralling from the centre of the disk to the outer edge thus forming
a master disk.

This master disk is then used to produce a mould which can be used to
produce a large volume of CDs that hold the same information as that of
master CDs.

How the data is retrieved from the compact disk?

The low power laser beam is focused on the polycarbonate plastic. The
laser beam travels through the polycarbonate plastic layer and gets
reflected back from the aluminium layer.

This reflected beam is now received by the photodetector which is also

positioned below the polycarbonate plastic.

When a laser beam falls on the pit which is a slightly rough surface the
intensity of the reflected beam is low. When the laser beam falls on the
land surface the reflected beam return with a higher intensity.

The photodetector receives the reflected beam and senses the change in
the intensity of the reflected beam thereby convert it into a digital signal. As
the beginning or the ending of pits when there occur a change in the
elevation of the reflected beam is recorded as 1. The smooth land surface
where there is no change in the elevation of the reflected beam is recorded
as 0 by the photodetector.

The figure below shows you several transitions of the laser beam between
lands and pits.

Advantages of CD:
1. It can store data for long time, i.e., durable memory.
2. It is a reliable and widely used memory.
3. It provides random data access.
4. It can not be affected by the magnetic field.
5. It is economical, i.e., stores more data in less space.
Disadvantages of CD:
1. It is a good memory but slower than a disk.
2. Writing or copying data on CD is not easy.
CD-ROM
Compact Disk Read-Only Memory (CD-ROM) is a read-only memory that is
used to store computer data. Earlier the CDs were implemented to store
audios and videos but as the CDs store data in digital form they can be
used to store computer data.

The audio and video appliance can tolerate some amount of error as it
does not reflect in the produced audio and video in a noticeable way. But
when it comes to computer data the computer appliances do not tolerate
any error. Now it is not possible to prevent physical imperfection while
indenting pits on the CDs. So some extra bits must be added to detect and
correct the error.

The CDs and CD-ROM has a single spiral track that starts from the centre
of the track and spiral out toward the outer edge. The data is stored in CD-
ROM in blocks i.e. sector. The number of sectors varies from track to track.
There are fewer sectors in the inner tracks of the CD and more sectors in
the outer track of the CD.

The sector at the outer and inner edge of the disk is of the same length.
These sectors are scanned with the low power laser beam at the same rate
while the disk is rotating. Though the rotating speed of the disk can vary.
To access the sectors near the centre, the disk rotates comparatively faster
as compared to access the sectors present at the outer edge of the disk.

CD-Recordable
CD-Recordable i.e. (CD-R) was the first kind of compact disk that could be
easily recorded by any computer user. This disk has a similar shiny spiral
track as we can see in CD and CD-ROM. This shiny track is cover
with organic dye at the time of manufacturing.

To record the data on the CD-R the disk is inserted into the CD-R drive and
a laser beam is focused on the drive which burns pits onto the dye. The
burned spot become opaque and the unburnt area still appears shiny.
When the laser beam with low power is focused on the disk to retrieve the
information. The opaque spots reflect light with less intensity and the shiny
parts reflect light with high intensity.

Remember the CD-R can be burnt or recorded once in its lifetime. Though
the unused portion of the CD-R can be used to record some more
information later.
 CD-Rewritable (CD-RW)
This CD can be recorded multiple times which means the user can write
and erase data from the CD-RW multiple times. This is because instead of
using the organic dye an alloy is used which includes silver, indium,
antimony, and tellurium. The melting point of this alloy is 500o C.

The alloy shows interesting behaviour when it is heated and cooled down.
When the alloy is heated above the melting point and cooled down it turns
into an amorphous state which is capable to absorb light.

In case the alloy is heated at 200o C and maintained at that temperature for
a certain period a process annealing takes place which turns the alloy into
the crystalline state. At this state the alloy allows the light to pass through it.

So here the pits can be created by heating the selected spots above the
melting point and the remaining parts between the pits are lands. The
stored data can further be deleted using the annealing process.

Digital Versatile Disk (DVD)

The DVD technology was first introduced in the year 1996 and has the
same appearance as that of the CD. The difference is in their storage size,
the DVD has much larger storage than that of CD and this is done by
implementing several changes in the design of the DVD.

The laser beam used imprint data in DVD has a shorter wavelength as
compared to the wavelength of laser beam we use for CDs. The shorter
wavelength of the laser beam helps the light to focus on a smaller spot.

Pits are much smaller as compared to pits of CD and even tracks are
placed much closer as compared to the tracks in CD. With all these
changes in design, the DVD has a storage size of 4.7 GB.

To increase the storage capacity even more the two-layered and two-sided
disk was introduced.

Advantages of Optical Storage Devices

 It is capable to store vast amount of data.
 Affordable price
 It can be recycled (Re-used).
 It has ultra data stability.
 Countable/uncountable storage units
 Best Durability, Transport-ability, and archiving.
Disadvantages Optical Storage Devices
 Some traditional PCs are not able to read these disks.
 It is getting trouble while recycling

CCD
A charge-coupled device (CCD) is an integrated circuit containing an array of linked, or
coupled, capacitors. Under the control of an external circuit, each capacitor can transfer
its electric charge to a neighboring capacitor. CCD sensors are a major technology used in digital
imaging.
Stands for "Charged Coupled Device." CCDs are sensors used
in digital cameras and video cameras to record still and moving images.
The CCD captures light and converts it to digital data that is recorded by
the camera. For this reason, a CCD is often considered the digital
version of film.
The quality of an image captured by a CCD depends on
the resolution of the sensor. In digital cameras, the resolution is
measured in Megapixels (or thousands of or pixels. Therefore, an 8MP
digital camera can capture twice as much information as a 4MP
camera. The result is a larger photo with more detail.

CCDs in video cameras are usually measured by physical size. For

example, most consumer digital cameras use a CCD around 1/6 or 1/5
of an inch in size. More expensive cameras may have CCDs 1/3 of an
inch in size or larger. The larger the sensor, the more light it can
capture, meaning it will produce better video in low light settings.
Professional digital video cameras often have three sensors, referred to
as "3CCD," which use separate CCDs for capturing red, green, and blue
hues.

CCDs are now commonly included in digital still and video cameras. They
are also used in astronomical telescopes, scanners, and bar code readers.
The devices have also found use in machine vision for robots, in optical
character recognition (OCR), in the processing of satellite photographs,
and in the enhancement of radar images, especially in meteorology.
 Bubble memory
Bubble memory is a type of non-volatile computer memory that uses a thin film of a magnetic
material to hold small magnetized areas, known as bubbles or domains, each storing one bit of
data. The material is arranged to form a series of parallel tracks that the bubbles can move along
under the action of an external magnetic field. The bubbles are read by moving them to the edge
of the material where they can be read by a conventional magnetic pickup, and then rewritten on
the far edge to keep the memory cycling through the material. In operation, bubble memories are
similar to delay line memory systems.
Bubble memory was a promising technology in the 1980s, offering similar
density to hard disk drives and similar performance to core memory, but
major advancements in both hard disk and semiconductor memory chips
pushed bubble memory into the shadows.

Bubble Memory

Bubble memory is conceptually a stationary disk with spinning bits.

RAID
Redundant array of independent disks (RAID) is a storage technology used to
improve the processing capability of storage systems. This technology is designed
to provide reliability in disk array systems and to take advantage of the
performance gains offered by an array of multiple disks over single-disk storage.
It combines multiple physical disk drive components into a single logical unit. Data in RAID is
distributed across the drives in one of several ways, referred to as RAID levels, depending on the
required level of redundancy and performance. The different schemas, or data distribution
layouts, are named by the word RAID followed by a number

Different RAID Levels

 RAID 0 – striping
 RAID 1 – mirroring
 RAID 5 – striping with parity
 RAID 6 – striping with double parity
 RAID 10 – combining mirroring and striping

Note

In all the diagrams mentioned below:

A, B, C, D, E,F,G and H – represents blocks

p1, p2,p3 and p4 represents parity

RAID LEVEL 0
RAID 0 divides a set of data among multiple hard drives, usually two drives.This configuration
has striping but no redundancy of data. It offers the best performance but no fault-tolerance.If
one drive fails then all data in the array is lost.

Advantages
 RAID 0 offers great performance, both in read and write operations. There is no overhead
caused by parity controls.
 All storage capacity is used, there is no overhead.
 The technology is easy to implement.

Disadvantages
 RAID 0 is not fault-tolerant. If one drive fails, all data in the RAID 0 array are lost. It should
not be used for mission-critical systems.

Ideal Use
 RAID 0 is ideal for non-critical storage of data
 Minimum 2 disks
 Excellent performance
 RAID LEVEL 1
RAID 1 stores an exact copy of your data on two or more drives. This makes your data much
more secure; if one drive in the system fails, your data can simply be retrieved from any other
drive in the system. This is known as data redundancy.

Advantages
 RAID 1 offers excellent read speed and a write-speed that is comparable to that of a single
drive
 In case a drive fails, data do not have to be rebuild, they just have to be copied to the
replacement drive.
 RAID 1 is a very simple technology.

Disadvantages
 The main disadvantage is that the effective storage capacity is only half of the total drive
capacity because all data get written twice.
 Software RAID 1 solutions do not always allow a hot swap of a failed drive. That means the
failed drive can only be replaced after powering down the computer it is attached to. For
servers that are used simultaneously by many people, this may not be acceptable. Such
systems typically use hardware controllers that do support hot swapping.

Ideal Use
 It is suitable for small servers in which only two data drives will be used
 Minimum 2 disks
 Excellent redundancy

RAID LEVEL 5
Level 5 is one of the most popular configuration of RAID and is the most common secure RAID
level. It requires at least 3 drives but can work with up to 16. Data blocks are striped across the
drives and on one drive a parity checksum of all the block data is written. The parity data are not
written to a fixed drive, they are spread across all drives.
 Advantages
 Read data transactions are very fast while write data transactions are somewhat slower.
 If a drive fails, you still have access to all data, even while the failed drive is being replaced
and the storage controller rebuilds the data on the new drive.

Disadvantages
 Drive failures have an effect on throughput, although this is still acceptable.
 This is complex technology. If one of the disks in an array using 4TB disks fails and is
replaced, restoring the data (the rebuild time) may take a day or longer, depending on the
load on the array and the speed of the controller. If another disk goes bad during that time,
data are lost forever.

Ideal Use
 Minimum 3 disks
 RAID 5 is a good all-round system that combines efficient storage with excellent security and
decent performance.
 It is ideal for file and application servers that have a limited number of data drives.

RAID LEVEL 6
Provides block-level striping with parity data distributed across all disks. It requires at least 4
drives and can withstand 2 drives dying simultaneously. The chances that two drives break down
at exactly the same moment are of course very small.This technique is similar to RAID 5.If a
drive in a RAID 5 systems dies and is replaced by a new drive, it takes hours to rebuild the
swapped drive. If another drive dies during that time, you still lose all of your data. With RAID 6,
the RAID array will even survive that second failure.
 Advantages
 Like with RAID 5, read data transactions are very fast.
 If two drives fail, you still have access to all data, even while the failed drives are being
replaced. So RAID 6 is more secure than RAID 5.

Disadvantages
 Write data transactions are slowed down due to the parity that has to be calculated.
 Drive failures have an effect on throughput, although this is still acceptable.
 This is complex technology. Rebuilding an array in which one drive failed can take a long
time.

Ideal Use
 RAID 6 is a good all-round system that combines efficient storage with excellent security and
decent performance.

RAID LEVEL 10
Combining RAID 1 and RAID 0, this level is referred to as RAID 10, which offers higher
performance than RAID 1 but at a much higher cost. In RAID 1+0, the data is mirrored and the
mirrors are striped.This is a hybrid RAID configuration. It provides security by mirroring all data
on secondary drives while using striping across each set of drives to speed up data transfers.
 Advantages
 If something goes wrong with one of the disks in a RAID 10 configuration, the rebuild time is
very fast since all that is needed is copying all the data from the surviving mirror to a new
drive. This can take as little as 30 minutes for drives of 1 TB.

Disadvantages
 Half of the storage capacity goes to mirroring, so compared to large RAID 5 or RAID 6
arrays, this is an expensive way to have redundancy.

Ideal Use
 Minimum 4 disks.
 Excellent performance

RAID is no substitute for back-up!

All RAID levels except RAID 0 offer protection from a single drive failure. A RAID 6 system even
survives 2 disks dying simultaneously. For complete security you do still need to back-up the
data from a RAID system.

Conclusion
Based on the number of available disk drives and your requirements for performance and
reliability. Disk drive usage, read performance, and write performance depend on the number of
drives in the array. In general, the more drives, the better the performance.

While RAID 0 is the least costly, it could never be used for databases unless you can withstand
data loss or rebuild adequately from other backed up media.

RAID 1 and 10 win on data protection, but lose in terms of disk costs. RAID 10 offers the best
performance and data protection, but at a cost.

RAID 5 offers the best trade-off in terms of price and performance, and includes data protection
for database use.

The Concept Of High Speed Memories-

Cache Memory:
Cache Memory is a special very high-speed memory. It is used to speed up and
synchronizing with high-speed CPU. Cache memory is costlier than main memory or
disk memory but economical than CPU registers. Cache memory is an extremely fast
memory type that acts as a buffer between RAM and the CPU. It holds frequently
requested data and instructions so that they are immediately available to the CPU
when needed.
Cache memory is used to reduce the average time to access data from the Main
memory. The cache is a smaller and faster memory which stores copies of the data
from frequently used main memory locations. There are various different independent
caches in a CPU, which store instructions and data.

Levels of memory:
 Level 1 or Register –
It is a type of memory in which data is stored and accepted that are immediately
stored in CPU. Most commonly used register is accumulator, Program counter,
address register etc.
 Level 2 or Cache memory –
It is the fastest memory which has faster access time where data is temporarily
stored for faster access.
The more cache there is, the more data can be stored closer to the CPU.

Cache is graded as Level 1 (L1), Level 2 (L2) and Level 3 (L3):

 L1 is usually part of the CPU chip itself and is both the smallest and the
fastest to access. Its size is often restricted to between 8 KB and 64 KB.
 L2 and L3 caches are bigger than L1. They are extra caches built between
the CPU and the RAM. Sometimes L2 is built into the CPU with L1. L2 and L3
caches take slightly longer to access than L1. The more L2 and L3 memory
available, the faster a computer can run.

 Level 3 or Main Memory –

It is memory on which computer works currently. It is small in size and once
power is off data no longer stays in this memory.
 Level 4 or Secondary Memory –
It is external memory which is not as fast as main memory but data stays
permanently in this memory.
Cache Performance:
When the processor needs to read or write a location in main memory, it first checks
for a corresponding entry in the cache.

 If the processor finds that the memory location is in the cache, a cache hit has
occurred and data is read from cache
 If the processor does not find the memory location in the cache, a cache miss has
occurred. For a cache miss, the cache allocates a new entry and copies in data from
main memory, then the request is fulfilled from the contents of the cache.
The performance of cache memory is frequently measured in terms of a quantity
called Hit ratio.
Hit ratio = hit / (hit + miss) = no. of hits/total accesses
We can improve Cache performance using higher cache block size, higher
associativity, reduce miss rate, reduce miss penalty, and reduce the time to hit in the
cache.
Cache Mapping:
There are three different types of mapping used for the purpose of cache memory
which are as follows: Direct mapping, Associative mapping, and Set-Associative
mapping. These are explained below.
1. Direct Mapping –
The simplest technique, known as direct mapping, maps each block of main
memory into only one possible cache line. or
In Direct mapping, assigne each memory block to a specific line in the cache. If a
line is previously taken up by a memory block when a new block needs to be
loaded, the old block is trashed. An address space is split into two parts index field
and a tag field. The cache is used to store the tag field whereas the rest is stored in
the main memory. Direct mapping`s performance is directly proportional to the Hit
ratio.
2. i = j modulo m
3. where
4. i=cache line number
5. j= main memory block number
m=number of lines in the cache
For purposes of cache access, each main memory address can be viewed as
consisting of three fields. The least significant w bits identify a unique word or
byte within a block of main memory. In most contemporary machines, the address
is at the byte level. The remaining s bits specify one of the 2s blocks of main
memory. The cache logic interprets these s bits as a tag of s-r bits (most significant
portion) and a line field of r bits. This latter field identifies one of the m=2r lines of
the cache.
2.Associative Mapping –
In this type of mapping, the associative memory is used to store content and addresses
of the memory word. Any block can go into any line of the cache. This means that the
word id bits are used to identify which word in the block is needed, but the tag
becomes all of the remaining bits. This enables the placement of any word at any
place in the cache memory. It is considered to be the fastest and the most flexible
mapping form.
3.Set-associative Mapping –
This form of mapping is an enhanced form of direct mapping where the drawbacks of
direct mapping are removed. Set associative addresses the problem of possible
thrashing in the direct mapping method. It does this by saying that instead of having
exactly one line that a block can map to in the cache, we will group a few lines
together creating a set. Then a block in memory can map to any one of the lines of a
specific set..Set-associative mapping allows that each word that is present in the cache
can have two or more words in the main memory for the same index address. Set
associative cache mapping combines the best of direct and associative cache mapping
techniques.
In this case, the cache consists of a number of sets, each of which consists of a
number of lines. The relationships are
m = v * k
i= j mod v

where
i=cache set number
j=main memory block number
v=number of sets
m=number of lines in the cache number of sets
k=number of lines in each set
 Application of Cache Memory –
1. Usually, the cache memory can store a reasonable number of blocks at any
given time, but this number is small compared to the total number of blocks in
the main memory.
2. The correspondence between the main memory blocks and those in the cache is
specified by a mapping function.

Types of Cache –
3. Primary Cache –
A primary cache is always located on the processor chip. This cache is small
and its access time is comparable to that of processor registers.
4. Secondary Cache –
Secondary cache is placed between the primary cache and the rest of the
memory. It is referred to as the level 2 (L2) cache. Often, the Level 2 cache is
also housed on the processor chip.
Locality of reference –
Since size of cache memory is less as compared to main memory. So to check which
part of main memory should be given priority and loaded in cache is decided based on
locality of reference.
Types of Locality of reference
1.Spatial Locality of reference
This says that there is a chance that element will be present in the close proximity
to the reference point and next time if again searched then more close proximity to the
point of reference.
2.Temporal Locality of reference
In this Least recently used algorithm will be used. Whenever there is page fault
occurs within a word will not only load word in main memory but complete page fault
will be loaded because spatial locality of reference rule says that if you are referring
any word next word will be referred in its register that’s why we load complete page
table so the complete block will be loaded.
Writing policies.
When a system writes data to cache, it must at some point write that data to the backing store as
well. The timing of this write is controlled by what is known as the write policy. There are two
basic writing approaches:

 Write-through: write is done synchronously both to the cache and to the backing store.
 Write-back (also called write-behind): initially, writing is done only to the cache. The write to
the backing store is postponed until the modified content is about to be replaced by another
cache block.

Replacement policies
To make room for the new entry on a cache miss, the cache may have to evict one of the
existing entries It uses to choose the entry to evict is called the replacement policy. The
fundamental problem with any replacement policy is that it must predict which existing
cache entry is least likely to be used in the future. Predicting the future is difficult, so
there is no perfect method to choose among the variety of replacement policies available.
One popular replacement policy, least-recently used (LRU), replaces the least recently
accessed entry.

Memory Interleaving
In computing, interleaved memory is a design which compensates for the relatively
slow speed of dynamic random-access memory (DRAM) or core memory, by spreading memory
addresses evenly across memory banks. That way, contiguous memory reads and writes use
each memory bank in turn, resulting in higher memory throughput due to reduced waiting for
memory banks to become ready for the operations.
Memory Interleaving is less or More an Abstraction technique. Though its a
bit different from Abstraction. It is a Technique which divides memory into a
number of modules such that Successive words in the address space are
placed in the Different module.
Consecutive Word in a Module:
 Figure-1: Consecutive Word in a Module

Let us assume 16 Data’s to be Transferred to the Four Module. Where

Module 00 be Module 1, Module 01 be Module 2, Module 10 be Module 3 &
Module 11 be Module 4. Also 10, 20, 30….130 are the data to be transferred.

From the figure above in Module 1, 10 [Data] is transferred then 20, 30 &
finally, 40 which are the Data. That means the data are added consecutively
in the Module till its max capacity.
Most significant bit (MSB) provides the Address of the Module & least
significant bit (LSB) provides the address of the data in the module.
For Example, to get 90 (Data) 1000 will be provided by the processor. In this
10 will indicate that the data is in module 10 (module 3) & 00 is the address
of 90 in Module 10 (module 3). So,
Module 1 Contains Data : 10, 20, 30, 40
Module 2 Contains Data : 50, 60, 70, 80
Module 3 Contains Data : 90, 100, 110, 120
Module 4 Contains Data : 130, 140, 150, 160
Consecutive Word in Consecutive Module:

Figure-2: Consecutive Word in Consecutive Module

Now again we assume 16 Data’s to be transferred to the Four Module. But

now the consecutive Data are added in Consecutive Module. That is, 10
[Data] is added in Module 1, 20 [Data] in Module 2 and So on.
Least Significant Bit (LSB) provides the Address of the Module & Most
significant bit (MSB) provides the address of the data in the module.
For Example, to get 90 (Data) 1000 will be provided by the processor. In this
00 will indicate that the data is in module 00 (module 1) & 10 is the address
of 90 in Module 00 (module 1). That is,
Module 1 Contains Data : 10, 50, 90, 130
Module 2 Contains Data : 20, 60, 100, 140
Module 3 Contains Data : 30, 70, 110, 150
Module 4 Contains Data : 40, 80, 120, 160

Types of interleaved memory

1. High order interleaving

2. Low order interleaving

In high order memory interleaving, most significant bits of the memory

address decides, memory banks where a particular location resides. But, in
low order interleaving least significant bits of the memory address decides
the memory banks.

One major difference between high order and low order interleaving is,
consecutive memory location is found in the same memory module in high
order interleaving. But in low order interleaving consecutive memory location
is found in consecutive banks.
Why we use Memory Interleaving? [Advantages]:
Whenever, Processor request Data from the main memory. A block (chunk)
of Data is Transferred to the cache and then to Processor. So whenever a
cache miss occurs the Data is to be fetched from main memory. But main
memory is relatively slower than the cache. So to improve the access time of
the main memory interleaving is used.
We can access all four Module at the same time thus achieving Parallelism.
From Figure 2 the data can be acquired from the Module using the Higher
bits. This method Uses memory effectively.

Associative Memory
An associative memory can be considered as a memory unit whose stored data can
be identified for access by the content of the data itself rather than by an address or
memory location.

Associative memory is often referred to as Content Addressable Memory (CAM).

When a write operation is performed on associative memory, no address or memory

location is given to the word. The memory itself is capable of finding an empty
unused location to store the word.

On the other hand, when the word is to be read from an associative memory, the
content of the word, or part of the word, is specified. The words which match the
specified content are located by the memory and are marked for reading.
Associative memory of conventional semiconductor memory (usually RAM)
with added comparison circuitry that enables a search operation to complete
in a single clock cycle. It is a hardware search engine, a special type of
computer memory used in certain very high searching applications.

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The following diagram shows the block representation of an Associative memory.

From the block diagram, we can say that an associative memory consists of a
memory array and logic for 'm' words with 'n' bits per word.

The functional registers like the argument register A and key register K each
have n bits, one for each bit of a word. The match register M consists of m bits, one
for each memory word.

The words which are kept in the memory are compared in parallel with the content of
the argument register.

The key register (K) provides a mask for choosing a particular field or key in the
argument word. If the key register contains a binary value of all 1's, then the entire
argument is compared with each memory word. Otherwise, only those bits in the
argument that have 1's in their corresponding position of the key register are
compared. Thus, the key provides a mask for identifying a piece of information which
specifies how the reference to memory is made.

The following diagram can represent the relation between the memory array and the
external registers in an associative memory.

The cells present inside the memory array are marked by the letter C with two
subscripts. The first subscript gives the word number and the second specifies the bit
position in the word. For instance, the cell Cij is the cell for bit j in word i.

A bit Aj in the argument register is compared with all the bits in column j of the array
provided that Kj = 1. This process is done for all columns j = 1, 2, 3......, n.

If a match occurs between all the unmasked bits of the argument and the bits in
word i, the corresponding bit Mi in the match register is set to 1. If one or more
unmasked bits of the argument and the word do not match, M i is cleared to 0.
Applications of Associative memory :-
1. It can be only used in memory allocation format.
2. It is widely used in the database management systems, etc.
Advantages of Associative memory :-
1. It is used where search time needs to be less or short.
2. It is suitable for parallel searches.
3. It is often used to speedup databases.
4. It is used in page tables used by the virtual memory and used in neural
networks.
Disadvantages of Associative memory :-
1. It is more expensive than RAM.
2. Each cell must have storage capability and logical circuits for matching its
content with external argument.
UNIT-6:The Input /Output System
Input/Output Devices or External or Peripheral Devices
Input and output devices allow the computer system to interact with the outside world
by moving data into and out of the system.
An input device is used to bring data into the system. An input device is essentially a
piece of hardware that sends data to a computer. Most input devices either interact
with or control the computer in some way. The most common input devices are the
mouse and the keyboard, but there are many others.

The key distinction between an input device and an output device is that the
former sends data to the computer, whereas the latter receives data from the
computer. Input and output devices that provide computers with additional
functionality are also called peripheral or auxiliary devices.

Following are some of the important input devices which are used in a computer −

 Keyboard
 Mouse
 Joy Stick
 Light pen
 Track Ball
 Scanner
 Graphic Tablet
 Microphone
 Magnetic Ink Card Reader(MICR)
 Optical Character Reader(OCR)
 Bar Code Reader
 Optical Mark Reader(OMR)

Some input devices :

Keyboard
Keyboard is the most common and very popular input device which helps to input
data to the computer. The layout of the keyboard is like that of traditional typewriter,
although there are some additional keys provided for performing additional
functions.

Keyboards are of two sizes 84 keys or 101/102 keys, but now keyboards with 104
keys or 108 keys are also available for Windows and Internet.
The keys on the keyboard are as follows −

S.No Keys & Description

 Typing Keys
1
These keys include the letter keys (A-Z) and digit keys (09) which generally give
the same layout as that of typewriters.

Numeric Keypad
2 It is used to enter the numeric data or cursor movement. Generally, it consists of a
set of 17 keys that are laid out in the same configuration used by most adding
machines and calculators.

Function Keys
3 The twelve function keys are present on the keyboard which are arranged in a row
at the top of the keyboard. Each function key has a unique meaning and is used for
some specific purpose.

Control keys
4 These keys provide cursor and screen control. It includes four directional arrow
keys. Control keys also include Home, End, Insert, Delete, Page Up, Page Down,
Control(Ctrl), Alternate(Alt), Escape(Esc).

Special Purpose Keys

5
Keyboard also contains some special purpose keys such as Enter, Shift, Caps
Lock, Num Lock, Space bar, Tab, and Print Screen.

Mouse
Mouse is the most popular pointing device. It is a very famous cursor-control device
having a small palm size box with a round ball at its base, which senses the
movement of the mouse and sends corresponding signals to the CPU when the
mouse buttons are pressed.
Generally, it has two buttons called the left and the right button and a wheel is
present between the buttons. A mouse can be used to control the position of the
cursor on the screen, but it cannot be used to enter text into the computer.

Advantages

 Easy to use
 Not very expensive
 Moves the cursor faster than the arrow keys of the keyboard.
Joystick
Joystick is also a pointing device, which is used to move the cursor position on a
monitor screen. It is a stick having a spherical ball at its both lower and upper ends.
The lower spherical ball moves in a socket. The joystick can be moved in all four
directions.

The function of the joystick is similar to that of a mouse. It is mainly used in

Computer Aided Designing (CAD) and playing computer games.

Light Pen
Light pen is a pointing device similar to a pen. It is used to select a displayed menu
item or draw pictures on the monitor screen. It consists of a photocell and an optical
system placed in a small tube.

When the tip of a light pen is moved over the monitor screen and the pen button is
pressed, its photocell sensing element detects the screen location and sends the
corresponding signal to the CPU.

Track Ball
Track ball is an input device that is mostly used in notebook or laptop computer,
instead of a mouse. This is a ball which is half inserted and by moving fingers on
the ball, the pointer can be moved.

Since the whole device is not moved, a track ball requires less space than a mouse.
A track ball comes in various shapes like a ball, a button, or a square.

Scanner
Scanner is an input device, which works more like a photocopy machine. It is used
when some information is available on paper and it is to be transferred to the hard
disk of the computer for further manipulation.

Scanner captures images from the source which are then converted into a digital
form that can be stored on the disk. These images can be edited before they are
printed.

The list of output devices can be as following:

1. Monitor
2. Printer
3. Audio Speakers
4. Headphones
 5. Projector
6. GPS
7. Sound Card
8. Video Card
9. Braille Reader
10. Plotter

There are multiple types of output devices which give result in multiple
formats as it differs according to the functions of output devices.

They are used in multiple areas. Some of them can be used for personal use
whereas some have to be used in the industries and factories.

Some Examples Output Devices And Their Functions

1. Monitor
The monitor is a common output device that comes in our mind. It shows
the display of the input you give using a keyboard or mouse. You need to
provide a power supply to the monitor. Also, the monitor is connected
through VGA Cable to the CPU. It does not work until you connect it to the
CPU. The monitor consists of a cathode ray tube and a fluorescent screen.

The monitor is also known as the Video Display Terminal (VDT)

and Visual Display Unit (VDU).

You can see the use of Monitors in Game Matches, Government Offices,
Public Places, Information Centers, Big Cities, etc. They display
advertisements, data, information, promos, videos, banners, etc.

Function of Monitor

The core function of the Monitor is to allow users to interact with the
computer.
Types of Computer Monitor

There are 8 types of computer monitors. These are listed as

1. Cathode Ray Tube Monitors (CRT)

2. Liquid Crystal Display Monitors (LCD)
3. TFT Monitors
4. Light Emitting Diodes Monitors (LED)
5. DLP Monitors
6. Touchscreen Monitor
7. Plasma Screen Monitors
8. OLED Monitors (Organic Light Emitting Diode)

Output Devices of computer In Hindi

2. Printer
Printers are the basic and common output devices used in the offices. They
take electronic data and gives the output as the hard copy. You can use
these printers for printing Images and Texts on the paper. The most
common printers used are Inkjet and Laser printers. Color prints and black
white prints are available in the printer.

Printers used to have their own ports. But, modern printers get connected
to the PC through USB ports cable. Also, there are printers available that
can connect via Bluetooth or WiFi.

Function

Print out the hardcopy of data as Text and Image onto the paper.

The printers have developed so much. The use of 3D printers has made
it possible to print out prosthetic biological body parts for humans as well. It
is also that China can build a house with this technology. It only takes
about 72 hours to do so.
Types of Printers

1. Laser Printers
2. Solid Ink Printers
3. LED Printers
4. Business Inkjet Printers
5. Home Inkjet Printers
6. Multifunction Printers
7. Dot Matrix Printers
8. 3D Printers

3. Audio Speakers
Speakers convert the signals into sound. Sound cards convert the signal so
that we can hear as a sound. In the desktop computer, you need to
connect an external speaker to hear the sound. In laptop computers, there
are inbuilt speakers.

Modern speakers are connected through Bluetooth these days.

Function

To convert the electronic signals into audio.

We can hear different forms of music such as gaming, music, news, radio,
etc. High strength speakers are used mostly in Studios, Cinema Hall,
Theatres, Concerts, etc.

You can see the speakers in different forms like Horns, Alarm, Notifier, etc.

Types of Speakers

1. Dynamic
2. Subwoofer
3. Horn
 4. Electrostatic
5. Planar-Magnetic

4. Projector
You might have watched a movie on movie theatres. The movie is projected
to the big white screen by the projector. The projector helps in the
projection of video, image, or any graphical contents to the wall.

These projectors can be connected to the PC through HDMI or VGA Cable.

Function

To project images, videos and graphical contents on to the wall.

Projectors are used in presentations, watching movies, teachings, etc.

Types of Projectors

1. Digital Light Processing (DLP)

2. Liquid Crystal Display (LCD)
3. Cathode Ray Tube (CRT)

5. Sound Card
Sound card process the signal from the motherboard and converts it to the
audio. They help speakers and headphones to function. These components
are not essential but they enhance the audio experience. If you listen to
music, watch videos, play games, record audio, then you need a sound
card.

Function

Process the electronic signal and help speakers to produce sound.

Types of Sound Card

1. On-Board Sound Cards

2. USB Sound Cards
3. PCMCIA / PC Cardbus

6. Video Card
The video card is the slot on the motherboard for enhancing the visuals of
video and graphical contents. It enhances the experiences of watching
movies, photos, playing games, etc. It increases the display quality of the
monitor.

Every computer has a default video card. You can add an external video
card that boosts up the visual elements. It gives faster and detailed visual
content.

7. Plotter
The plotter is similar to the print output devices like the office printer. This
hardware helps to print wide format materials like banners, brochures,
pamphlets, etc. This is a wide sized printer.

Input-Output Interface
Input-Output Interface is used as an method which helps in transferring of information
between the internal storage devices i.e. memory and the external peripheral device .
A peripheral device is that which provide input and output for the computer, it is also
called Input-Output devices. For Example: A keyboard and mouse provide Input to
the computer are called input devices while a monitor and printer that provide output
to the computer are called output devices. Just like the external hard-drives, there is
also availability of some peripheral devices which are able to provide both input and
output.
 Input-Output Interface

In micro-computer base system, the only purpose of peripheral devices is just to

provide special communication links for the interfacing them with the CPU. To
resolve the differences between peripheral devices and CPU, there is a special need
for communication links.
The major differences are as follows:
1. The nature of peripheral devices is electromagnetic and electro-mechanical. The
nature of the CPU is electronic. There is a lot of difference in the mode of
operation of both peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of
peripheral devices are slow than CPU.
3. In peripheral devices, data code and formats are differ from the format in the CPU
and memory.
4. The operating mode of peripheral devices are different and each may be controlled
so as not to disturb the operation of other peripheral devices connected to CPU.
There is a special need of the additional hardware to resolve the differences between
CPU and peripheral devices to supervise and synchronize all input and output
devices.

Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-output

devices.
2. It selects the input-output device which is appropriate for the interpretation of the
input-output device.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.
Device controller
Device drivers are software modules that can be plugged into an OS to handle a
particular device. Operating System takes help from device drivers to handle all I/O
devices.
The Device Controller works like an interface between a device and a device driver.
I/O units (Keyboard, mouse, printer, etc.) typically consist of a mechanical
component and an electronic component where electronic component is called the
device controller.
There is always a device controller and a device driver for each device to
communicate with the Operating Systems. A device controller may be able to
handle multiple devices. As an interface its main task is to convert serial bit stream
to block of bytes, perform error correction as necessary.
Any device connected to the computer is connected by a plug and socket, and the
socket is connected to a device controller. Following is a model for connecting the
CPU, memory, controllers, and I/O devices where CPU and device controllers all
use a common bus for communication.

Device Driver
Device driver is a specialized software program running as part of the
operating system that interacts with a device attached to a computer. It is
just a code inside the OS that allows to be empowered with the specific
commands needed to operate the associated device. OS manages and
controls the devices attached to the computer by providing required
functionality to the software programs for controlling different aspects of
the devices. OS does so by combining both hardware and software
techniques. The OS interacts with the I/O hardware via the device
driver software. The device driver software comes along with each device.
Device drivers are basically low-level programs that allow the kernel of
computer to communicate with different hardware devices, without
worrying about the details of how the hardware works. So, they provide the
kernel with the appropriate knowledge on how to control the devices.

– A device driver is a special type of software program that allows a

computer to interface and interact with a specific hardware device, such as
a printer, sound card, graphics card, etc., so that the computer should know
the configuration and specification of that device. Without the correct
device driver, the corresponding device won’t work correctly. Device
controller, on the other hand, is nothing but a hardware unit attached to the
I/O bus of the computer and provides an intermediate layer which receives
commands from the OS, such as read, write or more complex commands.

Significance

– A device driver is a software program with which the device controller

interacts with the operating system. Each device has its own device driver
and a device controller that is specific to the device. The device driver
presents a uniform interface to the operating system by hiding the
differences among the different device controllers. Device controllers, on
the other hand, operate on a bus, a device or a port, and control the signals
on the wires of the bus or the port. It makes sense of the incoming and
outgoing signals of the CPU.

Input Output Techniques

Data transfer between the CPU and I/O devices may be handled in a variety of
techniques. Some techniques use the CPU as an intermediate path, others
transfer the data directly to and from the memory unit. Data transferred to and
from peripherals is said to be I/O communication. Generally, I/O communication
is done in 3 ways. These are
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct Memory Access (DMA)

Programmed I/O:
In the programmed I/O method, the I/O device doesn’t have direct access to
memory. The data transfer from an I/O device to memory requires the execution
of a program or several instructions by CPU So that this method is said to be
Programmed I/O. In this method, the CPU stays in a program loop until the I/O
unit indicates that is ready for data transfer. It is a time-consuming process for
CPU. The programmed I/O method is particularly useful in small low-speed
computers.
The CPU sends the ‘Read‘ command to I/O device and wait in the program loop
until it receives a response from I/O device.
Overview of Programmed I/O

• Processor executes an I/O instruction by issuing command to appropriate I/O module

• I/O module performs the requested action and then sets the appropriate bits in the I/O status
register – I/O module takes not further action to alert the processor – it does not interrupt the
processor
• The processor periodically checks the status of the I/O module until it determines that the
operation is complete
I/O Commands

The processor issues an address, specifying I/O module and device, and an I/O command.
The commands are:
• Control: activate a peripheral and tell it what to do
• Test: test various status conditions associated with an I/O module and its peripherals
• Read: causes the I/O module to obtain an item of data from the peripheral and place it into
an internal register
• Write: causes the I/O module to take a unit of data from the data bus and transmit it to the
peripheral
Interrupt-initiated I/O:
The problem in programmed I/O is that the CPU has to wait for the ready signal
from the I/O device. The alternative method for this problem is Interrupt-initiated
I/O or Interrupt driven I/O. In this method, the CPU issue a read command to I/O
device about the status, and then go on to do some useful work. When the I/O
device ready, the I/O device sends an interrupt signal to the processor.

When the CPU received the interrupt signal from I/O device, it checks the status,
if the status is ready, then the CPU read the word form I/O device and write the
word into the main memory. If the operation was done successfully, then the
processor goes on to the next instruction.
• Overcomes the processor having to wait long periods of time for I/O modules
• The processor does not have to repeatedly check the I/O module status

I/O module view point

• I/O module receives a READ command form the processor
• I/O module reads data from desired peripheral into data register
• I/O module interrupts the processor
• I/O module waits until data is requested by the processor
• I/O module places data on the data bus when requested

Processor view point

• The processor issues a READ command
• The processor performs some other useful work
• The processor checks for interrupts at the end of the instruction cycle
• The processor saves the current context when interrupted by the I/O module
• The processor read the data from the I/O module and stores it in memory
• The processor the restores the saved context and resumes execution

Design Issues
How does the processor determine which device issued the interrupt
How are multiple interrupts dealt with
Device identification
• Multiple interrupt lines – each line may have multiple I/O modules
• Software poll – poll each I/O module
o Separate command line – TESTI/O
o Processor read status register of I/O module
o Time consuming
• Daisy chain
o Hardware poll
o Common interrupt request line
o Processor sends interrupt acknowledge
 o Requesting I/O module places a word of data on the data lines – “vector” that uniquely
identifies the I/O module – vectored interrupt
• Bus arbitration
o I/O module first gains control of the bus
o I/O module sends interrupt request
o The processor acknowledges the interrupt request
o I/O module places its vector of the data lines
Multiple interrupts
• The techniques above not only identify the requesting I/O module but provide methods of
assigning priorities
• Multiple lines – processor picks line with highest priority
• Software polling – polling order determines priority
• Daisy chain – daisy chain order of the modules determines priority
• Bus arbitration – arbitration scheme determines priority

Direct Access Memory (DMA):

Direct Memory Access (DMA) is a process where the data is transformed
between the microprocessor (CPU), memory and peripheral devices directly
without the involvement of the microprocessor (CPU). It is first initialized by CPU
and the CPU should send some useful information to DMA controller and letting
the DMA controller is to manage the memory buses directly, it would improve
the speed of data transfer. This process is managed by a chip known as a DMA
Controller (DMAC). The CPU is idle and it has no control of the memory buses. A
DMA controller takes over the buses to manage the transfer directly between
the I/O device and memory.

DMA Function
• DMA module on system bus used to mimic the processor.
• DMA module only uses system bus when processor does not need it.
• DMA module may temporarily force processor to suspend operations – cycle stealing.
DMA Operation
• The processor issues a command to DMA module
o Read or write o I/O device address using data lines
o Starting memory address using data lines – stored in address register
o Number of words to be transferred using data lines – stored in data register
• The processor then continues with other work
• DMA module transfers the entire block of data – one word at a time – directly to or from
memory without going through the processor
• DMA module sends an interrupt to the processor when complete

DMA and Interrupt Breakpoints during Instruction Cycle

• The processor is suspended just before it needs to use the bus.

• The DMA module transfers one word and returns control to the processor.
• Since this is not an interrupt the processor does not have to save context.
• The processor executes more slowly, but this is still far more efficient that either
programmed or interrupt-driven I/O.

DMA Configurations
• Single bus – detached DMA module
• Each transfer uses bus twice – I/O to DMA, DMA to memory
• Processor suspended twice

• Single bus – integrated DMA module

• Module may support more than one device
• Each transfer uses bus once – DMA to memory
• Processor suspended once

• Separate I/O bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once – DMA to memory
• Processor suspended once

Input/Output Processor
The DMA mode of data transfer reduces CPU’s overhead in handling I/O
operations. It also allows parallelism in CPU and I/O operations. Such
parallelism is necessary to avoid wastage of valuable CPU time while
handling I/O devices whose speeds are much slower as compared to CPU.
The concept of DMA operation can be extended to relieve the CPU further
from getting involved with the execution of I/O operations. This gives rises to
the development of special purpose processor called Input-Output
Processor (IOP) or IO channel.
The Input Output Processor (IOP) is just like a CPU that handles the details
of I/O operations. It is more equipped with facilities than those are available
in typical DMA controller. The IOP can fetch and execute its own instructions
that are specifically designed to characterize I/O transfers. In addition to the
I/O – related tasks, it can perform other processing tasks like arithmetic,
logic, branching and code translation. The main memory unit takes the
pivotal role. It communicates with processor by the means of DMA.
The Input Output Processor is a specialized processor which loads and
stores data into memory along with the execution of I/O instructions. It acts
as an interface between system and devices. It involves a sequence of
events to executing I/O operations and then store the results into the
memory.

Advantages –
 The I/O devices can directly access the main memory without the
intervention by the processor in I/O processor based systems.
 It is used to address the problems that are arises in Direct memory
access method.

External Comunication Interface

Communication Interface is essential for communicating with various subsystems of Embedded
System and with the external world.
ES-embedded system

External communication interfaces

RS-232:legacy,wired ,asynchronous serial interface. uses handshaking & control signals
for data transmissionUSB(universal serial bus):wired high speed bus. Core group
members, star topology:1 master, many slaves IrDA(Infrared):line of sight based
wrireless deviceBT(bluetooth):low cost low power short range wireless tech, bluetooth
protocol stack.Wi-Fi:networked communication devices, supports IP protocol.requires an
agent:wifi router/ access point.ZigBee:low power low cost network communication
protocol, low data rate, secure communication for Wireless PANGPRS(general
packet radio service):comm technique for transferring data over a mobile network.
Data split into various packets.
UNIT-7
Central Processing Unit:Instuction Set Arctitecture
The instruction set or the instruction set architecture (ISA) is the set of basic instructions that
a processor understands. The instruction set is a portion of what makes up an architecture.
The first two philosophies to instruction sets were: reduced (RISC) and complex (CISC).

CISC
Complex Instruction Set Computer (CISC) is rooted in the history of computing. Originally
there were no compilers and programs had to be coded by hand one instruction at a time. To
ease programming more and more instructions were added. Many of these instructions are
complicated combination instructions such as loops. In general, more complicated or specialized
instructions are inefficient in hardware, and in a typically CISC architecture the best performance
can be obtained by using only the most simple instructions from the ISA.
The most well known/commoditized CISC ISAs are the Motorola 68k and Intel x86 architectures.

RISC
Reduced Instruction Set Computer (RISC) was realized in the late 1970s by IBM. Researchers
discovered that most programs did not take advantage of all the various address modes that
could be used with the instructions. By reducing the number of address modes and breaking
down multi-cycle instructions into multiple single-cycle instructions several advantages were
realized:

 compilers were easier to write (easier to optimize).

 performance is increased for programs that did simple operations.
 the clock rate can be increased since the minimum cycle time was determined by the longest
running instruction.
The most well known/commoditized RISC ISAs are the PowerPC, ARM, MIPS and SPARC
architectures.
In the last few decades all CPUs made are GPR processors. The 2 major reasons
are that registers are faster than memory, the more data that can be kept internaly in
the CPU the faster the program will run. The other reason is that registers are easier
for a compiler to use.

Following are the instruction sets found in many of the microprocessors used
today. The ISA of a processor can be described using 5 catagories:

Operand Storage in the CPU

Where are the operands kept other than in memory?
Number of explicit named operands
How many operands are named in a typical instruction.
Operand location
Can any ALU instruction operand be located in memory? Or must all
operands be kept internaly in the CPU?
Operations
What operations are provided in the ISA.
Type and size of operands
What is the type and size of each operand and how is it specified?

Of all the above the most distinguishing factor is the first.

The 3 most common types of ISAs are:

1. Stack - The operands are implicitly on top of the stack.

2. Accumulator - One operand is implicitly the accumulator.
3. General Purpose Register (GPR) - All operands are explicitely mentioned,
they are either registers or memory locations.

Look at the assembly code of

C = A + B;

in all 3 architectures:

Stack Accumulator GPR

PUSH A LOAD A LOAD R1,A

PUSH B ADD B ADD R1,B

ADD STORE C STORE R1,C

POP C - -

Not all processors can be neatly tagged into one of the above catagories. The i8086
has many instructions that use implicit operands although it has a general register
set. The i8051 is another example, it has 4 banks of GPRs but most instructions
must have the A register as one of its operands.
What are the advantages and disadvantages of each of these approachs?
Stack

Advantages: Simple Model of expression evaluation (reverse polish). Short

instructions.
Disadvantages: A stack can't be randomly accessed This makes it hard to generate
eficient code. The stack itself is accessed every operation and becomes a
bottleneck.

Accumulator

Advantages: Short instructions.

Disadvantages: The accumulator is only temporary storage so memory traffic is
the highest for this approach.

GPR

Advantages: Makes code generation easy. Data can be stored for long periods in
registers.
Disadvantages: All operands must be named leading to longer instructions.

Instruction Sets Characteristics

Important instruction set design issues
The following are the most important fundamental design issues in
instruction design.

(i) Operation Repertoire : This issue is concerned with how many and
which operations are to be provided, and how complex operations should
be

(ii) Data Types : This issue deals with the various types of data upon which
operations are performed.

(iii) Instruction Format : This issue is concerned with instruction length (in
bits), number of addresses, size of various fields and so on.

(iv) Registers : This is concerned with the number of registers that can be
referenced by instructions, and their use.
 (v) Addressing: This issue is concerned with the mode or modes by which
the address of an operand is specified.

These fundamental issues are interrelated with each other and so they
must be considered together while designing an instruction set.

Types of instructions (Operations in the Instruction set)

The tasks carried out by a computer program consist of a sequence of small

steps, such as multiplying two numbers, moving a data from a register to a memory
location, testing for a particular condition like zero, reading a character from the
input device or sending a character to be displayed to the output device, etc.. A
computer must have the following types of instructions:

 Data transfer instructions

 Data manipulation instructions
 Program sequencing and control instructions
 Input and output instructions

Data transfer instructions perform data transfer between the various storage
places in the computer system, viz. registers, memory and I/O. Since, both the
instructions as well as data are stored in memory, the processor needs to read the
instructions and data from memory. After processing, the results must be stored in
memory. Therefore, two basic operations involving the memory are needed,
namely, Load (or Read or Fetch) and Store (or Write). The Load operation
transfers a copy of the data from the memory to the processor and the Store
operation moves the data from the processor to memory. Other data transfer
instructions are needed to transfer data from one register to another or from/to I/O
devices and the processor.

Data manipulation instructions perform operations on data and indicate the

computational capabilities for the processor. These operations can be arithmetic
operations, logical operations or shift operations. Arithmetic operations include
addition (with and without carry), subtraction (with and without borrow),
multiplication, division, increment, decrement and finding the complement of a
number. The logical and bit manipulation instructions include AND, OR, XOR,
Clear carry, set carry, etc. Similarly, you can perform different types of shift and
rotate operations.

We generally assume a sequential flow of instructions. That is, instructions that

are stored in consequent locations are executed one after the other. However, you
have program sequencing and control instructions that help you change the flow of
the program. This is best explained with an example. Consider the task of adding a
list of n numbers. A possible sequence is given below.

Move DATA1, R0
Add DATA2, R0
Add DATA3, R0
Add DATAn, R0
Move R0, SUM
The addresses of the memory locations containing the n numbers are
symbolically given as DATA1, DATA2, . . , DATAn, and a separate Add
instruction is used to add each Data to the contents of register R0. After all the
numbers have been added, the result is placed in memory location SUM. Instead of
using a long list of Add instructions, it is possible to place a single Add instruction
in a program loop, as shown below:

Move N, R1
Clear R0
LOOP Determine address of “Next” number and add “Next” number to R0
Decrement R1
Branch > 0, LOOP
Move R0, SUM

The loop is a straight-line sequence of instructions executed as many times as

needed. It starts at location LOOP and ends at the instruction Branch>0. During
each pass through this loop, the address of the next list entry is determined, and
that entry is fetched and added to R0. The address of an operand can be specified
in various ways.
Branch instruction is accomplished by recording the required information in
individual bits, often called condition code flags. These flags are usually
grouped together in a special processor register called the condition code
register or status register. Individual condition code flags are set to 1 or cleared
to 0, depending on the outcome of the operation performed. Some of the
commonly used flags are: Sign, Zero, Overflow and Carry.
The interrupt procedure is, in principle, quite similar to a subroutine call except for
three variations: (1) The interrupt is usually initiated by an internal or external
signal apart from the execution of an instruction (2) the address of the interrupt
service program is determined by the hardware or from some information from the
interrupt signal or the instruction causing the interrupt; and (3) an interrupt
procedure usually stores all the information necessary to define the state of the
CPU rather than storing only the program counter. Therefore, when the processor
is interrupted, it saves the current status of the processor, including the return
address, the register contents and the status information called the Processor Status
Word (PSW), and then jumps to the interrupt handler or the interrupt service
routine. Upon completing this, it returns to the main program.

Input and Output instructions are used for transferring information between the
registers, memory and the input / output devices. It is possible to use special
instructions that exclusively perform I/O transfers, or use memory – related
instructions itself to do I/O transfers.

Addressing Modes-

The different ways of specifying the location of an operand in an instruction are called
as addressing modes.

Types of Addressing Modes-

In computer architecture, there are following types of addressing modes-

1. Implied / Implicit Addressing Mode
2. Stack Addressing Mode
3. Immediate Addressing Mode
4. Direct Addressing Mode
5. Indirect Addressing Mode
6. Register Direct Addressing Mode
7. Register Indirect Addressing Mode
8. Relative Addressing Mode
9. Indexed Addressing Mode
10. Base Register Addressing Mode
11. Auto-Increment Addressing Mode
12. Auto-Decrement Addressing Mode

1. Implied Addressing Mode-

In this addressing mode,

 The definition of the instruction itself specify the operands implicitly.
 It is also called as implicit addressing mode.

Examples-

 The instruction “Complement Accumulator” is an implied mode instruction.

 In a stack organized computer, Zero Address Instructions are implied mode
instructions.
(since operands are always implied to be present on the top of the stack)

2. Stack Addressing Mode-

In this addressing mode,

 The operand is contained at the top of the stack.

Example-

ADD
 This instruction simply pops out two symbols contained at the top of the stack.
 The addition of those two operands is performed.
 The result so obtained after addition is pushed again at the top of the stack.

3. Immediate Addressing Mode-

In this addressing mode,

 The operand is specified in the instruction explicitly.
 Instead of address field, an operand field is present that contains the operand.
 Examples-

 ADD 10 will increment the value stored in the accumulator by 10.

 MOV R #20 initializes register R to a constant value 20.

4. Direct Addressing Mode-

In this addressing mode,

 The address field of the instruction contains the effective address of the operand.
 Only one reference to memory is required to fetch the operand.
 It is also called as absolute addressing mode.

Example-

 ADD X will increment the value stored in the accumulator by the value stored at
memory location X.
AC ← AC + [X]
 5. Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction specifies the address of memory location that
contains the effective address of the operand.
 Two references to memory are required to fetch the operand.

Example-

 ADD X will increment the value stored in the accumulator by the value stored at
memory location specified by X.
AC ← AC + [[X]]

6. Register Direct Addressing Mode-

In this addressing mode,

 The operand is contained in a register set.
 The address field of the instruction refers to a CPU register that contains the operand.
 No reference to memory is required to fetch the operand.
 Example-

 ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]

NOTE-

It is interesting to note-
 This addressing mode is similar to direct addressing mode.
 The only difference is address field of the instruction refers to a CPU register instead
of main memory.

7. Register Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction refers to a CPU register that contains the effective
address of the operand.
 Only one reference to memory is required to fetch the operand.
 Example-

 ADD R will increment the value stored in the accumulator by the content of memory
location specified in register R.
AC ← AC + [[R]]

NOTE-

It is interesting to note-
 This addressing mode is similar to indirect addressing mode.
 The only difference is address field of the instruction refers to a CPU register.

8. Relative Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of program counter
with the address part of the instruction.

Effective Address

= Content of Program Counter + Address part of the instruction

 NOTE-

 Program counter (PC) always contains the address of the next instruction to be
executed.
 After fetching the address of the instruction, the value of program counter immediately
increases.
 The value increases irrespective of whether the fetched instruction has completely
executed or not.

9. Indexed Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of index register
with the address part of the instruction.

Effective Address

= Content of Index Register + Address part of the instruction

 10. Base Register Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of base register
with the address part of the instruction.

Effective Address

= Content of Base Register + Address part of the instruction

 11. Auto-Increment Addressing Mode-

 This addressing mode is a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

= Content of Register

In this addressing mode,

 After accessing the operand, the content of the register is automatically incremented
by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 Only one reference to memory is required to fetch the operand.

Example-
 Assume operand size = 2 bytes.
Here,
 After fetching the operand 6B, the instruction register R AUTO will be automatically
incremented by 2.
 Then, updated value of RAUTO will be 3300 + 2 = 3302.
 At memory address 3302, the next operand will be found.

NOTE-

In auto-increment addressing mode,

 First, the operand value is fetched.
 Then, the instruction register RAUTO value is incremented by step size ‘d’.

12. Auto-Decrement Addressing Mode-

 This addressing mode is again a special case of Register Indirect Addressing Mode
where-
 Effective Address of the Operand

= Content of Register – Step Size

In this addressing mode,

 First, the content of the register is decremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 After decrementing, the operand is read.
 Only one reference to memory is required to fetch the operand.

Example-

Assume operand size = 2 bytes.

Here,
 First, the instruction register RAUTO will be decremented by 2.
 Then, updated value of RAUTO will be 3302 – 2 = 3300.
 At memory address 3300, the operand will be found.
 NOTE-

In auto-decrement addressing mode,

 First, the instruction register RAUTO value is decremented by step size ‘d’.
 Then, the operand value is fetched.

Instruction format

1. Instruction format describes the internal structures (layout design) of the bits of
an instruction, in terms of its constituent parts.
2. An Instruction format must include an opcode, and address is dependent on an
availability of particular operands.
3. The format can be implicit or explicit which will indicate the addressing mode for
each operand.
4. Designing of an Instruction format is very complex. As we know a computer
uses a variety of instructional. There are many designing issues which affect the
instructional design, some of them are given are below:
o Instruction length: It is a most basic issue of the format design. A longer
will be the instruction it means more time is needed to fetch the
instruction.
o Memory size: If larger memory range is to be addressed then more bits
will be required in the address field.
o Memory organization: If the system supports the virtual memory then
memory range which needs to be addressed by the instruction, is larger
than the physical memory.
o Memory transfer length: Instruction length should be equal to the data
bus length or it should be multiple of it.

The most common fields are:

 Operation field specifies the operation to be performed like addition.

 Address field which contains the location of the operand, i.e., register or
memory location.

 Mode field which specifies how operand is to be founded.

Instruction is of variable length depending upon the number of addresses it

contains. Generally, CPU organization is of three types based on the number
of address fields:
1. Single Accumulator organization

2. General register organization

3. Stack organization

In the first organization, the operation is done involving a special register

called the accumulator. In second on multiple registers are used for the
computation purpose. In the third organization the work on stack basis
operation due to which it does not contain any address field. Only a single
organization doesn’t need to be applied, a blend of various organizations is
mostly what we see generally.

Based on the number of address, instructions are

classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the
procedure.

1. Zero Address Instructions –

1. A stack-based computer does not use the address field in the instruction.
To evaluate an expression first it is converted to revere Polish Notation
i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location
1.

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

1.
2. One Address Instructions –
This uses an implied ACCUMULATOR register for data manipulation. One
operand is in the accumulator and the other is in the register or memory
location. Implied means that the CPU already knows that one operand is
in the accumulator so there is no need to specify it.

1.
Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location
1.

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STOR
E T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STOR
E X M[X] = AC

1.
1. Two Address Instructions –
This is common in commercial computers. Here two addresses can be
specified in the instruction. Unlike earlier in one address instruction, the
result was stored in the accumulator, here the result can be stored at
different locations rather than just accumulators, but require more number
of bit to represent address.

1. Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location
1.

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

1.
2. Three Address Instructions –
This has three address field to specify a register or a memory location.
Program created are much short in size but number of bits per instruction
increase. These instructions make creation of program much easier but it
does not mean that program will run much faster because now instruction
only contain more information but each micro operation (changing content
of register, loading address in address bus etc.) will be performed in one
cycle only.

1.
Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location
1.

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

 MUL X, R1, R2 M[X] = R1 * R2

1.

UNIT-8:Registers,Micro-Operationsand Instructions Execution

Basic Structure Of CPU(Central Processing Unit)

A central processing unit (CPU), also called a central processor, main processor or
just processor, is the electronic circuitry that executes instructions comprising a computer
program.
The form, design, and implementation of CPUs have changed over time, but their fundamental
operation remains almost unchanged. Principal components of a CPU include the arithmetic logic
unit (ALU) that performs arithmetic and logic operations, processor registers that
supply operands to the ALU and store the results of ALU operations, and a control unit that
orchestrates the fetching (from memory) and execution of instructions by directing the
coordinated operations of the ALU, registers and other components.

Block –Diagram
CPU itself has following three components.

 Memory or Storage Unit

 Control Unit
 ALU(Arithmetic Logic Unit)
Memory or Storage Unit/Registers
This unit can store instructions, data, and intermediate results. This unit supplies
information to other units of the computer when needed. It is also known as internal
storage unit or the main memory or the primary storage or Random Access Memory
(RAM).
Its size affects speed, power, and capability. Primary memory and secondary
memory are two types of memories in the computer. Functions of the memory unit
are −
 It stores all the data and the instructions required for processing.
 It stores intermediate results of processing.
 It stores the final results of processing before these results are released to an
output device.
 All inputs and outputs are transmitted through the main memory.

Control Unit
This unit controls the operations of all parts of the computer but does not carry out
any actual data processing operations.
Functions of this unit are −
 It is responsible for controlling the transfer of data and instructions among
other units of a computer.
 It manages and coordinates all the units of the computer.
 It obtains the instructions from the memory, interprets them, and directs the
operation of the computer.
 It communicates with Input/Output devices for transfer of data or results from
storage.
 It does not process or store data.

ALU (Arithmetic Logic Unit)

This unit consists of two subsections namely,

 Arithmetic Section
 Logic Section
Arithmetic Section
Function of arithmetic section is to perform arithmetic operations like addition,
subtraction, multiplication, and division. All complex operations are done by making
repetitive use of the above operations.
Logic Section
Function of logic section is to perform logic operations such as comparing,
selecting, matching, and merging of data.

Register Organization
Register organization is the arrangement of the registers in the processor.
The processor designers decide the organization of the registers in a
processor. Different processors may have different register organization.
Depending on the roles played by the registers they can be categorized
into two types, user-visible register and control and status register.

What is Register?
Registers are the smaller and the fastest accessible memory units in the
central processing unit (CPU). According to memory hierarchy, the
registers in the processor, function a level above the main
memory and cache memory. The registers used by the central unit are
also called as processor registers.

A register can hold the instruction, address location, or operands.

Sometimes, the instruction has register as a part of itself.

Types of Registers
As we have discussed above, registers can be organized into two main
categories i.e. the User-Visible Registers and the Control and Status
Registers. Although we can’t separate the registers in the processors
clearly among these two categories.

This is because in some processors, a register may be user-visible and in

some, the same may not be user-visible. But for our rest of discussion
 regarding register organization, we will consider these two categories of
register.

1. User Visible Registers

o General Purpose Register
o Data Register
o Address Register
o Condition Codes
2. Control and Status Registers
o Program Counter
o Instruction Register
o Memory Address Register
o Memory Buffer Register

User-Visible Registers
These registers are visible to the assembly or machine language
programmers and they use them effectively to minimize the memory
references in the instructions. Well, these registers can only
be referenced using the machine or assembly language.

The registers that fall in this category are discussed below:

1. General Purpose Register

The general-purpose registers detain both the addresses or the data.
Although we have separate data registers and address registers. The
general purpose register also accepts the intermediate results in the
course of program execution.

Well, the programmers can restrict some of the general-purpose registers

to specific functions. Like, some registers are specifically used for stack
operations or for floating-point operations. The general-purpose register
can also be employed for the addressing functions.
2. Data Register
The term itself describes that these registers are employed to hold the
data. But the programmers can’t use these registers for calculating
operand address.

3. Address Register
Now, the address registers contain the address of an operand or it can
also act as a general-purpose register. An address register may be
dedicated to a certain addressing mode. Let us understand this with the
examples.

(a) Segment Pointer Register

A memory divided in segments, requires a segment register to hold the
base address of the segment. There can be multiple segment registers.
As one segment register can be employed to hold the base address of the
segment occupied by the operating system. The other segment register
can hold the base address of the segment allotted to the processor.

(b) Index Register

The index register is employed for indexed addressing and it is initial
value is 0. Generally, it used for traversing the memory locations. After
each reference, the index register is incremented or decremented by 1,
depending upon the nature of the operation.
Sometime the index register may be auto indexed.

(c) Stack Pointer Register

The stack register has the address that points the stack top.

4. Condition Code
Condition codes are the flag bits which are the part of the control register.
The condition codes are set by the processor as a result of an operation
and they are implicitly read through the machine instruction.

The programmers are not allowed to alter the conditional codes. Generally,
the condition codes are tested during conditional branch operation.
Control and Status Registers
The control and status register holds the address or data that is important
to control the processor’s operation. The most important thing is that
these registers are not visible to the users. Below we will discuss all the
control and status registers are essential for the execution of an
instruction.

1. Program Counter
The program counter is a processor register that holds the address of the
instruction that has to be executed next. It is a processor which updates
the program counter with the address of the next instruction to be fetched
for execution.

2. Instruction Register
Instruction register has the instruction that is currently fetched. It helps
in analysing the opcode and operand present in the instruction.

3. Memory Address Register (MAR)

Memory address register holds the address of a memory location.

4. Memory Buffer Register (MBR)

The memory buffer register holds the data that has to be written to a
memory location or it holds the data that is recently been read.

The memory address registers (MAR) and memory buffer registers (MBR)
are used to move the data between processor and memory.
 Apart from the above registers, several processors have a register termed
as Program Status Word (PSW). As the word suggests it contains
the status information.

The fields included in Program Status Word (PSW):


o Sign: This field has the resultant sign bit of the last arithmetic operation
performed.
o Zero: This field is set when the result of the operation is zero.
o Carry: This field is set when an arithmetic operation results in a carry
into or borrow out.
o Equal: If a logical operation results in, equality the Equal bit is set.
o Overflow: This bit indicates the arithmetic overflow.
o Interrupt: This bit is set to enable or disable the interrupts.
o Supervisor: This bit indicates whether the processor is executing in
the supervisor mode or the user mode.

So, these are the types of registers a processor has. The processor
designer organizes the registers according to the requirement of the
processor.

Micro-Operation
In computer central processing units, micro-operations (also known as micro-ops)
are the functional or atomic, operations of a processor. These are low level
instructions used in some designs to implement complex machine instructions. They
generally perform operations on data stored in one or more registers. They transfer
data between registers or between external buses of the CPU, also performs arithmetic
and logical operations on registers.
In executing a program, operation of a computer consists of a sequence of instruction
cycles, with one machine instruction per cycle. Each instruction cycle is made up of a
number of smaller units – Fetch, Indirect, Execute and Interrupt cycles. Each of these
cycles involves series of steps, each of which involves the processor registers. These
steps are referred as micro-operations. the prefix micro refers to the fact that each of
the step is very simple and accomplishes very little. Figure below depicts the concept
being discussed here.
Types of Micro-Operations

The micro-operations in digital computers are of 4 types:

1. Register transfer micro-operations transfer binary information

from one register to another.

2. Arithmetic micro-operations perform arithmetic operations on

numeric data stored in registers.

3. Logic micro-operations perform bit manipulation operation on

non-numeric data stored in registers.

4. Shift micro-operations perform shift micro-operations

performed on data.

Arithmetic Micro-Operations

Some of the basic micro-operations are addition, subtraction,

increment and decrement.
Add Micro-Operation
It is defined by the following statement:

R3 → R1 + R2

The above statement instructs the data or contents of register R1 to

be added to data or content of register R2 and the sum should be
transferred to register R3.
Subtract Micro-Operation
Let us again take an example:

R3 → R1 + R2' + 1

In subtract micro-operation, instead of using minus operator we

take 1's compliment and add 1 to the register which gets
subtracted, i.e R1 - R2 is equivalent to R3 → R1 + R2' + 1
Increment/Decrement Micro-Operation
Increment and decrement micro-operations are generally
performed by adding and subtracting 1 to and from the register
respectively.

R1 → R1 + 1

R1 → R1 – 1

Symbolic Designation Description

R3 ← R1 + R2 Contents of R1+R2 transferred to R3.

R3 ← R1 - R2 Contents of R1-R2 transferred to R3.

R2 ← (R2)' Compliment the contents of R2.

R2 ← (R2)' + 1 2's compliment the contents of R2.

R3 ← R1 + (R2)' + 1 R1 + the 2's compliment of R2 (subtraction).

R1 ← R1 + 1 Increment the contents of R1 by 1.

R1 ← R1 - 1 Decrement the contents of R1 by 1.

Logic Micro-Operations
These are binary micro-operations performed on the bits stored in
the registers. These operations consider each bit separately and
treat them as binary variables.

Let us consider the X-OR micro-operation with the contents of two

registers R1 and R2.

P: R1 ← R1 X-OR R2

In the above statement we have also included a Control Function.

Assume that each register has 3 bits. Let the content of R1

be 010 and R2 be 100. The X-OR micro-operation will be:

Shift Micro-Operations
These are used for serial transfer of data. That means we can shift
the contents of the register to the left or right. In the shift
left operation the serial input transfers a bit to the right most
position and in shift right operation the serial input transfers a bit
to the left most position.

There are three types of shifts as follows:

a) Logical Shift

It transfers 0 through the serial input. The symbol "shl" is used for
logical shift left and "shr" is used for logical shift right.
R1 ← she R1

R1 ← she R1

The register symbol must be same on both sides of arrows.

b) Circular Shift

This circulates or rotates the bits of register around the two ends
without any loss of data or contents. In this, the serial output of the
shift register is connected to its serial input. "cil" and "cir" is used
for circular shift left and right respectively.

c) Arithmetic Shift

This shifts a signed binary number to left or right. An arithmetic

shift left multiplies a signed binary number by 2 and shift
left divides the number by 2. Arithmetic shift micro-operation
leaves the sign bit unchanged because the signed number remains
same when it is multiplied or divided by 2.

Instruction Executions and Micro-operations

Concept of instruction execution using the micro-operation- A simple
instruction may require :

 Instruction fetch : fetching the instruction from the memory.

 Instruction decode : decode the instruction.

 Operand address calculation : find out the effective address of the operands.

 Execution : execute the instruction.

 Interrupt Acknowledge : perform an interrupt acknowledge cycle if an

interrupt request is pending.
 Let us explain how these steps of instruction execution can be broken down to
micro-operations. For simplifying the discussion, let us assume that the machine
has the structure as shown in Figure . In addition, let us also assume that the
instruction set of the machine has only two addressing modes direct and indirect
memory addresses and a memory access take same time as that of a register
access that is one clock cycle. The digital circuits, which we use now-a-days,
are constructed with NAND or NOR gate instead of AND-OR-NOT gates.
NAND and NOR gates are called universal gates and can be used to implement
any digital circuit

Instruction Fetch : In this phase the instruction is brought from the address
pointed by PC to instruction register. The steps required are :

Instruction Decode : This phase is performed under the control of the Control
Unit of the computer. The Control Unit determines the operation that is to .
performed and the addressing mode of the data. In example, the addressing
modes can be direct or indirect.

Operand Address Calculation : In actual machines the effective address may

be a memory address, register or I/O port address. The register reference
instructions such as complement R1, clear R2 etc., normally do not require any
memory reference (assuming register indirect addressing is not being used) and
can directly go to the execute cycle. However, the memory reference instruction
can use several addressing modes. Depending on the type of addressing the
effective address (EA) of operands in the memory is calculated. The calculation
of effective address may require more memory fetches (for example in the case
of indirect addressing), thus in this step we may calculate the effective address
as :
Thus, the address portion of IR now contains the effective address, which is the
direct address of the operand.

Execution : Now the instruction is ready for execution. A different opcode will
require different sequence of steps for the execution. Therefore, let us discuss a
few examples of execution of some simple instructions for the purpose of
identifying some of the steps needed during instruction execution. Let us start
the discussions with a simple case of addition instruction. Suppose, we have an
instruction : Add R1, A which adds the content of memory location A to R1
register storing the result in R1. This instruction will be executed in the
following steps :
 Interrupt Processing : On completion of the execution of an instruction, the
machine checks whether there is any pending interrupt request for the interrupts
that are enabled. If an enabled interrupt has occurred then that Interrupt may be
processed. The nature of interrupt varies from machine to machine. However,
let us discuss one simple illustration of interrupt processing events. A simple
sequence of steps followed in interrupt phase is

After completing the above interrupt processing, CPU will fetch the next
instruction that may be interrupt service program instruction. Thus, during this
time CPU might be doing the interrupt processing or executing the user
program. Note- each instruction of interrupt service program is executed as an
instruction in an instruction cycle.
Instruction Pipelining
An instruction pipeline is a technique used in the design of computer to increase
their instruction throughput (the number of instructions that can be executed in a
unit of time). The basic instruction cycle is broken up into a series called a
pipeline. Rather than processing each instruction sequentially (one at a time,
finishing one instruction before starting the next), each instruction is split up
into a sequence of steps so different steps can be executed concurrently (at the
same time) and in parallel (by different circuitry).

Pipelining increases instruction throughput by performing multiple operations at

the same time (concurrently), but does not reduce instruction latency (the time
to complete a single instruction from start to finish) as it still must go through
all steps.

The number of dependent steps varies with the machine architecture. For
example :

 The IBM Stretch project proposed the terms Fetch, Decode, and Execute that
have become common.

 The classic RISC pipeline comprises :

1. Instruction fetch

2. Instruction decode and register fetch

3. Execute

4. Memory access For example let us assume five-stage pipeline in a RISC

machine which can be given as follows :

IF = Instruction Fetch,

ID = Instruction Decode,

EX = Execute,

MEM = Memory access,

WB = Register write back.

The pipeline allows overlapped execution of instructions. Thus during the
course of execution of an instruction the following pipeline may be obtained as
given in the figure below :

In the fourth clock cycle (the dark column), the earliest instruction is in MEM
stage, and the latest instruction has not yet entered the pipeline.

A processor is said to be fully pipelined if it can fetch an instruction on every

cycle. Thus, if some instructions or conditions require delays that inhibit
fetching new instructions, the processor is not fully pipelined.

Pipeline Hazards

The model of sequential execution assumes that each instruction completes

before the next one begins. This assumption is not true on a pipelined processor.
A situation where the expected result is problematic is known as a hazard.
Pipeline hazards are situations that prevent the next instruction in the instruction
stream from executing during its designated clock cycle. The instruction is said
to be stalled. When an instruction is stalled, all instructions later in the pipeline
than the stalled instruction are also stalled. Instructions earlier than the stalled
one can continue. No new instructions are fetched during the stall. Three
classes of hazards are :

(i) Structural : Hardware cannot support this combination of

instructionstwo instructions need the same resource.
(ii) Data : Instruction depends on result of prior instruction still in
the pipeline.
(iii) Control : Pipelining of branches and other instruction that
change the PC.

Several approaches have been taken for reducing branch

penalties such as : (a) Stall– stop loading instruction until result
is available

(b) Predict– assume an outcome and continue fetching (undo if

prediction is wrong) or lose cycles only on mis-prediction

(c) Delayed branch–specify in architecture that the instruction

immediately following branch is always executed

Example :

Let as assume the following two register instructions to a

hypothetical RISC processor :

1 : add 1 to R5

2 : copy R5 to R6

If the processor has the 5 steps listed in the initial illustration,

instruction 1 will be fetched at time t1 and its execution will be
complete at t5. Instruction 2 will be fetched at t2 and will be
complete at t6. The first instruction might store the incremented
number into R5 as its fifth step (register write back) at t5. But
the second instruction may get the number from R5 (to copy to
R6) in its second step (instruction decode and register fetch) at
time t3 which will invokes a hazard as the first instruction has
not incremented the value by then.

Writing computer programs in a compiled language does not

raise these concerns, as the compiler are being designed to
generate machine code that will avoid hazards.
UNIT-9:ALU Organisation

Simple ALU organisation

An ALU comprises circuits which perform data processing micro-operations. The
simplest organisation in this respect for fixed point ALU was proposed by John von
Neumann in his IAS computer design.

Figure: Structure of a Fixed point Arithmetic logic unit

The above structure has 3 registers AC, MQ and DR for data storage. Let's presume
that they are equal to one word each. Please consider that Parallel adders and other
logic circuits (these are the arithmetic, logic circuits) have two inputs and just one
output in this figure. It suggests that any ALU operation at most can have two input
values and will produce single output along with other status bits. In the current
case the two inputs are AC and DR registers whereas output is AC register. AC and
MQ registers are usually used as a single AC.MQ register. This register is capable of
right or left shift operations. A number of the micro-operations which can be
defined on this ALU are:

Addition : AC ← AC + DR

Subtraction : AC ← AC - DR
AND : AC ← AC ^ DR

OR : AC ← AC DR

Exclusive OR : AC ← AC (+) DR

NOT : AC ← AC

In this ALU organisation division and multiplication were implemented employing

shift-add/subtract operations. MQ (Multiplier-Quotient register) is a special register
used for implementation of division and multiplication. We aren't providing details
of how this register can be used for implementing division and multiplication
algorithms. For more details on these algorithms please refer to further readings.
An example of this type of algorithm is Booth's algorithm and you should refer to it
in further readings.

For division or multiplication operations DR register stores the divisor or

multiplicand respectively. The result of division or multiplication on applying certain
algorithm can finally be attained in AC.MQ register combination. These operations
can be signified as:

Multiplication : AC.MQ ← DR × MQ

Division : AC.MQ ← MQ ÷ DR

DR is another significant register which is used for storing second operand. Actually
it acts as a buffer register that stores the data brought from memory for an
instruction. In machines where we have general purpose registers any of the
registers can be utilized like AC, MQ and DR.

Sample ALU Design

The ALU (Arithmetic Logic Unit) is the part of a CPU that actually does
calculations and condition testing.

For example, if you wish to add two binary numbers, it is the ALU that is
responsible for producing the result. If your program needs to execute
some code if two values are equal it is the ALU that performs the
comparison between the values and then sets flags if the condition is met
or not.
Modern CPUs consist of millions of transistors (even billions now!) and
cannot possibly be duplicated at home. But a simple CPU (say, a Z80, for
example) has only 8500 transistors. Computers in the past (such as many of
the IBM mainframe computers) were actually built with discrete 4000 and
7400 series chips.

4-bit ALU that will be constructed with 4000 series and 7400 series chips.

Project Prerequisites
Because this project is rather complex it need the following:

 Basic understanding of boolean concepts

 Basic understanding of logic gates

Binary Addition
Two fundamental ALU operations are addition and subtraction.

The Theory
Adding binary digits (individual bits) is rather easy
and is shown in the list below (all the possible
combinations):
 0+0=0
 0+1=1
 1+0=1
 1 + 1 = 10 (This is also 0 + carry bit)

But how do we add binary numbers that are more than one digit long? This
is where the carry bit comes into play and we need to use long addition.

Carry bits are used as shown below where "0(c)" means "no carry bit" and
"1(c)" means "carry bit".

 0 + 0 +0(c) = 0
 0 + 1 +0(c) = 1
 1 + 0 +0(c) = 1
  1 + 1 +0(c) = 10
 0 + 0 +1(c) = 1
 0 + 1 +1(c) = 10
 1 + 0 +1(c) = 10
 1 + 1 +1(c) = 11

If we wish to add 10 and 10 in binary form, we would start by writing them

down in the form of long addition. We add the bits up in columns using the
rules above starting from the far right and moving to the left. When we
have a carry from a bit addition, we move it one column to the left, where it
gets included in the addition as a bit.

Long addition of binary numbers

In this example, we are adding 1011 and 0001 (11 + 1 = 12). Starting from
the far right we add 1 + 1, which gives us 10 (0 and a carry bit). Then we
move to the next column (the second from the right) and add all the bits.
Notice how the carry bit is also included in this addition operation. This
means we are adding three digits: 1 (the carry bit), 1, and 0.

For more information about Boolean arithmetic, check out this section of
the AAC textbook.

So now that we can see how to add two binary numbers on paper, let’s see
if we can make a circuit that adds two binary bits!
The Circuit
The half adder has two inputs and two outputs as shown in the diagram
below. The two inputs represent two individual bits, the Sum output
represents the sum of the two bits in the form of a single bit and the Carry
output is the carry bit from the addition.

Half adder circuit , which uses an AND gate and an exclusive-OR (XOR) gate

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Truth table for half adder

But what is wrong with this circuit? This circuit cannot take in a carry from a
previous operation! So how do we fix this? Well, this circuit isn’t called a
half adder for nothing! If we use two of these adders and an OR gate, we
can create a full adder that has two bit inputs, a carry in, a sum out, and a
carry out.

A full adder made by using two half adders and an OR gate

Unfortunately, for the 4-bit ALU, it would be impractical to use discrete

chips to create a 4-bit adder. So we will cheat and use a 4008 4-bit adder
IC. You can pick these up for a few dollars on eBay:
 4008 4-bit full adder pinout. Adapted from this image.

Binary Subtraction
The Theory
Now that we can add two 4-bit numbers, to do subtract binary numbers,
we will implement a binary system called “two’s complement”. The system
has a few rules:

1. To negate a number (e.g., change 5 into -5), flip all the bits and add 1.
2. A number is negative if the MSB (most significant bit) is 1. For example:

o 10010 is negative
o 00010 is positive

Note that by following rule 1 you can determine the value of a negative
binary number:

 0001 = 1: Negate this = (1110 + 1 = 1111) = -1

 1001 = -7: Negate this = (0110 + 1 = 0111) = -7
 0110 = 6: Negate this = (1001 + 1 = 1010) = -6

The two’s complement technique is beneficial because it allows us to

perform both addition and subtraction using the same adder circuit. So if
we wish to turn our 4-bit adder into a 4-bit adder/subtractor, we just need
to incorporate a single 4070 IC (quad XOR). We feed the binary number
inputs into one input of each XOR gate, use the other XOR input as an
add/subtract line, and then feed this same line into the carry in of the
adder.
When we wish to subtract B from A, we make the subtract line high. This
does two things:

 Flips all the incoming bits on input B

 Adds one to the adder

The complete 4-bit adder/subtractor

The final circuit will also use a 74HC125 quad buffer on the output so that
the adder/subtractor unit can be connected to a common data bus for the
output. The buffer also has an enable line that allows us to choose the
output from the adder/subtractor.
With the adding/subtracting unit done, it's time to look at the logical
functions.
Logical Functions
Logical functions are useful when bit manipulation is needed. Imagine a
microcontroller that has an 8-bit port, and you use the lower 4 bits to read
from a 4-bit data bus. When you read from the port you will need to
remove the upper four bits, as those bits can affect program execution. So
to remove these bits, you can mask them out with a logical AND function.
This function will AND bits from one word (the port) with another number
(the number that will remove the upper four bits). If we AND the port with
0x0F (0b00001111), we preserve the lower four bits (because x AND 1 = x)
and remove the upper four bits (because x AND 0 = 0).

 AND is used to remove bits

 NOT is used when you need to flip all the bits (0000 will become 1111)
 OR is used to merge bits (0110 OR 0001 is 0111)
 XOR is used to flip selected bits (0101 XOR 0100 is 0001)

The logical units in our ALU are AND, OR, XOR, and NOT gates connected
to buffers. An enable line feeds into each bus buffer for each logical unit so
that each unit can be selected individually.

 4081 - Quad AND gate

 4070 - Quad XOR gate
 4071 - Quad OR gate
 4049 - Hex NOT gate
 74HC125 - Output buffers (for bus isolation)
 Logic gates showing the four logical functions of our ALU

Note:

 A and B represent bit 0, 1, 2, or 3 from word A and the corresponding

bit from word B.
 NOT operations involve only one word; each bit in the word is
complemented, regardless of the state of the other word.

Bit Shifting & Comparisons

Bit shifting is also a very important function. These functions are commonly
found in microcontrollers with serial ports where data is streamed in bit by
bit. This means that, as the bits arrive, you need to take that bit, place it in
some byte at the beginning (or end), and then shift all the bits in the byte
either left or right (depending on where you put the incoming bit).
Interestingly, a bit shift to the right (e.g., 0010 becomes 0001) is equivalent
to division by two, and a bit shift to the left (e.g., 0010 becomes 0100) is
equivalent to multiplication by two.
Bit shifting can be done quite easily. The only chip needed is a buffer
because the physical data lines are simply rearranged.

Rotate left
 Rotate right

For a rotate left:

 Bit 0 is connected to bit 1 on the output

 Bit 1 is connected to bit 2 on the output
 Bit 2 is connected to bit 3 on the output
 Bit 3 is connected to bit 0 on the output

For a rotate right:

 Bit 0 is connected to bit 3 on the output

 Bit 1 is connected to bit 0 on the output
 Bit 2 is connected to bit 1 on the output
 Bit 3 is connected to bit 2 on the output

The last operation to be implemented in the ALU is the comparison, which

is very useful (and easy to add). We will employ the 4585 magnitude
comparator; what this chip does is take two 4-bit numbers and tell us
whether A > B, whether A < B, and whether A = B.
This is useful because it makes implementing "if" instructions much easier.
A lot of old processors do not have magnitude comparison abilities. This
meant that trying to determine if a number was greater than or less than
another number was less trivial—a subtraction could be done followed by
checking the sign bit, but that makes the code less clear. In this ALU all you
would need to do is just have the two numbers on the data bus and the
magnitude comparator will tell you immediately if the two numbers are
equal, less or greater.
The disadvantage of the 4585 comparator is that it is a magnitude
comparator and does not work with two's complement.

A 4585 magnitude comparator.

BOM - Bill Of Materials

Component Quantity

4008 (16 DIP) 1

4081 (14 DIP) 1

4070 (14 DIP) 2

 4071 (14 DIP) 1

4049 (16 DIP) 1

74HC125 7

100nF Capacitors 14

14 DIP Socket (for soldering the project) 11

16 DIP Socket (for soldering the project) 3

Besides these crucial components, it also need a method of creating the

circuit.

Putting It All Together!

Instead of trying to build the whole module on one board, build the ALU in
smaller sections which glue together via bus wires.

ALU is built on four separate stripboards which all fit on a custom mini shelf
(also made of stripboard).

 The front-side buses (left panel in the image) are the inputs A and B
 The back-side buses (right panel in the image) are the data output and
the function selection
UNIT-10:

Types of microinstruction
There are two types of microinstruction formats

1. Horizontal Format, called Horizontal microcode

2. Vertical Format, called Vertical microcode

In horizontal micro-instruction every bit of micro-instruction signifies a

control signal that directly controls a single bus line or occasionally a gate in the
machine. Though the length of such a micro-instruction can be hundreds of bits. A
typical horizontal micro-instruction with its related fields is demonstrated in Figure
below.
 (a) Horizontal Micro-instruction

(b) Vertical Micro-instructions

Figure: Micro- instruction Formats

In a vertical micro-instruction several similar control signals can be

encoded in a few micro-instruction bits. For example for 16 ALU operations that
may need 16 individual control bits in horizontal micro-instruction only 4 encoded
bits are required in vertical micro-instruction. In the same way in a vertical micro-
instruction only 3 bits are required to select one of eight registers. Though these
encoded bits need to be passed from the respective decoders to get the individual
control signals. This is shown in figure above.

Generally a horizontal control unit is faster however requires wider instruction

words while vertical control units though; require a decoder are shorter in length.
Most of systems employ neither purely vertical nor purely horizontal micro-
instructions figure (c) above.

ARITHMETIC PROCESSOR
An arithmetic processor comprising: an arithmetic logic unit having a plurality of arithmetic
circuits each for performing a group of associated arithmetic operations, such as finite field
operations, or modular integer operations. The arithmetic logic unit has an operand input data
bus, for receiving operand data thereon and a result data output bus for returning the results
of the arithmetic operations thereon. A register file is coupled to the operand data bus and the
result data bus. The register file is shared by the plurality of arithmetic circuits. Further a
controller is coupled to the ALU and the register file, the controller selecting one of the
plurality of arithmetic circuits in response to a mode control signal requesting an arithmetic
operation and for controlling data access between the register file and the ALU and whereby
the register file is shared by the arithmetic circuits.
Control Unit
This unit controls the operations of all parts of the computer but does not carry out
any actual data processing operations.
Functions of this unit are −
1. It coordinates the sequence of data movements into, out of, and between
a processor’s many sub-units.
2. It interprets instructions.
3. It controls data flow inside the processor.
4. It receives external instructions or commands to which it converts to
sequence of control signals.
5. It controls many execution units(i.e. ALU, data buffers and registers)
contained within a CPU.
6. It also handles multiple tasks, such as fetching, decoding, execution
handling and storing results.
Types of Control Unit
There are two types of control units:
1. Hardwired control unit and
2. Microprogrammable control unit.

1. Hardwired Control Unit –

In the Hardwired control unit, the control signals that are important for
instruction execution control are generated by specially designed
hardware logical circuits, in which we can not modify the signal generation
method without physical change of the circuit structure. The operation
code of an instruction contains the basic data for control signal
generation. In the instruction decoder, the operation code is decoded. The
instruction decoder constitutes a set of many decoders that decode
different fields of the instruction opcode.
As a result, few output lines going out from the instruction decoder
obtains active signal values. These output lines are connected to the
inputs of the matrix that generates control signals for executive units of
the computer. This matrix implements logical combinations of the
decoded signals from the instruction opcode with the outputs from the
matrix that generates signals representing consecutive control unit states
and with signals coming from the outside of the processor, e.g. interrupt
signals. The matrices are built in a similar way as a programmable logic
arrays.
Control signals for an instruction execution have to be generated not in a
single time point but during the entire time interval that corresponds to the
instruction execution cycle. Following the structure of this cycle, the
suitable sequence of internal states is organized in the control unit.
A number of signals generated by the control signal generator matrix are
sent back to inputs of the next control state generator matrix. This matrix
combines these signals with the timing signals, which are generated by
the timing unit based on the rectangular patterns usually supplied by the
quartz generator. When a new instruction arrives at the control unit, the
control units is in the initial state of new instruction fetching. Instruction
decoding allows the control unit enters the first state relating execution of
the new instruction, which lasts as long as the timing signals and other
input signals as flags and state information of the computer remain
unaltered. A change of any of the earlier mentioned signals stimulates the
change of the control unit state.
This causes that a new respective input is generated for the control signal
generator matrix. When an external signal appears, (e.g. an interrupt) the
control unit takes entry into a next control state that is the state concerned
with the reaction to this external signal (e.g. interrupt processing). The
values of flags and state variables of the computer are used to select
suitable states for the instruction execution cycle.
The last states in the cycle are control states that commence fetching the
next instruction of the program: sending the program counter content to
 the main memory address buffer register and next, reading the instruction
word to the instruction register of computer. When the ongoing instruction
is the stop instruction that ends program execution, the control unit enters
an operating system state, in which it waits for a next user directive.
2. Microprogrammable control unit –
The fundamental difference between these unit structures and the
structure of the hardwired control unit is the existence of the control store
that is used for storing words containing encoded control signals
mandatory for instruction execution.

In microprogrammed control units, subsequent instruction words are

fetched into the instruction register in a normal way. However, the
operation code of each instruction is not directly decoded to enable
immediate control signal generation but it comprises the initial address of
a microprogram contained in the control store.
 With a single-level control store:
In this, the instruction opcode from the instruction register is sent to the
control store address register. Based on this address, the first
microinstruction of a microprogram that interprets execution of this
instruction is read to the microinstruction register. This microinstruction
contains in its operation part encoded control signals, normally as few
bit fields. In a set microinstruction field decoders, the fields are
decoded. The microinstruction also contains the address of the next
microinstruction of the given instruction microprogram and a control
field used to control activities of the microinstruction address
generator.
 The last mentioned field decides the addressing mode (addressing
operation) to be applied to the address embedded in the ongoing
microinstruction. In microinstructions along with conditional addressing
mode, this address is refined by using the processor condition flags
that represent the status of computations in the current program. The
last microinstruction in the instruction of the given microprogram is the
microinstruction that fetches the next instruction from the main memory
to the instruction register.
 With a two-level control store:
In this, in a control unit with a two-level control store, besides the
control memory for microinstructions, a nano-instruction memory is
included. In such a control unit, microinstructions do not contain
encoded control signals. The operation part of microinstructions
contains the address of the word in the nano-instruction memory,
which contains encoded control signals. The nano-instruction memory
contains all combinations of control signals that appear in
microprograms that interpret the complete instruction set of a given
computer, written once in the form of nano-instructions.
 In this way, unnecessary storing of the same operation parts of
microinstructions is avoided. In this case, microinstruction word can be
much shorter than with the single level control store. It gives a much
smaller size in bits of the microinstruction memory and, as a result, a
much smaller size of the entire control memory. The microinstruction
memory contains the control for selection of consecutive
microinstructions, while those control signals are generated at the
basis of nano-instructions. In nano-instructions, control signals are
frequently encoded using 1 bit/ 1 signal method that eliminates
decoding.

Wilkes control unit

Prof. M. V. Wilkes of the Cambridge University Mathematical Laboratory
invented the term microprogramming in 1951. He offered a systematic
alternative process for designing control unit of a digital computer. At the time
of instruction executing a machine instruction, a sequence of transformations
and transfer of information from one register in processor to another take place.
These were also known as the micro operations. Due to the analogy between
the executions of individual steps in a machine instruction to execution of
individual instruction in a program. Wilkes introduced the idea of
microprogramming. Wilkes control unitreplaces the combinational and
sequential circuits of hardwired CU by a simple CU in conjunction with a storage
unit which stores the sequence of steps of instruction which is a micro-program.

In Wilkes microinstruction has two main components:

a) Control field that denotes the control lines which are to be activated and

b) Address field that provides address of the subsequent microinstruction to be

executed.

The figure below is an illustration of Wilkes control unit design.

Figure: Wilkes Control Unit

The control memory in Wilkes control is organized like a PLA's like matrix made
of diodes. This is partial matrix and comprises two components the control
signals and address of the subsequent micro-instruction. Register I comprises
the address of next micro-instruction which is one step of instruction execution,
for illustration T1 in M1 or T2 in M2 etc. as in Figure below. On decoding the
control signals are produced which cause execution of micro-operation(s) of that
step. Additionally the control unit denotes the address of next micro-operation
that gets loaded through register II to register I. Register I can also be loaded by
register II and enable IR input control signal. This will pass address of first micro-
instruction of execute cycle. At the time of a machine cycle one row of the matrix
is triggered. The first portion of the row produces the control signals which
control the operations of the processor. Second part produces the address of
row to be selected in next machine cycle.

At beginning of the cycle the address of the row to be selected is contained in

register I. This address is input to decoder that is activated by a clock pulse.

This triggers the row of control matrix. Two-register arrangement is required as

the decoder is a combinational circuit; with only one register output would
become input at the time of a cycle. This can be an unstable condition because
of repetitive loop.
Types of microinstruction
There are two types of microinstruction formats

1. Horizontal Format, called Horizontal microcode

2. Vertical Format, called Vertical microcode

In horizontal micro-instruction every bit of micro-instruction signifies a

control signal that directly controls a single bus line or occasionally a gate in the
machine. Though the length of such a micro-instruction can be hundreds of bits. A
typical horizontal micro-instruction with its related fields is demonstrated in Figure
below.

(a) Horizontal Micro-instruction

 (b) Vertical Micro-instructions

Figure: Micro- instruction Formats

In a vertical micro-instruction several similar control signals can be

encoded in a few micro-instruction bits. For example for 16 ALU operations that
may need 16 individual control bits in horizontal micro-instruction only 4 encoded
bits are required in vertical micro-instruction. In the same way in a vertical micro-
instruction only 3 bits are required to select one of eight registers. Though these
encoded bits need to be passed from the respective decoders to get the individual
control signals. This is shown in figure above.

Generally a horizontal control unit is faster however requires wider instruction

words while vertical control units though; require a decoder are shorter in length.
Most of systems employ neither purely vertical nor purely horizontal micro-
instructions figure (c) above.
Control Memory
Instruction Format
Micro-instruction Execution

The microinstruction cycle is the basic event on a microprogrammed processor. Each cycle is
made up the two parts: fetch and execute. This section deals with the execution of
microinstruction. The effect of the execution of a microinstruction is to generate control signals
for both the internal control to processor and the external control to processor.

A organization of a control unit is shown in Figure 7.4