Exercise Manual

for
Introduction to VHDL

Software Requirements to complete all exercises

1) The Quartus® II software version 9.1
2) ModelSim®-Altera® Edition tool version 6.5b OR ModelSim-Altera
Starter Edition tool version 6.5b

Use the link below to download the design files for the exercises:
http://www.altera.com/customertraining/ILT/Introduction_to_VHDL_9_1_v2.zip
Exercises Introduction to VHDL

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Introduction to VHDL Lab Overview

Objective: Build a sequential 8 x 8 multiplier

The objective of the following exercises is to build an 8 x 8 multiplier. The input to the
multiplier consists of two 8-bit multiplicands (dataa and datab) and the output from the
multiplier is a 16-bit product (product8x8_out). Additional outputs are a done bit
(DONE_FLAG) and seven signals to drive a seven segment display (seg_a, seg_b, seg_c,
seg_d, seg_e, seg_f, & seg_g).
This 8 x 8 multiplier requires four clock cycles to perform the full multiplication. During
each cycle, a pair of 4-bit portion of the multiplicands is multiplied by a 4 x 4 multiplier.
The multiplication result of these 4 bit slices is then accumulated. At the end of the four
cycles (during the 5th cycle), the fully composed 16-bit product can be read at the output.
The following equations illustrate the mathematical principles supporting this
implementation:
result[15..0] = a[7..0] * b[7..0]
= ( (a[7..4] * 2^4) + a[3..0] * 2^0 )
* ( (b[7..4] * 2^4) + b[3..0] * 2^0 )
= ( (a[7..4] * b[7..4]) * 2^8)
+ ( (a[7..4] * b[3..0]) * 2^4)
+ ( (a[3..0] * b[7..4]) * 2^4)
+ ( (a[3..0] * b[3..0]) * 2^0)
Figure 1 (below) illustrates the top-level block diagram of the 8 x 8 multiplier.
The labs are structured as a bottom-up design approach. In each of the first four
exercises, you will use targeted features of the VHDL language to build the individual
components of the 8 x 8 multiplier, compiling and simulating each component. Then, in
Exercise 5 you will put everything together in a top-level design. You will then compile
and simulate to verify the completeness of top-level design.
Good luck and have fun going through the exercises!

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dataa[7:0] mult4x4
mux4 aout[3:0]
datab[7:0] dataa[3:0]
product[7:0]
product[7:0]
dataa[3:0] bout[3:0]
start mux_in_a[3:0] datab[3:0]
dataa[7:4]
reset_a mux_in_b[3:0]
sel[1]
clk mux_sel
aout[3:0]
mux_out[3:0]

shifter
mux4 product[7:0]
datab[3:0] input[7:0] shift_out[15:0]
mux_in_a[3:0] shift_out[15:0]
shift[1:0]
datab[7:4] shift_cntrl[1:0]
mux_in_b[3:0]
sel[0]
mux_sel
bout[3:0]
mux_out[3:0]

reg16
clk
adder clk
shift_out[15:0] sclr_n
dataa[15:0] sclr_n product8x8[15:0]
sum[15:0]
sum[15:0] clk_ena reg_out[15:0]
product8x8[15:0] clk_ena
datab[15:0]
sum[15:0]
datain[15:0]

mult_control
sel[1:0]
clk input_sel[1:0]
clk
shift[1:0]
counter
shift_sel[1:0] clk
reset_a clk
reset_a state_outl[2:0] count[1:0]
state_out[2:0] count_out[1:0]
start
start done_flag aclr_n
start done
clk_ena
clk_ena
count[1:0]
count[1:0] sclr_n
sclr_n

seven_segment_cntrl done_flag
product8x8_out[15:0]
seg_a seg_a
state_out[2:0]
input[2:0] seg_b seg_b
seg_c seg_c
seg_d seg_d
seg_e seg_e
seg_f seg_f
seg_g seg_g

Figure 1 - 8 x 8 multiplier top level design block diagram

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Exercise 1a

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Exercise 1a
Objectives:
• Build a 16-bit adder using the ‘+’ operator
• Practice coding ENTITY-ARCHITECTURE structure
• See the effect of libraries references on compilation

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Step 1: Unzip the exercise files and open a Quartus II project

____ 1. Unzip the lab project files, if necessary. In an Windows Explorer window, go to the
directory C:\altera_trn\VHDL. (If you see a subfolder already there named
Introduction_to_VHDL_91, please delete.) Double-click the executable file named
Introduction_to_VHDL_9_1_v1.exe found in the C:\altera_trn\VHDL directory.
If you still cannot find this directory or file, ask your instructor for assistance. After
double-clicking, in the WinZip dialog box, simply click Unzip to automatically
extract the files into a newly created folder named Introduction_to_VHDL_91.
Close WinZip.
____ 2. Start the Quartus II software. In the Windows Start menu from the All Programs
list, go to the Altera folder and then the Quartus II 9.1 folder. Click Quartus II 9.1
(32-Bit) to start the program. There may also be a shortcut on the desktop.
If using another operating system, please ask the instructor how to open the Quartus
II software if you are unsure.
____ 3. Open the adder project. From the Quartus II File menu, choose Open Project.
Browse to the directory C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab1a
and select the file adder.qpf.
The project opens and you are ready to start coding your adder block.

Step 2: Write the code for a 16-bit adder

____ 1. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button. The New File dialog box will appear; select
VHDL File. Click OK.
____ 2. Write the source code for a 16-bit adder using the ‘+’ operator. Use the following
information as a guide:
a. Use the names in the diagram above to name your block and its ports (all
lower-case)
b. All inputs and outputs should be declared as standard logic.
c. Do not worry about rollover with this adder. This adder is already wide
enough to account for all the values it will be adding together.

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d. Make sure to include the library and package declarations at the beginning of
the file. You will need the STD_LOGIC_1164 and
STD_LOGIC_UNSIGNED packages.
e. If you would prefer using a different text editor, please feel free to do so. Just
make sure you save your VHDL file in the project directory.
____ 3. Save the file as adder.vhd. From the Quartus II File menu, select Save and save
your VHDL file as adder.vhd. It should be located in the
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab1a directory.

Step 3: Synthesize the design & check the code for correctness
____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button.
This will perform checks on the source code to make sure it using valid VHDL syntax
as well as check the design for being synthesizable.
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed. Be aware that most
error messages point to the line number that is causing the error. You may also right-
click on the message itself and choose Help to access the online help within the
Quartus II software for clues on how to fix your warning or error. Of course, ask
your instructor if you are unsure how to fix a particular warning or message. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Check operator overloading

____ 1. Comment out the second USE clause. In your adder.vhd file, use the VHDL
comment character to comment out the second of the two USE clauses (the one
enabling the use of the STD_LOGIC_UNSIGNED package) at the beginning of the
file. You should comment out only 1 line.
____ 2. Synthesize the design. From the Processing menu, select Start ⇒ Start Analysis &
Synthesis again OR click on the button.
What error messages did you receive? You should see the messages below.

The reason for the error message is operator overloading. The VHDL compiler does
not understand the arithmetic operation for STD_LOGIC_VECTOR data types. The
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STD_LOGIC_UNSIGNED package contains the function definition that describes
this arithmetic operation when used on STD_LOGIC_VECTOR data types.
Therefore, the library that contains this package and the package itself need to be
referenced in the design file.
____ 3. Restore (uncomment) the USE clause in adder.vhd and save.

Step 5: Perform an RTL simulation

You will now use the ModelSim-Altera Starter Edition simulation tool (or similar) to
verify the functionality of your design. A VHDL testbench file (adder_tb.vhd) has
already been created for you to provide the test vectors for your RTL simulation.
____ 1. Open the ModelSim-Altera simulation tool. In the Windows Start menu from the All
Programs list, go to the Altera folder and then the ModelSim-Altera 6.5b (Quartus
II 9.1) Starter Edition folder. Click ModelSim-Altera 6.5b (Quartus II 9.1)
Starter Edition to start the program. There may also be a shortcut on the desktop.
If using another simulation tool, see your instructor for steps on how to open and
execute that tool.
____ 2. Close the introductory window (if it appears).
____ 3. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab1a.
A ModelSim macro file called a .DO file has been created for you. This file named
adder_tb.do contains all of the stepts to run the ModelSim tool and peform
simulation. This includes:
a. Creating a working library using the vlib command
b. Compiling all of the VHDL files into the working library with the vcom
command.
c. Loading the simulator with the top-level testbench file using the vsim
command.
d. Opening the waveform window with the wave command.
e. Adding target signals to the wave window (and formatting them) using the add
wave command.
f. Advancing simulation using the run command.
You may open the adder_tb.do file in a text editor if you wish to view the specific
commands used.
____ 4. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file adder_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
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waveform window will open (as a separate window) with the dataa, datab and sum
signals added so you can verify that your vhdl code is functioning correctly.
____ 5. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

If your simulation does not match the above, edit your VHDL code as needed and then
save it. Re-run the adder_tb.do file (repeat #’s 4 and 5 above) to check your changes.
____ 6. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

Exercise Summary
• Coded a 16-bit adder block in VHDL using the STD_LOGIC data type and an
overloaded ‘+’ operator
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 1a
(Please continue to Exercise 1b)

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Exercise 1b

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Exercise 1b
Objectives:
• Build a 4x4 multiplier block using the ‘*’ operator
• Synthesize and verify its operation

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Step 1: Open a Quartus II project

____ 1. Open the multiplier project. In the Quartus II software, go to the File menu and
choose Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab1b and select the file
mult4x4.qpf.
The project opens and you are ready to start coding your 4x4 multiplier block.

Step 2: Write the code for a 4x4 multiplier

____ 1. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button . The New File dialog box will appear; select
VHDL File. Click OK.
____ 2. Write the source code for a 4x4 multiplier using the ‘*’ operator. Use the following
information as a guide:
a. The multiplier has two 4-bit multiplicand inputs and an 8-bit product output.
b. Use the names in the diagram above to name your block and its ports (all
lower-case)
c. All inputs and outputs should be declared as standard logic.
d. You will need the STD_LOGIC_1164 and STD_LOGIC_UNSIGNED
packages again.
____ 3. Save the file as mult4x4.vhd. From the Quartus II File menu, select Save and save
your VHDL file as mult4x4.vhd. It should be located in the
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab1b directory.

Step 3: Synthesize the design & check the code for correctness
____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
itself, the Quartus II online help, the class manual and your instructor. Repeat
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synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

You will now use the ModelSim-Altera Starter Edition simulation tool (or similar) to
verify the functionality of your design. A VHDL testbench file (mult4x4_tb.vhd) has
already been created for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab1b.
Again, a ModelSim macro file named mult4x4_tb.do has been created for you to run
the ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file mult4x4_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. the
waveform window will open (as a separate window) with the dataa, datab and
product signals added so you can verify that your vhdl code is functioning correctly.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

If your simulation does not match the above, edit your VHDL code as needed and
then save it. Re-run the mult4x4_tb.do file (repeat #’s 2 and 3 above) to check your
changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

Exercise Summary
• Coded a 4x4 multiplier block in VHDL using the STD_LOGIC data type and the ‘*’
operator
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

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END OF EXERCISE 1b

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Exercise 2a

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Exercise 2a
Objectives:
• Build a 4-bit 2:1 multiplexer using the IF-THEN statement
• Synthesize and verify its operation

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Step 1: Open a Quartus II project

____ 1. Open the multiplexer project. In the Quartus II software, go to the File menu and
choose Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab2a and select the file
mux4.qpf.
The project opens and you are ready to start coding your 2-1 multiplexer block.

Step 2: Write the code for a 2:1 multiplexer

____ 1. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button . The New File dialog box will appear; select
VHDL File. Click OK.
____ 2. Write the source code for a 4-bit 2:1 multiplexer using the IF-THEN sequential
statement. Use the following information as a guide:
a. The multiplexer has two 4-bit data inputs, a select line and a 4-bit output.
b. Describe the following behavior: if mux_sel is 0, then choose mux_in_a for
mux_out. if mux_sel is 1, then choose mux_in_b for mux_out.
c. Use the names in the diagram above to name your block and its ports (all
lower-case)
d. All inputs and outputs should be declared as standard logic.
e. Coding with sequential statements requires using an explicit PROCESS.
f. You will only need the STD_LOGIC_1164 package.
____ 3. Save the file as mux4.vhd. From the Quartus II File menu, select Save and save
your VHDL file as mux4.vhd. It should be located in the
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab2a directory.

Step 3: Synthesize the design & check the code for correctness

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____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
itself, the Quartus II online help, the class manual and your instructor. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

You will now use the ModelSim-Altera Starter Edition simulation tool (or similar) to
verify the functionality of your design. A VHDL testbench file (mux4_tb.vhd) has
already been created for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab2a.
Use the ModelSim macro file named mux4_tb.do, created for you, to run the
ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file mux4_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
waveform window will open (as a separate window) with the mux_in_a, mux_in_b,
mux_sel and mux_out signals added so you can verify that your VHDL code is
functioning correctly.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

If your simulation does not match the above, edit your VHDL code as needed and
then save it. Re-run the mult4x4_tb.do file (repeat #’s 2 and 3 above) to check your
changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

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Exercise Summary
• Coded a 4-bit 2:1 multiplexer block in VHDL using the IF-THEN sequential
statement
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 2a
(Please continue to Exercise 2b)

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Exercise 2b

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Exercise 2b
Objectives:
• Build a 8-bit to 16-bit left shifter using the IF-THEN statement
• Synthesize and verify its operation

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Step 1: Open a Quartus II project

____ 1. Open the shifter project. In the Quartus II software, go to the File menu and choose
Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab2b and select the file
shifter.qpf.
The project opens and you are ready to start coding your 8-to-16 left shifter block.

Step 2: Write the code for an 8-bit to 16-bit left shifter

____ 1. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button . The New File dialog box will appear; select
VHDL File. Click OK.
____ 2. Write the source code for a 8-bit to 16-bit left shifter using the IF-THEN sequential
statement. Use the following information as a guide:
a. The multiplexer has one 8-bit data input, a control line and a 16-bit output.
b. Describe the following behavior:
o When shift_cntrl is 0, then no shift (i.e. shift_out[7:0] equals
input[7:0]).
o When shift_cntrl is 1, then shift input to the left by 4 bits within
shift_out (i.e. shift_out[11:4] equals input[7:0]).
o When shift_cntrl is 2, then shift input to the left by 8 bits within
shift_out (i.e. shift_out[15:8] equals input[7:0]).
o When shift_cntrl is 3, then no shift (i.e. shift_out[7:0] equals
input[7:0]).
c. Use the names in the diagram above to name your block and its ports (all
lower-case)
d. All inputs and outputs should be declared as standard logic.
e. Coding with sequential statements requires using an explicit PROCESS.
f. You will only need the STD_LOGIC_1164 package.
g. Try to simplify choices when possible, recognize similarities between choices.

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____ 3. Save the file as shifter.vhd. From the Quartus II File menu, select Save and save
your VHDL file as shifter.vhd. It should be located in the
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab2b directory.

Step 3: Synthesize the design & check the code for correctness
____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
itself, the Quartus II online help, the class manual and your instructor. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

Use the ModelSim-Altera Starter Edition simulation tool (or similar) to verify the
functionality of your design. A VHDL testbench file (shifter_tb.vhd) has been created
for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab2b.
Use the ModelSim macro file named shifter_tb.do, created for you, to run the
ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file shifter_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
waveform window will open (as a separate window) with the shift_cntrl, input and
shift_out signals added so you can verify that your VHDL code is functioning
correctly.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

If your simulation does not match the above, edit your VHDL code as needed and

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then save it. Re-run the shifter_tb.do file (repeat #’s 2 and 3 above) to check your
changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

Exercise Summary
• Coded a 8-bit to 16-bit left shifter block in VHDL using the IF-THEN sequential
statement
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 2b

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Exercise 3

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Exercise 3
Objectives:
• Build a 7-segment LED display controller using the CASE statement
• Synthesize and verify its operation

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Step 1: Open a Quartus II project

____ 1. Open the 7-segment LED display controller project. In the Quartus II software, go to
the File menu and choose Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab3 and select the file
seven_segment_cntrl.qpf.
The project opens and you are ready to start coding your 7-segment LED display
control block.

Step 2: Write the code for a 7-segment LED display controller

____ 1. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button . The New File dialog box will appear; select
VHDL File. Click OK.
____ 2. Write the source code for a 7-segment LED display controller using the CASE
sequential statement. Use the following information as a guide:
a. The controller has one 3-input data input and 7 single-bit outputs each
controlling different segments of the 7-segment display
b. Describe the behavior as shown in the following table:

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Inputs Outputs
LED
input Display
seg_a seg_b seg_c seg_d seg_e seg_f seg_g
[2:0]

000 1 1 1 1 1 1 0 0
001 0 1 1 0 0 0 0 1
010 1 1 0 1 1 0 1 2
011 1 1 1 1 0 0 1 3
All other
1 0 0 1 1 1 1 E
values
c. Use the names in the diagram above to name your block and its ports (all
lower-case)
d. All inputs and outputs should be declared as standard logic.
e. Coding with sequential statements requires using an explicit PROCESS.
f. You will only need the STD_LOGIC_1164 package.
____ 3. Save the file as seven_segment_cntrl.vhd. From the Quartus II File menu, select
Save and save your VHDL file as seven_segment_cntrl.vhd. It should be located in
the C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab3 directory.

Step 3: Synthesize the design & check the code for correctness
____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
itself, the Quartus II online help, the class manual and your instructor. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

Use the ModelSim-Altera Starter Edition simulation tool (or similar) to verify the
functionality of your design. A VHDL testbench file (seven_segment_cntrl_tb.vhd)
has been created for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
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Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab3.

Use the ModelSim macro file named seven_segment_cntrl_tb.do, created for you, to
run the ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file seven_segment_cntrl_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
waveform window will open (as a separate window) with the input, seg_a, seg_b,
seg_c, seg_d, seg_e, seg_f and seg_g signals added so you can verify that your VHDL
code is functioning correctly.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

If your simulation does not match the above, edit your VHDL code as needed and
then save it. Re-run the seven_segment_cntrl_tb.do file (repeat #’s 2 and 3 above) to
check your changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

Exercise Summary
• Coded a 7-segment LED display controller in VHDL using the CASE sequential
statement
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 3

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Exercise 4a

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Exercise 4a
Objectives:
• Build a 16-bit register with synchronous control
• Synthesize and verify its operation

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Step 1: Open a Quartus II project

____ 1. Open the register project. In the Quartus II software, go to the File menu and choose
Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab4a and select the file
reg16.qpf.
The project opens and you are ready to start coding your 16-bit register block.

Step 2: Write the code for a 16-bit register with synchronous control

____ 4. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button . The New File dialog box will appear; select
VHDL File. Click OK.
____ 5. Write the source code for a 16-bit register with synchronous control using a
sequential PROCESS. Use the following information as a guide:
a. The register has a clock, a 16-bit data input, a synchronous clear, a
synchronous clock enable and a 16-bit data output.
b. Describe the following behavior:
o All transactions occur on the rising edge of a clk.
o on a rising edge clock, check to see if clk_ena is high.
o if clk_ena is high, check to see if sclr_n is low. if so, then the register
outputs are cleared.
o if clk_ena is high and sclr_n is not low, then the registers outputs are set
equal to the register inputs.
o if clk_ena is low, do nothing.
c. Use the names in the diagram above to name your block and its ports (all
lower-case)
d. All inputs and outputs should be declared as standard logic.
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e. All checking of synchronous register control signals occurs inside the IF-
THEN statement that checks for the clock condition.
f. Synchronous controls are not included in the sensitivity list.
g. Unless explicitly changed, outputs to a process will retain their value from the
previous process execution.
h. You will only need the STD_LOGIC_1164 package.
____ 6. Save the file as reg16.vhd. From the Quartus II File menu, select Save and save
your VHDL file as reg16.vhd. It should be located in the
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab4a directory.

Step 3: Synthesize the design & check the code for correctness
____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
itself, the Quartus II online help, the class manual and your instructor. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

Use the ModelSim-Altera Starter Edition simulation tool (or similar) to verify the
functionality of your design. A VHDL testbench file (reg16_tb.vhd) has been created
for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab4a.
Use the ModelSim macro file named reg16_tb.do, created for you, to run the
ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file reg16_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
waveform window will open (as a separate window) with the clk, sclr_n, clk_ena,
datain and reg_out signals added so you can verify that your VHDL code is
functioning correctly.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

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If your simulation does not match the above, edit your VHDL code as needed and
then save it. Re-run the reg16_tb.do file (repeat #’s 2 and 3 above) to check your
changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

Exercise Summary
• Coded a 16-bit register with synchronous controls in VHDL using a sequential
process
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 4a

(Please continue to Exercise 4b)

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Exercise 4b

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Exercise 4b
Objectives:
• Build a 2-bit counter with asynchronous control
• Synthesize and verify its operation

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Step 1: Open a Quartus II project

____ 1. Open the counter project. In the Quartus II software, go to the File menu and choose
Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab4b and select the file
counter.qpf.
The project opens and you are ready to start coding your 2-bit counter block.

Step 2: Write the code for a 2-bit counter with asynchronous control

____ 1. Create a VHDL file using the Quartus II text editor. From the Quartus II File menu
select New or click on the button . The New File dialog box will appear; select
VHDL File. Click OK.
____ 2. Write the source code for a 2-bit counter with asynchronous control using a
sequential PROCESS. Use the following information as a guide:
a. The register has a clock, an asynchronous clear and a 2-bit data output.
b. Describe the following behavior:
o The output of the counter goes to 00 immediately when aclr_n is low.
o if aclr_n is not low, then the output of the counter increments by 1 on
every rising edge of clk.
c. Use the names in the diagram above to name your block and its ports (all
lower-case)
d. All inputs and outputs should be declared as standard logic.
e. Use a VARIABLE class object to store the count value.
f. Checking of asynchronous register control signals occurs outside and before
the IF-THEN statement that checks for the clock condition.
g. Asynchronous controls are included in the sensitivity list.
h. You will need both the STD_LOGIC_1164 and STD_LOGIC_UNSIGNED
packages.

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____ 3. Save the file as counter.vhd. From the Quartus II File menu, select Save and save
your VHDL file as counter.vhd. It should be located in the
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab4b directory.

Step 3: Synthesize the design & check the code for correctness
____ 1. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 2. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
itself, the Quartus II online help, the class manual and your instructor. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

Use the ModelSim-Altera Starter Edition simulation tool (or similar) to verify the
functionality of your design. A VHDL testbench file (counter_tb.vhd) has been
created for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab4b.
Use the ModelSim macro file named counter_tb.do, created for you, to run the
ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file counter_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
waveform window will open (as a separate window) with the clk, aclr_n and
count_out signals added so you can verify that your VHDL code is functioning
correctly.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. From the View menu, click Zoom ⇒ Zoom Full. Your results should
look similar to the image below.

If your simulation does not match the above, edit your VHDL code as needed and
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then save it. Re-run the counter_tb.do file (repeat #’s 2 and 3 above) to check your
changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

Exercise Summary
• Coded a 2-bit counter with asynchronous control in VHDL using a sequential process
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 4b

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Exercise 5a

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Exercise 5
Objectives:
• Examine a state machine implementation

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You have now completed building all of the components necessary to build the 8x8
multiplier, except for the controlling state machine. Due to time, the controlling state
machine has been written for you and is located in
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab5a. The name of the file is
mult_control.vhd. You may open the file in the Quartus II text editor for review.
This state machine will manage all the operations that occur within the 8x8 multiplier
using 6 defined states: idle, lsb, mid, msb, calc_done and err. See the state diagram in
Figure 5-1 for more definition of its behavior.
The state machine in the LSB state multiplies the lowest 4 bits of the two 8-bit
multiplicands ( (a[3..0] * b[3..0] ) * 2^0 ). This intermediate result is
saved in an accumulator.
The state machine in the MID state performs cross multiplication ( ( a[3..0] * b[7..4] ) *
2^4 ) and ( ( a[7..4] * b[3..0] ) * 2^4 ). This is done in successive clock cycles. The
products of both multiply operations are added to the content of the accumulator as they
are completed and clocked back into the accumulator.
The state machine in the MSB state multiplies the highest 4 bits of the two 8-bit
multiplicands ( (a[7..4] * b[7..4] ) * 2^8 ). This product is added with the content of the
accumulator and clocked back into the accumulator.
This result is the final product:
result[15..0] = a[7..0] * b[7..0]
= ( (a[7..4] * b[7..4]) * 2^8)
+ ( (a[7..4] * b[3..0]) * 2^4)
+ ( (a[3..0] * b[7..4]) * 2^4)
+ ( (a[3..0] * b[3..0]) * 2^0)
The state machine in the CALC_DONE state asserts the done_flag output to indicate the
final product has been calculated and is ready for reading by downstream logic.
The state machine in the ERR state indicates incorrect inputs have been received.
There are two inputs to the state machine: start and count. The start signal is asserted
for once clock cycle to begin an 8x8 multiply operation on the next clock cycle. The start
signal must only be asserted for one clock cycle. The count signal is used by the state
machine to track the multiplication cycles.
The outputs of mult_control control the various other blocks in the design.

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CALC_ START = 0
IDLE input_sel = XX
DONE
state_out = shift_sel = XX
state_out = START = 0
input_sel = XX 000 done = 0
100 clk_ena = 0
shift_sel = XX
sclr_n = 1
done = 1
clk_ena = 0
sclr_n = 1 START = 0
START = 0 input_sel = XX
COUNT = 11 START = 1 shift_sel = XX
input_sel = 11 input_sel = XX done = 0 START = 1
shift_sel = 10 shift_sel = XX clk_ena = 0 input_sel = XX
done = 0 done = 0 sclr_n = 1 shift_sel = XX
clk_ena = 1 clk_ena = 0 done = 0
sclr_n = 1 sclr_n = 1 clk_ena = 1
sclr_n = 0
OTHERS
ERR input_sel = XX
state_out = shift_sel = XX
done = 0
101 clk_ena = 0
sclr_n = 1

OTHERS
MSB input_sel = XX
LSB
state_out = START = 1 state_out =
shift_sel = XX
input_sel = XX
011 done = 0
shift_sel = XX
001
clk_ena = 0
done = 0
sclr_n = 1
clk_ena = 1
OTHERS
sclr_n = 0
input_sel = XX START = 0
shift_sel = XX COUNT = 0
done = 0 input_sel = 00
START = 0 clk_ena = 0 shift_sel = 00
COUNT = 10 sclr_n = 1 done = 0
input_sel = 10 clk_ena = 1
shift_sel = 01 sclr_n = 1
done = 0
START = 0
clk_ena = 1
MID COUNT = 01
sclr_n = 1
input_sel = 01
state_out = shift_sel = 01
010 done = 0
XX = Don’t Care clk_ena = 1
sclr_n = 1

Figure 5-1: MULT_CONTROL state machine state diagram

END OF EXERCISE 5a
(Please continue to Exercise 5b)

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Exercise 5b

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Exercise 5b
Objectives:
• Complete the code to implement the 8x8 multiplier using COMPONENT
declarations and instantiations
• Synthesize and verify its operation

You now have all of the building blocks necessary to complete the 8x8 multiplier.
Making use of the knowledge you have gained up to this point, you would instantiate each
component in a top-level design and connect all signals as shown in Figure 5-2. To save
time, we have completed part of this for you. You will finish this task by instantiating
mult4x4 and shifter. You will also need to declare and connect the product signal.

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dataa[7:0] mult4x4 (u3)

mux4 (u1) aout[3:0]
datab[7:0] dataa[3:0] product[7:0]
dataa[3:0] bout[3:0] product[7:0]
start mux_in_a[3:0] datab[3:0]
dataa[7:4]
reset_a mux_in_b[3:0]
sel[1]
clk mux_sel
aout[3:0]
mux_out[3:0]

shifter (u4)
mux4 (u2) product[7:0]
datab[3:0] input[7:0] shift_out[15:0]
mux_in_a[3:0] shift_out[15:0]
shift[1:0]
datab[7:4] shift_cntrl[1:0]
mux_in_b[3:0]
sel[0]
mux_sel
bout[3:0]
mux_out[3:0]

reg16 (u7)
clk
adder (u8) clk
shift_out[15:0] sclr_n
dataa[15:0] sclr_n product8x8[15:0]
sum[15:0]
sum[15:0] clk_ena reg_out[15:0]
product8x8[15:0] clk_ena
datab[15:0]
sum[15:0]
datain[15:0]

mult_control (u6)
sel[1:0]
clk input_sel[1:0]
clk
shift[1:0]
counter (u5)
shift_sel[1:0] clk
reset_a clk
reset_a state_outl[2:0] count[1:0]
state_out[2:0] count_out[1:0]
start
start done_flag aclr_n
start done
clk_ena
clk_ena
count[1:0]
count[1:0] sclr_n
sclr_n

seven_segment_cntrl done_flag
(u9) product8x8_out[15:0]
seg_a seg_a
state_out[2:0]
input[2:0] seg_b seg_b
seg_c seg_c
seg_d seg_d
seg_e seg_e
seg_f seg_f
seg_g seg_g

Figure 5-2 - 8 x 8 multiplier top level design block diagram

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Step 1: Open a Quartus II project

____ 1. Open the 8x8 multiplier project. In the Quartus II software, go to the File menu and
choose Open Project. Browse to the directory
C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab5b and select the file
mult8x8.qpf.
The project opens so you can finish coding the 8x8 multiplier.

Step 2: Finish the code for a 8x8 multiplier

____ 1. Open the mult8x8.vhd file using the Quartus II text editor. From the Quartus II File
menu select Open or click on the button . The Open File dialog box will appear;
select mult8x8.vhd. Click Open.
____ 2. Finish the source code for the 8x8 multiplier using COMPONENT declarations
and instantiations. Use the following information as a guide.
a. Create a component declaration and instantiation for mult4x4 based on the
connections and instance name shown in Figure 5-2.
b. Create a component declaration and instantiation for shifter based on the
connections and instance name shown in Figure 5-2.
c. This will require declaring a new 8-bit internal signal named product for
connecting mult4x4 to shifter.
____ 3. Save the file. From the Quartus II File menu, select Save.

Step 3: Synthesize the design & check the code for correctness
Since the other source files are in different directories, before synthesizing, you must
directly add these other source files to this Quartus II project.
____ 1. Add the source files from the other projects. From the Quartus II Project menu,
select Add/Remove Files in Project. Click on the button and browse to each of
the subdirectories used for Exercises 1-5a to add each of the VHDL design files to this
project. This includes: adder.vhd (lab1a), mult4x4.vhd (lab1b), mux4.vhd
(lab2a), shifter.vhd (lab2b), seven_segment_cntrl.vhd (lab3), reg16.vhd (lab4a),
counter.vhd (lab4b) and mult_control.vhd (lab5a). MAKE SURE to click on the
Add button each time so that the file appears in the File name list.
____ 2. Synthesize the design. From the Quartus II Processing menu, select Start ⇒ Start
Analysis & Synthesis OR click on the button..
____ 3. Correct any warnings and errors. Check the Messages window of the Quartus II
software for any warning or error messages. Correct as needed using the message
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itself, the Quartus II online help, the class manual and your instructor. Repeat
synthesis and error checking until the Quartus II software reports that the “Analysis
& Synthesis was successful.”

Step 4: Perform an RTL simulation

Use the ModelSim-Altera Starter Edition simulation tool (or similar) to verify the
functionality of your design. A VHDL testbench file (mult8x8_tb.vhd) has been
created for you to provide the test vectors for your RTL simulation.
____ 1. Set the project directory. From the ModelSim File menu, select Change Directory.
Browse to the location C:\altera_trn\VHDL\Introduction_to_VHDL_91\lab5b.
Use the ModelSim macro file named mult8x8_tb.do, created for you, to run the
ModelSim tool and peform simulation.
____ 2. Execute the macro file. From the ModelSim Tools menu, select Tcl ⇒ Execute
Macro. Select the file mult8x8_tb.do and click Open.
The ModelSim tool will now compile all of the VHDL files and start simulation. The
waveform window will open (as a separate window) with all of the multiplier input
and output signals added so you can verify that your VHDL code is functioning
correctly. Dividers are used to separate different types of signals.
____ 3. Check simulation results for correct functionality. Bring the Wave window to the
foreground. Use the Zoom In tool to zoom until you can see the product output
calculations. Your results should look similar to Figure 5-3 below. Note that each
time done_flag goes high, the design is returning the product of the current inputs.
If your simulation does not match the above, edit your VHDL code as needed and
then save it. Re-run the mult8x8_tb.do file (repeat #’s 2 and 3 above) to check your
changes.
____ 4. End your simulation. From the ModelSim Simulate menu, select End Simulation
OR type quit –sim in the ModelSim Transcript window.

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Figure 5-3: 8x8 multiplier simulation results (1st 900 ns shown)

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Exercise Summary
• Finished coding the top-level 8x8 design by using component declarations and
instantiations.
• Simulated the VHDL code in the ModelSim tool to verify correct functionality

END OF EXERCISE 5b

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