Lecture 8b

Digital Logic - Sequential Logic

Applications of Flip-Flops
Counters
Chintan Kr Mandal

1 Counters
• A digital circuit which is used for a counting pulses is known counter.

• It is a group of flip-flops with a clock signal applied.

• Counter is the widest application of flip-flops.

• Counters are of two types.

1 Asynchronous or ripple counters
2 Synchronous counters.

Different Types of Counters

1. Binary Ripple Counter
2. Ring Counter

3. BCD Counter
4. Decade counter
5. Up down Counter
6. Frequency Counter

2 Asynchronous or Ripple Counters

• The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do
not occur at the same time.

• An asynchronous counter is one in which the flip-flops within the counter do not change states at exactly the same time
because they do not have a common clock pulse.

1
2.1 Asynchronous N Bit Binary Counter
2.2 A Asynchronous Two Bit Binary Counter

Asynchronous Two Bit Binary Counter

• The clock (CLK) is applied to the clock input (C) of only the first flop-flop, FFO, which is always the LSB.
• The second flip-flop, FF1, is triggered by the Q0 output of FFO.
• FFO changes state at the positive-going edge of each clock pulse.

• FF1 changes only when triggered by a positive-going transition of the Q0 output of FFO.
• Because of the inherent propagation delay time through a flip-flop, a transition of the input clock pulse (CLK) and a
transition of the Q0 output of FFO can never occur at exactly the same time.
• Therefore, the two flip-flops are never simultaneously triggered, so the counter operation is asynchronous.

Timing Diagram for Asynchronous Two Bit Binary Counter

Timing diagram for the counter

• Since it goes through a binary sequence, the counter is a binary counter.

• It actualIy counts the number of clock pulses up to three, and on the fourth pulse it recycles to its original state
(Q0 = 0, Q1 = 0).

• The term recycle is commonly applied to counter operation; it refers to the transition of the counter from its final state
back to its original state.

2.3 A Asynchronous Three Bit Binary Counter

2
2.4 Asynchronous Decade Counters
Modulus of a Counter
• The modulus of a counter is the number of unique states through which the counter will sequence.
• The maximum possible number of states (maximum modulus) of a counter is 2N , where N is the number of Flip-Flops
in the counter.

• Counters can be designed to have a number of states in their sequence that is less than the maximum of 2N .
• This type of sequence is called a truncated sequence.
• To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible
states.

• One common modulus for counters with truncated sequences is ten (called MOD1O).
• Counters with ten states in their sequence are called decade counters.

• A decade counter with a count sequence of zero (0000) through nine (1001) is a BCD decade counter because its
ten-state sequence produces the BCD code.
• This type of counter is useful in display applications in which BCD is required for conversion to a decimal readout.

Partial Decoding Design

We note that Q1 and Q3 are connected to the NAND gate inputs.
• This arrangement is an example of partial decoding
• The two unique states (Q1 = 1 and Q3 = 1) are sufficient to decode the count of ten because none of the other states
(zero through nine) have both Q1 and Q3 HIGH at the same time.

• When the counter goes into count ten (1010), the decoding gate output goes LOW and asynchronously resets all the
flip-flops.
• The resulting timing diagram shows a glitch on the Q1 waveform.
• The reason for this glitch is that Q1 must first go HIGH before the count of ten can be decoded.

• The counter is in the 1010 state for a short time before it is reset to 0000,thus producing the glitch on Q1 and the
resulting glitch on the CLR line that resets the counter.

3
3 Synchronous Counters
• The term synchronous refers to events that have a fixed time relationship with each other.
A synchronous counter is one in which all the flip-flops in the counter are clocked at the same time by a common
clock pulse.

3.1 Examples of Synchronous Counters

2 Bit Synchronous Counter

A 3-Bit Synchronous Binary Counter

4
A 4-Bit Synchronous Binary Counter

3.2 Design of Synchronous Counters: The Gray Code Counter

3.3 General Model for a Synchronous Counter

• The information stored in the memory section, as well as the inputs to the combinational logic (I0 , I1 , . . . , Im ), is
required for proper operation of the circuit.
• At any given time. the memory is in a state called the present state and will advance to a next state on a clock
pulse as determined by conditions on the excitation lines (Y0 , Y1 , . . . , Yp ).

• The present state of the memory is represented by the state variables (Q0 , Q1 , . . . , Qx ).
• These state variables, along with the inputs (I0 , I1 , . . . , Im ) determine the system outputs (O0 , O1 , . . . , On ).

3.4 Steps for Designing the Synchronous System

Step 1: State Diagram

• The first step in the design of a counter is to create a state diagram.

• A state diagram shows the progression of states through which the counter advances when it is clocked.
E.g. The state diagram for a basic 3-bit Gray code counter is shown.

5
Step 2: Next-State Table

• This table lists each state of the counter (present state) along with the corresponding next state.
• The next state is the state that the counter goes to from its present state upon applicaTion of a clock pulse.
• The next-state table is derived from the state diagram.

Note Q0 is the LSB

Step 3: Flip-Flop Transition Table

• All possible output transitions are listed by showing the Q output of the flip-flop going from present states to next
states.
• QN is the present state of the flip-flop (before a clock pulse) and QN +1 is the next state (after a clock pulse).
• For each output transition. the J and K inputs that will cause the transition to occur are listed.
An X indicates a ”don’t care” (the input can be either a 1 or a 0).

Step 4: Karnaugh Maps

Mapping procedure for the counter sequence for J0 and K0

6
Karnaugh maps for present-state J and K inputs.

Step 5: Logic Expressions for Flip-Flop Inputs

Step 6: Gray Code Counter Implementation

Gray Code Counter Implementation

1 Design the BCD Counter i.e. a counter counting from 0000 to 1001
2 Design the up-down BCD Counter i.e a counter counting from 0000 to 1001 and vice-versa

4 Cascaded Counters
• Counters can be connected in cascade to achieve higher-modulus operation.
• In essence, cascading means that the last-stage output of one counter drives the input of the next counter.

7
Example 1

Overall modulus of the cascaded counters is 32; that is, they act as a divide-by-32 counter.

Example 2

• The terminal count (TC) output of counter 1 is connected to the count enable (CTEN) input of counter 2.

• Counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or terminal state and its terminal
count output goes HIGH.
• This HIGH now enables counter 2 so that when the first clock pulse after counter 1 reaches its terminal count (CLK10),
counter 2 goes from its initial state to its second state.

• Upon completion of the entire second cycle of counter 1 (when counter 1 reaches terminal count the second time),
counter 2 is again enabled and advances to its next state.
• Since these are decade counters, counter 1 must go through ten complete cycles before counter 2 completes its first
cycle.
• In other words, for every ten cycles of counter 1, counter 2 goes through one cycle.

• Thus, counter 2 will complete one cycle after one hundred clock pulses.
• The overall modulus of these two cascaded counters is 10 X 10 = 100.