Asm 330 LHH
Asm 330 LHH
Description
The ASM330LHH is a system-in-package featuring a
3D digital accelerometer and a 3D digital gyroscope
with an extended temperature range up to +105 °C and
designed to address automotive non-safety
LGA-14L applications.
Typ: 2.5 x 3.0 x 0.83 mm3 ST’s family of MEMS sensor modules leverages the
robust and mature manufacturing processes already
used for the production of micromachined
Features accelerometers and gyroscopes to serve both the
automotive and consumer market. The ASM330LHH is
AEC-Q100 qualified AEC-Q100 compliant and industrialized through a
Extended temperature range dedicated MEMS production flow to meet automotive
reliability standards. All the parts are fully tested with
from -40 to +105 °C
respect to temperature to ensure the highest quality
Embedded compensation for high stability over level.
temperature The sensing elements are manufactured using ST’s
Accelerometer user-selectable full scale up to proprietary micromachining processes, while the IC
±16 g interfaces are developed using CMOS technology that
allows the design of a dedicated circuit which is
Extended gyroscope range from ±125 to trimmed to better match the characteristics of the
±4000 dps sensing element.
SPI & I²C host serial interface The ASM330LHH has a full-scale acceleration range of
Six-channel synchronized output to enhance ±2/±4/±8/±16 g and a wide angular rate range of
accuracy of dead-reckoning algorithms ±125/±250/±500/±1000/±2000/±4000 dps that enables
its usage in a broad range of automotive applications.
Smart programmable interrupts
All the design aspects of the ASM330LHH have been
Embedded 3 kbytes FIFO available to optimized to reach superior output stability, extremely
underload host processor low noise and full data synchronization to the benefit of
ECOPACK, RoHS and “Green” compliant sensor-assisted applications like dead reckoning and
sensor fusion.
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2 I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6.2 Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 I²C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3 Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.1 Block diagram of the gyroscope filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.2 Block diagrams of the accelerometer filters . . . . . . . . . . . . . . . . . . . . . . 32
6.5 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 ASM330LHH electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.1 PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2 FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.3 FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.4 FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.5 FIFO_CTRL4 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.6 COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.7 COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.8 INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.9 INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.10 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.11 CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.12 CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.13 CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.14 CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.15 CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.16 CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.17 CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.18 CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.19 CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.20 CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.21 ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.22 WAKE_UP_SRC (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.23 D6D_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.1 LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.2 LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
List of tables
List of figures
1 Overview
The ASM330LHH has been designed to feature the following on-chip functions:
3 kbytes data buffering:
– 100% efficiency with flexible configurations and partitioning
Event-detection interrupts (fully configurable):
– free-fall
– wakeup
– 6D orientation
– activity / inactivity recognition
3 Pin description
4 Module specifications
±2
a. The product is factory calibrated at 3.0 V. The operational power supply range is from 2.0 V to 3.6 V.
Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.
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4.6 Terminology
4.6.1 Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration
to the device. Because the sensor can measure DC accelerations, this can be done easily
by pointing the selected axis towards the ground, noting the output value, rotating the
sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing
so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and over time. The sensitivity tolerance describes
the range of sensitivities of a large number of sensors (see Table 3).
An angular rate gyroscope is a device that produces a positive-going digital output for
counterclockwise rotation around the axis considered. Sensitivity describes the gain of the
sensor and can be determined by applying a defined angular velocity to it. This value
changes very little over temperature and time (see Table 3).
5 Digital interfaces
SPI enable
CS I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C Serial Clock (SCL)
SCL/SPC
SPI Serial Port Clock (SPC)
I²C Serial Data (SDA)
SDA/SDI/SDO SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
SDO/SA0
I²C less significant bit of the device address
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up
resistors. When the bus is free, both the lines are high.
The I²C interface is implemeted with fast mode (400 kHz) I²C standards as well as with the
standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The Slave ADdress (SAD) associated to the ASM330LHH is 110101xb. The SDO/SA0 pin
can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is
connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is
connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to
connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I²C embedded inside the ASM330LHH behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted.
The increment of the address is configured by the CTRL3_C (12h) (IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 11 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 14. Transfer when master is receiving (reading) one byte of data from slave
Master ST SAD + W SUB SR SAD + R NMAK SP
Slave SAK SAK SAK DATA
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP
DAT
Slave SAK SAK SAK DATA DATA
A
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are, respectively, the serial port data input and output. Those lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
CTRL3_C (12h) (IF_INC) bit is ‘0’, the address used to read/write data remains the same for
every block. When the CTRL3_C (12h) (IF_INC) bit is ‘1’, the address used to read/write
data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
SPI read
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The SPI Read command is performed with 16 clock pulses. A multiple byte read command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
Figure 6. Multiple byte SPI read protocol (2-byte example) (in mode 3)
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The SPI Write command is performed with 16 clock pulses. A multiple byte write command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1 -7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 8. Multiple byte SPI write protocol (2-byte example) (in mode 3)
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6 Functionality
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The gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is
available, for more details about the filter characteristics see Table 53: Gyroscope LPF1
bandwidth selection. The digital LPF2 filter cannot be configured by the user and its cutoff
frequency depends on the selected gyroscope ODR, as indicated in the following table.
Data can be acquired from the output registers and FIFO.
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6.5 FIFO
The presence of a FIFO allows consistent power saving for the system since the host
processor does not need continuously poll data from the sensor, but It can wake up only
when needed and burst the significant data out from the FIFO.
The ASM330LHH embeds 3 kbytes of data in FIFO to store the following data:
Gyroscope
Accelerometer
Timestamp
Temperature
Writing data in the FIFO is triggered by the accelerometer / gyroscope data-ready signal.
The applications have maximum flexibility in choosing the rate of batching for physical
sensors with FIFO-dedicated configurations: accelerometer, gyroscope and temperature
sensor batching rates can be selected by the user. It is possible to select decimation for
timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG
byte that allows recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in
FIFO. If a change in the ODR or BDR (Batching Data Rate) configuration is performed, the
application can correctly reconstruct the timestamp and know exactly when the change was
applied without disabling FIFO batching. FIFO stores information of the new configuration
and timestamp in which the change was applied in the device.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and
FIFO_CTRL2 (08h) using the WTM[8:0] bits. To monitor the FIFO status, dedicated
registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh)) can be read to detect FIFO
overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number
of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and
INT2 pins of these status events, the configuration can be set in INT1_CTRL (0Dh) and
INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes:
Bypass mode
FIFO mode
Continuous mode
Continuous-to-FIFO mode
Bypass-to-continuous mode
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
7 Application hints
The device core is supplied through the Vdd line while the I/O pads are supplied through the
Vdd_IO line. As a common design practice, the power supply decoupling capacitors
C1 = 100 nF ceramic and C2 =10 μF aluminum should be placed as near as possible to
pin 8, while C3 = 100 nF ceramic should be positioned as close as possible to pin 5.
All the voltage and ground supplies must be present at the same time to have proper IC
behavior.
The functionality of the device and the measured acceleration/angular rate data are
selectable and accessible through the I²C or SPI interfaces. When using the I²C protocol,
CS must be tied high. Every time the CS line is set to low level, the I²C bus is internally
reset.
All the functions, the threshold and the timing of the two interrupt pins can be completely
programmed by the user through the I²C/SPI interface.
8 Register mapping
The table given below provides a list of the 8/16-bit registers embedded in the device and
the corresponding addresses.
9 Register description
The device contains a set of registers which are used to control its behavior and to retrieve
linear acceleration, angular rate and temperature data. The register addresses, made up of
7 bits, are used to identify them and to write the data through the serial interface.
TRIG_ Selects the trigger for the internal counter of batching events between XL and gyro.
COUNTER_ (0: XL batching event;
BDR 1: GYRO batching event)
In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the
CNT_BDR_ threshold for the internal counter of batching events. When this counter reaches the
TH_[9:8] threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2
(3Bh) is set to ‘1’.
0 0 Normal mode
0 1 Positive sign self-test
1 0 Not allowed
1 1 Negative sign self-test
0 0 Normal mode
0 1 Positive sign self-test
1 0 Negative sign self-test
1 1 Not allowed
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D6D_ Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
IA (0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
ZH
(0: event not detected; 1: event (over threshold) detected)
Z-axis low event (under threshold). Default value: 0
ZL
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
YH
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
YL
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
XH
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
XL
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready pulsed bit of
the COUNTER_BDR_REG1 (0Bh) register.
DIFF_ Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
FIFO_[9:8] In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)
The formula below can be used to calculate a better estimation of the actual timestamp
resolution:
TS_Res = 1 / (40000 + (0.0015 * INTERNAL_FREQ_FINE * 40000))
where INTERNAL_FREQ_FINE is the content of INTERNAL_FREQ_FINE (63h).
The formula below can be used to calculate a better estimation of the actual ODR:
ODR_Actual = (6667 + ((0.0015 * INTERNAL_FREQ_FINE) * 6667)) / ODR_Coeff
Selected_ODR ODR_Coeff
12.5 512
26 256
52 128
104 64
208 32
416 16
833 8
1667 4
3333 2
6667 1
The Selected_ODR parameter has to be derived from the ODR_XL selection (Table 39:
CTRL1_XL register description) in order to estimate the accelerometer ODR and from the
ODR_G selection (Table 41: CTRL2_G register description) in order to estimate the
gyroscope ODR.
0x01 Gyroscope
0x02 Accelerometer
0x03 Temperature
0x04 Timestamp
0x05 CFG_Change
The following distributions were calculated by measuring 100 samples at room temperature
in the characterization lab.
11 Soldering information
The LGA package is compliant with the ECOPACK, RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems.
12 Package information
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A (max) 330
B (min) 1.5
C 13 ±0.25
D (min) 20.2
N (min) 60
G 12.4 +2/-0
T (max) 18.4
13 Revision history
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ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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