Faculty of Engineering, Computing & Science

Unit Outline

EEE20001
Digital Electronics Design
Semester 2 2023

Please read this Unit Outline carefully. It includes:

PART A Unit summary
PART B Your Unit in more detail
PART C Further information
PART A: Unit Summary

Unit Code(s) EEE20001

Unit Title Digital Electronics Design
Duration Semester 2, 2023
Total Contact Hours 5 hours/week
Requisites:

Pre-requisites -
Co-requisites -
Concurrent pre-requisites -
Anti-requisites -
Assumed knowledge -
Credit Points 12.5
Campus/Location Sarawak
Mode of Delivery Face to face
As the minimum requirements of assessment to pass a unit
Assessment Summary and meet all Unit Learning Outcomes to a minimum
standard, a student must achieve:
(i) an aggregate mark of 50% or more, and
(ii) at least 40% in the final exam.
Students who do not successfully achieve hurdle
requirement (ii) will receive a maximum of 45% as the total
mark for the unit.

Aims
After successfully completing this unit, students should be able to apply a variety of
application-oriented digital electronics design skills, including:
• The design of significant combinatorial & synchronous digital systems
• Timing and hazard analysis for reliable digital circuit designs
• The use of Electronic Design Automation (EDA) tools for design, analysis and
simulation

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Unit Learning Outcomes
Students who successfully complete this Unit should be able to:
1. Design and implement combinatorial digital circuits using gates and logic
components such as multiplexers and decoders. (K2, K3, S1, S2, S3) (EAC PO3)

2. Design and implement synchronous digital systems including counters, arbitrary

sequence counters and general state machines. (K2, K3, S1, S2, S3)(EAC PO3)

3. Design and implement standard Mealy and Moore style state machines. (K2, K3,
S1, S2, S3) (EAC PO3)

4. Design and implement in programmable logic moderately complex digital systems

that incorporate control (ULO 3) and data operations (ULOs 1 and 2). (K2, K3,
S1, S2, S3) (EAC PO3)

5. Use a hardware description language (VHDL) to implement ULOs 1, 2, 3 and 4.

(K2, K3, S1, S2, S3) (EAC PO5)

6. Apply Electronic Design Automation (EDA) tools to carry out ULOs 1,2,3,4 and 5.
(S1, S2, S3) (EAC PO5)

7. Appreciate real-world considerations in the design of digital circuits e.g. non-ideal

inputs, timing requirements and hazards. (K2, K3, S1, S3) (EAC PO1)

8. Analyse a problem scenario leading to a design and implementation based upon

digital logic using appropriate techniques. (S1, S2, S3) (EAC PO2)

Graduate Attributes
This unit may contribute to the development of the following Swinburne Graduate Attributes:
 Communication skills
 Teamwork skills
 Digital literacies

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Content
Boolean Algebra and Logic Design
 Number systems
 Basic Theorems of Boolean Algebra
 Canonical and Standard Forms
 Logic Gate Implementations and Characteristics: propagation delays, logic levels and
compatibility.
Simplification of Boolean Functions
 Prime Implicants, etc
 Map and Tabulation Methods
 Technology Mapping for Gate Arrays
 Hazards in digital circuits.
Introduction to Logic Circuits
 Combinatorial Components
 Adders/Subtracters
 Logic and Arithmetic Units
 Decoders/Selectors
 Buses
 Priority Encoders
 Magnitude Comparators
 Shifters and Rotators
 Multipliers
 Real world considerations.
Programmable Logic Devices
 Read Only Memory
 Programmable Logic Arrays (PLAs)
 Programmable Array Logic (PALs) Devices
 Field Programmable Gate Arrays (FPGAs).
Synchronous Sequential Logic
 Latches
 Flip Flops
 Finite-State Machine (FSM) Model
 Synthesis and Analysis
 Designing State Machines using State Diagrams
 Designing State Machines using ASM (Algorithmic State Machine) Charts
 State Minimisation, Optimisation and Timing.
Hardware Description Languages (VHDL)
 Combinatorial descriptions
 Delta Delays
 VHDL hierarchy (Entities, modules, instantiation)
 Language constructs (conditional assignment, selected assignment)
 Synchronous descriptions (processes, if, case)
 VHDL test benches
 Synthesis considerations.

Key Program Outcomes (Swinburne Engineering Competencies) for this Unit of Study
This unit will contribute to your attaining the following Program Outcomes (Swinburne
Engineering competencies):

K2 Maths and IT as Tools: Proficiently uses relevant mathematics and computer and
information science concepts as tools in complex engineering activities.

K3 Discipline Specific: Proficiently applies advanced technical knowledge of Electrical

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 and Electronic Engineering within that context.

K4 Emerging Disciplinary Trends: Proficiently applies research principles and methods

on current or emerging complex problems of Electrical and Electronic Engineering.

S1 Engineering Methods: Applies engineering methods in practical applications and

complex engineering problems.

S2 Problem Solving: Systematically uses current or emerging knowledge and research

methods to undertake independent research in solving complex engineering problems and
as preparation for research higher degrees.

S3 Design: Systematically uses engineering methods in designing solutions to complex

engineering problems.

Key Engineering Accreditation Council (EAC) Program Outcomes for this Unit of
Study
This unit will contribute to your attaining the following Engineering Accreditation Council
(EAC) Program Outcomes:
PO1 Engineering Knowledge: Apply knowledge of mathematics, natural science,
engineering fundamentals and an engineering specialisation as specified in WK1 to WK4
respectively to the solution of complex engineering problems.
PO2 Problem Analysis: Identify, formulate, conduct research literature and analyse
complex engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences and engineering sciences. (WK1 to WK4)

PO3 Design/Development of Solutions: Design solutions for complex engineering

problems and design systems, components or processes that meet specified needs with
appropriate consideration for public health and safety, cultural, societal, and environmental
considerations. (WK5).

PO5 Modern Tool Usage: Create, select and apply appropriate techniques, resources, and
modern engineering and IT tools, including prediction and modelling, to complex engineering
problems, with an understanding of the limitations. (WK6)

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PART B: Your Unit in more detail
Unit Improvements
Feedback provided by previous students through the Student Survey has resulted in
improvements that have been made to this unit. Recent improvements include:
• The exam will be divided into two parts: 10 MCQ and 4 Structural Questions
• Provide support for the final exam preparation

Unit Teaching Staff

Name Role Room Phone Email Consultation Times

Tay Fei Siang Unit E315 260 851 [email protected] By appointment

Convenor through email

Learning and Teaching Structure

Activity Total Hours Hours per Week Teaching Period Weeks

Lectures 36 hours 3 hours Weeks 1 to 14

Tutorials 12 hours 2 hours Refer to Week by Week Schedule
Laboratory Work 14 hours 2 hours Refer to Week by Week Schedule

Week by Week Schedule

Week Week Beginning Teaching and Learning Activity Student Task or Assessment

• Introduction
1 Sep-4 • Number system
• Boolean Algebra Tut 1
2 Sep-11 • Boolean applications Do prelim for E1
E1 – Prototyping
• Karnaugh maps
3 Sep-18 Introduction. Collect and sign for
• NAND & NOR implementation
laboratory equipment.

Tut 2 & 3
• Hazards
4 Sep-25 Do prelim for E2
• Latches & flip-flops
E1 Due
• MSI logics
5 Oct-2 E2 – Basic Circuits
• Registers & Counters

Tut 4 & 5
6 Oct-9 • Sequential circuits Do prelim for E3
E2 Due

7 Oct-16 Tuition Week – Self Revision

• VHDL intro
8 Oct-23 E3 – MSI and Sequential Circuits
• VHDL constructs

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 Do prelim for E4
E3 Due
9 Oct-30 • VHDL for sequential circuits Tut 6 & 7

10 Nov-6 • VHDL for state machines E4 – Sate Machine Design

• VHDL system level
11 Nov-13 • VHDL design considerations E5 – VHDL Design Project session 1
• Common VHDL errors Tut 8 & 9

12 Nov-20 • State assignment and reduction E5 – VHDL Design Project session 2

• Arithmetic E5 – VHDL Design Project session 3

13 Nov-27
• SM charts Tut 10 & 11
Tuition Week – Self Revision
14 Dec-4
E5 Due

Assessment
a) Assessment Overview

Unit Learning
Individual Outcomes that Assessment
Tasks and Details Weighting
or Group this assessment Due Date
task relates to
E1 (Lab):
Group 5% 1,2,7
Prototyping Introduction
E2 (Lab):
Group 5% 2,3
Basic Circuits
E3 (Lab): Refer to the
Week by Week
MSI and Sequential Group 7.5% 1,3,4
Schedule
Circuits above.
E4 (Lab):
Group 7.5% 1,3,4
State Machine Design
E5 (Project):
Group 15% 5,6,7,8
VHDL Design Project
Final Exam Formal Exam
Individual 60% 1,2,3,4,5,8 Period

b) Minimum requirements to pass this Unit

As the minimum requirements of assessment to pass a unit and meet all Unit Learning
Outcomes to a minimum standard, a student must achieve:
(i) an aggregate mark of 50% or more, and
(ii) at least 40% in the final exam.
Students who do not successfully achieve hurdle requirement (ii) will receive a
maximum of 45% as the total mark for the unit.

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c) Examinations
If the unit you are enrolled in has an official examination, you will be expected to be
available for the entire examination period including any Special Exam period.
d) Submission Requirements
Assignments and other assessments are generally submitted online through the Canvas
assessment submission system which integrates with the Turnitin plagiarism checking
service.
Please ensure you keep a copy of all assessments that are submitted.
In cases where a hard copy submission is required an Assessment Cover Sheet must
be submitted with your assignment. The standard Assessment Cover Sheet is available
from the CANVAS course site.
e) Extensions and Late Submission
Late Submissions - Unless an extension has been approved, late submissions will result
in a penalty. You will be penalised 10% of your mark for each working day the task is
late, up to a maximum of 5 days. After 5 working days, a zero result will be recorded.
f) Referencing
To avoid plagiarism, you are required to provide a reference whenever you include
information from other sources in your work. Further details regarding plagiarism are
available in Section C of this document.
Referencing conventions required for this unit are: Swinburne Harvard Style
Helpful information on referencing can be found at
https://www.swinburne.edu.my/library/referencing
g) Groupwork Guidelines
A group assignment is the collective responsibility of the entire group, and if one
member is temporarily unable to contribute, the group should be able to reallocate
responsibilities to keep to schedule. In the event of longer-term illness or other serious
problems involving a member of group, it is the responsibility of the other members to
notify immediately the Unit Convenor or relevant tutor.
Group submissions must be submitted with an Assignment Cover Sheet, signed by all
members of the group.
All group members must be satisfied that the work has been correctly submitted. Any
penalties for late submission will generally apply to all group members, not just the
person who submitted.

Required Textbook(s)
Roth, HR, (2010) Fundamentals of Logic Design, 6th edn, Thomson-Brooks/Cole.
https://swinburne.librarynet.com.my/Angka.sa2/swinburne/BibDetail.htm?bibId=597588

Recommended Reading Materials

The Library has a large collection of resource materials, both texts and current journals. Listed below
are some references that will provide valuable supplementary information to this unit. It is also
recommended that you explore other sources to broaden your understanding.

Online Databases
https://www.swinburne.edu.my/library/databases/databases-a.php

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eBooks
https://www.swinburne.edu.my/library/databases/ebooks.php

Online Magazines
https://www.swinburne.edu.my/library/search/magazines.php

Wakerly, JF, Digital Design, Pearson-Prentice-Hall, 2006. ISBN 0-13-186389-4.

https://swinburne.librarynet.com.my/Angka.sa2/swinburne/BibDetail.htm?bibId=727985

Katz, RH, Borriello, G, Contemporary Logic Design, Pearson-Prentice-Hall, 2005. ISBN 0-201- 30857-
6.
https://swinburne.librarynet.com.my/Angka.sa2/swinburne/BibDetail.htm?bibId=373744

Ashenden, PJ, The Student's Guide to VHDL, Morgan-Kaufmann, 1998. ISBN 1-55860-520-7
https://swinburne.librarynet.com.my/Angka.sa2/swinburne/BibDetail.htm?bibId=597531

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PART C: FURTHER INFORMATION

For further information on any of these topics, refer to Swinburne’s Current

Students web page https://www.swinburne.edu.my/current-students

Student behaviour and wellbeing

All students are expected to: act with integrity, honesty and fairness: be inclusive, ethical and
respectful of others; and appropriately use University resources, information, equipment and facilities.
All students are expected to contribute to creating a work and study environment that is safe and free
from bullying, violence, discrimination, sexual harassment, vilification and other forms of unacceptable
behaviour.
The Student Handbook describes what students can reasonably expect from Swinburne in order to
enjoy a quality learning experience. The Handbook also sets out what is expected of students with
regards to your studies and the way you conduct yourself towards other people and property.
You are expected to familiarise yourself with University regulations and policies and are obliged to
abide by these, including the Student Academic Misconduct Regulations, Student General
Misconduct Regulations and the People, Culture and Integrity Policy. Any student found to be in
breach of these may be subject to disciplinary processes.
Examples of expected behaviours are:
• conducting yourself in teaching areas in a manner that is professional and not disruptive to
others
• following specific safety procedures in Swinburne laboratories, such as wearing appropriate
footwear and safety equipment, not acting in a manner which is dangerous or disruptive (e.g.
playing computer games), and not bringing in food or drink
• following emergency and evacuation procedures and following instructions given by
staff/wardens in an emergency response

Canvas
You should regularly access the Swinburne learning management system, Canvas, which is available
via the Current Students webpage or https://swinburnesarawak.instructure.com/ Canvas is updated
regularly with important unit information and communications.

Communication
All communication will be via your Swinburne email address. If you access your email through a
provider other than Swinburne, then it is your responsibility to ensure that your Swinburne email is
redirected to your private email address.

Academic Integrity
Academic integrity is about taking responsibility for your learning and submitting work that is honestly
your own. It means acknowledging the ideas, contributions and work of others; referencing your
sources; contributing fairly to group work; and completing tasks, tests and exams without cheating.
Swinburne University uses the Turnitin system, which helps to identify inadequate citations, poor
paraphrasing and unoriginal work in assignments that are submitted via Canvas. Your Unit Convenor
will provide further details.
Plagiarising, cheating and seeking an unfair advantage with regards to an exam or assessment are all
breaches of academic integrity and treated as academic misconduct.
Plagiarism is submitting or presenting someone else’s work as though it is your own without full and
appropriate acknowledgement of their ideas and work. Examples include:
• using the whole or part of computer program written by another person as your own

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 • using the whole or part of somebody else’s written work in an essay or other assessable
work, including material from a book, journal, newspaper article, a website or database, a set
of lecture notes, current or past student’s work, or any other person’s work
• poorly paraphrasing somebody else’s work
• using a musical composition or audio, visual, graphic and photographic work created by
another
• using realia created by another person, such as objects, artefacts, costumes, models
• submitting assessments that have been developed by another person or service (paid or
unpaid), often referred to as contract cheating
• presenting or submitting assignments or other work in conjunction with another person or
group of people when that work should be your own independent work. This is regardless of
whether or not it is with the knowledge or consent of the other person(s). Swinburne
encourages students to talk to staff, fellow students and other people who may be able to
contribute to a student’s academic work but where an independent assignment is required,
the work must be the student’s own
• enabling others to plagiarise or cheat, including letting another student copy your work or by
giving access to a draft or completed assignment
The penalties for academic misconduct can be severe, ranging from a zero grade for an assessment
task through to expulsion from the unit and, in the extreme, exclusion from Swinburne.

Student support
Swinburne offers a range of services and resources to help you complete your studies successfully.
Your Unit Convenor or Student Development and Support can provide information about the study
support and other services available for Swinburne students.

Special consideration
If your studies have been adversely affected due to serious and unavoidable circumstances outside of
your control (e.g. severe illness or unavoidable obligation), you may be able to apply for special
consideration (SPC).
Applications for Special Consideration to be submitted to Student Information Centre (SIC) normally
no later than 5.00pm on the third working day after the submission/sitting date for the relevant
assessment component.

Accessibility needs
Sometimes students with a disability, a mental health or medical condition or significant carer
responsibilities require reasonable adjustments to enable full access to and participation in education.
Your needs can be addressed to Student Counsellors. The plan makes recommendations to
university teaching and examination staff. You must notify AccessAbility Services of your disability or
condition within one week after the commencement of your unit to allow the University to make
reasonable adjustments.

Review of marks
An independent marker reviews all fail grades for major assessment tasks. In addition, a review of
assessment is undertaken if your final result is between 45 and 49 or within 2 marks of any grade
threshold.
If you are not satisfied with the result of an assessment, you can ask the Unit Convenor to review the
result as a local resolution. Your request must be made in writing within 10 working days of receiving
the result. The Unit Convenor will review your result to determine if your result is appropriate.
If you are dissatisfied with the outcomes of the review, you can lodge a formal complaint and apply for
Reassessment.

Feedback, complaints and suggestions

In the first instance, discuss any issues with your Unit Convenor. If you are dissatisfied with the
outcome of the discussion or would prefer not to deal with your Unit Convenor, then you can complete
a feedback form. See Complaints & Feedback.

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Advocacy
Should you require assistance with any academic issues, University statutes, regulations, policies and
procedures, you are advised to seek advice from Student Support and Advocacy within the University.
For more information, please see Student Support and Advocacy.

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