2022 2nd International Conference on Intelligent Technologies (CONIT)

Karnataka, India. June 24-26, 2022

Design Methods in Nanotechnology Using

Quantum Dot Cellular Automata (QCA)
Madhavi Repe1 Dr. Sanjay Koli2
Department of Electronics and Telecommunication Engineering, Department of Electronics and Telecommunication Engineering,
SavitriBai Phule Pune University SavitriBai Phule Pune University
Research scholar, GHRCEM, Wagholi Pune India and Assistant HOD, E&TC, Dr D Y Patil School of Engineering, Charholi
Professor at Dr. D Y Patil Institute of Technology, Bk., Via. Lohegaon, Pune, India
Pimpri,Pune, India [email protected]
[email protected]
[email protected]

Abstract— Quantum Dot Cellular Automata is the extension

of CMOS technology. In CMOS technology further scaling
down is not possible. QCA is the solution for it and overcomes
2022 International Conference on Intelligent Technologies (CONIT) | 978-1-6654-8407-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/CONIT55038.2022.9848011

the drawbacks in CMOS. This paper gives the evaluation of

sequential circuit designs and techniques used to design flip
flop. This will help the researchers to compare, combine and
innovate other ways to further improve the parameters like cell
count, device density, delay and energy dissipation. This paper Fig. 1. Cell structure
gives comparison of methods used to design flip flops and the
best among them. D FF designed using traditional Majority
gate or rotated three input majority gate gives optimized result
in terms of cells, area and clock cycle. It makes use of just 20
cells, 0.02μm2 area and 1 clock cycle. QCADesigner version
2.0.3 software and QCADesinger E is used to verify the
simulation results in QCA. Further optimization and
digitalization is possible by improving the parameters and by
making use of innovative methods.

Keywords—Quantum Dot Cellular Automata (QCA), CMOS,

Sequential Circuits, Majority Gate (MG), Random Access
Memory (RAM), Nanotechnology, Flip Flop.
Fig. 2. States of a cell
I. INTRODUCTION
ሺఘభ ାఘయ ሻିሺఘమ ାఘర ሻ
Beyond CMOS technology is the Nanotechnology. QCA P= …………………………… (1)
ఘభ ାఘమ ାఘయ ାఘర ሻ
(Quantum Dot Cellular Automata) is the best solution for
CMOS limitations like power consumption, short channel In QCA, QCA wire, inverter and Majority Gate (MG) are
effect, parasitic capacitance, high lithography and leakage the three main components.
current. QCA is the best technology amongst the various
alternatives introduced in [1-3]. QCA wires are used to transfer information from one cell
to other. QCA has two types of wires, 450 wires and 900 wires
QCA cells, is the main logic unit in Quantum Dot Cellular due to two orientations of cells [5]. These wires are as shown
Automata which has four quantum dots placed at the four in figure 3 and figure 4 respectively.
corners of square. Each cell consists of two mobile electrons.
These electrons can tunnel between the quantum dots with
quantum mechanics technique [4]. Due to columbic repulsion
electrons will try to occupy the diagonally opposite positions
in a cell [5]. These electrons give two possibilities and these
possibilities are termed as cell polarizations or states of cell.
Depending on the position of electrons in a cell, cell can be
said to be in state 0 or state 1. It can also be used to represent Fig. 3. 450 wire
a binary 0 or a binary 1. The placement of quantum dots with
electrons is shown in figure1. Figure 2 shows state 0 and
state 1 of a cell. States of a cell is decided by using the
quantum dot numbering and electron placement in a dot.
Equation 1 is used to find the polarization of a cell.
Fig. 4. 900 wire

978-1-6654-8407-7/22/$31.00 ©2022 IEEE 1

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 Inverter is the basic building block in designing digital
circuits. Researchers have designed different inverters to
achieve best results in terms of parametric optimization.
Inverter using two cells in QCA is shown in figure 5 and a
more robust fork shaped QCA inverter is shown in figure 6.

Fig. 5. QCA Inverter

Fig. 8. QCA clock phases

II. METHODOLOGIES
Sequential circuits are designed in QCA using different
methods. Flip flops are the basic building blocks in sequential
circuits. In this section, methods used to design different
types of flip flops are discussed. These designed flip flops are
further used to design applications in embedded systems to
increase the speed of operation, reduce energy dissipation and
increase device density.
Till now, researchers designed flip flops by considering
Fig. 6. Fork shaped robust QCA Inverter the Boolean expression simplification, using 2:1 multiplexer,
2:1 multiplexer and XOR gate, three input traditional MG or
MG, as the name suggests gives the majority of the three rotated MG, three input or five input majority gate, to
inputs at the output. A three input MG consist of 5 quantum improve the speed different clocking schemes can be used
cells, three are input cells, 1 of them is a device cell or middle like 2-D Wave clocking, using characteristics equations of the
cell and the output cell. MG is used to design ‘OR’ gate and flip flops, cell placements or cell arrangement method etc.
‘AND’ gate by making one of the input polarized to ‘0’ to get
AND gate and as a OR gate by making one of the input D FFs are designed with different triggering methods. D
polarized to ‘1’. The majority gate is shown in figure 7. FF can be achieved using positive edge triggering, negative
edge triggering and dual edge triggering. These types of flip
flops are designed using a converter QCA layout. An ‘edge to
level’ or a ‘level to edge’ converter QCA layout is designed
in order to get triggered flip flop designs.
Table 1 to 4 shows the methods used to design all the flip
flops like SR FF, D FF, JK FF and T FF. Table 5 shows
different applications designed using these flip flops. All the
design layouts are done with coplanar crossover.

TABLE I. METHODS USED TO DESIGN SR FLIP FLOPS

Circuit Method Used Nos of Total Delay
Designed cells Area
(μm2)
SR FF [7] 1 MG, 3 Inverters 14 0.012 1
Developed a standard
SR FF [8] 38 0.040 1.50
equation
SR FF [9] 2:1 Mux and MV3 40 0.04 1

TABLE II. METHODS USED TO DESIGN D FLIP FLOPS

Fig. 7. Three input Majority Gate Circuit Method Used Nos of Total Delay
Designed cells Area
Clocking in QCA is one of the important and totally (μm2)
different concepts as compared to CMOS clocking [6]. QCA D FF [7] 1 MG 20 0.02 1
clocking provides synchronization and providing power to D FF [8] Using SR FF [8] 43 0.042 1.25
quantum dots for tunnelling. Zone clocking is used in QCA in Using inversion
D FF [10] between S and R 21 0.024 1
which each cell is clocked using four phase clocking scheme.
inputs of SR FF
These four phases are Switch, Hold, Release and Relax. D FF [11] Efficient 2:1 Mux 35 0.03 2
Clock phases are indicated in figure 8. Rising Edge Using rising edge 56 0.06 2.5

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 Triggered D FF Converters FF is designed efficiently using traditional 3 input MG and
[12] rotated 3 input MG. D FF parameters with both these
Falling Edge methods makes use of very less number of cells, area and just
Using falling edge
Triggered D FF 56 0.06 2.5
[12]
Converters 0.5 or 1 clock cycle. JK FF and T FF with 3 MGs and 2
Dual Edge inverters is the best method among the all.
Using Dual edge
Triggered D FF 83 0.08 2.5
Converters III. IMPLEMENTATIONS
[12]
Rising Edge Using Level to edge
The design layout and simulation result of the efficient
Triggered D FF Converter, Mux, 53 0.04 2.25
[13] MG and Inverter flip flops is shown in figure 9 to figure 13. The layout shows
Falling Edge Using Level to edge the number of cells used, total area required in terms of length
Triggered D FF Converter, Mux, 53 0.04 2.25 and width (L x W) with QCADesigner software. It makes use
[13] MG and Inverter of standard cells of 18x18 nm. The coloured cells indicate the
Dual Edge Using Level to edge different clock phases as indicated in figure 8.
Triggered D FF Converter, Mux, 65 0.05 2.25
[13] MG and Inverter Simulation result shows the input and output waveforms
Level Triggered for a particular flip flop design with polarization achieved at
Rotated 3 input MG 23 0.02 0.5
D FF [14] the output and also the error free result.
Positive Edge
Triggered D FF Rotated 3 input MG 47 0.04 1.75
[14]
Negative Edge
Triggered D Rotated 3 input MG 47 0.04 1.75
FF[14]
Dual Edge
Triggered D FF Rotated 3 input MG 81 0.1 2.25
[14]
Level Triggered
5 input Rotated MG 37 0.035 0.75
D FF [15]
Positive Edge
Triggered D FF 5 input Rotated MG 59 0.06 2
[15]
Negative Edge
Triggered D 5 input Rotated MG 59 0.06 2
FF[15]
Dual Edge
Triggered D FF 5 input Rotated MG 91 0.11 2.25
[15]

TABLE III. METHODS USED TO DESIGN JK FLIP FLOPS

Circuit Method Used Nos of Total Delay
Designed cells Area
(μm2)
JK FF [7] 3 MG, 2 Inverters 21 0.03 1
Updating standard
JK FF [8] 78 0.071 1.50 Fig. 9. Layout and simulation result of efficient SR FF [7]
equation [8]
JK FF [9] 2, 2:1 Mux 52 0.06 0.75

TABLE IV. METHODS USED TO DESIGN T FLIP FLOPS

Circuit Method Used Nos of Total Delay
Designed cells Area
(μm2)
T FF [7] 3 MG, 2 Inverters 30 0.03 1
T FF [8] Using JK FF [8] 81 0.066 1.50
Using XOR gate
T FF [9] 43 0.047 1
and 2:1 Mux

TABLE V. METHODS USED TO DESIGN APPLICATION

Circuit Method Used Nos of Total Delay
Designed cells Area
(μm2)
Shift Register
using JK FF Using JK FF [7] 173 0.16 1
[7]
Shift Register
Using D FF[7] 138 0.14 4
using D FF [7]
5 input Rotated
RAM[15] 75 0.098 1.5
MG

The tabular data in terms of various parameters depicts

that SR FF designed with MG and inverter gate is efficient
considering cell count, total cell area and speed parameters. D Fig. 10. Layout and simulation result of efficient D FF [7]

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 Fig. 13. Layout and simulation result of efficient T FF [7]

The efficient and error free designed flip flops methods

are summarized in table 6. Researchers can use this as a
reference to innovate different combination of methods or
new method to get optimized parameters in order to get
further improvements especially speed parameter in
sequential circuits.

TABLE VI. SUMMARY OF EFFICIENT DESIGN METHODS

Fig. 11. Layout and simulation result of efficient Negative edge triggered
D FF [14] Circuit Designed Method Nos of Total Delay
Used cells Area
(μm2)
1 MG, 3
SR FF [7] 14 0.012 1
Inverters
D FF [7] 1 MG 20 0.02 1
Positive or Negative
Rotated 3
Edge Triggered D 47 0.04 1.75
input MG
FF[14]
Dual Edge Triggered Rotated 3
81 0.1 2.25
D FF [14] input MG
3 MG, 2
JK FF [7] 21 0.03 1
Inverters
3 MG, 2
T FF [7] 30 0.03 1
Inverters
Shift Register using Using D
138 0.14 4
D FF [7] FF[7]
5 input
RAM[15] Rotated 75 0.098 1.5
MG

IV. CONCLUSIONS
All the recent papers are reviewed and the efficient
method in terms of optimized parameters is concluded.
Sequential circuits like counters, registers, memory blocks
and other complex embedded applications can be designed
with any of these methods by observing the evaluation
achieved to get optimized design in terms of cell count,
device density and speed. D FF with edge triggering shows
that use of Mux, MG, converter and rotated 3 input MG are
the best method to get all optimized parameters except clock
Fig. 12. Layout and simulation result of efficient JK FF [7]
cycles required. A novel method for this can be designed to
increase the speed of operation and hence the computation
speed in complex digital circuits or embedded systems. P.
Azhagu Pradeepa et. al have given the efficient method
among the all. Researchers can make use of these efficient
methods and can use them in building different applications
to achieve improvement in either of these parameters. The
layout and simulation is performed in QCADesigner 2.0.3
and QCA Designer E software.

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