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What Are UVM Phases

UVM phases are predefined virtual functions/tasks in UVM components that define the order of operations for classes extending from UVM components. This allows components like the test, environment, driver, and monitor to be created, connected, and execute their functionality in synchronization. The main phases are build, connect, run, extract, check, and report, with run being the task that drives simulation and the others being top-down or bottom-up functions.

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Kishore Kishu
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235 views

What Are UVM Phases

UVM phases are predefined virtual functions/tasks in UVM components that define the order of operations for classes extending from UVM components. This allows components like the test, environment, driver, and monitor to be created, connected, and execute their functionality in synchronization. The main phases are build, connect, run, extract, check, and report, with run being the task that drives simulation and the others being top-down or bottom-up functions.

Uploaded by

Kishore Kishu
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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What are UVM Phases?

-> UVM Phases are predefined virtual function / tasks defined in UVM component

which are supposed to be populated by classes extending from UVM component.

-> These pre-defined virtual methods give each class (extended from UVM component) in the

TB a common understanding of what should be executed in each phase.

-> This allows the entire TB components to be created, connected, and their functionality executed

in synchronization.

-> In simpler terms, the test, environment, agent, driver, monitor, sequencer, scoreboard,

and subscriber i.e each component will have common understanding when to be created,

when to make connections with each other, and when to start executing the functionality

written in the run phase and when to stop and complete the simulation in well defined order.

What are different phases in UVM

What are the phases in uvm ?

Build - Build the TB components (Top - Down)

Connect - Connects the components using TLM

End of elaboration - Fianl adjustments in infrastructure.

Start of simulation - Marketing purposes

Run phase - Actual simulation happens, Driver drives the data to dut and

monitor captures the response back from the dut.(task)

Extract - retrives and processes the information from the SB and coverage model

Check - Compares the data

Report - Final report on compared data

Final - Completes if any outstanding actions are pending. (Bottom up)

Why do we require phases in UVM?

-> Basically, all the components in the TB need to work as a team for the TB to work in perfect sync.
Phases helps in fulfilling this objective.

-> The UVM TB follows a pre-defined sequence of UVM_PHASES and having said that;

the TB will only move on to the next phase if all the TB components are done with executing their

respective phase’s work.

-> Yes, UVM waits for all the quicker & slower ones…

which are top_down and bottom_up approches in it ?

top-down : Build phase

final phase

bottom_up :Connect phase

End of elaboration phase

Start of simulation phase

Extract phase

Check phase

Report phase

task : run phase

Which phase is top _down approach? why?

Reason why build phase is Top down in UVM

-> Generally when we are building a testbench in uvm if we look at the hierarchy we will find

at the top there is something called as tb_top or top module which is the static part of

the testbench.

-> So when run_test is called from the top module it initiates uvm phasing mechanism which in

turn called uvm_test and it executes the build phase of the test class.

The build phase of test in turn called the environment and then environment is going to call

the agent and so on.

-> Basically the child class can not inherit the properties or it can not be built until the
upper level components in the hierarchy wouldn’t get created.

-> The build phase has to be constructed first so that the top level components has to be built

before moving down to the next level of hierarchy

How the phases will be triggered?

To start a UVM Testbench, the run_test() method has to be called from the static part of the
Testbench

i.e called from an initial block in the top module of the Testbench.

Once the run_test() method is called, it constructs the root component of the UVM
environment

& then triggers the UVM Phasing process.

what is the Usage of run time phases in uvm

1. stimulus generation

2. reset the DUT

3. configure and program the DUT

4. Generation of testcases

5. shutdown

-> phase synchronization using uvm_domain

-> creation of user defined phases

-> synchronisingand unsynchronising of inter-dependent phases using sync and unsynchronising

-> insertion of used defined phases using before_phase

-> phase

which phase will consume time?why?

- run phase will consume time


- it comsume time as it is Used for stimulus generation, driving, monitoring,and checking.

Which phase are functions and tasks.

the run phase is a task and all other phases are function

Why are phases introduced for UVM based SV TB but not for Verilog-based TB?

- All components are static in Verilog-based TB whereas SV introduced OOP feature in the TB.

- In Verilog, as modules are static, users don’t have to care about their creation as they would

have already created at the beginning of the simulation.

- In the case of UVM based SV TB, class objects can be created at any time during the simulation

based on the requirement.

- Hence, it is required to have proper synchronization to avoid objects/components being called

before they are created, The UVM phasing mechanism serves the purpose of synchronization.

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