A B C D E

1 1

2
Compal Confidential 2

FH5AT/FH4AT MB Schematic Document

https://vinafix.com
LA-K091P
3 3

Rev: 1.B

2020.07.08

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 1 of 102
A B C D E
 A B C D E

Interleaved Memory
Compal Confidential
Model Name: TGL-UP3 DDR4-ON BOARD 4G 512Mbx16
Project Name: LA-K091P
page 24 260pin DDR4-SO-DIMM X1
OR
1 1

DDR4-ON BOARD 8G 1024Mbx16 page 23

page 72
page 24
page 66 page 38 page 38
I/O b0ard
DIMMB DIMMA USB 2.0 Finger CMOS Touch
Memory BUS 1.2V DDR4 2400/2666/3200
Type-A conn Print Camera Screen
eDP page 38
Dual Channel
DDIx2 USBx8
48MHz USB2 port5 USB2 port 7 USB2 port 8 USB2 port 9
DDIA
USB2 port 1 USB2 port 3 USB2 port 4
HDMI Conn.page 39
Processor
page 42
HDMI x 4 lanes HDMI repeater DDIB
USB3.0 USB charger
PS8409 Intel Tiger Lake U Type-C conn SLGC55544
page 71
2 2

USB3.0 page 71
HD Audio Type-A conn
3.3V 24MHz USB3.0
Type-A conn
HDA Codec Type-C MUX
ALC255page 56 RTS5441

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Tiger Lake PCH-LP
Lane0
USB3 port 1
Lane2
USB3 port 3
Lane3
USB3 port 4
Flexible IO Lane8 Lane9 Lane10 Lane11
45.5 x 25 mm Lane4~7 PCIE port9 PCIE port10 SATA port0 SATA port1
Int. Speaker Int. DMIC UAJ PCIE port5~port8 support CNVi
on Camera PCIe 1.0
page 56 page 38 page 56 2.5GT/s PCIe 1.0 SATA Gen 3 SATA Gen 1
15W 2.5GT/s 6.0 Gb/s 1.5. Gb/s

TGL-U 4+2 PCIE 3.0 x4

3
1499pin BGA 8GT/s
LAN(GbE) NGFF WLAN SATA HDD SATA ODD 3

eSPI BUS I2C BUS

page 06~19
M.2 SSD Realtek 8111H Conn. Conn.
SPI page 51
page 67

CLK=24MHz
SPI ROM RJ45 conn. page 52
RTC CKT. ENE 128Mb page 68
page 11 KB9052 page 9
page 58 page 67

Power On/Off CKT. PS2 BUS

page 63

Int.KBD Touch Pad

DC/DC Interface CKT. Sub Board
page 70
LS-K-091P
IO/B page 63 page 63
page 72
4 Power Circuit DC/DC 4

page 81~102

LS-K093P
HS/B
Fan Control page 67
page 77
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3 Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 2 of 102
A B C D E
 A

Board ID Table for AD channel BOM Structure Table SOC SMBUS Address Table (TBC)
Vcc 3.3V HW Function BOM Structure Address (8bit)
Ra 100K +/- 1% SOC_SMBUS Net Name Power Rail Device Address (7 bit)
Write Read
Board ID /PCB Revision Rb V BID min V BID TYP V BID Max EC AD3 UMA SKU UMA@
0 --> 0.1 0 0V 0.300 V 0x00 - 0x13 +3V_PRIM DIMM1 TBC TBC 0xA0
1 --> 0.2 12K +/- 1% 0.347 V 0.354 V 0.36 V 0x14 - 0x1E CMC CMC@ SOC_SMBCLK level shift to
2 --> 0.3 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1F - 0x25 SOC_SMBDATA +3VS
G-sensor TBC TBC 0xA4
3 --> 0.4 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x26 - 0x30 EMI / EMC / ESD EMC@ XEMC@
4 --> 0.5 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3A
SOC_SML0CLK
5 --> 0.6 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3B - 0x45 RF Components @RF@ SOC_SML0DATA +3V_PRIM NC TBC TBC TBC
6 --> 0.7 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x46 - 0x54
7 --> 0.8 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64 Premium/Volume PREM@ VOL@ EC TBC TBC TBC
SOC_SML1CLK
SOC_SML1DATA +3V_PRIM
CNVI CNVi@ NC TBC TBC TBC
HSIO Port Table (CPU) USB2.0 Port Table
HSIO Port Capable Port Allocation PCIE CLK NOTE UART UART@
USB2.0 Port Device EC SMBUS Address Table
Address (8bit)
0 PCIe4 #1 1 USB Type-C ( MB ) CPU ES2_3@ ES2_i5@ ES2_i7@ EC_SMBUS Port Power Rail Device Address (7 bit)
Write Read
1 PCIe4 #2
No use NA PCIe interface 2 NA
2 PCIe4 #3 Finger Print FP@ FPEMC@ FP3V@ FP5V@ BAT 0x16 TBC TBC
EC_SMB_CK1
3 PCIe4 #4 3 USB Type-A ( MB) EC_SMB_DA1 +3VLP_EC CHGR 0x12 TBC TBC
ODD ODD@
4 USB Type-A ( MB )
HSIO Port Table (PCH)
5 USB Type-A ( IO Board ) GLITCH GLITCH@ EC_SML1CLK TBC TBC TBC
HSIO Port Capable Port Allocation PCIE CLK NOTE EC_SML1DATA NC NC
6 NA
Touch screen I2CTS@ USBTS@
0 USB3.1 #1 / PCIe #1 USB3.1 Type C NA USB3.1 interface I2C/USB
7 FP
1 USB3.1 #2 / PCIe #2 NA NA NA 8 Camera Board ID EVT@ DVT@ PVT@ I2C Address Table (TBC)
Address (8bit)
9 TP I2C Port Power Rail Device Address (7 bit)
2 USB3.1 #3 / PCIe #3 USB3.1 Type A NA USB3.1 interface TPM TPM@ Write Read
10 BT
USB3.1 Type A I2C 0 NC NA 0x0FH TBC TBC
3 USB3.1 #4 / PCIe #4 (with charger) NA USB3.1 interface Gsensor GSEN@
I2C 1 NC NA 0x48H TBC TBC
4 PCIe #5 Charger CHG@
5 PCIe #6
SSD (NGFF Key M) CLK1 & CLKREQ#1 PCIe interface I2C 2 NC NA TBC TBC TBC
6 PCIe #7 /GbE over 3 cell battery 3S@
7 PCIe #8 /GbE
I2C 3 +3VS Touch Pad 0x2CH TBC TBC
NC Components @
8 PCIe #9 /GbE GLAN CLK2 & CLKREQ#2 PCIe interface
I2C 4 NC NA 0FH TBC TBC

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MD BOM select SDP@
1
9 PCIe #10 WLAN CLK3 & CLKREQ#3 PCIe interface X76SAM4@ X76HYN4@ X76MIC4@ I2C 5 +3VS Touch Screen 1

ISH_I2C 2 (need check) ( I2C interface ) TBC TBC TBC

DDP@
10 PCIe #11 /SATA0 HDD NA SATA interface X76HYN8@ NODX76@
ISH_I2C 0 NC NA TBC TBC TBC
MD BOM select MEM@
11 PCIe #12 /SATA1 ODD NA SATA interface
ISH_I2C 1 NC NA TBC TBC TBC
ME Cnnector CONN@
Load BOM Option Table
43#
FH4AT/
Load BOM Option
Audio 255@ 256@ 255M@ Voltage Rails
FH5AT Power Plane Description S0 S0ix S3 S4/S5
431AMXBOL01/ PCB PCB@ +19V_ADPIN Adapter power supply N/A N/A N/A N/A
431AMXBOL51 GSEN@/FP@/255@/CHG@/TPM@/PREM@/DVT@/MEM@/CNVi@/CMC@/GLITCH@/UMA@/3S@/ES2_i3@/FP3V@/USBTS@/PCB@
+12.6V_BATT+ Battery power supply N/A N/A N/A N/A
431AMXBOL04/ +19VB AC or battery power rail for power circuit N/A N/A N/A N/A
431AMXBOL52 GSEN@/FP@/255@/CHG@/TPM@/PREM@/DVT@/MEM@/CNVi@/CMC@/GLITCH@/UMA@/3S@/ES2_i5@/FP3V@/USBTS@/PCB@ Power Function
+VCCIN Core voltage for CPU ON OFF OFF OFF
431AMXBOL03/ Adaptor 45W@ 65W@ +VCCIN_AUX CPU and PCH merged auxiliary power rail ON OFF OFF OFF
431AMXBOL53 GSEN@/FP@/255@/CHG@/TPM@/PREM@/DVT@/MEM@/CNVi@/CMC@/GLITCH@/UMA@/3S@/ES2_i7@/FP3V@/USBTS@/PCB@
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF OFF
TEMP. protect OTP@
+1.05V_VCCST Sustain voltage for CPU standby modes ON ON ON OFF
4 cell battery 4S_BATT@ +1.05VS_VCCSTG Gated sustain voltage for CPU standby modes ON OFF OFF OFF

EMI EMI@ @EMI@

+1.2V_VDDQ DDR4/L-RS +1.2V power rail and CPU digital PLL ON ON ON OFF
RF Components @RF@ +2.5V DDR4/L-RS +2.5V power rail ON ON ON OFF
+1.8VALW_PRIM TCSS/AGSH TypeC sub system / CPU analog power supply ON OFF OFF OFF
+1.8VALW System +1.8V power rail ON ON ON ON*
+1.8VS System +1.8VS power rail ON ON OFF OFF
+3VALW System +3VALW always on power rail ON ON ON ON*
+3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON
X4E/X76 +3VALW +3VALW power for PCH DSW rails ON ON ON ON*
X63/X4P Load BOM Option
+3V_PRIM +3VALW power for PCH suspend rails ON ON ON ON*
+3VS System +3VS power rail ON ON OFF OFF
X76826BOL51 X76HYN4@/SDP@
+1.8VS_DGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF
+1.8VS_DGPU +1.8VS power rail for GPU ON OFF OFF OFF
X76826BOL52 X76MIC4@/SDP@
+VGA_CORE Power rail for GPU ON OFF OFF OFF
+5VALW System +5VALW power rail ON ON ON ON*
X76826BOL53 X76SAM4@/SDP@
+5VS System +5VS power rail ON ON OFF OFF
+3VL_RTC RTC power ON ON ON ON
X76826BOL54 X76HYN8@/DDP@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF
X4EAMXBOL01 FPEMC@/EMC@/ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

Notes List
www.teknisi-indonesia.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 3 of 102
A
 5 4 3 2 1

[FQA01-Power Map_TGL-UP3_DDR4_Volume_S0ix]

D D

C C

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B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power MAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 4 of 102
5 4 3 2 1
 5 4 3 2 1

[ FH5AT-PWR Sequence_TGL-UP3_DDR4_Volume_S0iX ]

G3 > S0 > S5 OK, S0iX what for BIOS update

G3->S0 S0-> S0iX S0iX ->S0 S0->S5
AC_IN AC_IN

+3VLP +3VLP
2.865ms

D
EC_ON EC_ON D

+5VALW +5VALW
2.76ms

220ms
ON/OFFBTN#
ON/OFFBTN#

3V_EN -- 50.9us
91.69ms 3V_EN
+3VALW 552.5us
709us +3VALW
+1.8VALW 585.8us
1.887ms tPCH31 tPCH06 +1.8VALW
+VCCINAUX 5.002ms
2.915ms +VCCINAUX
VCCIN_AUX_CORE_VID 675.5us
630us VCCIN_AUX_CORE_VID
VCCST_OVERRIDE_LS 552.5us
VCCST_OVERRIDE_LS
+1.05VO_EXTBYPASS 931.1us
1.842ms +1.05VO_EXTBYPASS
EC_RSMRST# 8.16s
29.41ms tPCH03 EC_RSMRST#
PCH_DPWROK 8.16s
tPCH07 PCH_DPWROK
AC_PRESENT_R 240.2us
9.988ms AC_PRESENT_R
PBTN_OUT# 230.5us
120ms PBTN_OUT#
19.99ms

C PM_SLP_S4# 507us PM_SLP_S4# C

2.3s

PM_SLP_S3# 343.4us PM_SLP_S3#

SYSON 552.4ms (to slp_s4#) SYSON

7.759ms

+1.2V_VDDQ 530.2ms +2.5V

750us

+2.5V
1.331ms 530.8ms +1.2V_VDDQ

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CPU_C10_GATE# 507us CPU_C10_GATE#
1.041ms

+1.05V_VCCST 9.2s +1.05V_VCCST

SUSP# 22.77ms SUSP#

26.23ms

+5VS 23.7ms +5VS

1.435ms

+3VS 43.47ms +3VS

1.088ms

+1.8VS 24.45ms +1.8VS

687us

EC_VCCST_PG 20.09ms EC_VCCST_PG

tCPU00 46.44ms

B B
SM_PG_CTRL 26.06us SM_PG_CTRL

+0.6VS_VTT
9.425us 125.1us +0.6VS_VTT

20.12ms VR_ON
VR_ON
46.45ms

+VCCIN 67.03us +VCCIN

2.102ms

VR_PWRGD 900ns( to vr_on) VR_PWRGD

2.177ms

PCH_PWROK tPCH08 20.13ms PCH_PWROK

tCPU16 66.47ms

+1.05V_VCCIO_OUT 7.8us +1.05V_VCCIO_OUT

807.1ms

SYS_PWROK 22.83ms SYS_PWROK

109.9ms

SOC_PLTRST# SOC_PLTRST#
tPCH33 814.1ms

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K092P
Date: Wednesday, July 08, 2020 Sheet 5 of 102
5 4 3 2 1
 A B C D E

+3VS

ZZZ
RC1 1 2 2.2K_0201_5% SOC_DP2_CTRL_DATA PCB DAZ
RC2 1 2 2.2K_0201_5% SOC_DP2_CTRL_CLK

LA-K091/LS-K091/LS-K096
1 PCB FH5AT LA-K091P LS-K091P/K096P 1
UC1A
EDP_TXP3 DAZ34G00203
AC2 AY2
<38> EDP_TXP3 EDP_TXN3 DDIA_TXP_3 TCP0_TXRX_P1 PCB@
AC1 AY1
<38> EDP_TXN3 EDP_TXP2 DDIA_TXN_3 TCP0_TXRX_N1
AD2 BB1
<38> EDP_TXP2 EDP_TXN2 DDIA_TXP_2 TCP0_TXRX_P0
AD1 BB2
<38> EDP_TXN2 EDP_TXP1 DDIA_TXN_2 TCP0_TXRX_N0
AF1 AM5
<38> EDP_TXP1 EDP_TXN1 DDIA_TXP_1 TCP0_TX_P1
AF2 AM7
<38> EDP_TXN1 EDP_TXP0 DDIA_TXN_1 TCP0_TX_N1
AG2 AT7
<38> EDP_TXP0 EDP_TXN0 DDIA_TXP_0 TCP0_TX_P0
AG1 AT5
<38> EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 AP7
EDP_AUXP AJ2 TCP0_AUX_P AP5
<38> EDP_AUXP DDIA_AUX_P TCP0_AUX_N
EDP_AUXN AJ1
<38> EDP_AUXN DDIA_AUX_N AT2
1 SOC_GPP_E22 DN4 TCP1_TXRX_P1 AT1
T1 TP@ 1 SOC_GPP_E23 DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
T2 TP@ GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AU2
EDP_HPD DR5 TCP1_TXRX_N0 AD5
<38> EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1
TCP1_TX_N1
AD7 Tiger Lake-UP3 CPU SKU
SOC_DP2_P3 T12 AH7
<39> SOC_DP2_P3 SOC_DP2_N3 DDIB_TXP_3 TCP1_TX_P0
HDMI CLK T11 AH5
<39> SOC_DP2_N3 SOC_DP2_P2 DDIB_TXN_3 TCP1_TX_N0
Y11 AF7
HDMI
<39>
DATA00 <39>
SOC_DP2_P2
SOC_DP2_N2
SOC_DP2_N2 Y9 DDIB_TXP_2
DDIB_TXN_2
TCP1_AUX_P
TCP1_AUX_N
AF5 i7-1165G7-QVBA
SOC_DP2_P1 T9 UC1
<39> SOC_DP2_P1 SOC_DP2_N1 DDIB_TXP_1
HDMI DATA01 <39> P9 BF1
SOC_DP2_N1 SOC_DP2_P0 DDIB_TXN_1 TCP2_TXRX_P1
V11 BF2
<39> SOC_DP2_P0 SOC_DP2_N0 DDIB_TXP_0 TCP2_TXRX_N1
HDMI DATA02 <39> V9 BE2
SOC_DP2_N0 DDIB_TXN_0 TCP2_TXRX_P0 BE1
AB9 TCP2_TXRX_N0 BD7
2 AD9 DDIB_AUX_P TCP2_TX_P1 BD5 2
DDIB_AUX_N TCP2_TX_N1 TGL-UP3_BGA1449
AY5
SOC_DP2_CTRL_CLK TCP2_TX_P0 S IC FH8069004529905 QVBA B1 2.8G BGA S
DM29 AY7
<39> SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0 SA0000DRG30
DK27 BB5
<39> SOC_DP2_CTRL_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P QS_i7@
BB7
SOC_DP2_HPD DG43 TCP2_AUX_N
<39> SOC_DP2_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD BK1
TPM_PIRQ# DG47 TCP3_TXRX_P1 BK2
<66> TPM_PIRQ# GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
DJ47 BJ2
CHECK SW GPIO 12/10 GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0
TCP3_TXRX_N0
BJ1 i5-1135G7-QVBD
DU8 BM7 UC1
DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1 BM5

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GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1 BH5
DF6 TCP3_TX_P0 BH7
DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX_N
GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# TC_RCOMP_P TGL-UP3_BGA1449
DM23 AN2 RC11 1 2 150_0201_1%
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P TC_RCOMP_N S IC FH8069004530601 QVBD B1 2.4G BGA S
AN1
TC_RCOMP_N SA0000DRR20
DK23
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO DSI_DE_TE_2 QS_i5@
DN21 M8 RC14 1 2 100K_0201_5%
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
DF43 AB1 DDI_RCOMP RC15 1 2 150_0201_1%
1 SOC_GPP_A19 DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
T3 TP@ 1 SOC_GPP_A20 DF47 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK CE4 DISP_UTILS 1
T4 TP@ GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1 TP@ T5 i3-1115G4-QVBG
USB_OC1# DH52 UC1
<71> USB_OC1# USB_OC2# DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
<71> USB_OC2# GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
3 SOC_ENVDD DM8 3
<38> SOC_ENVDD SOC_ENBKL EDP_VDDEN
DN8
<58> SOC_ENBKL SOC_BKL_PW M EDP_BKLTEN
DG10
<38> SOC_BKL_PW M EDP_BKLTCTL
TGL-UP3_BGA1449
S IC FH8069004531502 QVBG B1 3G BGA S
TGL-U_BGA1449
SA0000DRS20
@ QS_i3@

+3VALW _PRIM

RC181 1 2 10K_0201_5% USB_OC2#

RC4012 1 2 10K_0201_5% USB_OC1#

RC307 1 2 100K_0201_5% SOC_DP2_HPD

RC16 1 2 100K_0201_5% EDP_HPD

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(1/14)DDI,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 22, 2020 Sheet 6 of 102
A B C D E
 A B C D E

+3VS
CHECK power net name, 12/13 www.teknisi-indonesia.com
+1.05VS_VCCSTG_OUT_LGC_TERM

1
1 @ 2 SOC_GPP_E7
RC23 10K_0201_5% RC24 UC1U
1K_0201_5%
1
+1.05V_VCCST CATERR# M7 K4 SOC_XDP_TRST# 1
H_PECI BK9 CATERR# PROC_TRST# B9 SOC_XDP_TMS
<58> H_PECI

2
1 2 H_PROCHOT#_R E2 PECI PROC_TMS D12 SOC_XDP_TDO
<58,84> H_PROCHOT# PROCHOT# PROC_TDO
RC25 499_0201_1% H_THERMTRIP# M5 A12 SOC_XDP_TDI
1 2 CATERR# 2 1 THRMTRIP# PROC_TDI B6 SOC_XDP_TCK0
RC26 1K_0201_5% EMC@ CC1 100P_0201_50V8J PROC_POPIRCOMP CT39 PROC_TCK
2 1 H_THERMTRIP# PCH_OPIRCOMP CB9 PROC_POPIRCOMP D8 SOC_XDP_TCK0
RC27 1K_0201_5% ESD request 1 SOC_TP_1 CW12 PCH_OPIRCOMP PCH_JTAGX A9 SOC_XDP_TMS
T6 TP@ 1 SOC_TP_2 CM39 TP_1 PCH_TMS E12 SOC_XDP_TDO
CC2 2 1 0.1U_0201_10V6K T7 TP@ TP_2 PCH_TDO B12 SOC_XDP_TDI
XDP_ITP_PMODE DF4 PCH_TDI A7 PCH_JTAG_TCK1
XEMC@ DBG_PMODE PCH_TCK H4 SOC_XDP_TRST# 1 T520 TP@
T196 1 SOC_GPP_B14 DB42 PCH_TRST#
TP@ EC_TP_INT# DB41 GPP_B4/CPU_GP3 C11 XDP_PREQ# 1 T518 TP@
<58,63> EC_TP_INT# GPP_B3/CPU_GP2 PROC_PREQ#
ESD request SOC_GPP_E7 DF8 D11 XDP_PRDY# 1 T519 TP@
DU5 GPP_E7/CPU_GP1 PROC_PRDY#
GPP_E3/CPU_GP0 G1 SOC_EAR
SOC_GPP_H2 DF31 EAR_N_TEST_NCTF
SOC_GPP_H1 DV32 GPP_H2 DT15
SOC_GPP_H0 DW32 GPP_H1 GPP_F7 DR15
<68> SOC_GPP_H0 GPP_H0 GPP_F9 DT14
DJ27 GPP_F10
GPP_H19/TIME_SYNC0

RC30 2 1 PROC_POPIRCOMP TGL-U_BGA1449

49.9_0201_1% @
RC31 2 1 PCH_OPIRCOMP
49.9_0201_1% +3VALW _PRIM
+1.05VS_VCCSTG
2 2

1
RC32

1
100K_0201_5%
RC34
@ 1K_0201_5%

2
DC9 1 2 H_PROCHOT#
<17> VCCIN_AUX_CORE_ALERT#_R

2
RB751S40T1G_SOD523-2
SOC_EAR

+3VALW _PRIM SOC_WWAN_RST#

https://vinafix.com

1
This strap should sample LOW. There should NOT be
RC35 1 @ 2 4.7K_0201_5% SOC_GPP_H2 any on-board device driving it to opposite direction RC38
SOC_GPP_H2 during strap sampling.
INTERNAL PD 20K 1K_0201_5%
RC36 1 @ 2 4.7K_0201_5% SOC_GPP_H1 BOOT STRAP3 - BIT3 @
This is bit 1 of a total of 4-bit encoded pin straps for

2
SOC_GPP_H0 boot configuration.
RC296 1 @ 2 4.7K_0201_5% Refer to Boot Strap 0 (on GPP_C5) for the encoding.
INTERNAL PD 20K

SOC_GPP_H1
BOOT STRAP1 - BIT2
This is bit 1 of a total of 4-bit encoded pin straps for
boot configuration. ESD request
Refer to Boot Strap 0 (on GPP_C5) for the encoding.
INTERNAL PD 20K
H_PECI CC3 2 1 0.1U_0201_10V6K
SOC_GPP_H0
3 BOOT STRAP1 - BIT1 XEMC@ 3
This is bit 1 of a total of 4-bit encoded pin straps for
boot configuration.
Refer to Boot Strap 0 (on GPP_C5) for the encoding.
INTERNAL PD 20K
+1.05VS_VCCSTG_OUT_LGC_TERM

SOC_XDP_TMS 51_0201_5% 2 CMC@ 1RC247

SOC_XDP_TDI 51_0201_5% 2 CMC@ 1RC248

SOC_XDP_TDO 100_0201_5% 2 CMC@ 1RC253

+1.05VO_OUT_FET

XDP_ITP_PMODE
RC260 1 CMC@ 2 1K_0201_5% XDP_ITP_PMODE DFX TEST MODE SOC_XDP_TCK0 51_0201_5% 2 CMC@ 1RC267
INTERNAL PU 20K
This strap should sample high. There should NOT be PCH_JTAG_TCK1
any on-board device driving it to opposite direction 51_0201_5% 2 @ 1RC270
during strap sampling.
XDP_ITP_PMODE
DFX TEST MODE
INTERNAL PU 20K
This strap should sample high. There should NOT be
any on-board device driving it to opposite direction
4 during strap sampling. 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(1/14)DDI,MSIC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 7 of 102
A B C D E
 5 4 3 2 1

Follow Intel DDR4 NIL

DDR4: Refer to 609003_TGL_U_DDR4_SODIMM_RVP_SCH_REV0p5

D D

UC1B UC1C

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)

<23> DDR_A_D[0..7] DDR_A_D7 (IL) DDR4/LP4/LP5/LP5 CMD Flip DDR_A_CLK1 <24> DDR_B_D[0..7] DDR_B_D7 DDR4/LP4/LP5/LP5 CMD Flip DDR_B_CLK1
CP53 BT42 AL53 R41 1
DDR_A_D6 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P DDR_A_CLK#1 DDR_A_CLK1 <23> DDR_B_D6 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P DDR_B_CLK#1 TP@ T511
CP52 BT41 AL52 R42 1
DDR_A_D5 DDR0_CLK_N1 / DDR3_CLK_N / DDR3_CLK_N / DDR3_CLK_N
DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 DDR_A_CLK#1 <23> DDR_B_D5 DDR1_CLK_N1 / DDR7_CLK_N / DDR7_CLK_N / DDR7_CLK_N
DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6 TP@ T512
CP50 BP52 AL50 M52
DDR_A_D4 CP49 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P BP53 DDR_B_D4 AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P M53
DDR_A_D3 CU53 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 NC / DDR2_CLK_N / DDR2_CLK_N / DDR2_CLK_N CD42 DDR_B_D3 AP53 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC / DDR6_CLK_N / DDR6_CLK_N / DDR6_CLK_N AC42
DDR_A_D2 CU52 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P CD41 DDR_B_D2 AP52 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P AC41
DDR_A_D1 CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC / DDR1_CLK_N / DDR1_CLK_N / DDR1_CLK_N CC52 DDR_A_CLK0 DDR_B_D1 AP50 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC / DDR5_CLK_N / DDR5_CLK_N / DDR5_CLK_N Y52 DDR_B_CLK0
DDR_A_D0 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P DDR_A_CLK#0 DDR_A_CLK0 <23> DDR_B_D0 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P DDR_B_CLK#0 DDR_B_CLK0 <24>
CU49 CC53 AP49 Y53
<23> DDR_A_D[8..15] DDR_A_D15 DDR0_CLK_N0 / DDR0_CLK_N / DDR0_CLK_N / DDR0_CLK_N
DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDR_A_CLK#0 <23> <24> DDR_B_D[8..15] DDR_B_D15 DDR1_CLK_N0 / DDR4_CLK_N / DDR4_CLK_N / DDR4_CLK_N
DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR_B_CLK#0 <24>
CH53 AF53
DDR_A_D14 CH52 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 DDR4/LP4/LP5/LP5 CMD BT45 DDR_B_D14 AF52 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7 DDR4/LP4/LP5/LP5 CMD Flip R47
DDR_A_D13 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 Flip NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P DDR_B_D13 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
CH50 BT47 AF50 R45
DDR_A_D12 CH49 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC / DDR3_CKE1 / DDR3_WCK_N / DDR3_WCK_N BN51 DDR_B_D12 AF49 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC / DDR7_CKE1 / DDR7_WCK_N / DDR7_WCK_N K51
DDR_A_D11 CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P BN53 DDR_B_D11 AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P K53
DDR_A_D10 CL52 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 NC / DDR2_CKE1 / DDR2_WCK_N / DDR2_WCK_N CD45 DDR_B_D10 AH52 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC / DDR6_CKE1 / DDR6_WCK_N / DDR6_WCK_N AC47
DDR_A_D9 CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P CD47 DDR_B_D9 AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P AC45
DDR_A_D8 CL49 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC / DDR1_CKE1 / DDR1_WCK_N / DDR1_WCK_N CA51 DDR_B_D8 AH49 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC / DDR5_CKE1 / DDR5_WCK_N / DDR5_WCK_N W51
<23> DDR_A_D[16..23] DDR_A_D23 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P <24> DDR_B_D[16..23] DDR_B_D23 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
CT47 CA53 AR41 W53
DDR_A_D22 CV47 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC / DDR0_CKE1 / DDR0_WCK_N / DDR0_WCK_N DDR_B_D22 AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC / DDR4_CKE1 / DDR4_WCK_N / DDR4_WCK_N
DDR_A_D21 CT45 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4/LP5/LP5 CMD Flip BU52 DDR_A_CKE1 DDR_B_D21 AR42 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 DDR4/LP4/LP5/LP5 CMD Flip P52 DDR_B_CKE1 1
DDR_A_D20 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1 DDR_A_CKE0 DDR_A_CKE1 <23> DDR_B_D20 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1 DDR_B_CKE0 TP@ T513
CV45 BL50 DDR_A_CKE0 <23> AV41 J50 DDR_B_CKE0 <24>
DDR_A_D19 CT42 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0 DDR_B_D19 AR45 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4 DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
DDR_A_D18 CV42 DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4/LP5/LP5 CMD Flip
CF42 DDR_A_CS#1 DDR_B_D18 AV45 DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3 DDR4/LP4/LP5/LP5 CMD Flip
AE42 DDR_B_CS#1 1
DDR_A_D17 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5 DDR_A_CS#0 DDR_A_CS#1 <23> DDR_B_D17 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1 / DDR5_CA1 / DDR5_CA1 / DDR5_CA5 DDR_B_CS#0 TP@ T514
CT41 CF47 AR47 AE47
DDR_A_D16 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4 DDR_A_CS#0 <23> DDR_B_D16 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0 / NC / DDR5_CS1 / DDR5_CA4 DDR_B_CS#0 <24>
CV41 AV47
<23> DDR_A_D[24..31] DDR_A_D31 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0 DDR4/LP4/LP5/LP5 CMD Flip <24> DDR_B_D[24..31] DDR_B_D31 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 DDR4/LP4/LP5/LP5 CMD Flip
CK47 CE53 AJ41 N42
DDR_A_D30 CM47 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6 CE50 DDR_B_D30 AJ42 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0 N45
DDR_A_D29 CK45 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 BL53 DDR_B_D29 AL41 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1 N44
DDR_A_D28
DDR_A_D27
CM45 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5
DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4
NC/DDR2_CS0/DDR2_CA2/DDR2_CA2
NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
BP47 Check symbol DDR_B_D28
DDR_B_D27
AL42 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5
DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4
NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
N47
Check symbol
CK42 BP42 AJ45 J53
DDR_A_D26 CM42 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4/DDR3_CA5/DDR3_CA1 BP45 DDR_B_D26 AJ47 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2 AC50
DDR_A_D25 CM41 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1 BP44 DDR_B_D25 AL45 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5 AC53
DDR_A_D24 CK41 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0 DDR_B_D24 AL47 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
<23> DDR_A_D[32..39] DDR_A_D39 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR_A_DQS7 <24> DDR_B_D[32..39] DDR_B_D39 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR_B_DQS7
BF53 BB44 A43 K36
DDR_A_D38 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3 DDR_A_DQS#7 DDR_A_DQS7 <23> DDR_B_D38 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7 DDR_B_DQS#7 DDR_B_DQS7 <24>
BF52 BD44 B43 K38
DDR_A_D37 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3 DDR_A_DQS6 DDR_A_DQS#7 <23> DDR_B_D37 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7 DDR_B_DQS6 DDR_B_DQS#7 <24>
BF50 BK44 DDR_A_DQS6 <23> D43 G44 DDR_B_DQS6 <24>
DDR_A_D36 BF49 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2 BH44 DDR_A_DQS#6 DDR_B_D36 E44 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6 J44 DDR_B_DQS#6
C DDR_A_D35 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4 DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2 DDR_A_DQS5 DDR_A_DQS#6 <23> DDR_B_D35 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 DDR_B_DQS5 DDR_B_DQS#6 <24> C
BH53 BA51 A46 D39
DDR_A_D34 DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3 DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3 DDR_A_DQS#5 DDR_A_DQS5 <23> DDR_B_D34 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7 DDR_B_DQS#5 DDR_B_DQS5 <24>
BH52 BA50 B46 C39
DDR_A_D33 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3 DDR_A_DQS4 DDR_A_DQS#5 <23> DDR_B_D33 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7 DDR_B_DQS4 DDR_B_DQS#5 <24>
BH50 BG51 D46 C45
DDR_A_D32 DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1 DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2 DDR_A_DQS#4 DDR_A_DQS4 <23> DDR_B_D32 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6 DDR_B_DQS#4 DDR_B_DQS4 <24>
BH49 BG50 DDR_A_DQS#4 <23> E47 D45 DDR_B_DQS#4 <24>
<23> DDR_A_D[40..47] DDR_A_D47 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 DDR_A_DQS3 <24> DDR_B_D[40..47] DDR_B_D47 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 DDR_B_DQS3
AY53 CK44 E38 AJ44
DDR_A_D46 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7 DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1 DDR_A_DQS#3 DDR_A_DQS3 <23> DDR_B_D46 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 DDR_B_DQS#3 DDR_B_DQS3 <24>
AY52 CM44 D38 AL44
DDR_A_D45 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6 DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1 DDR_A_DQS2 DDR_A_DQS#3 <23> DDR_B_D45 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5 DDR_B_DQS2 DDR_B_DQS#3 <24>
AY50 CT44 B38 AV44
DDR_A_D44 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5 DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0 DDR_A_DQS#2 DDR_A_DQS2 <23> DDR_B_D44 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 DDR_B_DQS#2 DDR_B_DQS2 <24>
AY49 CV44 A38 AR44
DDR_A_D43 DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4 DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0 DDR_A_DQS1 DDR_A_DQS#2 <23> DDR_B_D43 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4 DDR_B_DQS1 DDR_B_DQS#2 <24>
BC53 CK51 DDR_A_DQS1 <23> E41 AG51 DDR_B_DQS1 <24>
DDR_A_D42 BC52 DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1 CK50 DDR_A_DQS#1 DDR_B_D42 D40 DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3 DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5 AG50 DDR_B_DQS#1
DDR_A_D41 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS0 DDR_A_DQS#1 <23> DDR_B_D41 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 DDR_B_DQS0 DDR_B_DQS#1 <24>
BC50 CR51 B40 AN51
DDR_A_D40 DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS#0 DDR_A_DQS0 <23> DDR_B_D40 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4 DDR_B_DQS#0 DDR_B_DQS0 <24>
BC49 CR50 A40 AN50
<23> DDR_A_D[48..55] DDR_A_D55 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#0 <23> <24> DDR_B_D[48..55] DDR_B_D55 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4 DDR_B_DQS#0 <24>
BK47 G42
DDR_A_D54 BK45 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7 DDR4/LP4/LP5/LP5 CMD Flip CF44 DDR_A_ODT1 DDR_B_D54 G41 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7 DDR4/LP4/LP5/LP5 CMD Flip AE44 DDR_B_ODT1 1 T517
DDR_A_D53 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6 DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6 DDR_A_ODT0 DDR_A_ODT1 <23> DDR_B_D53 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6 DDR_B_ODT0 TP@
BH47 CF45 J41 AE45
DDR_A_D52 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5 DDR0_ODT0 / DDR1_CS0 / DDR1_CA2 / DDR1_CA2 DDR_A_ODT0 <23> DDR_B_D52 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2 DDR_B_ODT0 <24>
BH45 J42
DDR_A_D51 BH42 DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4 DDR4/LP4/LP5/LP5 CMD Flip
CB47 DDR_A_MA16 DDR_B_D51 G45 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4 DDR4/LP4/LP5/LP5 CMD Flip AA47 DDR_B_MA16
DDR_A_D50 DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3 DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1 DDR_A_MA15 DDR_A_MA16 <23> DDR_B_D50 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1 DDR_B_MA15 DDR_B_MA16 <24>
BK42 CB44 J45 AA44

https://vinafix.com
DDR_A_D49 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2 DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1 DDR_A_MA14 DDR_A_MA15 <23> DDR_B_D49 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 DDR_B_MA14 DDR_B_MA15 <24>
BK41 CB45 DDR_A_MA14 <23> G47 AA45 DDR_B_MA14 <24>
DDR_A_D48 BH41 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1 DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0 CF41 DDR_A_MA13 DDR_B_D48 J47 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 AE41 DDR_B_MA13
<23> DDR_A_D[56..63] DDR_A_D63 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0 DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3 DDR_A_MA12 DDR_A_MA13 <23> <24> DDR_B_D[56..63] DDR_B_D63 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 DDR_B_MA12 DDR_B_MA13 <24>
BD47 BU53 G38 P53
DDR_A_D62 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7 DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5 DDR_A_MA11 DDR_A_MA12 <23> DDR_B_D62 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5 DDR_B_MA11 DDR_B_MA12 <24>
BB47 BT51 G36 N51
DDR_A_D61 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6 DDR0_MA11/NC/DDR2_CS1/DDR2_CA4 DDR_A_MA10 DDR_A_MA11 <23> DDR_B_D61 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4 DDR_B_MA10 DDR_B_MA11 <24>
BD45 BV42 H36 U42
DDR_A_D60 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5 DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5 DDR_A_MA9 DDR_A_MA10 <23> DDR_B_D60 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5 DDR_B_MA9 DDR_B_MA10 <24>
BB45 BU50 DDR_A_MA9 <23> H38 P50 DDR_B_MA9 <24>
DDR_A_D59 BB42 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4 DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6 BY53 DDR_A_MA8 DDR_B_D59 N36 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6 U53 DDR_B_MA8
DDR_A_D58 DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3 DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0 DDR_A_MA7 DDR_A_MA8 <23> DDR_B_D58 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0 DDR_B_MA7 DDR_B_MA8 <24>
BB41 CA50 L36 W50
DDR_A_D57 DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2 DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1 DDR_A_MA6 DDR_A_MA7 <23> DDR_B_D57 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 DDR_B_MA6 DDR_B_MA7 <24>
BD42 BY52 L38 U52
DDR_A_D56 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1 DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1 DDR_A_MA5 DDR_A_MA6 <23> DDR_B_D56 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 DDR_B_MA5 DDR_B_MA6 <24>
BD41 BY50 N38 U50
DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0 DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0 DDR_A_MA4 DDR_A_MA5 <23> DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0 DDR_B_MA4 DDR_B_MA5 <24>
CD51 DDR_A_MA4 <23> AA51 DDR_B_MA4 <24>
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2 CD53 DDR_A_MA3 DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 AA53 DDR_B_MA3
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3 DDR_A_MA2 DDR_A_MA3 <23> DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 DDR_B_MA2 DDR_B_MA3 <24>
BV47 U47
DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2 DDR_A_MA1 DDR_A_MA2 <23> DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2 DDR_B_MA1 DDR_B_MA2 <24>
CE52 AC52
DDR0_MA1/NC/DDR0_CS1/DDR0_CA4 DDR_A_MA0 DDR_A_MA1 <23> DDR1_MA1/NC/DDR4_CS1/DDR4_CA4 DDR_B_MA0 DDR_B_MA1 <24>
BV41 U41
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4 DDR_A_MA0 <23> DDR1_MA0/NC/DDR7_CS1/DDR7_CA4 DDR_B_MA0 <24>
DDR4/LP4/LP5/LP5 CMD Flip DDR_A_BG1 DDR4/LP4/LP5/LP5 CMD Flip DDR_B_BG1
BN50 K50
DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0 DDR_A_BG0 DDR_A_BG1 <23> DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 DDR_B_BG0 DDR_B_BG1 <24>
BL52 J52
DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1 DDR_A_BG0 <23> DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1 DDR_B_BG0 <24>
DDR4/LP4/LP5/LP5 CMD Flip DDR_A_BA1 DDR4/LP4/LP5/LP5 CMD Flip DDR_B_BA1
CB42 AA42
DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0 DDR_A_BA0 DDR_A_BA1 <23> DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0 DDR_B_BA0 DDR_B_BA1 <24>
BV44 DDR_A_BA0 <23>
U44 DDR_B_BA0 <24>
DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6 DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
DDR4/LP4/LP5/LP5 CMD Flip BT53 DDR_A_ACT# N53 DDR_B_ACT#
DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3 DDR_A_ACT# <23> DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3 DDR_B_ACT# <24>
B B
DDR4/LP4/LP5/LP5 CMD Flip BV45 DDR_A_PAR U45 DDR_B_PAR
DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3 DDR_A_PAR <23> DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3 DDR_B_PAR <24>
AU50 DDR_A_ALERT# AU53 DDR_B_ALERT#
DDR0_ALERT# +0.6V_A_VREFCA DDR_A_ALERT# <23> DDR1_ALERT# +0.6V_B_VREFCA DDR_B_ALERT# <24>
AU49 AU52
DDR0_VREF_CA +0.6V_A_VREFCA DDR1_VREF_CA +0.6V_B_VREFCA
E52 DDR_PG_CTRL Trace width/Spacing >= 20mils Trace width/Spacing >= 20mils
DDR_VTT_CTL DV47 DDR_DRAMRST# TGL-U_BGA1449
DRAM_RESET# C49 SM_RCOMP0 RC43 1 2 100_0201_1%
DDR_RCOMP @

TGL-U_BGA1449
@

+1.2V_VDDQ
1

UC1D
CRB 1205 RC3998
Buffer with Open Drain Output 470_0402_5%

For VTT power control DV24

2

+1.2V_VDDQ +3VS DW47 RSVD_2

DDR_DRAMRST# DW49 RSVD_3
DDR_DRAMRST# <23,24> RSVD_4
0.1U_0201_10V6K 2 1 CC7 A48
RSVD_5
1

1
UC2 RC47 CC380
1 5 100K_0201_5% 0.1U_0201_10V6K TGL-U_BGA1449
NC VCC XEMC@ @
DDR_PG_CTRL 2 XEMC@ 2
2

A 4 DDR_PG_CTRL 1 2
Y SM_PG_CTRL <86>
3 CC8 100P_0201_50V8J
A GND A
74AUP1G07GW_TSSOP5 ESD PLACE NEAR TO SoC
ESD request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(3/14)DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 8 of 102
5 4 3 2 1
 5 4 3 2 1

SOC_SPI_0_D0 check power level & TLS en or not? 1213

BOOT HALT +1.8VALW_PRIM
NO INTERNAL PU/PD
HIGH: ENABLED SOC_GPP_C2
LOW: DISABLED TLS CONFIDENTIALITY SOC_GPP_C2
UC1E 4.7K_0201_5% 1 2 RC51
INTERNAL PD 20K
SOC_SPI_0_D2 HIGH: TLS CONFIDENTIALITY ENABLE
External pull-up is required. Recommend 100K if pulled LOW: TLS CONFIDENTIALITY DISABLE(Default)
up to 3.3V or 75K if pulled up to 1.8V.
(Link to DDR and TPM)
SOC_SPI_0_CLK DJ37 DK21 SOC_SMBCLK
NO INTERNAL PU/PD <66> SOC_SPI_0_CLK SOC_SPI_0_D3 SPI0_CLK GPP_C0/SMBCLK SOC_SMBDATA SOC_SMBCLK <23,66>
DG35 DM19 SOC_SMBDATA <23,66> RVP is different from EDS description +3VALW_PRIM
SOC_SPI_0_D2 DJ39 SPI0_IO3 GPP_C1/SMBDATA DN19 SOC_GPP_C2
SOC_SPI_0_D3 SOC_SPI_0_D1 DJ33 SPI0_IO2 GPP_C2/SMBALERT# SOC_SML0ALERT#
External pull-up is required. Recommend 100K if pulled <66> SOC_SPI_0_D1 SOC_SPI_0_D0 SPI0_MISO SOC_SML0CLK ESPI OR EC LESS SOC_SML0ALERT#
DJ35 DK19 4.7K_0201_5% 1 @ 2 RC61
up to 3.3V or 75K if pulled up to 1.8V. <66> SOC_SPI_0_D0 SOC_SPI_0_CS#1 SPI0_MOSI GPP_C3/SML0CLK SOC_SML0DATA INTERNAL PD 20K
1 DF35 DM17 (Link to TBT, remove)
+3V_SPI NO INTERNAL PU/PD T12 TP@ SOC_SPI_0_CS#0 SPI0_CS1# GPP_C4/SML0DATA SOC_SML0ALERT# HIGH: ESPI DISABLE
DG37 DN17
SOC_SPI_0_CS#2 SPI0_CS0# GPP_C5/SML0ALERT# LOW: ESPI ENABLE
DF39 This strap is used in conjunction with Boot
D <66> SOC_SPI_0_CS#2 SPI0_CS2# SOC_SML1CLK D
DK17 Strap 1,2,3, (on GPP_H0, GPP_H1, GPP_H2 respectively).
PROJECT_ID1 GPP_C6/SML1CLK SOC_SML1DATA SOC_SML1CLK <58>
DJ6 DJ17 (Link to EC/VGA)
SOC_SPI_0_D0 GPP_E11/SPI1_CLK/THC0_SPI1_CLK GPP_C7/SML1DATA SOC_GPP_B23 SOC_SML1DATA <58>
RC58 1 2 4.7K_0201_5% DN5 CY50 +3VALW_PRIM
DR9 GPP_E2/SPI1_IO3/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1# EMI Suggestion
RC59 1 2 100K_0201_5% SOC_SPI_0_D2 ODD_STRAP DM6 GPP_E1/SPI1_IO2/THC0_SPI1_IO2 DN53 ESPI_CLK RC66 1 EMC@ 2 49.9_0201_1% ESPI_CLK_R SOC_SML0CLK 499_0201_1% 1 2 RC52
GPP_E12/SPI1_MISO_IO1/THC0_SPI1_IO1 GPP_A5/ESPI_CLK ESPI_IO3 ESPI_IO3_R ESPI_CLK_R <58> SOC_SML0DATA
DK6 DJ53 RC68 1 2 15_0201_1% 499_0201_1% 1 2 RC53
SOC_SPI_0_D3 PROJECT_ID0 GPP_E13/SPI1_MOSI_IO0/THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK# ESPI_IO2 ESPI_IO2_R ESPI_IO3_R <58> SOC_SML1CLK
RC60 1 2 100K_0201_5% DK8 DH50 RC69 1 2 15_0201_1% To EC (Link to Re- timer) 1K_0201_5% 1 2 RC54
SOC_TS_PWR_EN GPP_E10/SPI1_CS#/THC0_SPI1_CS#GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1 ESPI_IO1_R ESPI_IO2_R <58> SOC_SML1DATA
DV11 DP50 RC71 1 2 15_0201_1% 1K_0201_5% 1 2 RC55
<78> SOC_TS_PWR_EN GPP_E8/SPI1_CS1#/SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO0 ESPI_IO0_R ESPI_IO1_R <58>
DW9 DP52 RC72 1 2 15_0201_1%
SOC_GPP_E6 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0_R <58>
DT8 DK52
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_RST# ESPI_CS# <58>
DL50
RAM_ID0 GPP_A6/ESPI_RESET# ESPI_RST# <58>
DN15
CODEC_ID DK13 GPP_F11/THC1_SPI2_CLK +3VS
RAM_ID3 DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3
RAM_ID2 DN13 GPP_F14/GSXDIN/THC1_SPI2_IO2
CC152 2 1 10P_0201_50V8J SOC_SPI_0_CLK RAM_ID1 DJ15 GPP_F13/GSXSLOAD/THC1_SPI2_IO1 SOC_SMBDATA RC4001 1 2 2.2K_0402_5%
TS_MODE DK15 GPP_F12/GSXDOUT/THC1_SPI2_IO0
XEMC@ DN10 GPP_F16/GSXCLK/THC1_SPI2_CS# SOC_SMBCLK RC4002 1 2 2.2K_0402_5%
DV14 GPP_F18/THC1_SPI2_INT#
GPP_F17/THC1_SPI2_RST# 10P_0201_50V8J1 2 CC154
EMC Suggestion DH3
DH4 CL_CLK @RF@
DF2 CL_DATA
CL_RST#
RF Suggestion
TGL-U_BGA1449
@

75K_0201_5% 1 @ 2 RC78 ESPI_CS#

100K_0201_5% 1 GLITCH@2 RC79 SOC_SPI_0_CLK
Codec Strap TS MODE Strap ODD Strap project ID Strap +3VALW_PRIM 75K_0201_5% 1 GLITCH@2 RC81 ESPI_RST#

+3VALW_PRIM +3VALW_PRIM

1
Follow 607872_TGL_UY_PDG for Glitch
1

RC211 RC210
RC4004 RC4025 10K_0402_5% 10K_0402_5%
C C
10K_0402_5% 10K_0402_5% @ @

2
255@ USBTS@ PROJECT_ID0
PROJECT_ID1
2

CODEC_ID TS_MODE ODD_STRAP

1
RC4029 RC212 Project_ID1 Project_ID0
1

10K_0402_5% 10K_0402_5% GPP_E11 GPP_E10 PartNumber - Description

RC4005 RC4026 RC209 @ @
10K_0402_5% 10K_0402_5% 10K_0402_5% TBD 0 0 TBD

2
255M@ I2CTS@ ODD@
TBD 0 1 TBD
2

+3VALW_PRIM
TBD 1 0 TBD
TBD 1 1 TBD

1
https://vinafix.com
SOC_GPP_B23
CPUNSSC CLOCK FREQ RC75
INTERNAL PD 20K @
HIGH: 19.2 MHz (form internal divider) 4.7K_0201_5%
LOW: 38.4 MHz (direct form crystal) (Default)

2
SOC_GPP_B23

Memory Down Strap

X76826BOL51 X76878BOL32

RC3997 10K_0402_5% RC3993 10K_0402_5%

X76HYN4@ SD028100280 X76MIC8@ SD028100280
RC3993 10K_0402_5% RC3994 10K_0402_5%
X76HYN4@ SD028100280 X76MIC8@ SD028100280
RC3995 10K_0402_5% RC3996 10K_0402_5% EMC Suggestion
X76HYN4@ SD028100280 X76MIC8@ SD028100280
RC3996 10K_0402_5% RC3997 10K_0402_5% CC145
B X76HYN4@ SD028100280 X76MIC8@ SD028100280 ESPI_CLK_R 1 2 B

Single SPI ROM_CS0# 10P_0201_50V8J

X76826BOL52 X76826BOL55 Follow 607872_TGL_UY_PDG XEMC@
33Ohm_5% for 1.8V, 62Ohm_5% for 3.3V 16M SPI ROM(Support ISH)
RC3992 10K_0402_5% +3V_SPI
X76MIC4@ SD028100280 RC3992 10K_0402_5% SOC_SPI_0_D1 RC82 1 2 62_0201_1% SOC_SPI_0_D1_R
RC3993 10K_0402_5% HYN832@ SD028100280 +3VALW_PRIM SOC_SPI_0_D0 RC83 1 2 62_0201_1% SOC_SPI_0_D0_R UC3 CC101 2 0.1U_0201_10V6K
X76MIC4@ SD028100280 RC3993 10K_0402_5% SOC_SPI_0_CLK RC84 1 EMC@ 2 62_0201_1% SOC_SPI_0_CLK_R SOC_SPI_0_CS#0 1 8
RC3995 10K_0402_5% HYN832@ SD028100280 SOC_SPI_0_D3 RC85 1 2 62_0201_1% SOC_SPI_0_D3_R SOC_SPI_0_D1_R 2 CS# VCC 7 SOC_SPI_0_D3_R
X76MIC4@ SD028100280 RC3994 10K_0402_5% To SPI ROM SOC_SPI_0_D2_R 3 DO HOLD# 6 SOC_SPI_0_CLK_R 1 2
1

WP# CLK
1

RC3996 10K_0402_5% HYN832@ SD028100280 4 5 SOC_SPI_0_D0_R CC11

X76MIC4@ SD028100280 RC3996 10K_0402_5% VSS DI 10P_0201_50V8J +1.8VALW_PRIM
HYN832@ SD028100280 RC3992 RC3990 RC3994 RC3991 XM25QH128AHIGT_SO8 XEMC@
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
X76826BOL53 NODX76@ NODX76@ NODX76@ NODX76@ SOC_SPI_0_D2 RC86 1 2 62_0201_1% SOC_SPI_0_D2_R DVT modify SA0000B8400
2
2

RAM_ID0

1
RAM_ID1
RC3997 10K_0402_5% RAM_ID2 RC4009
X76SAM4@ SD028100280 RAM_ID3 100K_0201_5%
RC3990 10K_0402_5%
1

1
1
1

X76SAM4@ SD028100280

2
RC3995 10K_0402_5% RC3997 RC3993 RC3995 RC3996 MAF - Master Attached Flash
X76SAM4@ SD028100280 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% From EC Single SPI Flash attached to SPI Bus
RC3996 10K_0402_5% @ @ @ @ (For share ROM) EC FW access through eSPI Bus
X76SAM4@ SD028100280
2

2
2
2

SOC_GPP_E6
X76826BOL54

1
SOC_GPP_E6
RC4006 JTAG ODT DISABLE
RC3992 10K_0402_5% NO INTERNAL PU/PD
100K_0201_5% HIGH: JTAG ODT ENABLED
X76HYN8@ SD028100280 @ LOW: JTAG ODT DISABLED
RC3990 10K_0402_5%

2
X76HYN8@ SD028100280
RC3995 10K_0402_5%
X76HYN8@ SD028100280 +3VALW_PRIM +3V_SPI
RC3996 10K_0402_5%
X76HYN8@ SD028100280 3mA
RC87 1 @ 2 0_0402_5%

A RAM_ID3 RAM_ID2 *RAM_ID1 *RAM_ID0 PartNumber - Description A

Hynix 4GB 0 0 0 0 SA0000BMN30 ( S IC D4 512M16 H5AN8G6NCJR-VKC FBGA ABO! )

Micron 4GB 0 0 0 1 SA0000CMS40 (S IC D4 512M16 MT40A512M16TB-062E:J ABO!)
Samsung 4GB 0 0 1 0 SA0000B6F30 (S IC D4 512M16 K4A8G165WC-BCTD FBGA ABO!)
Hynix 8GB 2666 0 0 1 1 SA0000BZJ40 (S IC D4 16G/2666 H5ANAG6NCMR-VKC ABO!)
Micron 8GB 0 1 0 0 SA0000D3U40 (S IC D4 16G/3200 MT40A1G16KD-062E:E ABO!)
Hynix 8GB 3200 SA0000CZ160 ( S IC D4 16G/3200 H5ANAG6NCMR-XNC ABO ! )
0 1 0 1 Security Classification Compal Secret Data Compal Electronics, Inc.
No OnBoard
1 1 1 1 No On Board Memory Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title
Memory
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(4/14)SPI,ESPI,SMB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 9 of 102
5 4 3 2 1
 5 4 3 2 1

UC1G

D DW15 GPP_R support per DR38 HDA_BIT_CLK D

DW24 GPP_F8/I2S_MCLK2_INOUT Gruoup voltage config GPP_R0/HDA_BCLK/I2S0_SCLK DU37 HDA_SYNC
GPP_D19/I2S_MCLK1 to 1.8V or 3.3V GPP_R1/HDA_SYNC/I2S0_SFRM DT37 HDA_SDOUT
(for TBT, remove) DG41 GPP_R2/HDA_SDO/I2S0_TXD DV37 HDA_SDIN0
DT38 GPP_A23/I2S1_SCLK GPP_R3/HDA_SDI0/I2S0_RXD
DV38 GPP_R7/I2S1_SFRM DV41 HDA_RST#
HDA_SDIN1 DW38 GPP_R6/I2S1_TXD GPP_R4/HDA_RST# DL53 PCH_DMIC_CLK
GPP_R5/HDA_SDI1/I2S1_RXD GPP_A7/I2S2_SCLK/DMIC_CLK_A0 PCH_DMIC_DATA PCH_DMIC_CLK <56>
DG51
DN31 GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 DG50 PCH_DMIC_DATA <56>
DM31 GPP_S6/SNDW3_CLK/DMIC_CLK_A0 GPP_A10/I2S2_RXD/DMIC_DATA1
GPP_S7/SNDW3_DATA/DMIC_DATA0 DL49 CLKREQ_CNV#
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1 CLKREQ_CNV# <52>
DK33 DL52
DK31 GPP_S4/SNDW2_CLK/DMIC_CLK_A1 GPP_A11/PMC_I2C_SDA/I2S3_SCLK
GPP_S5/SNDW2_DATA/DMIC_DATA1 DH49 SOC_BT_ON RC4028 1 2 0_0201_5% BT_ON
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0 BT_ON <52,58>
DW35
DV35 GPP_S2/SNDW1_CLK/DMIC_CLK_B0 DF33 SNDW _RCOMP RC90 1 2
GPP_S3/SNDW1_DATA/DMIC_CLK_B1 GPP_S Group SNDW_RCOMP 200_0201_1%
DT32 only use 1.8V
DR35 GPP_S0/SNDW0_CLK
GPP_S1/SNDW0_DATA

TGL-U_BGA1449
@

C C

HDA_SDOUT
HDA for AUDIO FLASH DESCRIPTOR SECURITY OVERRIDE
INTERNAL PD 20K
HDA_SDOUT_R RC95 1 2 33_0201_5% HDA_SDOUT
To Enable ME Override HIGH: OVERRIDEN
<56> HDA_SDOUT_R LOW: SECURITY MEASURES NOT OVERRIDEN (DEFAULT)
HDA_BIT_CLK_RRC96 1 EMC@ 2 33_0201_5% HDA_BIT_CLK
<56> HDA_BIT_CLK_R HDA_SYNC_R RC98 HDA_SYNC
1 2 33_0201_5%
<56> HDA_SYNC_R HDA_RST#_R RC4000 HDA_RST#
1 2 33_0201_5% DVT modify
<56> HDA_RST#_R HDA_SDIN0
<56> HDA_SDIN0 R1
@

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1 2 HDA_SDOUT
<58> ME_EN

0_0201_5%

1
RC97
100K_0201_5%

2
@
572631_ICL_PCH_LP_EDS_Vol_1_Rev_0p7
VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
Need to sync with codec VDDIO

100K_0201_5% 1 GLITCH@2 RC101 HDA_BIT_CLK

B 33K_0201_5% 1 GLITCH@2 RC102 HDA_RST# B
33K_0201_5% 1 @ 2 RC103 HDA_SDIN1

Follow
607872_TGL_UY_PDG for Glitch

CC146 2 1 10P_0201_50V8J HDA_BIT_CLK_R

XEMC@

EMC Suggestion

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(5/14)HDA,SNDW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 10 of 102
5 4 3 2 1
 5 4 3 2 1

+3VS

CLKREQ_PCIE#1 10K_0201_5% 1 2 RC105

UC1K CLKREQ_PCIE#2 10K_0201_5% 1 2 RC106
BW1 DU14 CLKREQ_PCIE#3 10K_0201_5% 1 2 RC107
BW2 CLKOUT_PCIE_P6
GPP_F19/SRCCLKREQ6# DF23
CLKOUT_PCIE_N6
GPP_H11/SRCCLKREQ5# DG25
CB2 GPP_H10/SRCCLKREQ4# DT24 CLKREQ_PCIE#3
CLKOUT_PCIE_P5GPP_D8/SRCCLKREQ3# CLKREQ_PCIE#3 <52>
CB1 DT30 CLKREQ_PCIE#2
CLKOUT_PCIE_N5GPP_D7/SRCCLKREQ2# CLKREQ_PCIE#2 <51>
DV30 CLKREQ_PCIE#1
GPP_D6/SRCCLKREQ1# CLKREQ_PCIE#1 <68>
DW30
BW4 GPP_D5/SRCCLKREQ0# DIS dGPU funtion, remove +3VALW
Follow CLKOUT_PCIE_P4 SOC_XTAL38.4_OUT
BW5 DM1
607872_TGL_UY_PDG_Rev0p5 for Glitch CLKOUT_PCIE_N4 XTAL_OUT DL1 SOC_XTAL38.4_IN PM_BATLOW# 8.2K_0201_5% 2 1 RC112
CLK_PCIE_P3 CL7 XTAL_IN W AKE# 8.2K_0201_5% 2 1 RC114
<52> CLK_PCIE_P3 CLK_PCIE_N3 CLKOUT_PCIE_P3 LAN_WAKE#
WLAN CL8 3.3V DW41 SUSCLK 10K_0201_5% 2 1 RC115
+3VALW <52> CLK_PCIE_N3 CLKOUT_PCIE_N3 GPD8/SUSCLK SPIVCCIOSEL 4.7K_0201_5% 2 @ 1 RC116
CLK_PCIE_P2 CB4 DT47 SOC_RTCX2 SPIVCCIOSEL
D PM_SLP_S0# <51> CLK_PCIE_P2 CLK_PCIE_N2 CLKOUT_PCIE_P2 RTCX2 SOC_RTCX1 3.3V / 1.8V SELECT FOR SPI D
RC121 1 GLITCH@2 100K_0201_5% LAN <51> CLK_PCIE_N2 CB5 DR47 4.7K_0201_5% 2 1 RC117
CLKOUT_PCIE_N2 RTCX1 HIGH: 1.8V
RC125 1 GLITCH@2 100K_0201_5% PM_SLP_S4# CLK_PCIE_P1 BY4 DN37 SOC_RTCRST# LOW: 3.3V
PM_SLP_S3# <68> CLK_PCIE_P1 CLK_PCIE_N1 CLKOUT_PCIE_P1 RTCRST# SOC_SRTCRST# Follow 609003_TGL_U_DDR4_SODIMM_RVP_SCH
RC127 1 GLITCH@2 100K_0201_5% SSD BY3 DK37
SLP_SUS# <68> CLK_PCIE_N1 CLKOUT_PCIE_N1 SRTCRST#
RC128 1 GLITCH@2 100K_0201_5% SUSCLK 1K_0201_5% 1 @ 2 RC119
CN7
PVT modify CN8 CLKOUT_PCIE_P0
dGPU DIS f0r dGPU function, remove CLKOUT_PCIE_N0
XCLK_BIASREF DJ5
Follow
2 1
RC120 60.4_0402_1% XCLK_BIASREF 609003_TGL_U_DDR4_SODIMM_RVP_SCH
TGL-U_BGA1449
+3VS
@

CPU_C10_GATE# RC122 1 @ 2 100K_0201_5% PVT modify

RC4030 1 GLITCH@2 100K_0201_5%
PVT modify
ESD request H_PROCPWRGD need close CPU
+3VALW UC1L
SLP_SUS# DV49 BM9 H_PROCPWRGD 1 TP@T35
<58> SLP_SUS# SLP_SUS# PROCPWRGD
RC136 1 2 10K_0201_5% SYS_RESET# DK41 PBTN_OUT#_R EC_VCCST_PG 1 2
T524TP@ 1 PM_SLP_S5# DM43 3.3V GPD3/PWRBTN# DN41 PM_BATLOW# EMC@ CC151 0.1U_0201_10V6K
2 1 PM_SLP_S4# DJ41 GPD10/SLP_S5# GPD0/BATLOW# DK43 AC_PRESENT_R
CC147
GPD5/SLP_S4# GPD1/ACPRESENT
check need PH? 1209
EMC@ 0.1U_0201_10V6K PM_SLP_S3# DJ43 3.3V
<16> PM_SLP_S3# PM_SLP_A# GPD4/SLP_S3#
T525TP@ 1 DR41 CW40
CC150 2 1 SOC_PLTRST# T527TP@ 1 PM_SLP_WLAN# DT44 GPD6/SLP_A# GPP_B11/PMCALERT# DN27 CPU_C10_GATE#
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <16>
EMC@ 0.1U_0201_10V6K DG31 SX_EXIT_HOLDOFF#
PM_SLP_S0# GPP_H3/SX_EXIT_HOLDOFF# SX_EXIT_HOLDOFF# <58>
DD42 check remove 1213 ESD Suggestion
<58,66> PM_SLP_S0# PM_SLP_LAN# GPP_B12/SLP_S0#
ESD Suggestion T526TP@ 1 DN39 DK39 W AKE#
SLP_LAN# WAKE#
EC_RSMRST# DM35 3.3V DM41 LAN_WAKE#
PCH_PWROK <58> EC_RSMRST# SYS_RESET# RSMRST# GPD2/LAN_WAKE#
2 1 DD10 3.3V DT41 GPD11 1
SOC_PLTRST# SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON TP@ T36
RC333 100K_0201_5% DD41
GPP_B13/PLTRST# DN43
EMC@ 3.3V
GPD7
TBT retimer_rst, remove
2 1 PCH_DPWROK DK35
<58> PCH_DPWROK SYS_PWROK DSW_PWROK VCCSTPWRGOOD_TGSS RC134
C3892 100P_0201_50V8J DF10 CE5 1 @ 2 0_0201_5%
<58> SYS_PWROK PCH_PWROK SYS_PWROK VCCSTPWRGOOD_TCSS EC_VCCST_PG
DN35 BP8
C3891 <58> PCH_PWROK PCH_PWROK VCCST_PWRGD VCCST_OVERRIDE
BP9 RC135 1 @ 2 0_0201_5% VCCST_OVERRIDE_R
2 1 SYS_PWROK SM_INTRUDER# DM37 VCCST_OVERRIDE
SPIVCCIOSEL DT49 INTRUDER# DR12
ESD Suggestion SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# DW12
100P_0201_50V8J GPP_F21/EXT_PWR_GATE2#
C C
EMC@
+RTCVCC TGL-U_BGA1449
@
RC138 1 2 20K_0201_5% SOC_SRTCRST#

CC21 1 2 1U_0201_6.3V6M

SOC_RTCX2 1 2 SOC_RTCX2_R 1 2
RC139 1 2 20K_0201_5% SOC_RTCRST# PVT modify RC113 0_0201_5% CC25
SOC_RTCRST# <58>
8.2P_0201_50V8B
CC22 1 2 1U_0201_6.3V6M
RC141 1 @ 2 0_0201_5% AC_PRESENT_R
<58> AC_PRESENT

2
JCMOS1 1 @ 2 0_0603_5% CLR CMOS
RC142 1 @ 2 0_0201_5% PBTN_OUT#_R RC140 YC1
<58> PBTN_OUT#

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10M_0201_1% 32.768KHZ_9PF_X1A000141000200
RC143 1 2 1M_0201_5% SM_INTRUDER# PDG 6.2.5

1
@ RC334 1 2 1M_0201_5% INTRUDER# should have a weak external pull-up to VccRTC tCPU22/ tPCH28b

1
RC144 1 2 100K_0201_5% EC_RSMRST# @ DC3 @
EC_RSMRST# RC4013 1 2 0_0201_5% PCH_DPWROK 2 SOC_RTCX1 1 2 SOC_RTCX1_R 1 2
1 PM_SLP_S3# RC324 0_0201_5% CC24
PCH_PWROK 3 8.2P_0201_50V8B

REMOVE TD CIRCUIT, CHECK POWER LEVEL LRB715FT1G_SOT323-3

SOC_XTAL38.4_IN
1217
tPLT17 SOC_XTAL38.4_OUT
RC149 1 2 200K _0201_1%
+1.05V_VCCST EMI Suggestion
DC5 @

1
From EC(open-drain) VR_ON 2
<58,88> VR_ON
1

1 PM_SLP_S3# RC148 RC146

RC145 EC_VCCST_PG_R 3 33_0201_5% 33_0201_5%
1K_0201_5% EMC@ EMC@
LRB715FT1G_SOT323-3

2
SOC_XTAL38.4_OUT_R

SOC_XTAL38.4_IN_R
2

RC147 1 2 60.4_0201_1% EC_VCCST_PG

<58> EC_VCCST_PG_R

B B

VCCST_EN 1
YC2
3
2 2 4 2 CC27
CC26
DC6 12P_0201_50V8J 38.4MHZ_10PF_8Y38420005 12P_0201_50V8J
2
<17,91> VCCIN_AUX_CORE_VID0_R 1 1
1
3 VCCIN_AUX_CORE_VID <16>
<17,91> VCCIN_AUX_CORE_VID1_R
LRB715FT1G_SOT323-3
@

PCH PLTRST Buffer

DVT modify
+3VALW_PRIM
RC150
100K_0201_5% 1 2 RC151 VCCST_OVERRIDE_LS SOC_PLTRST# 1 @ 2 PLT_RST_R#
VCCST_OVERRIDE_N PLT_RST_R# <51,52,66,68>
100K_0201_5% 1 2 RC152
100K_0201_5% 1 2 RC153 VCCST_OVERRIDE_R
VCCST_OVERRIDE_LS <16> 0_0201_5%

1
3

QC2A RC154
VCCST_OVERRIDE_N
D
5 G PJT138KA_SOT363-6 100K_0201_5%
S GLITCH@
4

2
VGS(Max) : 1.5 V
PJT138KA_SOT363-6
6

VGS(Max) : 1.5 V
VCCST_OVERRIDE_R
D
2 G

A S A
1

QC2B

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(6/14)CLK,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 22, 2020 Sheet 11 of 102
5 4 3 2 1
 5 4 3 2 1

+3VALW_PRIM

UC1F

RC156 1 2 1K_0201_5% I2C_3_SCL Track Pad

RC157 1 2 1K_0201_5% I2C_3_SDA
DIS for dGPU function, remove DC53 DR27
SOC_GPP_B18 DA51 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD DW27
GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD TBT Retimer PWR_EN, remove
DC49 DV25 SOC_GPP_D16 1
PCH_SPKR GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS# TP@ T38
DC50 DT25
<56> PCH_SPKR DC52 GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5 DVT modify
GPP_B15/GSPI0_CS0# DB45 SOC_NGFF_PWREN
D
CHECK SW GPIO 12/10 GPP_B6/ISH_I2C0_SCL SOC_NGFF_PWREN <68> D
G_INT# CY49 DB44
+3VS <66> G_INT# GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA
CY53
CY52 GPP_B22/GSPI1_MOSI CY39 SOC_GPP_B8 1
MXM VRAM strap, remove GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL TP@ T191
DA50 DB47 SOC_GPP_B7 1
GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA TP@ T192
RC161 1 2 1K_0201_5% I2C_5_SCL 1 SOC_GPP_C9 DV21 DD47 I2C_5_SCL
I2C_5_SDA T197 TP@ SOC_GPP_C8 GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL I2C_5_SDA I2C_5_SCL <38>
RC162 1 2 1K_0201_5% eDP Touch, MIPI CVF 1 DT21 DD44
T31 TP@ SOC_GPP_C11 GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA I2C_5_SDA <38>
T198 TP@ 1 DR21
1 SOC_GPP_C10 DW21 GPP_C11/UART0_CTS# DJ8 I2C_TS_INT#
T199 TP@ GPP_C10/UART0_RTS# GPP_E16/ISH_GP7 I2C_TS_INT# <38> TBT SLP_DS2#, change to I2C touch INT#
(For R-BOM) WWAN_RST# - > 1.8V DR7 SOC_DGPU_PRSNT#
GPP_E15/ISH_GP6 need sw confirm 1206
DV19 DR24
For EC Debug UART / MIPI60 DT19 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5 DU25
RC163 1 2 49.9K_0201_1% UART_2_CRXD_DTXD DR18 GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4 DV31
DIS f0r dGPU function, remove GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3
DU19 DU31 MXM GPIO, remove
RC164 1 2 49.9K_0201_1% UART_2_CTXD_DRXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2 DT27
UART_2_CTXD_DRXD DJ21 GPP_D1/ISH_GP1/BK1/SBK1 DV27
<52> UART_2_CTXD_DRXD UART_2_CRXD_DTXD DG23 GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0
<52> UART_2_CRXD_DTXD GPP_C20/UART2_RXD GPP_RCOMP
DJ19 DR51 RC166 1 2
DF21 GPP_C23/UART2_CTS# GPP_RCOMP 200_0201_1%
TBT AUX, remove GPP_C22/UART2_RTS# DN33 SOC_GPP_T3 1
GPP_T3 SOC_GPP_T2 TP@ T39
DV18 DT35 1
GPP_C17/I2C0_SCL GPP_T2 TP@ T40
ALS remove DW18
GPP_C16/I2C0_SDA DG17
DJ23 GPP_U5 DG19
DT18 GPP_C19/I2C1_SCL GPP_U4
EC HID Device 1209 ??
GPP_C18/I2C1_SDA
DJ29
DJ31 GPP_H5/I2C2_SCL
GPP_H4/I2C2_SDA
I2C_3_SCL DF29
<63> I2C_3_SCL I2C_3_SDA GPP_H7/I2C3_SCL
Track Pad DG29
<63> I2C_3_SDA GPP_H6/I2C3_SDA
DF25
DF27 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD

TGL-U_BGA1449
C @ C

Strap Pin +3VS

For BIOS Verify UMA/DIS SKU
+3VS
1 UMA@ 2 SOC_DGPU_PRSNT#

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RC4018 4.7K_0201_5%
4.7K_0201_5%

4.7K_0201_5%
1

1 @ 2
RC169 100K_0201_5%
RC170

RC171

@ @
SOC_GPP_B18 PD on DB
No Reboot
2

INTERNAL PD 20K
HIGH: No Reboot
SOC_GPP_B18 LOW: Reboot Enable (Default)
GPP_E15 DGPU_PRSNT#

SPKR
DIS,Optimus 0
PCH_SPKR TOP SWAP OVERRIDE
UMA 1
INTERNAL PD 20K
20K_0201_5%
20K_0201_5%

1
1

HIGH: Top swap enable

LOW: Disable (Default)
RC175
RC174

@ @
2
2

B B

www.teknisi-indonesia.com
to dGPU Connect to SOC GPIO

DIS f0r dGPU function, remove

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(7/14)GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 12 of 102
5 4 3 2 1
 5 4 3 2 1

PDG 6.8.6
For integrated Bluetooth* functionality with the IntelR Wireless-AC (CNVi) solution,
Tiger Lake PCH-LP USB 2.0 port # 10 must be used.
UC1I
SATA_CTX_DRX_P1 BT7 CV4 USB20_P10
<67> SATA_CTX_DRX_P1 SATA_CTX_DRX_N1 BT8 PCIE12_TXP/SATA1_TXP USB2P_10 CY3 USB20_N10 USB20_P10 <52>
<67> SATA_CTX_DRX_N1 SATA_CRX_DTX_P1 CE2 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_N10 <52> NGFF WLAN (BT)
ODD <67> SATA_CRX_DTX_P1 SATA_CRX_DTX_N1 PCIE12_RXP/SATA1_RXP USB20_P9
CE1 DD5
<67> SATA_CRX_DTX_N1 PCIE12_RXN/SATA1_RXN USB2P_9 DD4 USB20_N9 USB20_P9 <38>
SATA_CTX_DRX_P0 BT9 USB2N_9 USB20_N9 <38> Touch Panel
<67> SATA_CTX_DRX_P0 SATA_CTX_DRX_N0 BV9 PCIE11_TXP/SATA0_TXP CW9 USB20_P8
<67> SATA_CTX_DRX_N0 SATA_CRX_DTX_P0 CF4 PCIE11_TXN/SATA0_TXN USB2P_8 DA9 USB20_N8 USB20_P8 <38>
HDD <67> SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 CF3 PCIE11_RXP/SATA0_RXP USB2N_8 USB20_N8 <38> Camera
D <67> SATA_CRX_DTX_N0 PCIE11_RXN/SATA0_RXN D
DD1 USB20_P7
PCIE_CTX_DRX_P10 BV7 USB2P_7 DD2 USB20_N7 USB20_P7 <66>
<52> PCIE_CTX_DRX_P10 PCIE_CTX_DRX_N10 BV8 PCIE10_TXP USB2N_7 USB20_N7 <66> Finger Print
<52> PCIE_CTX_DRX_N10 PCIE_CRX_DTX_P10 CG2 PCIE10_TXN DA1
WLAN (Gen1) <52> PCIE_CRX_DTX_P10 PCIE_CRX_DTX_N10 PCIE10_RXP USB2P_6
CG1 DA2
<52> PCIE_CRX_DTX_N10 PCIE10_RXN USB2N_6
PCIE_CTX_DRX_P9 BY7 DA12 USB20_P5
<51> PCIE_CTX_DRX_P9 PCIE_CTX_DRX_N9 BY8 PCIE9_TXP USB2P_5 DA11 USB20_N5 USB20_P5 <72>
<51> PCIE_CTX_DRX_N9 PCIE_CRX_DTX_P9 CG5 PCIE9_TXN USB2N_5 USB20_N5 <72> USB3.1 Type-A Port (SUB)
LAN (Gen1) <51> PCIE_CRX_DTX_P9 PCIE_CRX_DTX_N9 PCIE9_RXP USB20_P4
CG4 DC8
<51> PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_4 DC7 USB20_N4 USB20_P4 <71>
PCIE_CTX_DRX_P8 CB8 USB2N_4 USB20_N4 <71> USB3.1 Type-A Port (MB)
<68> PCIE_CTX_DRX_P8 PCIE_CTX_DRX_N8 CB7 PCIE8_TXP DB4 USB20_P3
<68> PCIE_CTX_DRX_N8 PCIE_CRX_DTX_P8 CK5 PCIE8_TXN USB2P_3 DB3 USB20_N3 USB20_P3 <71>
<68> PCIE_CRX_DTX_P8 PCIE_CRX_DTX_N8 CK4 PCIE8_RXP USB2N_3 USB20_N3 <71> USB3.1 Type-A Port (MB)
<68> PCIE_CRX_DTX_N8 PCIE8_RXN DA5
PCIE_CTX_DRX_P7 CD9 USB2P_2 DA4
<68> PCIE_CTX_DRX_P7 PCIE_CTX_DRX_N7 CD8 PCIE7_TXP USB2N_2
<68> PCIE_CTX_DRX_N7 PCIE_CRX_DTX_P7 CK1 PCIE7_TXN DC11 USB20_P1
<68> PCIE_CRX_DTX_P7 PCIE_CRX_DTX_N7 PCIE7_RXP USB2P_1 USB20_N1 USB20_P1 <43>
CK2 DC9 USB3.1 Type-C Port (MB)
<68> PCIE_CRX_DTX_N7 PCIE7_RXN USB2N_1 USB20_N1 <43> +3VS
SSD (Gen3) PCIE_CTX_DRX_P6 SATA_GP0
CG8 DP4
<68> PCIE_CTX_DRX_P6 PCIE_CTX_DRX_N6 CG7 PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0 DF41 SATA_GP1 SATA_GP0 2 1
<68> PCIE_CTX_DRX_N6 PCIE_CRX_DTX_P6 CL4 PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM 10K_0201_5% RC182
<68> PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6 CL3 PCIE6_RXP DD8 SATA_GP1 2 1
<68> PCIE_CRX_DTX_N6 PCIE6_RXN GPP_E9/USB_OC0# DJ45 10K_0201_5% RC183
PCIE_CTX_DRX_P5 CJ8 GPP_A16/USB_OC3#/I2S4_SFRM
<68> PCIE_CTX_DRX_P5 PCIE_CTX_DRX_N5 CJ7 PCIE5_TXP DN6
<68> PCIE_CTX_DRX_N5 PCIE_CRX_DTX_P5 CN2 PCIE5_TXN GPP_E5/DEVSLP1 DG8 DEVSLP0
<68> PCIE_CRX_DTX_P5 PCIE_CRX_DTX_N5 PCIE5_RXP GPP_E4/DEVSLP0 DEVSLP0 <67>
CN1
<68> PCIE_CRX_DTX_N5 PCIE5_RXN DN29
USB3_CTX_DRX_P4 CR8 GPP_H15/M2_SKT2_CFG3 DK29
<71> USB3_CTX_DRX_P4 USB3_CTX_DRX_N4 CR7 PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2 DT31 SOC_GPP_H13 1 T200
<71> USB3_CTX_DRX_N4 USB3_CRX_DTX_P4 CN5 PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1 DR32 SOC_TS_RST# TP@
USB3.1 Type-A (MB JUSB2) <71> USB3_CRX_DTX_P4 USB3_CRX_DTX_N4 PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0 SOC_TS_RST# <38>
CN4
C <71> USB3_CRX_DTX_N4 PCIE4_RXN/USB31_4_RXN DV9 PCIE_RCOMPP RC184 1 2 100_0201_1% C
USB3_CTX_DRX_P3 CU8 PCIE_RCOMP_P DT9 PCIE_RCOMPN
<71> USB3_CTX_DRX_P3 USB3_CTX_DRX_N3 CU7 PCIE3_TXP/USB31_3_TXP PCIE_RCOMP_N
<71> USB3_CTX_DRX_N3 USB3_CRX_DTX_P3 CT2 PCIE3_TXN/USB31_3_TXN DC12 USB2_VBUSSENSE
USB3.1 Type-A (MB JUSB1) RC185 1 2 10K_0201_1%
<71> USB3_CRX_DTX_P3 USB3_CRX_DTX_N3 CT1 PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE DF1 USB2_ID RC186 1 2 10K_0201_1%
<71> USB3_CRX_DTX_N3 PCIE3_RXN/USB31_3_RXN USB_ID DE1 USB2_COMP RC187 1 2 113_0201_1%
CW8 USB2_COMP
CW7 PCIE2_TXP/USB31_2_TXP E3 RSVD_BSCAN 1 T43
CU3 PCIE2_TXN/USB31_2_TXN RSVD_BSCAN TP@
CT4 PCIE2_RXP/USB31_2_RXP
PCIE2_RXN/USB31_2_RXN
USB3_CTX_DRX_P1 DA8
USB3.1 Type-C (MB JTYPEC1) <42> USB3_CTX_DRX_P1 USB3_CTX_DRX_N1 PCIE1_TXP/USB31_1_TXP
DA7
<42> USB3_CTX_DRX_N1 USB3_CRX_DTX_P1 CV2 PCIE1_TXN/USB31_1_TXN
<42> USB3_CRX_DTX_P1 USB3_CRX_DTX_N1 CV1 PCIE1_RXP/USB31_1_RXP

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<42> USB3_CRX_DTX_N1 PCIE1_RXN/USB31_1_RXN
TGL-U_BGA1449
@

UC1H
B P5 V5 B
P7 PCIE4_TX_P_3 PCIE4_TX_P_1 V7
N1 PCIE4_TX_N_3 PCIE4_TX_N_1 T1
N2 PCIE4_RX_P_3 PCIE4_RX_P_1 T2
PCIE4_RX_N_3 PCIE4_RX_N_1 DIS dGPU function, remove
DIS dGPU function, remove T5 Y5
T7 PCIE4_TX_P_2 PCIE4_TX_P_0 Y7
dGPU PCIE4_TX_N_2 PCIE4_TX_N_0
R1 V1
R2 PCIE4_RX_P_2 PCIE4_RX_P_0 V2
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMPP RC188 1 2 2.2K_0201_1%
PCIE4_RCOMP_P V12 PCIE4_RCOMPN
PCIE4_RCOMP_N
TGL-U_BGA1449
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(8/14)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 13 of 102
5 4 3 2 1
 5 4 3 2 1

UC1J
D D
D22 DK47 CNV_CTX_DRX_P1
CSI_F_DP_1 CNVI_WT_D1P CNV_CTX_DRX_P1 <52>
B22 DM47 CNV_CTX_DRX_N1
CSI_F_DN_1 CNVI_WT_D1N CNV_CTX_DRX_N1 <52>
E22 DN49 CNV_CTX_DRX_P0
CSI_F_DP_0 CNVI_WT_D0P CNV_CTX_DRX_P0 <52>
D20 DR49 CNV_CTX_DRX_N0
CSI_F_DN_0 CNVI_WT_D0N CNV_CTX_DRX_N0 <52>
A20 DN45 CLK_CNV_CTX_DRX_P
CSI_F_CLK_P CNVI_WT_CLKP CLK_CNV_CTX_DRX_P <52>
B20 DN47 CLK_CNV_CTX_DRX_N
CSI_F_CLK_N CNVI_WT_CLKN CLK_CNV_CTX_DRX_N <52>
B18 DU43 CNV_CRX_DTX_P1
CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 <52>
A18 DV43
CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_CRX_DTX_P0 CNV_CRX_DTX_N1 <52>
D18 DR44
CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P CNV_CRX_DTX_N0 CNV_CRX_DTX_P0 <52>
E18 DT43
CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N CLK_CNV_CRX_DTX_P CNV_CRX_DTX_N0 <52>
C16 DV44 CLK_CNV_CRX_DTX_P <52>
D16 CSI_E_CLK_P CNVI_WR_CLKP DW44 CLK_CNV_CRX_DTX_N
CSI_E_CLK_N CNVI_WR_CLKN CLK_CNV_CRX_DTX_N <52> +1.8VALW _PRIM
D15 DN51 CNV_W T_RCOMP RC189 1 2 150_0201_1%
E15 CSI_C_DP_2 CNVI_WT_RCOMP
A15 CSI_C_DN_2 DJ13 CNV_RGI_CRX_DTX CNV_BRI_CRX_DTX 20K_0201_5% 1 @ 2 RC190
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNV_RGI_CTX_DRX CNV_RGI_CRX_DTX <52>
B15 DG13 CNV_RGI_CTX_DRX <52>
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD DF15 CNV_BRI_CRX_DTX CNV_RGI_CRX_DTX 20K_0201_5% 1 @ 2 RC191
GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_BRI_CTX_DRX CNV_BRI_CRX_DTX <52>
L18 DF17 CNV_BRI_CTX_DRX <52>
N18 CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS#
L20 CSI_C_DN_1 DJ10 SOC_GPP_F5 1
CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ TP@ T63
N20 DV15
G20 CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING DK10 CNV_RF_RESET#
CSI_C_CLK_P GPP_F4/CNV_RF_RESET# CNV_RF_RESET# <52> +1.8VALW _PRIM
H20
CSI_C_CLK_N
H16
G16 CSI_B_DP_1
C G18 CSI_B_DN_1 C
CSI_B_DP_0

1
H18
L16 CSI_B_DN_0 RC192
N16 CSI_B_CLK_P CNV_RGI_CTX_DRX 100K_0201_5%
CSI_B_CLK_N M.2 CNVI MODES
G14 LOW = Integrated CNVi enable.

2
H14 CSI_B_DP_2 HIGH = Integrated CNVi disable. CNV_RGI_CTX_DRX
CSI_B_DN_2 NO INTERNAL PU/PD
L14
N14 CSI_B_DP_3
CSI_B_DN_3
RC194 1 2 CSI_RCOMP K14
CSI_RCOMP

1
150_0201_1%

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DK25 RC195
DM25 GPP_H23/IMGCLKOUT4 4.7K_0201_5%
DN25 GPP_H22/IMGCLKOUT3 @
DJ25 GPP_H21/IMGCLKOUT2

2
DR30 GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT_0/BK4/SBK4

TGL-U_BGA1449
@

B B

www.teknisi-indonesia.com
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(9/14)CSI,CNV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 14 of 102
5 4 3 2 1
 5 4 3 2 1

Package size?
EMC CAPS-PLACE
< 5mm from SOC VCCIN
+VCCIN +VCCIN +VCCIN
DVT modify
UC1M

100P_0201_50V8J
A24 G32

CC94

100P_0201_50V8J
1 1 1 1

0.1U_0201_10V6K

2.2P_0201_50V8C
A26 VCCIN_1 VCCIN_66 H24

EMC@ CC95

EMC@ CC96

CC93
A29 VCCIN_2 VCCIN_67 H26
D D
A30 VCCIN_3 VCCIN_68 H30
A33 VCCIN_4 VCCIN_69 H32 2 2 2 2

EMC@
VCCIN_5 VCCIN_70

@
A35 J1
AY39 VCCIN_6 VCCIN_71 J2
B24 VCCIN_7 VCCIN_72 K1
B26 VCCIN_8 VCCIN_73 K2
B29 VCCIN_9 VCCIN_74 K24
B30 VCCIN_10 VCCIN_75 K26
B33 VCCIN_11 VCCIN_76 K30
B35 VCCIN_12 VCCIN_77 K32
BA10 VCCIN_13 VCCIN_78 L24
BA40 VCCIN_14 VCCIN_79 L26
BB39 VCCIN_15 VCCIN_80 L30
BB9 VCCIN_16 VCCIN_81 L32
BC10 VCCIN_17 VCCIN_82 N24
BC40 VCCIN_18 VCCIN_83 N26
BD39 VCCIN_19 VCCIN_84 N30
BD9 VCCIN_20 VCCIN_85 N32
BE10 VCCIN_21 VCCIN_86 P24
BE40 VCCIN_22 VCCIN_87 P26
BF9 VCCIN_23 VCCIN_88 P28
BG10 VCCIN_24 VCCIN_89 P30
BG40 VCCIN_25 VCCIN_90 P32
BH12 VCCIN_26 VCCIN_91 T21
BH39 VCCIN_27 VCCIN_92 T23
BH9 VCCIN_28 VCCIN_93 T25
BJ10 VCCIN_29 VCCIN_94 T27
BJ40 VCCIN_30 VCCIN_95 T31
C BK39 VCCIN_31 VCCIN_96 U23 C
BL10 VCCIN_32 VCCIN_97 U27
BL40 VCCIN_33 VCCIN_98 U29
BM39 VCCIN_34 VCCIN_99 U31
BN40 VCCIN_35 VCCIN_100 U33 +1.05V_VCCST
BP12 VCCIN_36 VCCIN_101 V23
BP39 VCCIN_37 VCCIN_102 V25
BR10 VCCIN_38 VCCIN_103 V27
BR40 VCCIN_39 VCCIN_104 V29
VCCIN_40 VCCIN_105

1
BT12 V31
BT39 VCCIN_41 VCCIN_106 V33
BU10 VCCIN_42 VCCIN_107 W22 @

https://vinafix.com
BU40 VCCIN_43 VCCIN_108 W24
BV12 VCCIN_44 VCCIN_109 W28

56_0201_1%
100_0201_1%

100_0201_1%
RC198 2

RC326 2

RC200 2
BY12 VCCIN_45 VCCIN_110 W32
CA10 VCCIN_46 VCCIN_111
CB12 VCCIN_47 R38
VCCIN_48 VCCIN_SENSE VCC_SENSE_VCCIN <88>
D24 R37
VCCIN_49 VSSIN_SENSE VSS_SENSE_VCCIN <88>
D26
D29 VCCIN_50 M12 SOC_SVID_DAT
VCCIN_51 VIDSOUT SOC_SVID_DAT <88>
D30 M11 SOC_SVID_CLK
VCCIN_52 VIDSCK SOC_SVID_CLK <88>
D33 P12 SOC_SVID_ALERT#
VCCIN_53 VIDALERT# SOC_SVID_ALERT# <88>
D35
E24 VCCIN_54
E26 VCCIN_55
E27 VCCIN_56
E29 VCCIN_57
E30 VCCIN_58
E32 VCCIN_59
B E33 VCCIN_60 B
G2 VCCIN_61
G24 VCCIN_62
G26 VCCIN_63
G30 VCCIN_64
VCCIN_65

TGL-U_BGA1449
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(10/14)Power, SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 15 of 102
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCSTG_OUT_LGC +1.05VS_VCCSTG_OUT_LGC_TERM
+1.05VS_VCCSTG_OUT_FUSE DVT modify

+1.2V_VDDQ UC1O +1.05VS_VCCSTG_OUT_FUSE 1 @ 2

AF9 RC203 0_0402_5%

AA39 VCCSTG_OUT_1 AF12
AB40 VDD2_1 VCCSTG_1 AD12
AC39 VDD2_2 VCCSTG_2

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
AD40 VDD2_3 AN10

CC33

CC155

CC156
VDD2_4 VCCSTG_OUT_2 1 1 1
AD51 AM9 +1.05V_VCCIO_OUT
AD52 VDD2_5 VCCSTG_OUT_3 AG10 @ @ @
AE39 VDD2_6 VCCSTG_OUT_4 +1.05VS_VCCSTG_OUT_LGC
EMC CAPS-PLACE AF40 VDD2_7
VDD2_8 VCCION_OUT
V15 2 2 2
AG39
< 4mm from SOC VDDQ AH40 VDD2_9 M9 +1.05V_VCCST
+1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ VDD2_10VCCSTG_OUT_LGC
with each pair < 12mm Apart DVT modify DVT modify DVT modify
AJ39
AK40 VDD2_11 BT2
D
12pF* 3 (EMC@) AK51 VDD2_12
VDD2_13
VCCST_1
VCCST_2
BT1 CC 33 clsoe AF9 D
AK52 BT4 +1.05VS_VCCSTG
2.2pF* 3 (EMC@) AL39 VDD2_14 VCCST_3 CC155 close AD12

100P_0201_50V8J

100P_0201_50V8J

100P_0201_50V8J
VDD2_15
AM40 BP2
CC156 close AN10

CC35

CC37

CC39
1 1 1 1 1 1 VDD2_16 VCCSTG_3
AN39 BP1

CC34

CC36

CC38
2.2P_0201_50V8C

2.2P_0201_50V8C

2.2P_0201_50V8C
AP40 VDD2_17 VCCSTG_4 BP4
AR39 VDD2_18 VCCSTG_5
2 2 2 2 2 2 VDD2_19

EMC@

EMC@

EMC@
AT52
VDD2_20

EMC@

EMC@

EMC@
AU40
AW40 VDD2_21
AW51 VDD2_22
AW52 VDD2_23
BD51 VDD2_24
BD52 VDD2_25
BK51 VDD2_26
BK52 VDD2_27
BV51 VDD2_28
BV52 VDD2_29 +1.05V_VCCST +1.05VS_VCCSTG
CA40 VDD2_30
CC40 VDD2_31
ESD request only for LA-K091 CC49 VDD2_32

1U_0201_10V6M
1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M
CC50 VDD2_33
Add 2*0.1u CAP for +1.2V_VDDQ

CC47
CC44

CC45

CC46
VDD2_34 1 1 1 1
CE40
VDD2_35
near PJM3 CG40
CH39 VDD2_36
@ @
VDD2_37 2 2 2 2
TOP*1 BOT*1 CJ40
CL40 VDD2_38
CN40 VDD2_39
+1.2V_VDDQ CP47 VDD2_40
CR40 VDD2_41
D50 VDD2_42
E51 VDD2_43
F49 VDD2_44
T51 VDD2_45
0.1U_0201_10V6K

0.1U_0201_10V6K

1 1 VDD2_46
T52
CC387

CC388

VDD2_47

2 2 TGL-U_BGA1449
EMC@

EMC@

C C

PVT modify

+1.05V_VCCST

+1.05VO_OUT_FET
DVT modify VCCST
I (Max) : 0.455 A(+1.05V_VCCST)
+1.05V_VCCST_R
RDS(Typ) : 3.5 mohm
RC284 1 @ 2 0_0402_5%
V drop : 0.0016V
1U_0201_6.3V6M

1 1
CC51

Imax : 0.445 A CC53

0.1U_0201_10V6K

https://vinafix.com
2 UC12 2 DVT modify,
Main use SE00000TG00 S CER CAP 1000P VOL@
1 10 50V K X7R 0201
2nd use SE170102K80 S CER CAP 1000P RC4017
+5VALW IN1 OUT1 25V K X7R 0201
0_0603_5%
VCCST_EN_LS_R 2 9 CC104 1 2 1000P_0201_50V7K
2

3 EN1 CT1 8
VCCSTG_EN_LS_R 4 VBIAS GND 7 CC383 1@ 2 1000P_0201_50V7K
EN2 CT2
1
@ 5 6 +1.05VS_VCCSTG
CC52 IN2 OUT2
1U_0201_6.3V6M

0.1U_0201_16V6K 1 11
2 GND PAD +1.05VS_VCCSTG_R
CC60

1 2

PREM@ S IC G2894KD1U TDFN2X3

Imax : 0.119 A RC287
0_0402_5%
VCCSTG
I (Max) : 0.119 A(+1.05VS_VCCSTG)
1
2 CC62
SA0000D5C00 PREM@ RDS(Typ) : 3.5 mohm Place on CPU Side
footprint use 0.1U_0201_10V6K
PREM@
V drop : 0.0004V
1uF* 10
2
SA00007QK00 10uF* 16
47uF * 2
CPU_C10_GATE# stable to +1.05VS_VCCSTG <= 65us (tCPU26)

B B

PREM Path +1.2V_VDDQ +1.2V_VDDQ +1.2V_VDDQ

VCCST_EN_LS 1 @ 2 VCCST_EN_LS_R VCCSTG_EN_LS 1 @ 2 VCCSTG_EN_LS_R
RC205 RC213
1U_0201_6.3V6M

0_0201_5% 1 0_0201_5% PVT modify

2
CC55

PREM@

1U_0201_10V6M

1U_0201_10V6M
1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

1U_0201_10V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

47U_0603_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

47U_0603_6.3V6M
RC288

CC69

CC70
CC74

CC75

CC76

CC77

CC78

CC79

CC105

CC106
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1
CC113

CC120

CC160

CC121
CC68

CC119
CC73

CC114

CC115

CC116

CC117

CC118

CC157

CC159

CC158

CC162

CC161

CC122
@ 100K_0201_5%
2

2
1

2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

VCCST/VCCSTG Enable PM_SLP_S3# RC304 1 2 0_0201_5%

<11> PM_SLP_S3#
ICL have EC_VCCST_EN SUSP# RC4027 1 @ 2 0_0201_5%
<58,78,84,86> SUSP#
check need it? or use syson/susp? 1210

+3VALW_PRIM

1 DC7
CC101 2
0.1U_0201_10V6K 1 VCCST_EN_LS
A @ 3 A
DVT modify 2
5

UC11 LRB715FT1G_SOT323-3
VCCIN_AUX_CORE_VID 1
P

<11> VCCIN_AUX_CORE_VID INB VCCST_STG_COM_EN

4
VCCST_OVERRIDE_LS 2 O
<11> VCCST_OVERRIDE_LS
G

INA
MC74VHC1G32DFT2G_SC70-5~D DC8
3

2
SA0000C8300 1 VCCSTG_EN_LS
@ 3

LRB715FT1G_SOT323-3
1 2 PVT modify PREM@
Security Classification Compal Secret Data Compal Electronics, Inc.
RC340 0_0201_5% PREM Path 2019/09/20 2020/12/31 Title
CPU_C10_GATE# 1 @ 2
Issued Date Deciphered Date
<11> CPU_C10_GATE#
RC331 0_0201_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(11/14)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Friday, August 07, 2020 Sheet 16 of 102
5 4 3 2 1
 5 4 3 2 1

+1.8VALW_PRIM PVT modify +1.8V_PRIM_MCP

RC219 1 @ 2 0_0603_5%

+1.8V_PRIM_MCP +1.8V_VCCA_CLKLDO
+3VALW +3VALW_DSW @
L1 1 2 Package size?
4.7UH_UHP252012BF-4R7M_20%
RC216 1 @ 2 0_0402_5%
EMC CAPS-PLACE

2
RC220
1 2 0_0402_5%
< 5mm from SOC VCCIN_AUX
D
RC218 D
0_0402_5% +VCCIN_AUX

1
DVT modify
1
+3VALW TO +3V_PRIM

100P_0201_50V8J
CC81

CC98

EMC@ CC100
1 1 1 1

100P_0201_50V8J

2.2P_0201_50V8C
0.1U_0201_10V6K
47U_0603_6.3V6M

EMC@ CC99

CC97
1354mA 2
+3VALW +3VALW_PRIM
2 2 2 2

EMC@
JPC7

@
1 2
1 2
JUMP_43X39
@ 1
CC82
4.7U_0402_6.3V6M
+VCCIN_AUX UC1N +1.8V_PRIM_MCP
2
AB12 CY18
AC10 VCCIN_AUX_1 VCCPRIM_1P8_1 CY20
AE10 VCCIN_AUX_2 VCCPRIM_1P8_2 CY24
AK2 VCCIN_AUX_3 VCCPRIM_1P8_3 CY26
AR10 VCCIN_AUX_4 VCCPRIM_1P8_4 DA18
AT12 VCCIN_AUX_5 VCCPRIM_1P8_5 DA20
AU10 VCCIN_AUX_6 VCCPRIM_1P8_6 DA22
AW10 VCCIN_AUX_7 VCCPRIM_1P8_7 DA24
BV1 VCCIN_AUX_8 VCCPRIM_1P8_8 DA26
BV39 VCCIN_AUX_9 VCCPRIM_1P8_9 DC18
BW40 VCCIN_AUX_10 VCCPRIM_1P8_10 DC20
BY39 VCCIN_AUX_11 VCCPRIM_1P8_11 DC22
CC1 VCCIN_AUX_12 VCCPRIM_1P8_12 DC24
CD12 VCCIN_AUX_13 VCCPRIM_1P8_13 DC26
CF10 VCCIN_AUX_14 VCCPRIM_1P8_14 DD20
CG12 VCCIN_AUX_15 VCCPRIM_1P8_15 DD22
+1.05VO_VNNBYPASS CH10 VCCIN_AUX_16 VCCPRIM_1P8_16 DV22 +3VALW_PRIM
CJ1 VCCIN_AUX_17 VCCPRIM_1P8_17
C CJ12 VCCIN_AUX_18 DA35 +VO_VCCDCPRTC C
CK10 VCCIN_AUX_19 VCCPRIM_3P3_1 DC28
CL12 VCCIN_AUX_20 VCCPRIM_3P3_2 DC30
+1.05VO_EXTBYPASS CM10 VCCIN_AUX_21 VCCPRIM_3P3_3 DD30
1 CP1 VCCIN_AUX_22 VCCPRIM_3P3_4 +0.85VO_VCCLDOSTD

100K_0201_5%
CP10 VCCIN_AUX_23 DV34
R5 VCCIN_AUX_24
CR12 DCPRTC
CT10 VCCIN_AUX_25 DV46 +1.8V_VCCA_CLKLDO
@ CU12 VCCIN_AUX_26 VCCLDOSTD_0P85
100K_0201_5%

VCCIN_AUX_27
1

CY1 DV16 +1.24VO_VCCDPHY

AK1 VCCIN_AUX_28 VCCA_CLKLDO_1P8_1 DC15
R6

+3VALW_PRIM
VCCIN_AUX_29 VCCA_CLKLDO_1P8_2 +1.05VO_VCCDSW
@ AV9 DV28
<91> VSS_SENSE_VCCIN_AUX AT9 VCCIN_AUX_VSSSENSE VCCDPHY_1P24
<91> VCC_SENSE_VCCIN_AUX
2

RC225 1 2 100K_0201_5% VCCIN_AUX_CORE_VID0_R VCCIN_AUX_VCCSENSE DD38 +1.05VO_OUT_FET

https://vinafix.com
RC226 1 2 100K_0201_5% VCCIN_AUX_CORE_VID1_R DD17 VCCDSW_1P05
DD18 VCC_VNNEXT_1P05_1 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET_1 BR4
DA15 VCC1P05_OUT_FET_2 BT5 +1.05VO_OUT_PCH
DA17 VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET_3
DVT modify VCC_V1P05EXT_1P05_2 DA31
RC222 1 @ 2 0_0201_5% VCCIN_AUX_CORE_ALERT# DB39 VCCPRIM_1P05_1 DC33
<7> VCCIN_AUX_CORE_ALERT#_R VNN_CTRL GPP_B2/VRALERT# VCCPRIM_1P05_2 +RTCVCC
1 DV12 DC31
T194 TP@ 1 V1.05P_CTRL DT12 GPP_F22/VNN_CTRL VCCPRIM_1P05_3 +3VALW_DSW
DVT modify T195 TP@ GPP_F23/V1P05_CTRL
VCCRTC
DC35 +3VALW_PRIM for HDA=3V
<11,91> VCCIN_AUX_CORE_VID0_R RC223 1 @ 2 0_0201_5% VCCIN_AUX_CORE_VID0 DB37 DD37
RC224 1 @ 2 0_0201_5% VCCIN_AUX_CORE_VID1 DB38 GPP_B0/CORE_VID0 VCCDSW_3P3 DA28 +3VALW_PRIM
<11,91> VCCIN_AUX_CORE_VID1_R GPP_B1/CORE_VID1 VCCPGPPR ?
CY31
? +1.8V_PRIM_MCP
VCCPRIM_3P3_5 CY33
VCCPRIM_3P3_6 CV39 +VCCANA_EHV
VCCPRIM_1P8_18
AP12 1 TP@T84
RSVD_1
TGL-U_BGA1449
B
@ NOTE: B
576591-tgl-pch-lp-eds-vol1of2-rev0p5
VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
Need to sync with codec VDDIO.
607872_TGL_UY_PDG_Rev0p5
When configured as 3.3V or 1.8V, VCCPGPPR can be merged directly with
either VCCPRIM_1P8 or VCCPRIM_3P3 depending on their operating voltage.

RTC Battery
MAX. 8000mil
+RTCBATT
+RTCBATT W=20mil
JRTC1
1 2 1
+RTCVCC 2 1
RC227 1K_0402_5% DC1 W=40mil 2
+1.8V_PRIM_MCP +3VALW_PRIM +1.24VO_VCCDPHY +VO_VCCDCPRTC +CHGRTC 2 2mA
+3VALW_DSW +1.05VO_VCCDSW +0.85VO_VCCLDOSTD 1 3
3 4 GND
0.1U_0201_10V6K

GND

1U_0201_6.3V6M
CC88
1U_0201_10V6M

1 1
0.1U_0201_10V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M

0.1U_0201_10V6K
LRB715FT1G_SOT323-3 ACES_50271-0020N-001
1U_0201_10V6M

1 1 1 1 1 1 1 2 1
CC84 CC85 @ W=20mil
CC87

CC89
CC384

CONN@

CC92
CC91
@ CC83 1U_0201_10V6M 2.2U_0201_6.3V6M @ @
CC86

CC90

1U_0201_10V6M 2 2
A
2 2 2 2 2 2 2 1 2 SP02000RO00 A

DVT modify

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(12/14)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 17 of 102
5 4 3 2 1
 5 4 3 2 1

UC1Q UC1R
UC1P
BY44 CY44 DP53 K34
A27 B19 BY45 VSS_109 VSS_169 CY45 DR11 VSS_2 VSS_46 K48
D D
A32 VSS_223 VSS_289 B2 BY47 VSS_110 VSS_170 CY47 DR16 VSS_3 VSS_47 K5
A45 VSS_224 VSS_290 B23 BY49 VSS_111 VSS_171 CY5 DR22 VSS_4 VSS_48 L22
A49 VSS_225 VSS_291 B27 BY9 VSS_112 VSS_172 D27 DR28 VSS_5 VSS_49 L28
AA41 VSS_226 VSS_292 B32 C13 VSS_113 VSS_173 D32 DR34 VSS_6 VSS_50 L34
AA48 VSS_227 VSS_293 B36 C19 VSS_114 VSS_174 D36 DR40 VSS_7 VSS_51 L39
AB5 VSS_228 VSS_294 B39 C23 VSS_115 VSS_175 D42 DR46 VSS_8 VSS_52 L41
AB7 VSS_229 VSS_295 B42 CA48 VSS_116 VSS_176 D49 DT4 VSS_9 VSS_53 L42
AB8 VSS_230 VSS_296 B48 CB41 VSS_117 VSS_177 D5 DT50 VSS_10 VSS_54 L44
AC44 VSS_231 VSS_297 B52 CC10 VSS_118 VSS_178 DA30 DU11 VSS_11 VSS_55 L45
AC49 VSS_232 VSS_298 B8 CC3 VSS_119 VSS_179 DA33 DU16 VSS_12 VSS_56 L47
AD4 VSS_233 VSS_299 BA48 CC5 VSS_120 VSS_180 DA53 DU22 VSS_13 VSS_57 L49
AD48 VSS_234 VSS_300 BA53 CD44 VSS_121 VSS_181 DC17 DU28 VSS_14 VSS_58 M1
AD8 VSS_235 VSS_301 BB4 CD48 VSS_122 VSS_182 DD15 DU34 VSS_15 VSS_59 M2
AF4 VSS_236 VSS_302 BB8 CD7 VSS_123 VSS_183 DD24 DU40 VSS_16 VSS_60 M50
AF8 VSS_237 VSS_303 BC1 CE49 VSS_124 VSS_184 DD26 DU46 VSS_17 VSS_61 N22
AG41 VSS_238 VSS_304 BC2 CG48 VSS_125 VSS_185 DD28 DV1 VSS_18 VSS_62 N28
AG42 VSS_239 VSS_305 BD12 CG51 VSS_126 VSS_186 DD31 DV40 VSS_19 VSS_63 N34
AG44 VSS_240 VSS_306 BD4 CG52 VSS_127 VSS_187 DD33 DV52 VSS_20 VSS_64 N39
AG45 VSS_241 VSS_307 BD48 CG9 VSS_128 VSS_188 DD35 DW51 VSS_21 VSS_65 N41
AG47 VSS_242 VSS_308 BD8 CH41 VSS_129 VSS_189 DD39 E13 VSS_22 VSS_66 N48
AG48 VSS_243 VSS_309 BF39 CH42 VSS_130 VSS_190 DD45 E19 VSS_23 VSS_67 P11
AG53 VSS_244 VSS_310 BF4 CH44 VSS_131 VSS_191 DD51 E35 VSS_24 VSS_68 P14
AH4 VSS_245 VSS_311 BF41 CH45 VSS_132 VSS_192 DD52 E48 VSS_25 VSS_69 P16
AH8 VSS_246 VSS_312 BF42 CH47 VSS_133 VSS_193 DE3 G22 VSS_26 VSS_70 P18
AK12 VSS_247 VSS_313 BF44 CJ3 VSS_134 VSS_194 DE5 G28 VSS_27 VSS_71 P20
AK4 VSS_248 VSS_314 BF45 CJ5 VSS_135 VSS_195 DF19 G34 VSS_28 VSS_72 P22
AK48 VSS_249 VSS_315 BF47 CJ9 VSS_136 VSS_196 DF37 G39 VSS_29 VSS_73 P33
AK5 VSS_250 VSS_316 BF5 CK39 VSS_137 VSS_197 DG15 G48 VSS_30 VSS_74 P35
C AK7 VSS_251 VSS_317 BF7 CK48 VSS_138 VSS_198 DG21 G51 VSS_31 VSS_75 P4 C
AK8 VSS_252 VSS_318 BF8 CK53 VSS_139 VSS_199 DG27 G52 VSS_32 VSS_76 P49
AM1 VSS_253 VSS_319 BG48 CL9 VSS_140 VSS_200 DG33 H12 VSS_33 VSS_77 P8
AM2 VSS_254 VSS_320 BG53 CN12 VSS_141 VSS_201 DG39 H22 VSS_34 VSS_78 R39
AM4 VSS_255 VSS_321 BH1 CN48 VSS_142 VSS_202 DG45 H28 VSS_35 VSS_79 R44
AM8 VSS_256 VSS_322 BH2 CN51 VSS_143 VSS_203 DG5 H34 VSS_36 VSS_80 T19
AN41 VSS_257 VSS_323 BH4 CN52 VSS_144 VSS_204 DG53 H8 VSS_37 VSS_81 T29
AN42 VSS_258 VSS_324 BH8 CN9 VSS_145 VSS_205 DG6 J39 VSS_38 VSS_82 T33
AN44 VSS_259 VSS_325 BK12 CP3 VSS_146 VSS_206 DJ1 J49 VSS_39 VSS_83 T4
AN45 VSS_260 VSS_326 BK4 CP41 VSS_147 VSS_207 DJ2 K16 VSS_40 VSS_84 T48
AN47 VSS_261 VSS_327 BK48 CP42 VSS_148 VSS_208 DJ4 K18 VSS_41 VSS_85 T8
AN48 VSS_262 VSS_328 BK8 CP44 VSS_149 VSS_209 DK51 K20 VSS_42 VSS_86 U19

https://vinafix.com
AN53 VSS_263 VSS_329 BL49 CP45 VSS_150 VSS_210 DL3 K22 VSS_43 VSS_87 U25
AP4 VSS_264 VSS_330 BM1 CP5 VSS_151 VSS_211 DL5 K28 VSS_44 VSS_88 U39
AP8 VSS_265 VSS_331 BM4 CR48 VSS_152 VSS_212 DM10 VSS_45 VSS_89 U49
AT4 VSS_266 VSS_332 BM41 CR53 VSS_153 VSS_213 DM15 VSS_90 V19
AT48 VSS_267 VSS_333 BM42 CR9 VSS_154 VSS_214 DM21 VSS_91 V4
AT51 VSS_268 VSS_334 BM44 CT5 VSS_155 VSS_215 DM27 VSS_92 V8
AT8 VSS_269 VSS_335 BM45 CU4 VSS_156 VSS_216 DM33 VSS_93 W1
AV12 VSS_270 VSS_336 BM47 CU9 VSS_157 VSS_217 DM39 VSS_94 W16
AV39 VSS_271 VSS_337 BM8 CV10 VSS_158 VSS_218 DM4 VSS_95 W26
AV4 VSS_272 VSS_338 BN48 CV48 VSS_159 VSS_219 DM45 VSS_96 W30
AV5 VSS_273 VSS_339 BP41 CV5 VSS_160 VSS_220 DN1 VSS_97 W39
AV7 VSS_274 VSS_340 BP49 CV51 VSS_161 VSS_221 DN2 VSS_98 W41
AV8 VSS_275 VSS_341 BP5 CV52 VSS_162 VSS_222 VSS_99 W42
AW1 VSS_276 VSS_342 BP50 CY17 VSS_163 VSS_100 W44
AW2 VSS_277 VSS_343 BP7 CY22 VSS_164 VSS_101 W45
AW48 VSS_278 VSS_344 BT44 CY35 VSS_165 VSS_102 W47
AY4 VSS_279 VSS_345 BT48 CY41 VSS_166 VSS_103 W48
B AY41 VSS_280 VSS_346 BU49 CY42 VSS_167 VSS_104 Y4 B
AY42 VSS_281 VSS_347 BV3 VSS_168 VSS_105 Y49
AY44 VSS_282 VSS_348 BV48 VSS_106 Y50
AY45 VSS_283 VSS_349 BV5 TGL-U_BGA1449 VSS_107 Y8
AY47 VSS_284 VSS_350 BW10 VSS_108
VSS_285 VSS_351 @
AY8 BY41
AY9 VSS_286 VSS_352 BY42 TGL-U_BGA1449
B13 VSS_287 VSS_353
VSS_288 @

TGL-U_BGA1449
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(13/14)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 18 of 102
5 4 3 2 1
 5 4 3 2 1

+1.05V_VCCIO_OUT

RC250 1 2 1K_0201_5% CFG1

RC251 1 2 1K_0201_5% CFG2 UC1T
RC252 1 2 1K_0201_5% CFG3
RC256 1 @ 2 10K_0201_5% CFG4 T15 A51
RC259 1 @ 2 10K_0201_5% CFG7 CFG14 V17 CFG_15 RSVD_TP_7 B51
RC262 1 2 1K_0201_5% CFG9 U15 CFG_14 RSVD_TP_8
RC264 1 2 1K_0201_5% CFG10 K11 CFG_13 C1
RC266 1 2 1K_0201_5% CFG11 CFG11 K12 CFG_12 RSVD_TP_9 D2
RC271 1 @ 2 10K_0201_5% CFG14 CFG10 K9 CFG_11 RSVD_TP_10
CFG9 T17 CFG_10 CP39
D D
K7 CFG_9 RSVD_TP_11 CU40
CFG7 H7 CFG_8 RSVD_TP_12 AK9
K8 CFG_7 RSVD_12
H9 CFG_6 AH9
CFG Signals CFG_5 RSVD_13
CFG4 E6
(For Strap & XDP) CFG3 H5 CFG_4 DW6
CFG2 E9 CFG_3 RSVD_14 DV6
CFG1 D9 CFG_2 RSVD_15
E7 CFG_1 DV4
CFG_0 RSVD_TP_13 DW3
CFG_RCOMP B5 RSVD_TP_14
CFG_RCOMP

1
DU1
RC228 U17 RSVD_TP_15 DT2
49.9_0402_1% H11 CFG_17 RSVD_TP_16
CFG_16 DW2
1 BPM#3 Y1 RSVD_TP_17 DV2
T531 TP@

2
1 BPM#2 M4 BPM#_3 RSVD_TP_18
T530 TP@ BPM#_2
T529 TP@ 1 BPM#1 AB4 E1
1 BPM#0 Y2 BPM#_1 RSVD_TP_19 F1
T528 TP@ BPM#_0 RSVD_TP_20
A3 AB2
B3 RSVD_6 RSVD_16
RSVD_7 DR1
TCSS_RCOMP AR2 RSVD_TP_21 DR2
CFG4 TCP0_MBIAS_RCOMP RSVD_TP_22
Display port presence strap AL10
RSVD_TP_2

1
LOW : Enable AM12 DR53
RC335 AH12 RSVD_TP_3 RSVD_TP_23 DW5
An external display port device is connected to RSVD_TP_4 RSVD_TP_24
2.2K_0201_1% AJ10
C
the embedded displayport AR1 RSVD_TP_5 DV51 C
HIGH : Disable RC233 1 2 1K_0201_5% CFG4 RSVD_TP_6 VSS_1 DW52

2
No physical display port attached to embedded display port BN10 TP_3 DV53
RC4014 1 @ 2 1K_0201_5% CFG14 BM12 RSVD_8 TP_4 W34
DD13 RSVD_9 RSVD_17 V35
RC207 1 @ 2 1K_0201_5% CFG7 DF13 RSVD_10 RSVD_18
RSVD_11 D52 SKTOCC# 1
CFG7 SKTOCC# TP@ T112
PEG Training CFG14
LOW : PEG Wait for BIOS for training. PEG60 Lane Reversal
HIGH : (default) PEG Train immediately following HIGH : (Default) Normal TGL-U_BGA1449
RESET# de assertion. LOW : Reversed @

https://vinafix.com DF53
UC1S

C53
RSVD_19 RSVD_23 T35
DF52 RSVD_24 E53
RSVD_20 RSVD_25 CF39
1 DT52 RSVD_26 U35
T113 TP@ PCH_IST_TP_1 RSVD_27
T114 TP@ 1 DU53 F53
PCH_IST_TP_0 RSVD_28 B53
DF50 RSVD_29 AP9
DF49 RSVD_21 RSVD_30 A52
0109 remove ES1@ componet RSVD_22 RSVD_31
T115 TP@ 1 CY30 BF12
B 1 CY15 RSVD_TP_25 RSVD_TP_28 V21 B
T521 TP@ RSVD_TP_26 RSVD_TP_29 W20
1 D4 RSVD_TP_30 U37
T120 TP@ RSVD_TP_27 RSVD_TP_31 CD39
1 A6 RSVD_TP_32 U21
T123 TP@ IST_TP_1 RSVD_TP_33
T125 TP@ 1 A4 CB39
IST_TP_0 RSVD_32 BB12
RSVD_TP_34 W37
RSVD_TP_35 AY12
RSVD_TP_36 W38
RSVD_TP_37 U38
RSVD_TP_38 CY28 1
RSVD_TP_39 TP@ T522

TGL-U_BGA1449
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(14/14)RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 19 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for SOC/PCH/FCH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 20 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for SOC/PCH/FCH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 21 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for SOC/PCH/FCH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 22 of 102
5 4 3 2 1
 A B C D E

JDIMM2A
DDR_A_CLK0 137 STD 8 DDR_A_D62
<8>

<8>
DDR_A_DQS#[0..7]

DDR_A_D[0..63]
DDR_A_CLK#0
DDR_A_CLK1
139
138
CK0(T)
CK0#(C)
CK1(T)
DQ0
DQ1
DQ2
7
20
DDR_A_D59
DDR_A_D61 Standard Type
DDR_A_CLK#1 140 21 DDR_A_D57
DVT modify, remove PU circuit CK1#(C) DQ3 4 DDR_A_D58
<8> DDR_A_DQS[0..7] DDR_A_CKE0 109 DQ4 3 DDR_A_D60 2-3A to 1 DIMMs/channel
DDR_A_CKE1 110 CKE0 DQ5 16 DDR_A_D63
CKE1 DQ6 17 DDR_A_D56
<8> DDR_A_MA[0..16] DDR_A_CS#0 DQ7 DDR_A_DQS7
149 13
DDR_A_BA0 DDR_A_CS#1 157 S0# DQS0(T) 11 DDR_A_DQS#7
<8> DDR_A_BA0 DDR_A_BA1 DDR_A_SA2 S1# DQS0#(C)
162
<8> DDR_A_BA1 DDR_A_BG0 DDR_A_SA1 S2#/C0 DDR_A_D51 +1.2V_VDDQ +1.2V_VDDQ
165 28
<8> DDR_A_BG0 DDR_A_BG1 DDR_A_SA0 S3#/C1 DQ8 DDR_A_D52
29 JDIMM2B
<8> DDR_A_BG1 DDR_A_ACT# DDR_A_ODT0 DQ9 DDR_A_D55
155 41 STD
<8> DDR_A_ACT# ODT0 DQ10

1
1 DDR_A_ALERT# DDR_A_ODT1 161 42 DDR_A_D49 111 141 1
<8> DDR_A_ALERT# DDR_A_PAR RD54 RD241 RD56 ODT1 DQ11 DDR_A_D48 VDD1 VDD11
24 112 142
<8> DDR_A_PAR 0_0402_5% @ 0_0402_5% @
0_0402_5% @ DDR_A_BG0 DQ12 DDR_A_D53 VDD2 VDD12
115 25 Data swap 12/12 117 147
DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D50 118 VDD3 VDD13 148
DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D54 +1.2V_VDDQ 123 VDD4 VDD14 153

2
DDR_A_CLK0 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS6 124 VDD5 VDD15 154
<8> DDR_A_CLK0 DDR_A_CLK#0 BA1 DQS1(T) DDR_A_DQS#6 +0.6V_A_VREFCA VDD6 VDD16
32 129 159
<8> DDR_A_CLK#0 DQS1#(C)

1
DDR_A_CLK1 DDR_A_MA0 144 130 VDD7 VDD17 160
<8> DDR_A_CLK1 DDR_A_CLK#1 DDR_A_MA1 A0 DDR_A_D45 VDD8 VDD18
133 50 RD46 135 163
<8> DDR_A_CLK#1 DDR_A_MA2 132 A1 DQ16 49 DDR_A_D46 1K_0402_1% 136 VDD9 VDD19
DDR_A_MA3 131 A2 DQ17 62 DDR_A_D41 Data swap 12/12 +0.6V_DDRA_VREFCA VDD10
DDR_A_CKE0 DDR_A_MA4 128 A3 DQ18 63 DDR_A_D40 RD49 255 258
<8> DDR_A_CKE0 +3VS +0.6VS_VTT

2
DDR_A_CKE1 DDR_A_MA5 126 A4 DQ19 46 DDR_A_D44 2_0402_1% VDDSPD VTT
<8> DDR_A_CKE1 DDR_A_CS#0 DDR_A_MA6 A5 DQ20 DDR_A_D47
20mils
127 45 2 1 164 257
<8> DDR_A_CS#0 DDR_A_CS#1 DDR_A_MA7 A6 DQ21 DDR_A_D42 VREFCA VPP1 +2.5V
122 58 1 259
<8> DDR_A_CS#1 DDR_A_MA8 A7 DQ22 DDR_A_D43 VPP2
125 59
DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS5 CD66 1 99
A9 DQS2(T) 1

1
SOC_SMBDATA DDR_A_MA10 146 53 DDR_A_DQS#5 0.022U_0402_16V7K 2 VSS VSS 102
<9,66> SOC_SMBDATA SOC_SMBCLK DDR_A_MA11 A10_AP DQS2#(C) 2 VSS VSS
120 RD47 CD65 5 103
<9,66> SOC_SMBCLK DDR_A_MA12 A11 DDR_A_D38 0.1U_0201_10V6K VSS VSS
119 70 1K_0402_1% 6 106
A12 DQ24

1
DDR_A_MA13 158 71 DDR_A_D36 2 9 VSS VSS 107
DDR_A_ODT0 DDR_A_MA14 151 A13 DQ25 83 DDR_A_D32 RD50 10 VSS VSS 167
<8> DDR_A_ODT0

2
DDR_A_ODT1 DDR_A_MA15 156 A14_WE# DQ26 84 DDR_A_D34 14 VSS VSS 168
<8> DDR_A_ODT1 24.9_0402_1%
DDR_A_MA16 152 A15_CAS# DQ27 66 DDR_A_D39 15 VSS VSS 171
A16_RAS# DQ28 67 DDR_A_D37 18 VSS VSS 172

2
DDR_A_ACT# 114 DQ29 79 DDR_A_D35 19 VSS VSS 175
ACT# DQ30 80 DDR_A_D33 22 VSS VSS 176
DDR_A_PAR 143 DQ31 76 DDR_A_DQS4 23 VSS VSS 180
DDR_A_ALERT# 116 PARITY DQS3(T) 74 DDR_A_DQS#4 26 VSS VSS 181
RD63 2 1 240_0402_1% DDR_A_EVENT# 134 ALERT# DQS3#(C) 27 VSS VSS 184
<8,24>
+1.2V_VDDQ
DDR_DRAMRST#
DDR_DRAMRST# 108 EVENT#
RESET# DQ32
174 DDR_A_D14
DDR_A_D13
Place near to SO-DIMM connector. 30 VSS
VSS
VSS
VSS
185
173 31 188
DQ33 187 DDR_A_D11 35 VSS VSS 189
SOC_SMBDATA 254 DQ34 186 DDR_A_D9 36 VSS VSS 192
CD30 2 1 .1U_0402_16V7K SOC_SMBCLK 253 SDA DQ35 170 DDR_A_D15 39 VSS VSS 193
XEMC@ SCL DQ36 169 DDR_A_D12 Data swap 12/12 40 VSS VSS 196
DDR_A_SA2 166 DQ37 183 DDR_A_D8 43 VSS VSS 197
DDR_A_SA1 260 SA2 DQ38 182 DDR_A_D10 44 VSS VSS 201
DDR_A_SA0 256 SA1 DQ39 179 DDR_A_DQS1 47 VSS VSS 202
SA0 DQS4(T) 177 DDR_A_DQS#1 48 VSS VSS 205
DQS4#(C) 51 VSS VSS 206
92 195 DDR_A_D5 52 VSS VSS 209
2 CB0_NC DQ40 DDR_A_D6 VSS VSS 2
91 194 56 210
101 CB1_NC DQ41 207 DDR_A_D3 57 VSS VSS 213
105 CB2_NC DQ42 208 DDR_A_D2 60 VSS VSS 214
88 CB3_NC DQ43 191 DDR_A_D4 61 VSS VSS 217
87 CB4_NC DQ44 190 DDR_A_D7 64 VSS VSS 218
100 CB5_NC DQ45 203 DDR_A_D0 65 VSS VSS 222
104 CB6_NC DQ46 204 DDR_A_D1 68 VSS VSS 223
RD61 2 1 240_0402_1% DDR_A_DQS8 97 CB7_NC DQ47 200 DDR_A_DQS0 69 VSS VSS 226
+1.2V_VDDQ DDR_A_DQS#8 DQS8(T) DQS5(T) DDR_A_DQS#0 VSS VSS
RD62 2 1 240_0402_1% 95 198 72 227
DQS8#(C) DQS5#(C) 73 VSS VSS 230
216 DDR_A_D31 77 VSS VSS 231
12 DQ48 215 DDR_A_D24 78 VSS VSS 234
+1.2V_VDDQ DM0#/DBI0# DQ49 DDR_A_D26 VSS VSS
33 228 81 235
54 DM1#/DBI1# DQ50 229 DDR_A_D28 82 VSS VSS 238
Layout Note: DM2#/DBI2# DQ51 DDR_A_D27 VSS VSS
75 211 85 239
Place near JDIMM2 178 DM3#/DBI3# DQ52 212 DDR_A_D29 86 VSS VSS 243
199 DM4#/DBI4# DQ53 224 DDR_A_D25 89 VSS VSS 244
220 DM5#/DBI5# DQ54 225 DDR_A_D30 90 VSS VSS 247

https://vinafix.com
+1.2V_VDDQ 241 DM6#/DBI6# DQ55 221 DDR_A_DQS3 93 VSS VSS 248
96 DM7#/DBI7# DQS6(T) 219 DDR_A_DQS#3 94 VSS VSS 251
DM8#/DBI8# DQS6#(C) 98 VSS VSS 252
VSS VSS
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 262 261
237 DDR_A_D17 GND GND
CD32

CD35

CD36

CD37

CD290

CD287

CD284

CD289
CD33

CD70

CD288

CD283

CD285
CD34

CD69

CD286

DQ56 236 DDR_A_D23

DQ57 249 DDR_A_D20 FOX_AS0A821-H4SB-7H
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DQ58 250 DDR_A_D16 CONN@
DQ59 232 DDR_A_D21
DQ60 SP07001GA00
233 DDR_A_D19
DQ61 245 DDR_A_D22 Data swap 12/12
DQ62 246 DDR_A_D18
DQ63 242 DDR_A_DQS2
DQS7(T) 240 DDR_A_DQS#2
DQS7#(C)
+1.2V_VDDQ

FOX_AS0A821-H4SB-7H
Interleaved Memory
CONN@
SP07001GA00
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

Compatible with SP07001HW00

1

1
1

1
1

1
CD42
CD41

CD43

CD45

CD279

CD277

CD275

CD282

CD280

CD276
CD38

CD39

CD40

CD44

CD281

CD278

3 3
2

2
2

2
2

www.teknisi-indonesia.com
VDDQ
1uF*16
10uF*16
330uF*1

Refer for DDR4 SO-DIMM Decoupling Caps

607872_TGL_UY_PDG_Rev0p5

Layout Note: Layout Note: Layout Note:

Place near JDIMM1.257,259 Place near JDIMM2.255 Place near JDIMM1.258

VPP +3VS
VDDSPD VTT
+2.5V +0.6VS_VTT
1uF*2 0.1uF*2 1uF*4
10uF*2 2.2uF*2 10uF*2
1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

1 1 1 1 1 1 1 1
1
1

1
1

CD64
CD240

CD257
CD68

CD67

CD63
CD62
CD291

CD295

CD294
CD239
CD292

CD55

CD293

4 4
2
2

2
2

2 2 2 2 2 2 2 2

Security Classification
2018/12/27
Compal Secret Data
2019/12/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 23 of 102
A B C D E
 5 4 3 2 1

+DDR_VREF_CA +DDR_VREF_CA
+DDR_VREF_CA +DDR_VREF_CA
U2 U3
U4 U5
M1 G2 DDR_B_D13 M1 G2 DDR_B_D26
DVT modify VREFCA DQL0 F7 DDR_B_D12 DVT modify VREFCA DQL0 F7 DDR_B_D29 M1 G2 DDR_B_D45 M1 G2 DDR_B_D62
DQL1 H3 DDR_B_D14 DQL1 H3 DDR_B_D30 DVT modify VREFCA DQL0 F7 DDR_B_D43 DVT modify VREFCA DQL0 F7 DDR_B_D56

.1U_0402_16V7K

.1U_0402_16V7K
DDR_B_MA0 P3 DQL2 H7 DDR_B_D10 DDR_B_MA0 P3 DQL2 H7 DDR_B_D24 DQL1 H3 DDR_B_D44 DQL1 H3 DDR_B_D58
1 1

.1U_0402_16V7K

.1U_0402_16V7K
DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D15 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D27 DDR_B_MA0 P3 DQL2 H7 DDR_B_D41 DDR_B_MA0 P3 DQL2 H7 DDR_B_D60

CD124

CD125
A1 DQL4 A1 DQL4 1 A0 DQL3 1 A0 DQL3
DDR_B_MA2 R3 H8 DDR_B_D11 DDR_B_MA2 R3 H8 DDR_B_D28 DDR_B_MA1 P7 H2 DDR_B_D46 DDR_B_MA1 P7 H2 DDR_B_D61

CD126

CD127
DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D8 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D31 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D42 DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D57
2 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D9 2 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D25 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D47 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D59
DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7 2 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D40 2 MEM@ DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D63
DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA5 P8 A4 DQL7
DDR_B_MA7 R8 A6 A3 DDR_B_D6 DDR_B_MA7 R8 A6 A3 DDR_B_D19 DDR_B_MA6 P2 A5 DDR_B_MA6 P2 A5
DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D2 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D22 DDR_B_MA7 R8 A6 A3 DDR_B_D39 DDR_B_MA7 R8 A6 A3 DDR_B_D55
D A8 DQU1 A8 DQU1 A7 DQU0 A7 DQU0 D
DDR_B_MA9 R7 C3 DDR_B_D5 DDR_B_MA9 R7 C3 DDR_B_D21 DDR_B_MA8 R2 B8 DDR_B_D33 DDR_B_MA8 R2 B8 DDR_B_D52
DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D1 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D16 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D37 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D51
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D7 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D23 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D35 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D48
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D0 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D20 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D36 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D54
DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D4 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D17 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D32 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D53
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D3 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D18 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D38 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D49
A14/WE DQU7 A14/WE DQU7 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D34 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D50
DDR_B_BA0 N2 DDR_B_BA0 N2 A14/WE DQU7 A14/WE DQU7
<8> DDR_B_BA0 DDR_B_BA1 BA0 DDR_B_BA1 BA0 DDR_B_BA0 DDR_B_BA0
<8> DDR_B_BA1 N8 B3 +1.2V_VDDQ N8 B3 +1.2V_VDDQ N2 N2 +1.2V_VDDQ
BA1 VDD B9 BA1 VDD B9 DDR_B_BA1 N8 BA0 B3 DDR_B_BA1 N8 BA0 B3
VDD VDD BA1 VDD +1.2V_VDDQ BA1 VDD
+1.2V_VDDQ E2 D1 +1.2V_VDDQ E2 D1 B9 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD +1.2V_VDDQ DMU/DBIU VDD +1.2V_VDDQ DMU/DBIU VDD
J1 J1 E7 G7 E7 G7
VDD J9 VDD J9 DML/DBIL VDD J1 DML/DBIL VDD J1
VDD L1 VDD L1 VDD J9 VDD J9
DDR_B_CLK0 K7 VDD L9 DDR_B_CLK0 K7 VDD L9 VDD L1 VDD L1
<8> DDR_B_CLK0 DDR_B_CLK#0 CK_t VDD DDR_B_CLK#0 CK_t VDD DDR_B_CLK0 VDD DDR_B_CLK0 VDD
<8> DDR_B_CLK#0 K8 R1 K8 R1 K7 L9 K7 L9
DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_CLK#0 K8 CK_t VDD R1 DDR_B_CLK#0 K8 CK_t VDD R1
<8> DDR_B_CKE0 CKE VDD CKE VDD DDR_B_CKE0 CK_c VDD DDR_B_CKE0 CK_c VDD
K2 T9 K2 T9
CKE VDD CKE VDD
A1 A1
VDDQ A9 VDDQ A9 A1 A1
VDDQ C1 VDDQ C1 VDDQ A9 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ C1 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ D9 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F2 VDDQ F2
DDR_B_ODT0 K3 VDDQ G1 DDR_B_ODT0 K3 VDDQ G1 VDDQ F8 VDDQ F8
<8> DDR_B_ODT0 DDR_B_CS#0 ODT VDDQ DDR_B_CS#0 ODT VDDQ DDR_B_ODT0 VDDQ DDR_B_ODT0 VDDQ
<8> DDR_B_CS#0 L7 G9 L7 G9 K3 G1 K3 G1
DDR_B_MA16 L8 CS VDDQ J2 DDR_B_MA16 L8 CS VDDQ J2 DDR_B_CS#0 L7 ODT VDDQ G9 DDR_B_CS#0 L7 ODT VDDQ G9
DDR_B_MA15 M8 A16/RAS VDDQ J8 DDR_B_MA15 M8 A16/RAS VDDQ J8 DDR_B_MA16 L8 CS VDDQ J2 DDR_B_MA16 L8 CS VDDQ J2
A15/CAS VDDQ A15/CAS VDDQ DDR_B_MA15 M8 A16/RAS VDDQ J8 DDR_B_MA15 M8 A16/RAS VDDQ J8
B2 RD206 B2 RD207 A15/CAS VDDQ A15/CAS VDDQ
VSS 10mils VSS 10mils
E1 240_0402_1% E1 240_0402_1% B2 10mils RD208 B2 10mils
VSS E9 VSS_E9_U2 1 DDP@ 2 VSS E9 VSS_E9_U3 1 DDP@ 2 VSS E1 240_0402_1% VSS E1
VSS G8 VSS G8 VSS E9 VSS_E9_U4 1 DDP@ 2 VSS E9 VSS_E9_U5
DDR_B_DQS#0 A7 VSS K1 RD79 DDR_B_DQS#2 A7 VSS K1 VSS G8 VSS G8
DDR_B_DQS0 DQSU_c VSS 10mils DDR_B_DQS2 DQSU_c VSS 10mils DDR_B_DQS#4 VSS DDR_B_DQS#6 VSS
B7 K9 0_0402_5% B7 K9 A7 K1 10mils A7 K1 DDP@
DDR_B_DQS#1 F3 DQSU_t VSS M9 DDR_B_BG1_R 1 SDP@ 2 DDR_B_DQS#3 F3 DQSU_t VSS M9 DDR_B_BG1_R DDR_B_DQS4 B7 DQSU_c VSS K9 DDR_B_DQS6 B7 DQSU_c VSS K9
DQSL_c VSS DQSL_c VSS DQSU_t VSS DQSU_t VSS

1
DDR_B_DQS1 DDR_B_DQS3 DDR_B_DQS#5 DDR_B_BG1_R DDR_B_DQS#7

240_0402_1%
RD209
G3 N1 G3 N1 F3 M9 F3 M9
DQSL_t VSS T1 RD78 DQSL_t VSS T1 DDR_B_DQS5 G3 DQSL_c VSS N1 DDR_B_DQS7 G3 DQSL_c VSS N1

DDR_B_BG1_R
MEMRST# P1 VSS 0_0201_1% MEMRST# P1 VSS DQSL_t VSS T1 DQSL_t VSS T1
RESET 1 DDP@ 2 DDR_B_BG1 RESET MEMRST# P1 VSS MEMRST# P1 VSS
1 MEM@ 2 RD210 F9 1 MEM@ 2 RD211 F9 RESET RESET

2
240_0402_1% ZQ 240_0402_1% ZQ 1 MEM@ 2 RD212 F9 1 MEM@ 2 RD213 F9
DDR_A_BG1(RD78, Intel:549352) ZQ ZQ
C 1. Near SOC side 240_0402_1% 240_0402_1% C
DDR_B_ACT# L3 A2 DDR_B_ACT# L3 A2
<8> DDR_B_ACT# DDR_B_BG0 ACT VSSQ 2. BO1+BO2+M small then other
DDR_B_BG0 ACT VSSQ DDR_B_ACT# DDR_B_ACT#
10mils
<8> DDR_B_BG0 M2 A8 CMD 25mils M2 A8 L3 A2 L3 A2
N9 BG0 VSSQ C9 N9 BG0 VSSQ C9 DDR_B_BG0 M2 ACT VSSQ A8 DDR_B_BG0 M2 ACT VSSQ A8
DDR_B_ALERT# TEN VSSQ 3. BO1+BO2 small then 800mils DDR_B_ALERT# TEN VSSQ BG0 VSSQ BG0 VSSQ
<8> DDR_B_ALERT# P9 D2 P9 D2 N9 C9 N9 C9
DDR_B_PAR T3 ALERT VSSQ D8 DDR_B_PAR T3 ALERT VSSQ D8 DDR_B_ALERT# P9 TEN VSSQ D2 DDR_B_ALERT# P9 TEN VSSQ D2
<8> DDR_B_PAR PAR VSSQ PAR VSSQ DDR_B_PAR ALERT VSSQ DDR_B_PAR ALERT VSSQ
E3 E3 T3 D8 T3 D8
T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3 PAR VSSQ E3
B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ NC VSSQ
R9 H1 R9 H1 +2.5V B1 F1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1 R9 VPP VSSQ H1
96-BALL VSSQ 96-BALL VSSQ VPP VSSQ H9 VPP VSSQ H9
SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ 96-BALL VSSQ
SDRAM DDR4 SDRAM DDR4
K4AAG165WA-BCTD_FBGA96 K4AAG165WA-BCTD_FBGA96
@ @ K4AAG165WA-BCTD_FBGA96 K4AAG165WA-BCTD_FBGA96
@ @

https://vinafix.com
TERMINATION
+1.2V_VDDQ

+0.6VS_VTT
DDR_B_CLK0 RD214 1 MEM@ 2 36_0201_1% 1 2
<8> DDR_B_MA[0..16] DDR_B_CLK#0 RD215 1 MEM@ 2 36_0201_1%
CD50 DDR_B_MA14 RD218 1 MEM@ 2 36_0201_1%
<8> DDR_B_DQS#[0..7] DDR_B_CS#0
0.01U_0402_16V7K RD217 1 MEM@ 2 36_0201_1%
DDR_B_CLK0 DDR_B_MA15 RD220 1 MEM@ 2 36_0201_1%
<8> DDR_B_DQS[0..7] 1 MEM@
DDR_B_MA12 RD219 1 MEM@ 2 36_0201_1%
CD51
<8> DDR_B_D[0..63] DDR_B_CLK#0 3.3P_0402_50V8W
2@
VDDQ <8> DDR_B_BG1 DDR4 mapping SDP DDP +1.2V_VDDQ DDR_B_MA13 RD222 1 MEM@ 2 36_0201_1%
1uF*16 DDR_B_MA8 RD221 1 MEM@ 2 36_0201_1%
10uF*5 E9 VSS UZQ +0.6V_B_VREFCA CD51 close to CPU DDR_B_PAR RD223 1 MEM@ 2 36_0201_1%
DDR_B_MA11 RD224 1 MEM@ 2 36_0201_1%
M9 VSS BG1

2
+0.6VS_VTT
4 as near each on board RAM device as possible Follow MA51 RD195
+1.2V_VDDQ T7 NC VSS
1.8K_0402_1%
+DDR_VREF_CA DDR_B_BG1_R DDR_B_MA1
CD232

CD233

CD228
CD235

CD217

CD225

CD229
CD236

CD218

CD227
CD210

CD211

CD215

CD216

CD226
CD231

CD213

CD214
CD230

CD234

CD212

RD11 RD86 1 DDP@ 2 36_0201_1% RD225 1 MEM@ 2 36_0201_1%

RCOMP[0] 2.7_0402_1%
MEM@ DDR_B_MA5 RD226 1 MEM@ 2 36_0201_1%
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (SOC side) 200_1% 121_1%

1
2 MEM@ 1 DDR_B_MA7 RD228 1 MEM@ 2 36_0201_1%
B B
+ CD237 +1.2V_VDDQ DDR_B_MA9 RD227 1 MEM@ 2 36_0201_1%
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

330U_D2_2V_Y
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @
2 SGA00009S00 SDP@ SDP@
1
DDR_B_ALERT# RD41 2 1 49.9_0402_1%
330U 2V H1.9 RD206 RD208 CD24 DDR_B_BG0 RD229 1 MEM@ 2 36_0201_1%
9mohm POLY 0_0402_5% 0_0402_5% 0.022U_0402_16V7K
2
MEM@ INTEL suggest 50ohm 1% DDR_B_MA10 RD230 1 MEM@ 2 36_0201_1%
SD028000080 SD028000080 MEM@ DDR_B_MA3 RD232 1 MEM@ 2 36_0201_1%
DDR_B_BA1 RD231 1 MEM@ 2 36_0201_1%

2
1
SDP@ SDP@
RD207 RD209 RD13 RD200
0_0402_5% 0_0402_5% 24.9_0402_1% 1.8K_0402_1%
SD028000080 SD028000080 MEM@ DDR_B_CKE0 RD234 1 MEM@ 2 36_0201_1%
MEM@ DDR_B_MA16 RD233 1 MEM@ 2 36_0201_1%

1
2

+1.2V_VDDQ DDR_B_ODT0 RD235 1 MEM@ 2 36_0201_1%

DDR_B_ACT# RD236 1 MEM@ 2 36_0201_1%

DDR_B_MA2 RD216 1 MEM@

CD266
CD263
CD264

CD267

2 36_0201_1%
1 1 1 1
DDR_B_MA4 RD238 1 MEM@ 2 36_0201_1%
DDR_B_BA0
10U_0402_6.3V6M

1U_0201_6.3V6M
10U_0402_6.3V6M

1U_0201_6.3V6M

DIS change to R-short RD237 1 MEM@ 2 36_0201_1%

2 2 2 2 DDR_B_MA0 RD239 1 MEM@ 2 36_0201_1%
DDR_B_MA6 RD240 1 MEM@ 2 36_0201_1%
DDR_DRAMRST# 1 MEM@ 2 MEMRST#
<8,23> DDR_DRAMRST#
RD202 0_0402_5%
U2 Hynix4GB U3 Hynix4GB U4 Hynix4GB U5 Hynix4GB
1 X76HYN4@ X76HYN4@ X76HYN4@ X76HYN4@
SA0000BMN30 SA0000BMN30 SA0000BMN30 SA0000BMN30
@ CD219 Hynix4G
.1U_0402_16V7K
Add for cap downsize 2 U2 Micron4GB U3 Micron4GB U4 Micron4GB U5 Micron4GB
X76MIC4@ X76MIC4@ X76MIC4@ X76MIC4@
SA0000CMS40 SA0000CMS40 SA0000CMS40 SA0000CMS40
Micron4GB

U2 Samsung4GB U3 Samsung4GB U4 Samsung4GB U5 Samsung4GB

X76SAM4@ X76SAM4@ X76SAM4@ X76SAM4@
SA0000B6F30 SA0000B6F30 SA0000B6F30 SA0000B6F30
Micron4GB

VPP U2 Hynix8GB U3 Hynix8GB U4 Hynix8GB U5 Hynix8GB

VTT X76HYN8@ X76HYN8@ X76HYN8@ X76HYN8@
1uF*8 SA0000BZJ40 SA0000BZJ40 SA0000BZJ40 SA0000BZJ40
10uF*3 1uF*8 Hynix8GB
A A
10uF*2
U2 Hynix8GB U3 Hynix8GB U4 Hynix8GB U5 Hynix8GB
X76MIC8@ X76MIC8@ X76MIC8@ X76MIC8@
+2.5V +0.6VS_VTT
SA0000D3U40 SA0000D3U40 SA0000D3U40 SA0000D3U40
CD238

CD241
CD254

CD255

CD220

CD222
CD256

CD244

CD270
CD245

CD221

CD269
CD243

CD271

Micron8GB
CD246

CD249
CD247

CD250

CD223
CD251

CD253
CD248

CD224

CD273
CD274
CD252

CD272

1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 U2 Hynix8GB U3 Hynix8GB U4 Hynix8GB U5 Hynix8GB
HYN832@ HYN832@ HYN832@ HYN832@
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M
1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

SA0000CZ160 SA0000CZ160 SA0000CZ160 SA0000CZ160

2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M
1U_0201_6.3V6M

1U_0201_6.3V6M

Hynix8GB 3200
2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification
2018/12/27
Compal Secret Data Compal Electronics, Inc.
Issued Date Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 ON BOARD CHIPS
2 as near each on board RAM device as possible AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Add for cap downsize
2 as near each on board RAM device as possible Add for cap downsize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 24 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for DDR2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 25 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for DDR3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 26 of 102
5 4 3 2 1
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S PEG 1/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 27 of 102
A B C D E
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S VRAM 2/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 28 of 102
A B C D E
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S LVDS 3/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 29 of 102
A B C D E
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S POWER & GND 4/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 30 of 102
A B C D E
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S POWER & GND 5/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 31 of 102
A B C D E
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S Lower Rank0 6/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 32 of 102
A B C D E
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17S Lower Rank1 7/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 33 of 102
A B C D E
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for DGPU
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 34 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16P_GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 35 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for N16P_GDDR5_A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 36 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DGPU_DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 37 of 102
5 4 3 2 1
 1 2 3 4 5

+3VS

UV5 +LCDVDD
Place closed to JEDP1
5 1
IN OUT +19VB +INVPWR_B+ +3VS +LCDVDD
Max: 222mA
1 2 1 1 Inrush: 1.5A
CV22 GND
1U_0201_6.3V6M 4 3 W=60mils LV1 W=60mils
EN OC CV1 HCB2012KF-221T30_0805
2 1 1
CV21 2 2 0.1U_0201_10V6K 1 2
SY6288C20AAC_SOT23-5 4.7U_0402_6.3V6M @ 3S@ CV269 CV270

1000P_0402_50V7K
CV268 XEMC@
SM01000EJ00 3000ma 1 1 0.1U_0201_10V6K .1U_0402_16V7K
CV267 2 2
220ohm@100mhz @
DCR 0.04 68P_0402_50V8J
SOC_ENVDD I (Max) : 0.372 A(+3VS_EDP) XEMC@
A <6> SOC_ENVDD A

1
GLITCH@ 2 2
RDS(Typ) : 70 mohm
High active RV337
V drop : 0.026 V
EN_VL:1.1V 100K_0402_5%

2 TD Used 680P
For ICL Gitch
+3VS

Note: Unmount LX1 when panel boost 100K_0402_5% 1 @ 2 RV338 EDP_AUXN_C

100K_0402_5% 1 @ 2 RV339 EDP_AUXP_C
circuit was use. (2S battery cell)

Camera
To eDP Panel
USB20_N8 RV333 1 2 0_0402_5% USB20_N8_CAMERA 1 @ 2 BKOFF#_R
<13> USB20_N8 <58> EC_BKOFF#
From EC RV12
0_0201_5%

1
USB20_P8 USB20_P8_CAMERA

100K_0402_5%
RV334 1 2 0_0402_5%
<13> USB20_P8

RV13
GLITCH@

2
B B
RV16 1 @ 2 BKL_PWM_LCD To eDP Panel
From SoC
<6> SOC_BKL_PWM
0_0201_5%
+INVPWR_B+
eDP Conn.

1
CONN@
RV17 W=60mils
100K_0201_5% 1
@ 2 1 41
3 2 G1 42

2
4 3 G2 43
5 4 G3 44
BKL_PWM_LCD 6 5 G4 45
BKOFF#_R 7 6 G5 46
+LCDVDD EDP_HPD 8 7 G6
<6> EDP_HPD 8
9

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10 9
W=60mils 11 10
12 11
13 12
CV271 1 2 .1U_0402_16V7K EDP_AUXN_C 14 13
<6> EDP_AUXN
CV272 1 2 .1U_0402_16V7K EDP_AUXP_C 15 14 eDP
<6> EDP_AUXP 15
16
CV273 1 2 .1U_0402_16V7K EDP_TXP0_C 17 16 (4-Lane)
<6> EDP_TXP0 EDP_TXN0_C 17
CV274 1 2 .1U_0402_16V7K 18
USB/I2C Touch Screen Co-Lay <6> EDP_TXN0
19 18
CV275 1 2 .1U_0402_16V7K EDP_TXP1_C 20 19
<6> EDP_TXP1 EDP_TXN1_C 20
CV276 1 2 .1U_0402_16V7K 21
<6> EDP_TXN1 22 21
CV277 1 2 .1U_0402_16V7K EDP_TXP2_C 23 22
<6> EDP_TXP2 EDP_TXN2_C 23
CV278 1 2 .1U_0402_16V7K 24
<6> EDP_TXN2 TS_I2C_INT#_GND 25 24
CV279 1 2 .1U_0402_16V7K EDP_TXP3_C 26 25
<6> EDP_TXP3 EDP_TXN3_C 26
CV280 1 2 .1U_0402_16V7K 27
<6> EDP_TXN3 SOC_TS_RST#_R 28 27
USB20_P9_R 29 28
C USB20_N9_R 30 29 C
31 30
32 31
Touch +TS_PWR 32
Screen 33
+3VS TS_EN 34 33
<58> TS_EN 35 34
+3VS USB20_N8_CAMERA 35
36
100K_0402_5% 1 I2CTS@ 2 TS_I2C_INT#_GND USB20_P8_CAMERA 37 36
For 37
RV319 Camera 38
DMIC_CLK_R 39 38
SOC_TS_RST# 1 I2CTS@ 2 100K_0402_5% <56> DMIC_CLK_R DMIC_DATA_R 40 39
<56> DMIC_DATA_R 40
RV320

JEDP1
STARC_107K40-000001-G2
SP010014B10

DMIC_DATA_R
USB20_P9 RV14 1 2 0_0402_5% USB20_P9_R DMIC_CLK_R
<13> USB20_P9
USBTS@

2
USB20_N9 RV15 1 2 0_0402_5% USB20_N9_R
<13> USB20_N9
USBTS@
3

2
3

I2C_5_SCL RV313 1 2 0_0201_5% DV15 DV1

<12> I2C_5_SCL
I2CTS@ AZC199-02SPR7G_SOT23-3 XEMC@
1

I2C_5_SDA RV314 1 2 0_0201_5% XEMC@ YSLC05CH_SOT23-3

<12> I2C_5_SDA
I2CTS@
1

Reserve I2C Touch

1
D SOC_TS_RST# RV316 1 2 0_0201_5% SOC_TS_RST#_R D
<13> SOC_TS_RST#
I2CTS@

I2C_TS_INT# RV317 1 2 0_0201_5% TS_I2C_INT#_GND

<12> I2C_TS_INT#
I2CTS@
2

RV318 RV315
Reserve for EMC/ESD Suggestion 0_0201_5% 0_0201_5%
USBTS@ USBTS@
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

Reserve for EMC/ESD Suggestion
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / DMIC / IR Camera / Touch
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 38 of 102
1 2 3 4 5
 5 4 3 2 1

+1.2V_HDMI
+5VALW
HDMI_L_CLKN For HDMI DDC Capacitance Leakage issue
CV281 Improve Intra-pair Skew on CLK+/-
1U_0201_6.3V6M

22P_0402_50V8J
LV2

1
2 1 +5VS_DISP EMC@ SM070003V00
1

10U_0402_6.3V6M

10U_0402_6.3V6M
RV341 UV17 HDMI_RT_CLKN 2 1
UV16
W=40mils 2
4.99K_0402_1% DV12 XEMC@

CV282
+3VS 10 1 +5VS 3 CV283 HDMI_RT_HPD 6 3 HDMI_CTRL_CLK
VDD VOUT 2 1 1 OUT I/O4 I/O2
9 2 HDMI_RT_CLKP 3 4

CV286

CV284
@ 3.3P_0402_50V8
@

2
CV285 8 VIN VOUT 3 1 1
VIN VOUT IN 1
10U_0402_6.3V6M 7 4
2 1 6 VIN ADJ/NC 5 2 2 2 CV287 HCM1012GH900BP_4P 5 2
EN PGOOD GND 0.1U_0201_10V6K HDMI_L_CLKP VDD GND
D D

1
11 2
PAD RV343 AP2330W-7_SC59-3
RT9059GQW_WDFN10_3X3 10K_0402_1% 4 1 HDMI_CTRL_DAT
SA00004ZA00 +5VS_DISP I/O3 I/O1
SA000071S00 HDMI_RT_TX_N0 RV344 1 @ 2 0_0402_5% HDMI_L_TX_N0
S IC RT9059GQW WDFN 10P LDO AZC099-04S.R7G_SOT23-6

2
HDMI_RT_TX_P0 RV345 1 @ 2 0_0402_5% HDMI_L_TX_P0
SC300001G00
ZZZ2

HDMI_RT_TX_N1 RV346 1 @ 2 0_0402_5% HDMI_L_TX_N1

HDMI_RT_TX_P1 HDMI_L_TX_P1 DV13

RV347 1 @ 2 0_0402_5%
HDMI_L_CLKP 1 1 10 9 HDMI_L_CLKP
HDMI_ROYALTY
ROYALTY HDMI W/LOGO+HDCP HDMI_L_CLKN 2 2 9 8 HDMI_L_CLKN
RO0000003HM
45@ HDMI_RT_TX_N2 RV348 1 @ 2 0_0402_5% HDMI_L_TX_N2 HDMI_L_TX_P0 4 4 7 7 HDMI_L_TX_P0

+3VS HDMI_RT_TX_P2 RV349 1 @ 2 0_0402_5% HDMI_L_TX_P2 HDMI_L_TX_N0 5 5 6 6 HDMI_L_TX_N0

3 3
+1.2V_HDMI

0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 1 1 8

CV290
AZ1045-04F_DFN2510P10E-10-9

CV289
CV288
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

2 2 2 XEMC@
1 1 1 1 1 1 SC300001Y00
UV18 DV14
CV291

CV292

CV293

CV294

CV295

CV296

6 1 HDMI_L_TX_N1 1 1 10 9 HDMI_L_TX_N1
2 2 2 2 2 2 30 VDD12 VDD33 24
11 VDD12 VDD33 HDMI_L_TX_P1 2 2 HDMI_L_TX_P1
VDDA12 9 8
43
46 VDDRX12 23 HDMI_RT_TX_P2 HDMI_L_TX_N2 4 4 HDMI_L_TX_N2
VDDRX12 OUT_D2p 7 7
15 22 HDMI_RT_TX_N2
C 18 VDDTX12 OUT_D2n HDMI_L_TX_P2 5 5 HDMI_L_TX_P2 C
VDDTX12 6 6
37 20 HDMI_RT_TX_P1
POWERSWITCH OUT_D1p 19 HDMI_RT_TX_N1 3 3
0.1U_0201_10V6K 2 1 CV297 SOC_DP2_P0_C 38 OUT_D1n
<6> SOC_DP2_P0 SOC_DP2_N0_C IN_D2p HDMI_RT_TX_P0
0.1U_0201_10V6K 2 1 CV298 39 17 8
<6> SOC_DP2_N0 IN_D2n OUT_D0p 16 HDMI_RT_TX_N0
0.1U_0201_10V6K 2 1 CV299 SOC_DP2_P1_C 41 OUT_D0n
<6> SOC_DP2_P1 2 1 CV300 SOC_DP2_N1_C 42 IN_D1p 14 HDMI_RT_CLKP AZ1045-04F_DFN2510P10E-10-9
0.1U_0201_10V6K
<6> SOC_DP2_N1 IN_D1n OUT_CLKp 13 HDMI_RT_CLKN XEMC@ SC300001Y00
0.1U_0201_10V6K 2 1 CV301 SOC_DP2_P2_C 44 OUT_CLKn PH in SOC Side
<6> SOC_DP2_P2 2 1 CV302 SOC_DP2_N2_C 45 IN_D0p 33 SOC_DP2_CTRL_DATA
0.1U_0201_10V6K
<6> SOC_DP2_N2 IN_D0n SDA_SRC/AUXN 34 SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA <6>
2 1 CV303 SOC_DP2_P3_C 47 SCL_SRC/AUXP 8 HDMI_CTRL_DAT SOC_DP2_CTRL_CLK <6>
0.1U_0201_10V6K
<6> SOC_DP2_P3 2 1 CV304 SOC_DP2_N3_C 48 IN_CLKp SDA_SNK 7 HDMI_CTRL_CLK
0.1U_0201_10V6K
<6> SOC_DP2_N3 IN_CLKn SCL_SNK DVT modify

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HDMI_DCIN_EN 3 40 SOC_DP2_HPD_R 1 @ 2
HDMI_EQ 5 DCIN_ENB HPD_SRC 21 HDMI_RT_HPD SOC_DP2_HPD <6>
+3VS HDMI_I2C_ADDR 31 EQ HPD_SNK RV350 0_0402_5%
I2C_ADDR
10
RSV1
2

25 32 HDMI_ID
RV351 26 NC HDMI_ID 9
RSV2 HDMI_CEC 12
10K_0402_5% Placed close to REXT pin. CEC_EN
RV352 1 2 4.99K_0402_1% 36 29 TP@ T509
1

RESET# 4 REXT CSCL 28 TP@

PDB CSDA T510
RESET# 35
Enhance Vswing HDMI_PRE 27 RESETB
1 PRE
CV305 2 49
1U_0201_6.3V6M TESTMODEB EPAD

2
PS8409AQFN48GTR2-A0_QFN48_6X6
SA0000AC330
HDMI connector
B S IC PS8409AQFN48GTR2-A2-M2 QFN 48P REPEATER JHDMI1 B
HDMI_RT_HPD 19
18 HP_DET
+5VS_DISP +5V
17
HDMI_DCIN_EN HDMI_CTRL_DAT 16 DDC/CEC_GND
HDMI_CTRL_CLK 15 SDA
DC coupling enable; Internal pull up, 3.3V I/O. SCL
1

14
@ L: DC coupling input 13 Utility
RV353 H: Default,AC coupling input HDMI_L_CLKN 12 CEC
4.7K_0402_5% 11 CK-
HDMI_L_CLKP 10 CK_shield
2

+5VS_DISP HDMI_L_TX_N0 9 CK+

8 D0-
HDMI_L_TX_P0 7 D0_shield
HDMI_L_TX_N1 6 D0+
5 D1-
HDMI_L_TX_P1 4 D1_shield 23
+3VS HDMI_L_TX_N2 3 D1+ GND1 22
2 D2- GND2 21
D2_shield GND3

1
HDMI_L_TX_P2 1 20
D2+ GND4
1

RV355 RV356
@ HDMI_PRE 2K_0402_5% 2K_0402_5% ACON_HMRBL-AK120D
RV354 DC232007600
1

4.7K_0402_5% Receiver equalization setting(Internal 150K PD) Output pre-emphasis setting;Internal pull-up 3.3V I/O CONN@

2
(*) L: programmable EQ for channel loss up to 5.3dB L: Pre-emphasis =2.5dB
2

HDMI_EQ @ RV357 HDMI_CTRL_DAT

( ) H: programmable EQ for channel loss up to 10dB 4.7K_0402_5% H: Default, No Pre-emphasis Footprint from Freed_RRS
1

( ) M: programmable EQ for channel loss up to 14dB

2

@ HDMI_CTRL_CLK
RV358
4.7K_0402_5%
2

A A

+3VS
+3VS
1
1

I2C Slave Address selection; Internal pull down;3.3V I/O @ HDMI_ID enable ; Internal pull down;3.3V I/O
@ RV360
RV359 L: Default, Slave address 0x10-0x2F. 4.7K_0402_5% L: Default, HDMI ID enable
4.7K_0402_5% H: Alternative salve address 0x90-0x9F, 0xD0-0xDF. H: HDMI ID disable Security Classification Compal Secret Data Compal Electronics, Inc.
2

HDMI_ID
2

HDMI_I2C_ADDR 2019/09/20 2020/12/31 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI REDRIVER (PS8409)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, August 12, 2020 Sheet 39 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CloverFalls Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 40 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 41 of 102
5 4 3 2 1
 1 2 3 4 5

+5VALW +5VALW_MUX

UT5
5 1
IN OUT

10U_0402_6.3V6M

0.1U_0201_10V6K
2 1 1
RT248 GND

CT210

CT211
1 2 4 3
<58> EC_TYPEC_EN EN OC
SY6288C20AAC_SOT23-5 2 2
0_0201_5%
@
Close to Pin19
A A
DVT modify,
remove CPU path

UT2
DVT modify

VMON 17 12 CC1_VCONN CC1_VCONN CT511 1 2 220P_0402_50V8J

VMON CC1 CC1_VCONN <43>
14 CC2_VCONN CC2_VCONN CT512 1 2 220P_0402_50V8J
CC2 CC2_VCONN <43>
OCP_DET# 16
+5VALW_MUX +USB3_VCCC <43> OCP_DET# OCP_DET
To VBUS PWR EN USBC_EN 15
B VBUS_EN B
<43> USBC_EN Type-C Port Side DVT modify
11 USBC0_CC_TX_P2 CT44 1 2 0.1U_0201_10V6K USBC0_CC_TX_P2_C
C_TX2_1P/2N USBC0_CC_TX_P2_C <43>
1

DVT modify System side 10 USBC0_CC_TX_N2 CT45 1 2 0.1U_0201_10V6K USBC0_CC_TX_N2_C

C_TX2_1N/2P USBC0_CC_TX_N2_C <43>
RT154
RT152 200K_0402_1% USB3_CRX_DTX_P1 CT40 1 2 0.22U_0402_10V6K USB3_CRX_C_DTX_P1 4
4.7K_0402_5% <13> USB3_CRX_DTX_P1 USB3_CRX_DTX_N1 CT41 1 2 0.22U_0402_10V6K USB3_CRX_C_DTX_N1 5 SSRX_1P/2N 24 USBC0_CC_RX_P2 CT46 1 2 0.33U_0201_6.3V6M USBC0_CC_RX_P2_C
<13> USB3_CRX_DTX_N1 SSRX_1N/2P C_RX2_1P/2N USBC0_CC_RX_P2_C <43>
1 USBC0_CC_RX_N2 CT47 1 2 0.33U_0201_6.3V6M USBC0_CC_RX_N2_C USBC0_CC_RX_N2_C <43>
2

OCP_DET# VMON C_RX2_1N/2P

DVT modify
1

USB3_CTX_DRX_P1 CT42 1 2 0.22U_0402_10V6K USB3_CTX_C_DRX_P1 6 10 Gbps 2:1 MUX 8 USBC0_CC_TX_P1 CT48 1 2 0.1U_0201_10V6K USBC0_CC_TX_P1_C
<13> USB3_CTX_DRX_P1 USB3_CTX_DRX_N1 CT43 USB3_CTX_C_DRX_N1 SSTX_1P/2N C_TX1_1P/2N USBC0_CC_TX_N1 CT49 1 USBC0_CC_TX_N1_C USBC0_CC_TX_P1_C <43>
RT153 RT155 1 2 0.22U_0402_10V6K 7 9 2 0.1U_0201_10V6K
<13> USB3_CTX_DRX_N1 SSTX_1N/2P C_TX1_1N/2P USBC0_CC_TX_N1_C <43>
10K_0402_1% 10K_0402_1%

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2 USBC0_CC_RX_P1 CT50 1 2 0.33U_0201_6.3V6M USBC0_CC_RX_P1_C USBC0_CC_RX_P1_C <43>
2

C_RX1_1P/2N 3 USBC0_CC_RX_N1 CT51 1 2 0.33U_0201_6.3V6M USBC0_CC_RX_N1_C

C_RX1_1N/2P USBC0_CC_RX_N1_C <43>
PLUG_ORI 23
M1 21 GPIO
M0 22 CURRENT_M1
CURRENT_M0
+3VO_MUX +3VO_MUX USBC0_CC_RX_P2_C
USBC0_CC_RX_N2_C

VCON_IN
LDO_3V3
18
REXT
1

2
5V_IN
1
1

RT163 25 RT164 RT165 220K_0201_1%

RT156 @ 6.2K_0402_1% E-PAD 220K_0201_1%
10K_0402_5% RT158 RT160 RTS5441E-GRT_QFN24_4X4

20

19

13
10K_0402_5% 10K_0402_5%
2

1
DVT modify
2
2

RT162 0_0402_5% +3VO_MUX +5VALW_MUX

M0 1 @ 2
PLUG_ORI TYPEC_1P5A <43,58> USBC0_CC_RX_P1_C
M1 USBC0_CC_RX_N1_C
1 1
C CT52 CT53 C
4.7U_0402_6.3V6M 0.1U_0201_10V6K
1

2
CHECK??? need starp or contral from PCH?
1

2 2 RT166 RT167
RT159 @ RT161 @ 1209 Close to Pin13 220K_0201_1% 220K_0201_1%
RT157 10K_0402_5% 10K_0402_5%
10K_0402_5%
2

1
2

5441E Current Limit RTS5441 M0 truth table by 2018 BIOS spec

M1 M0 MODE TYPEC_1P5A_EC MODE limit point Condition
L H 0.9A H 3A 3.5A AC mode or Battery >30%
H L 1.5A L 1.5A 1.92A Battery <30% when DC mode
H H 3A

confirm realtek hand-shake

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 42 of 102
1 2 3 4 5
 1 2 3 4 5

+5VALW +USB3_VCCC RSET SILERGY SY6861B1 MOS Current Limit

1
TYPEC_1P5A TYPEC_3A RSET(kΩ) MODE limit point

SGA00003700
150U_D2_6.3VY_R15M
CT70
1 RT172 RT173 RT174

0.1U_0201_10V6K

0.1U_0402_25V6

22U_0805_25V6M

22U_0805_25V6M
1 1 1 1 6.2K_0402_5% 4.3K_0402_5% 8.2K_0402_5% L L 6.2 0.9A 1.09A

CT71

CT72 @

CT73 @

CT74 @
+
L H 3.53 1.5A 1.92A

3 2
2N7002KDW _SOT363-6
2 2 2 2 2 D QV9B H L 2.54 2A 2.67A
5 TYPEC_3A <58>
UT6 G
*H H 1.94 3A 3.5A
A 6 1 A
IN OUT S

4
6
RSET 5 2 D
SET GND 1 @ 2 2
OCP_DET# <42> TYPEC_1P5A <42,58>
RT171 0_0402_5% G
4 3 From PCH, check BIOS for GPIO 1209
<42> USBC_EN EN FLAG S QV9A

1
1

SY6861B1ABC_TSOT23-6 1 2N7002KDW _SOT363-6

RT170
47K_0402_5% footprint : G518 CT75
0.1U_0201_10V6K
PN : SA0000BDN00(SILERGY SY6861B1) 2 @
2

DT1
DT4 EMC@
USBC0_CC_TX_P1_C 1 1 10 9 USBC0_CC_TX_P1_C CC2_VCONN 1 1 10 9 CC2_VCONN
<42> USBC0_CC_TX_P1_C
USBC0_CC_TX_N1_C 2 2 9 8 USBC0_CC_TX_N1_C 2 2 9 8
<42> USBC0_CC_TX_N1_C
USB20_P1_L 4 4 7 7 USB20_P1_L USBC0_CC_TX_N2_C 4 4 7 7 USBC0_CC_TX_N2_C
<42> USBC0_CC_TX_N2_C
USB20_N1_L 5 5 6 6 USB20_N1_L USBC0_CC_TX_P2_C 5 5 6 6 USBC0_CC_TX_P2_C
B
<42> USBC0_CC_TX_P2_C B
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
EMC@ SC300001Y00
SC300001Y00
DT3 EMC@
DT2 CC1_VCONN CC1_VCONN
1 1 10 9
TBTA_SBU2 1 1 10 9 TBTA_SBU2

https://vinafix.com
TBTA_SBU1 2 2 9 8 TBTA_SBU1
2 2 9 8
USBC0_CC_RX_N2_C 4 4 7 7 USBC0_CC_RX_N2_C
USBC0_CC_RX_N1_C USBC0_CC_RX_N1_C <42> USBC0_CC_RX_N2_C
4 4 7 7
<42> USBC0_CC_RX_N1_C USBC0_CC_RX_P2_C USBC0_CC_RX_P2_C
5 5 6 6
USBC0_CC_RX_P1_C USBC0_CC_RX_P1_C <42> USBC0_CC_RX_P2_C
5 5 6 6
<42> USBC0_CC_RX_P1_C
3 3
3 3
8 +USB3_VCCC +USB3_VCCC
8
AZ1045-04F_DFN2510P10E-10-9
AZ1045-04F_DFN2510P10E-10-9
EMC@
SC300001Y00 JTYPEC1
SC300001Y00 A1 B1
GND GND
USBC0_CC_TX_P1_C A2 B2 USBC0_CC_TX_P2_C
C USBC0_CC_TX_N1_C A3 SSTXP1 SSTXP2 B3 USBC0_CC_TX_N2_C C
0.1U_0402_25V6 2 1 CT510 SSTXN1 SSTXN2
A4 B4 CT82 1 2 0.1U_0402_25V6
VBUS VBUS
1
CT90 <42> CC1_VCONN A5 B5 CC2_VCONN <42>
10U_0603_25V6M CC1 CC2
USB20_P1_L A6 B6 USB20_P1_L
2 USB20_N1_L A7 DP1 DP2 B7 USB20_N1_L
LT1 EMC@ 3 DN1 DN2

2
2 1 USB20_P1_L TBTA_SBU1 A8 B8 TBTA_SBU2
<13> USB20_P1 2 1 SBU1 SBU2
0.1U_0402_25V6
2 1 CT81 A9 B9 CT83 1 2 0.1U_0402_25V6
3 4 USB20_N1_L DT5 EMC@ VBUS VBUS
<13> USB20_N1 3 4 USBC0_CC_RX_N2_C USBC0_CC_RX_N1_C
PESD24VS2UT_SOT23-3 A10 B10
DLM0NSN900HY2D_4P SCA00004500 USBC0_CC_RX_P2_C A11 SSRXN2 SSRXN1 B11 USBC0_CC_RX_P1_C
1

SSRXP2 SSRXP1
SM070005U00 A12 B12
GND GND
1 6
2 GND GND 7
3 GND GND 8
4 GND GND 9
5 GND GND 10
GND GND
LOTES_AUSB0164-P005A
CONN@
DC23300LZ00
D D

CC1_VCONN & CC2_VCONN need 20miil trace width.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port0 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 43 of 102
1 2 3 4 5
 1 2 3 4 5

A A

B B

https://vinafix.com

C C

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port1 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 44 of 102
1 2 3 4 5
 1 2 3 4 5

A A

B B

https://vinafix.com

C C

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port1 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 45 of 102
1 2 3 4 5
 1 2 3 4 5

A A

B B

https://vinafix.com

C C

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port2 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 46 of 102
1 2 3 4 5
 1 2 3 4 5

A A

B B

https://vinafix.com

C C

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port2 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 47 of 102
1 2 3 4 5
 1 2 3 4 5

A A

B B

https://vinafix.com

C C

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TBT_TYPE-C_Port3 (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 48 of 102
1 2 3 4 5
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for TBT_TYPE-C_Port3 (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 49 of 102
5 4 3 2 1
 1 2 3 4 5

A A

B B

https://vinafix.com

C C

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C_Power Path
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 50 of 102
1 2 3 4 5
 A B C D E

LAN-RTL8111H W=60mil
IDC=1200mA
W=60mil
300mA
+LAN_VDD +3V_LAN
W=60mil
1.4A
+REGOUT RL10 1 @ 2 0_0603_5%
PVT modify
+3VALW +3V_LAN
RL1 1 1 1 1 1 1 1 1 1 1 1 1 1

0.1U_0201_10V6K
CL7

0.1U_0201_10V6K
CL25

0.1U_0201_10V6K
CL23

0.1U_0201_10V6K
CL3

0.1U_0201_10V6K
CL8

0.1U_0201_10V6K
CL9

1U_0201_6.3V6M
CL4

1U_0201_6.3V6M
CL24

4.7U_0402_6.3V6M
CL10

4.7U_0402_6.3V6M
C11

1U_0201_6.3V6M
CL12

0.1U_0201_10V6K
CL13

0.1U_0201_10V6K
CL14
60mil 0_0805_5%
1 2
UL2 60mil
5 1 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1

@
IN OUT
2
GND
4 3

@
EN OC
Place near Pin 3,8,22,30 Place near Pin 22 For surge improvement Place near Pin 11,32
2 2 SY6288C20AAC_SOT23-5
@ Place near Pin 11,32 For downsize CL12 change to 1uF
CL22 CL5 Add 1 cap for downsize reserved
1U_0201_6.3V6M 1U_0201_6.3V6M LAN_PW R_EN
1 1 LAN_PW R_EN <58>

UL3
From EC
High active.
EN threshold voltage min:1.2V typ:1.6V max:2.0V reserve EC_PME# pull high 100K to +3VALW_EC
Current limit threshold 1.5~2.8A
LAN_MIDI0+ PCIE_CRX_C_DTX_P9
PCIe X1
1 17 CL1 1 2 0.1U_0201_10V6K PCIE_CRX_DTX_P9 <13>
LAN_MIDI0- 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N9 CL2 1 2 0.1U_0201_10V6K (link to PICe Port 9)
MDIN0 HSON PCIE_CRX_DTX_N9 <13>
+LAN_VDD 3 19 PLT_RST_R#
AVDD10 PERSTB PLT_RST_R# <11,52,66,68>
LAN_MIDI1+ 4 20 ISOLATEB
LAN_MIDI1- 5 MDIP1 ISOLATEB 21 EC_PME#
MDIN1 LANWAKEB EC_PME# <58>
LAN_MIDI2+ 6 22 +LAN_VDD
LAN_MIDI2- 7 MDIP2 DVDD10 23 +3V_LAN RL36 1 2 10K_0402_5%
MDIN2 VDDREG +3V_LAN
2 +LAN_VDD 8 24 +REGOUT 2
LAN_MIDI3+ 9 AVDD10 REGOUT 25 DVT modify
LAN_MIDI3- 10 MDIP3 LED2 26 GPO
MDIN3 LED1/GPIO @ T532
+3V_LAN 11 27
CLKREQ_PCIE#2 12 AVDD33 LED0 28 XTLI PVT modify
<11> CLKREQ_PCIE#2 PCIE_CTX_C_DRX_P9 CLKREQB CKXTAL1 XTLO_R
PCIe X1 <13> PCIE_CTX_DRX_P9 0.1U_0201_10V6K 1 2 CL20 13 29 2 1 XTLO
0.1U_0201_10V6K 1 2 CL21 PCIE_CTX_C_DRX_N9 14 HSIP CKXTAL2 30 +LAN_VDD RM25 680_0402_5%
<13> PCIE_CTX_DRX_N9 HSIN AVDD10
15 31 LAN_RST 1 2
<11> CLK_PCIE_P2 REFCLK_P RSET +3V_LAN 2.49K_0402_1% +3V_LAN
PU at PCH side PCIe CLK 16 32 RL6
<11> CLK_PCIE_N2 REFCLK_N AVDD33 +3VS
33
GND
LAN Connector

1
1
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RL4 RL8
10K_0402_5% 1K_0402_5%
JRJ45 @

2
2
RTL8111H-CG_QFN32_4X4 12 GPO ISOLATEB
RJ45_MIDI3- 8 GND
SA000080P00 PR4-

2
11
RJ45_MIDI3+ 7 GND RL9
PR4+
15K_0402_1%
RJ45_MIDI1- 6
PR2-

1
RJ45_MIDI2- 5
PR3-
RJ45_MIDI2+ 4
PR3+
RJ45_MIDI1+ 3
PR2+
3 RJ45_MIDI0- 2 YL1 3
PR1- 10 25MHZ_20PF_7R25000001
RJ45_MIDI0+ 1 GND
PR1+ 9 XTLI 1 3 XTLO
GND 1 3
NC NC
1 1
TR1 SINGA_2RJ1660-000111F
CONN@ CL26 2 4 CL27
LAN_TERMAL 1 24 MCT1 27P_0402_50V8J 27P_0402_50V8J
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+
LTCX008KA00 2 2
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- DVT modify
TD1- MX1- 40mil SJ10000TO00
4 21 MCT2 RJ45_GND 1 2 LANGND
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ C1
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- 10P_0201_50V8J 12/21 change YL1 size to 20x16
TD2- MX2- 40mil
7 18 MCT3 LANGND
TCT3 MCT3

1
LAN_MIDI2+ 8 17 RJ45_MIDI2+
LAN_MIDI2- 9 TD3+
TD3-
MX3+
MX3-
16 RJ45_MIDI2- @ ESD
DVT modify
J1 JP2
10 15 MCT4 JUMP_43X118 XEMC@ PLT_RST_R#
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ B88069X9231T203_4P5X3P2-2
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3- 1

2
TD4- MX4- D1 XEMC@
RL35
RL34
RL33
RL32

EMC@ CL28
AZ5125-02S.R7G_SOT23-3 100P_0201_50V8J

1
GST5009-E 2
1
2
2
2
2

SP050006800
4
C2 4
.1U_0402_16V7K
2
Place close to TCT pin
1
1
1
1
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D
75_0402_1%~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

RJ45_GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-RTL8111H
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 22, 2020 Sheet 51 of 102
A B C D E
 A B C D E

NGFF Wireless LAN / BT (Key E) [PCIE+USB/CNVi]

www.teknisi-indonesia.com
1 1

+3VALW +3VS_WLAN
CNVi use ALW power rail / PCIE WLAN use VS rail
autodetct and change EN pin power domain by BIOS

UM1 W=60mils
5 1 +3VS_WLAN
IN OUT
1 2 1 1 RM6 INTEL RF Linda suggest reserve for CNVi
CM19 GND CM1 CM3 2 1 200K_0402_1%WLAN_PME#
EC_WLAN_ON
@

4 3
<58> EC_WLAN_ON EN OC
1U_0201_6.3V6M 4.7U_0402_6.3V6M 0.1U_0201_10V6K
2 SY6288C20AAC_SOT23-5 2 2

UART_2_CRXD_R_DTXD RM45 1 UART@ 2 0_0402_5%

UART_2_CTXD_R_DRXD RM46 1 UART@ 2 0_0402_5% UART_2_CRXD_DTXD <12>
UART_2_CTXD_DRXD <12>

Co-layout with CNVi for UART Debug and BT signal

RM56
2 1CLKREQ_CNV#_R
10K_0402_5%
KEY E +3VS_WLAN

JNGFF1
1 2
GND_1 3.3VAUX_2 @ T52
USB2 P10 3 4 CNVI@
<13> USB20_P10 USB_D+ 3.3VAUX_4
5 6 1 RM41 2
2 (For Bluetooth) <13> USB20_N10 USB_D- LED1# 2
7 8 75K_0402_5% 1.8V
CNV_CRX_DTX_N1 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RW9 1 CNVi@ 2 33_0201_5%
<14> CNV_CRX_DTX_N1 CNV_CRX_DTX_P1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <14>
11 12
<14> CNV_CRX_DTX_P1 SDIO_CMD PCM_OUT CLKREQ_CNV#_R
13 14 RW35 1 CNVi@ 2 33_0201_5% CLKREQ_CNV# <10>
CNV_CRX_DTX_N0 15 SDIO_DAT0 PCM_IN 16
<14> CNV_CRX_DTX_N0 CNV_CRX_DTX_P0 SDIO_DAT1 LED2# @ T267
CNVi Rx 17 18
<14> CNV_CRX_DTX_P0 SDIO_DAT2 GND_18
19 20 DVT modify
CLK_CNV_CRX_DTX_N 21 SDIO_DAT3 UART_WAKE 22 UART_2_CRXD_R_DTXD RW36 1 CNVi@ 2 49.9_0402_1%
<14> CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P SDIO_WAKE UART_TX CNV_BRI_CRX_DTX <14>
23
<14> CLK_CNV_CRX_DTX_P SDIO_RST UART X
24 UART_2_CTXD_R_DRXD RW17 1 CNVi@ 2 0_0402_5%
PH +3VS at SOC side, for win7 USB3 debug CNV BT X
UART_RX CNV_RGI_CRX_R_DTX CNV_RGI_CTX_DRX <14>
25 26 RW18 1 CNVi@ 2 49.9_0201_1%
PCIE_CTX_C_DRX_P10 GND_33 UART_RTS CNV_BRI_CTX_R_DRX CNV_RGI_CRX_DTX <14>
CW9 1 2 0.1U_0201_10V6K 27 28 RW19 1 CNVi@ 2 0_0201_5% 1.8V
<13> PCIE_CTX_DRX_P10 PCIE_CTX_C_DRX_N10 PET_RX_P0 UART_CTS E51TXD_P80DATA_R CNV_BRI_CTX_DRX <14>
PCIe X1 CW10 1 2 0.1U_0201_10V6K 29 30 RW20 1 @ 2 0_0201_5% E51TXD_P80DATA <58>
<13> PCIE_CTX_DRX_N10 PET_RX_N0 CLink_RST E51RXD_P80CLK_R
31 32 RW21 1 @ 2 0_0201_5%
PCIE_CRX_DTX_P10 GND_39 CLink_DATA E51RXD_P80CLK <58>
(link to PICe Port 10) 33 34
<13> PCIE_CRX_DTX_P10 PCIE_CRX_DTX_N10 PER_TX_P0 CLink_CLK
35 36
<13> PCIE_CRX_DTX_N10 PER_TX_N0 COEX3
37 38

https://vinafix.com
CLK_PCIE_P3 39 GND_45 COEX2 40
PCIe CLK <11> CLK_PCIE_P3 CLK_PCIE_N3 REFCLK_P0 COEX1
41 42 0102 remove WLAN_SUSCLK
<11> CLK_PCIE_N3 REFCLK_N0 SUSCLK(32KHz) WL_RST#_R
(From PCH CLKOUT3) 43 44 RW26 1 @ 2 0_0201_5% PLT_RST_R#
CLKREQ_PCIE#3 GND_51 PERST0# BT_ON PLT_RST_R# <11,51,66,68>
45 46
<11> CLKREQ_PCIE#3 WLAN_PME# CLKREQ0# W_DISABLE2# WL_OFF# BT_ON <10,58>
47 48
<58> WLAN_PME# PEWAKE0# W_DISABLE1# WL_OFF# <58> E51TXD_P80DATA_R
49 50
CNV_CTX_DRX_N1 51 GND_57 I2C_DAT 52
<14>
<14>
CNV_CTX_DRX_N1
CNV_CTX_DRX_P1
CNV_CTX_DRX_P1 53 RSVD/PCIE_RX_P1 I2C_CLK 54 P80CLK and BT_ON enable seperate.
RSVD/PCIE_RX_N1 I2C_IRQ

1
55 56 REFCLK_CNV_R
CNV_CTX_DRX_N0 GND_63 RSVD_64 @ T508
57 58 RM19
<14> CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 RSVD/PCIE_TX_P1 RSVD_66
CNVi Tx 59 60 100K_0402_5%
<14> CNV_CTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62
CLK_CNV_CTX_DRX_N 63 GND_69 RSVD_70 64
<14> CLK_CNV_CTX_DRX_N

2
CLK_CNV_CTX_DRX_P 65 RSVD_71 3.3VAUX_72 66
<14> CLK_CNV_CTX_DRX_P RSVD_73 3.3VAUX_74 +3VS_WLAN
67
GND_75 68
69 GND1 +3VS_WLAN
GND2
CM2/CM4/CM31 close to pin64,66
1 1 1
BELLW_80152-3221 CM4 CM2 CM32 CM32/CM33/CM34 close to pin2,4
CONN@ @ @ 1 1 1
4.7U_0402_6.3V6M CM35 CM33 CM34
SP070013E00 2 2 2 @ @ @
0.1U_0201_10V6K 4.7U_0402_6.3V6M
2 4.7U_0402_6.3V6M 2 2
3 3
0.1U_0201_10V6K 4.7U_0402_6.3V6M

reserve for BT_ON OD pull high (1.0)

BT_ON 1 2
+3VS_WLAN
8.2K_0402_5% RM49

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF WL(KEY E) / WWAN(KRY B)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 52 of 102
A B C D E
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for WIGIG/WIDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 53 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PCIE Device
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 54 of 102
5 4 3 2 1
 5 4 3 2 1

www.teknisi-indonesia.com
D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for PCIE Device
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 55 of 102
5 4 3 2 1
 1 2 3 4 5

Int. Speaker Conn.

HD Audio Codec add 1 cap for MLCC downsize
+PVDD_HDA
SPKR+ LA2 1
SPK_R bead on sub/B
2 0_0603_5%
40mil SPK_R+
SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04 +5VS (output = 300 mA) +VDDA SPKR- LA3 1 2 0_0603_5% SPK_R- SPK_R+ <72>
40mil 40mil JPA1 40mil SPK_R- <72>
LA1 2 1 1 2 Add resistor for R/L channel balance
+VDDA 1 2 DVT modify JSPK1
HCB2012KF-221T30_0805 1 1 1

1
10_0603_5%2SPKL+_R LA4 SPK_L+

0.1U_0201_10V6K
CA2

0.1U_0201_10V6K
CA3

.1U_0402_16V7K
CA4
JUMP_43X79 4.75V SPKL+
RA3 EMC@1 2 PBY160808T-121Y-N_2P 1

10U_0402_6.3V6M

10U_0402_6.3V6M
10_0603_5%2SPKL-_R LA5 EMC@1 2 PBY160808T-121Y-N_2P SPK_L- 2 1

CA1
SPKL-

CA34
@ RA4
2 3

2
2 2 @ +AVDD1_HDA 2 G1 4
EMI request for solve EMI noise, SM01000OW00. G2
XEMC@
GND & GNDA moat

3
GND GND CVILU_CI4202M2HR0-NH
GND CONN@ GND
A
XEMC@ XEMC@ SP02001CK00 A
Place near Pin41 Place near Pin46 DA1 DA2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
add 1 cap for MLCC downsize CA35 1 2 10U_0402_6.3V6M add 1 cap for MLCC downsize
GND 20mil

1
CA5 1 2 10U_0402_6.3V6M RA1 1 2 0_0603_5% GND
+VDDA
1 GND

1
0.1U_0201_10V6K
CA8
Pin9 need to matching with SOC HDA CA6 1 2 0.1U_0201_10V6K CA9 CA36
interface.

10U_0402_6.3V6M

10U_0402_6.3V6M
2 1 Place near Pin9 +3VS_DVDDIO
+3VS

2
RA2 0_0402_5% 2 @
+3VS_DVDD GND & GNDA moat
20mil GNDA
2 1 Place near Pin26
+3VS
RA5 0_0402_5%
1

1
+1.8VS_VDDA

0.1U_0201_10V6K
CA11
CA37 CA10 2 1 +1.8VS
1 RA6 0_0402_5%

1
0.1U_0201_10V6K
CA12
CA13

10U_0402_6.3V6M

10U_0402_6.3V6M
2

2
2
DVT modify #575412 WHL DG p292_

10U_0402_6.3V6M
2
XEMC@ 2 @ add 2pF cap on HDA_SDO and HDA_RST# close to CPU
add 2pF cap on HDA_SDI close to codec
1 2 DMIC_CLK Place near Pin1 GND GNDA 11/26
CA32
10P_0201_50V8J HDA_SDIN0_AUDIO

41

46

26

40
1

9
UA1 Place near Pin40
Reserved for EMI

DVDD

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
add 1 cap for MLCC downsize
GND 1
CA31

LINE1-L 22 2P_0201_25V8B
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL- 2
UA1 LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPKR+ GND
B LINE2-R(PORT-E-R) SPK-OUT-R+
SPK-OUT-R-
44 SPKR- Digital MIC B
RING2 17
40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2
ALC256-CG MQFN 48P CODEC MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT PCH_DMIC_CLK 1 @ 2 RA57
Combo MIC HPOUT-L(PORT-I-L) <10> PCH_DMIC_CLK
256@ +MICBIAS 31 33 HP_RIGHT 0_0402_5%
+MICBIAS LINE1-VREFO-L HPOUT-R(PORT-I-R) PCH_DMIC_DATA
SA000080Q00 30 1 @ 2 RA58
LINE1-VREFO-R 10 HDA_SYNC_R <10> PCH_DMIC_DATA
0_0402_5%
DMIC_DATA 2 SYNC 6 HDA_BIT_CLK_R HDA_SYNC_R <10>
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R <10> TO eDP Conn
GPIO1/DMIC-CLK 1 XEMC@ 2 1 2 CA15 XEMC@ GND DMIC_DATA DMIC_DATA_R
RA10 0_0402_5% 22P_0402_50V8J 2 RA35
1 @
EC_MUTE# 47 5 HDA_SDOUT_R 0_0402_5% DMIC_DATA_R <38>
<58> EC_MUTE# HDA_RST#_R 2 PDB SDATA-OUT HDA_SDIN0_AUDIO HDA_SDOUT_R <10> DMIC_CLK DMIC_CLK_R
Pin11,12 <10> HDA_RST#_R 255@ 1 11 8 1 RA33 2
HDA_SDIN0 <10>
2 1
0_0402_5% RA41 RESETB SDATA-IN 33_0402_5% LA6 XEMC@ BLM15PX221SN1D_2P DMIC_CLK_R <38>
ALC255: RESETB, PCBEEP 48 SM01000Q500

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ALC256 : Floating ( I2C )
10mil
MONO_IN 12
PCBEEP
SPDIF-OUT/GPIO2
PC_BEEP
Digital MIC
16
HP_PLUG# RA13
Close
2
codec1 200K_0402_1% SENSE_A 13 MONO-OUT
2 1 100K_0402_1% 14 SENSE A +MIC2_VREFO
+3VS RA14
SENSE B 29 10U_0402_6.3V6M 1 2 CA18
MIC2-VREFO GND
1

37
CA19 35 CBP 7 10U_0402_6.3V6M 1 2 CA20
CBN LDO3-CAP GNDA
2 256@ 1 2.2U_0402_6.3V6M 39
+1.8VS_VDDA
Headphone Out
2

0_0402_5% RA43 LDO2-CAP 27 10U_0402_6.3V6M 1 2 CA21 +MIC2_VREFO

LDO1-CAP GNDA
+3VS_DVDD
2 255@ 1 CPVDD 36
0_0402_5% RA42 CPVDD 1 RA15 2
Pin20 28 CODEC_VREF 100K_0402_5% 10mil
ALC255 : 3.3V VREF

2.2U_0402_6.3V6M
2 1 20
+3VALW CPVREF
ALC256 : 3.3V or 5V

0.1U_0201_10V6K
CA23
RA16 0_0402_5% 15 1
JDREF

1
CA24
Power for combo jack depop 10U_0402_6.3V6M 1 2 CA22 19 34 CPVEE
GNDA MIC-CAP CPVEE RA19 RA20
circuit at system shutdown mode 2.2K_0402_5% 2.2K_0402_5%

2
1
4 @ 2
49 DVSS 25 CA26
Pin4

2
Thermal PAD AVSS1 38 2.2U_0402_6.3V6M
ALC283 : DVSS

2
C AVSS2 C
ALC255/256/233 : DC DET (For Japen customer only) Place near pin28 GNDA SLEEVE SLEEVE <72>
ALC255-CG_MQFN48_6X6
SA000082700 GND RING2
Pin36 255@
RING2 <72>
ALC255 : 3.3V GND
GNDA
ALC256 : 1.8V
LINE1-L 1 2
CA29 4.7U_0402_6.3V6M
RA21 CA27 Pin15
22K_0402_5% .1U_0402_16V7K HP_LEFT RA24 1 2 0_0603_5% HPOUT_L_1
DOS mode 2 1 BEEP#_R 1 2 MONO_IN ALC283 : Ref. Resistor for Jack Detect HPOUT_L_1 <72>
<58> BEEP#
Pin16 ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port HP_PLUG#
HP_PLUG# <72>
255@
RA22 CA33 ALC255: MONO-OUT HP_RIGHT RA27 1 2 0_0603_5% HPOUT_R_1
HPOUT_R_1 <72>
2

ALC256 : BEEP
4.7K_0402_5%

OS mode 22K_0402_5% 1 .1U_0402_16V7K

PC_BEEP
CA28 XEMC@
100P_0201_50V8J

2 1 1 2
<12> PCH_SPKR
RA23

256@ LINE1-R 1 2
2 CA30 4.7U_0402_6.3V6M
1

+MICBIAS DA5
2 2 RA29 1
4.7K_0402_5%
1

DVT modify GND 3 2 RA32 1

4.7K_0402_5%
BAT54A-7-F_SOT23-3
GND & GNDA moat SCSBAT54100
1 2 RA51
0_0402_5%
@ SYMBOL:SCSBAT540A0
1 2 RA52
0_0402_5%
@
D 1 2 RA53 D
0_0402_5%
@
1 2 RA54
0_0402_5%
@
1 2 RA55
0_0402_5%
@
1 2 RA56
0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
@ Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

GND GNDA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio_ALC256&711/Audio Conn.
Vendor suggest: AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
At least one Ground short close to codec. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 56 of 102
1 2 3 4 5
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for Audio Ampfilper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 57 of 102
5 4 3 2 1
 5 4 3 2 1

+1.8VALW_PRIM
near SOC SOC_RTCRST# <11>

1
EC_RST# D

1U_0201_6.3V6M
C3853 1 2 0.1U_0201_10V6K 1

C3886
EC_CLR_CMOS 2 QB6
G L2N7002WT1G_SC-70-3

1
S

3
2 RB26
10K_0402_5%

Vendor suggest

2
+3VLP_EC +3VLP +3VLP_EC +3VLP_ECA +VTT_EC +1.05V_VCCST
R3985
0_0603_5% L17
1 @ 2 EC_PME# 1 @ 2 1 2 R3983 2 1 0_0402_5%
D D
RB5 47K_0402_5% BLM15AX601SN1D _2P

4.7U_0402_6.3V6M
EC_PME# PU +3V_LAN at LAN side SM01000KL00 1

0.1U_0201_10V6K

0.1U_0201_10V6K
1 1 1 1
+3VLP_EC

C3881

C3880
C3849
+3VLP_EC +1.8VALW_PRIM +1.8VALW_ESPI +VTT_EC

C3887
C3884 0.1U_0201_10V6K
0.1U_0201_10V6K 2
R3970 1 2 2.2K_0402_5% EC_SMB_CK1 2 2 2 R3984 2 Vendor suggest LID_SW# RB15 1 2 100K_0402_5%
R3971 1 2 2.2K_0402_5% EC_SMB_DA1 0_0402_5%
1 2

ECAGND
ECAGND <83>

111

117

124
22
33
96

67
U11

9
ESPI Bus Pin : 1~14

PECI_VTT
VCC_ESPI
VCC
VCC
VCC

AVCC
VCC0

VCC_IO2
Power rail
C3885
XEMC@
2 1 2
XEMC@

R3972
1 ESPI_CLK_R EMI TP_PWR_EN 1
eSPI & MISC
21
<63> TP_PWR_EN 1ESPI_ALERT# 2 GA20/GPIO00 PWM0/GPIO0F 23 EC_VCCST_PG_R <11>
22P_0402_50V8J 33_0402_5% T135 TP@ FP_PWR_EN ESPI_ALERT#/GPIO01 PWM1/GPIO10 BEEP# <56>
3 PWM Output 26
<66> FP_PWR_EN 4 GPIO02 FANPWM0/GPIO12 27 FAN_PWM1 <77> SYS_PWROK_R 2 1
VCC SYS_PWROK <11>
1 2 SYS_PWROK <9> ESPI_CS# 5 ESPI_CS# FANPWM1/GPIO13
@
<9> ESPI_IO3_R 7 ESPI_IO3
R3874 10K_0402_5% RB11 0_0402_5%
<9> ESPI_IO2_R 8 ESPI_IO2 63 BATT_TEMP
VCC_ESPI
<9> ESPI_IO1_R ESPI_IO1 AD0/GPIO38 VCIN1_BATT_DROP BATT_TEMP <83,84>
10 64
<9> ESPI_IO0_R ESPI_IO0 AD1/GPIO39 65 ADP_I VCIN1_BATT_DROP <83>
ESPI_CLK_R 12 AD2/GPIO3A 66 AD_BID ADP_I <83,84>
Reserved R3874,as Schematic checklist requirement, AD Input
<9> ESPI_CLK_R EC_KBL_EN 13 ESPICLK AVCC AD3/GPIO3B 75 CHG_ILMSEL
PVT modify <63> EC_KBL_EN EC_RST# 37 GPIO05 AD4/GPIO42 76 IDCHG
CHG_ILMSEL <71>
DB1
For Thermal Portect Shutdown
<77> EC_RST# EC_1.8V_EN ECRST# AD5/GPIO43 IDCHG <84>
20 VCC RB751V-40_SOD323-2
<87> EC_1.8V_EN TYPEC_1P5A 38 GPIO0E 3V_EN
MAINPWON 1 2
<42,43> TYPEC_1P5A 14 GPIO1D 3V_EN <85>
VCC_ESPI
<9> ESPI_RST# ESPI_RST#/GPIO07 68
R3973 1 @ 2 4.7K_0402_5% OPMODE +3VLP_EC RB37 470K_0402_1% DA0/GPIO3C 70 OPMODE 3V_EN_R 1 2 RB17 1 2
DA Output DA1/GPIO3D EC_WLAN_ON
1 2 KSI0 55 AVCC 71 RB16 1M_0402_5%
C 56 KSI0/GPIO30 DA2/GPIO3E 72 WL_OFF# EC_WLAN_ON <52> C
KSI1 1K_0402_5%
57 KSI1/GPIO31 DA3/GPIO3F WL_OFF# <52>
1A modify for 9052 susp# glitch issue KSI2
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
59 KSI3/GPIO33 SCL2/GPIO4A 84 EC_USB_EN EC_MUTE# <56>
KSI4
KSI4/GPIO34 SDA2/GPIO4B WLAN_PME# EC_USB_EN <71,72>
OPMODE (Internal Pull High) : KSI5 60 85
61 KSI5/GPIO35 SCL3/GPIO4C 86 SPOK_5V WLAN_PME# <52> +3VS
KSI6 VCC
62 KSI6/GPIO36 SDA3/GPIO4D 87 TP_CLK SPOK_5V <85>
KSI7
Pull Up : Intel eSPI Master Attached Flash Sharing Topology KSO0 39 KSI7/GPIO37
PS2 Interface
PSCLK3/GPIO4E 88 TP_DATA TP_CLK <63>
KSO0/GPIO20 PSDAT3/GPIO4F TP_DATA <63>
--> For KB9042 / KB9052 KSO1 40
KSO2 41 KSO1/GPIO21 EC_MUTE# R3961 1 @ 2 10K_0402_5%
KSO3 42 KSO2/GPIO22 97 SOC_ENBKL
Pull Down : Intel Legacy Wire-OR share ROM. KSO4 43 KSO3/GPIO23 SHICS#/GPIO60 98 EC_TS_PWR_EN SOC_ENBKL <6>
--> For KB9022/9042 Use KSO5 44 KSO4/GPIO24 SHICLK/GPIO61 99 EC_TS_PWR_EN <78> DVT modify
KSO5/GPIO25 Int. K/B GPIO SHIDO/GPIO62 VCIN0_PH AC_IN
KSO6 45 VCC 109 C3879 1 2 100P_0201_50V8J
KSO7 46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH <83>

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KSO8 47 KSO7/GPIO27 VCC R3964 1 @ 2 4.7K_0402_5%
KSO9 48 KSO8/GPIO28 119 EC_TYPEC_EN
KSO[0..17] 49 KSO9/GPIO29 MISO_SHR_ROM/GPIO5B 120 EC_BT_ON EC_TYPEC_EN <42>
KSO10 RB36
<63> KSO[0..17] KSO11 50 KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C 126 EC_CLR_CMOS 1 2 0_0201_5% BT_ON
KSO11/GPIO2B SPI ROM SPICLK_SHR_ROM/GPIO58 CHG_CTL1 BT_ON <10,52>
KSI[0..7] KSO12 51 VCCIO2 128
<63> KSI[0..7] 52 KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A CHG_CTL1 <71>
KSO13 @
KSO14 53 KSO13/GPIO2D PVT modify
KSO15 54 KSO14/GPIO2E 73 EC_TP_INT# PCH_PWROK SYS_PWROK_R

<11,66> PM_SLP_S0#
PM_SLP_S0# 1
RB35
@ 2
0_0402_5%
EC_SLP_S0IX#_R
KSO16
KSO17
81
82
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
AVCC AD6/GPIO40
AD7/GPIO41
LOCK#/GPIO50
74
89
90
SYS_PWROK_R
BATT_4S
BATT_BLUE_LED#
EC_TP_INT#

BATT_4S <84>
<7,63>
ESD 2
C3888
GPIO52 BATT_BLUE_LED# <72> 2
VCC 91 CHG_EN C3883 100P_0201_50V8J
EC_SMB_CK1 77 CAPSLED#/GPIO53 92 PWR_LED# CHG_EN <71>
GPIO 100P_0201_50V8J EMC@
<83,84> EC_SMB_CK1 EC_SMB_DA1 78 SCL0/GPIO44 WDT_LED/GPIO54 93 BATT_AMB_LED# PWR_LED# <72> 1
EMC@
<83,84> EC_SMB_DA1 SOC_SML1CLK SDA0/GPIO45 SCROLED#/GPIO55 BATT_AMB_LED# <72> 1
79 95 SYSON
<9> SOC_SML1CLK SOC_SML1DATA 80 SCL1_BT/GPIO46 GPIO56 121 VR_ON SYSON <86>
<9> SOC_SML1DATA SPOK_3V 15 SDA1_BT/GPIO47 GPIO57 127 PCH_DPWROK VR_ON <11,88>
SMBUS VCCIO2
<85,87> SPOK_3V AC_PRESENT 19 SCL4/GPIO08 GPIO59 PCH_DPWROK <11>
VCC
<11> AC_PRESENT TS_EN 17 SDA4/GPIO0D PVT modify
<38> TS_EN TYPEC_3A SCL5/GPIO0B EC_RSMRST# VCOUT1_PROCHOT#
RB28 0_0402_5% 18 100
B SPOK_3V 2 1 <43> TYPEC_3A SDA5/GPIO0C FANFB2/GPIO63 101 EC_SLP_S0IX#_R EC_RSMRST# <11> DVT modify B
FANFB3/GPIO64 102 VCIN1_ADP_PROCHOT
VCIN1/GPIO65 VCIN1_ADP_PROCHOT <83> 1
SPOK_5V 1 RB27 2 0_0402_5% SPOK_3V_5V 103 VCOUT1_PROCHOT#
GPIO VCOUT1/GPIO66
@ VCC_ESPI VCC 104 MAINPWON C3878
LAN_PWR_EN VCOUT0/GPIO67 EC_BKOFF# MAINPWON <77,83,85> 100P_0201_50V8J
6 105
<51> LAN_PWR_EN TP_EN 16 GPIO04 GPIO68 106 SX_EXIT_HOLDOFF# EC_BKOFF# <38> 2
<63> TP_EN ME_EN 25 OWM/GPIO0A GPIO69 107 3V_EN_R SX_EXIT_HOLDOFF# <11> EMC@
<10> ME_EN FAN_SPEED1 28 PWM2/GPIO11 GPIO6A 108 EC_PME#
<77> FAN_SPEED1 29 FANFB0/GPIO14 GWG/GPIO6B EC_PME# <51>
E51TXD_P80DATA 30 FANFB1/GPIO15
<52> E51TXD_P80DATA E51RXD_P80CLK TXD/GPIO16 GPIO AC_IN
For abnormal shutdown 31 VCC 110
<52> E51RXD_P80CLK PCH_PWROK 32 RXD/GPIO17 AC_IN/GPIO79 112 EC_ON AC_IN <84>
<11> PCH_PWROK PWR_SUSP_LED# 34 POWER_FAIL1/GPIO18 GPXIOD02/GPIO7A 114 EC_ON <85>
DB2 VCC0 ON/OFFBTN#
<72> PWR_SUSP_LED# VR_PWRGD PWM3/GPIO19 GPIO7B LID_SW# ON/OFFBTN# <63>
RB751V-40_SOD323-2 36 GPIO 115
SPOK_3V_5V EC_RSMRST# <88> VR_PWRGD NUMLED#/GPIO1A GPXIOD04/GPIO7C LID_SW# <63,72>
1 2 116 SUSP#
GPIO7D SUSP# <16,78,84,86>
DB3 118 H_PECI_R R3966 1 2 43_0402_1%
PECI/GPIO7F H_PECI <7>

2
RB751V-40_SOD323-2 PBTN_OUT# 122
1 2 PCH_PWROK <11> PBTN_OUT# CHG_CTL3 123 XCLKI/GPIO5D VCCIO2 VCC_IO2 RB38
<71> CHG_CTL3 GPIO5E
100K_0201_5%
125 SLP_SUS#
GPIO7E SLP_SUS# <11>
AGND

DB4
GND
GND
GND
GND
GND

1
RB751V-40_SOD323-2 PVT modify
1 2 PCH_DPWROK 1A modify for 9052 susp# glitch issue
KB9052Q-D_LQFP128_14X14
11
24
35
94
113

69

SA0000BCG30
20mil
ECAGND

Board ID RB4 DVT@ 1 2 BATT_TEMP

+3VLP_EC 12K_0402_5% C3882 100P_0201_50V8J
SD028120280 1 2
L16 BLM15AX601SN1D _2P
2

RB4 DVT3@ SM01000KL00

RB1 20K_0402_1% PVT modify
Ra 100K_0402_1% SD034200280
A ECAGND A
RB4 PVT@ RB25
1

AD_BID 33K_0402_1% 2 1 VCOUT1_PROCHOT#

SD034330280 0_0402_5%
1

1
RB4 CB4 H_PROCHOT# 2 1 VR_HOT#
<7,84> H_PROCHOT# VR_HOT# <88>
Rb 0_0402_5% 0.1U_0201_10V6K RB20 0_0402_5%
EVT@ @
2
2

Security Classification
2019/04/12
Compal Secret Data
2020/04/12 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Analog Board ID definition, EC_ENE KB9052Q
Please see page 3. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 22, 2020 Sheet 58 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for KBC&SIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 59 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for Secure & Reset IC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 60 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for SMB/I2C Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 61 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for LEDs Controller
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 62 of 102
5 4 3 2 1
KB Conn. JKB1 JKB2

30 30
29 GND2 29 GND2
KSO16 28 GND1 KSO16 28 GND1
KSO17 27 28 KSO17 27 28
RK1 KSO0 26 27 KSO0 26 27
100K_0402_5% KSO1 25 26 KSO1 25 26
2 1 KSO2 24 25 KSO2 24 25
+3VLP 24 24
ON/OFF BTN
<58> ON/OFFBTN# ON/OFFBTN#
KSO3
KSO4
KSO5
KSO6
23
22
21
20
23
22
21
KSO3
KSO4
KSO5
KSO6
23
22
21
20
23
22
21
TP/B Conn.
KSO7 19 20 KSO7 19 20
KSO8 18 19 KSO8 18 19
KSO9 17 18 KSO9 17 18
KSO10 16 17 KSO10 16 17
KSO11 15 16 KSO11 15 16
DVT: remove SWK1 switch button KSO12 14 15 KSO12 14 15
KSO13 13 14 KSO13 13 14
KSO14 12 13 KSO14 12 13 +3V_PTP
KSO15 11 12 KSO15 11 12 +3VS RK3
KSI0 10 11 KSI0 10 11 +3VALW 0_0402_5%
KSI1 9 10 KSI1 9 10 2 @ 1
KSI[0..7] KSI2 8 9 KSI2 8 9
KSI[0..7] <58> 8 8
KSI3 7 KSI3 7
KSO[0..17] KSI4 6 7 KSI4 6 7 UK1
KSO[0..17] <58> 6 6
KSI5 5 KSI5 5 5 1
KSI6 4 5 KSI6 4 5 IN OUT
4 4 1
KSI7 3 KSI7 3 2 +3V_PTP
2 3 2 3 GND CK1
ON/OFFBTN# 1 2 ON/OFFBTN# 1 2 4 3
1 1 EN OC 4.7U_0402_6.3V6M

2
2
1
CVILU_CF20282U0RG-10-NH CVILU_CF20282U0RG-10-NH CK3 SY6288C20AAC_SOT23-5
RK4
SP01002FT00 SP01002FT00 1U_0201_6.3V6M 10K_0402_5%
CONN@ CONN@ 2
TP_PWR_EN <58>

1
KB BackLight TP_PWR_EN follow SYSON behavior
EC_TP_INT#

+5VS JBL1
JBL2
U1 1
5 1 +5VS_BL 2 1 1
IN OUT 3 2 +5VS_BL 2 1
2 4 3 3 2
GND 4 4 3 +3V_PTP +3V_PTP
4 3 5 4
<58> EC_KBL_EN EN OC GND
6 5
SY6288C20AAC_SOT23-5 GND 6 GND
GND

1
CONN@ RK7 RK10

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5
1 ACES_51524-00401-001 CONN@ 2.2K_0402_5% 2.2K_0402_5%

G
ACES_51524-00401-001 QK1B +3V_PTP
C3
SP010023G00 2N7002KDW _SOT363-6
0.1U_0201_10V6K
SP010023G00

2
2 3 4 I2C_3_SCL_R

S
<12> I2C_3_SCL

1
D
RK5 RK6
1 2 4.7K_0402_5% 4.7K_0402_5%
RK8 @ 0_0402_5%

2
G

2
QK1A
2N7002KDW _SOT363-6 TP_CLK
I2C_3_SDA_R <58> TP_CLK TP_DATA
6 1
Lid Switch

S
<12> I2C_3_SDA <58> TP_DATA

D
1 @ 2
RK9 0_0402_5%

+3VLP reserve JLID1 conn

JLID1 +3V_PTP
1
LID_SW # 2 1 @ CK2
<58,72> LID_SW # 2
3 5 0.1U_0201_10V6K
3 GND JTP1
4 6 2 1
4 GND 1
TP_CLK 2 1
JXT_FP202DH-004M10M TP_DATA 3 2
EC PS2 4 3
CONN@ 4
I2C_3_SDA_R 5
SP010022U00 I2C_3_SCL_R 6 5
PCH I2C EC_TP_INT# 7 6
<7,58> EC_TP_INT# TP_EN 7
<58> TP_EN 1 8
8
CK6
1000P_0402_50V7K 9
EMC@ 2 GND 10
GND
HEFEN_AFA02-S08FIA-2H
CONN@
ESD Suggestion SP01002PE00
DVT modify
680P to 1000P for cost down action

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 63 of 102
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for KB/TP/LED/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 64 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for KB/TP/LED/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 65 of 102
5 4 3 2 1
 A B C D E

G-Sensor reserved for BA serial

+3VS

1
RZ1 +3VS
10K_0402_5%
GSEN@ UZ1 GSEN@
1 CZ1 1 2 10U_0402_6.3V6M

2
1 8 Vdd_IO 1
4 CS 14 CZ2 1 2 GSEN@
<9,23> SOC_SMBCLK 6 SCLSPC Vdd 0.1U_0201_10V6K
<9,23> SOC_SMBDATA SDA/SDI/SDO
+3VS RZ2 1 @ 2 10K_0402_5% 7
RO25 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT#
16 INT1 9 G_INT2 G_INT# <12>
15 ADC1 INT2 G_INT2 <67>
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

2 2

TPM 2.0 https://vinafix.com

Finger Print
Power Souce Check DVT:update JFP1 define
+FP_VCC

JFP1
EGIS ETU801 +FP_VCC=5V 1
USB20_P7_L 1
+3VALW +3VALW_TPM +3VS +3VS_TPM ELAN SA464K-2200 +FP_VCC=3.3V USB20_N7_L
2
3 2
add 1 cap for MLCC downsize 4 3
1 TPM@ 2 1 TPM@ 2 5 4
5
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

RW1 0_0603_5% RW2 0_0603_5% 6

6
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
CW2 TPM@

CW4 TPM@

CW5 TPM@

CW6 TPM@
TPM@ CW7

TPM@ CW1

TPM@ CW8

TPM@ CW3

1 1 1 1 7
7
1

1
1

8
8
9
near pin1
2

2
2

2 2 2 2 10 GND
3 GND 3
CONN@
JXT_FP201H-008G10M
add 1 cap for MLCC downsize
SP010020S00
+3VALW_TPM near pin8,22
+FP_VCC

RW16 1 TPM@ 2 10K_0402_5% TPM_PIRQ# +3VALW RK16 1 FP3V@ 2 0_0603_5% UK6

+5VALW RK17 1 FP5V@ 2 0_0603_5% 5 1
IN OUT
1
UW1 2 FP@ SM070005U00
1 GND CK12 DLM0NSN900HY2D_4P
VSB +3VALW_TPM USB20_P7 USB20_P7_L
2 TPM@ 1 29 4 3 4.7U_0402_6.3V6M 2 1
<11,58> PM_SLP_S0# SDA/GPIO0 EN OC 2 <13> USB20_P7 2 1
RW10 0_0402_5% 30 8 1
SCL/GPIO1 VHIO +3VS_TPM
22 CK11 SY6288C20AAC_SOT23-5
6 VHIO FP@ FP@ USB20_N7 3 4 USB20_N7_L
GPIO3 <13> USB20_N7 3 4
2 1U_0201_6.3V6M
SOC_SPI_0_D1 RW5 2 TPM@ 1 51_0402_5% TPM_SPI_SO 24 NC 3 2 LK2 FPEMC@
SOC_SPI_0_D0 TPM_SPI_SI MISO NC FP_PWR_EN <58>
RW13 2 TPM@ 1 51_0402_5% 21 5
TPM_PIRQ# 2 TPM@ 1 TPM_PIRQ#_R 18 MOSI/GPIO7 NC 7
RW11 0_0402_5% PIRQ/GPIO2 NC 9 DK2 FPEMC@
NC 10 6 3 USB20_N7_L
SOC_SPI_0_CLK RW14 2 TPM@ 1 51_0402_5% TPM_SPI_CLK 19 NC 11 I/O4 I/O2
SOC_SPI_0_CS#2 RW15 2 TPM@ 1 0_0402_5% TPM_SPI_CS#2 20 SCLK NC 12
PLT_RST_R# RW12 2 TPM@ 1 0_0402_5% TPM_RST# 17 SCS/GPIO5 NC 14
27 PLTRST NC 15 5 2
13 NC NC 26 VDD GND
GPIO4 NC 25
NC 28
4 NC 31 4 1 USB20_P7_L
@ T283 PP/GPIO6 NC +FP_VCC I/O3 I/O1
32
4 NC AZC099-04S.R7G_SOT23-6 4
16
GND 23
GND 33
PGND
SOC_SPI_0_D1 NPCT750AAAYX_QFN32_5X5
<9> SOC_SPI_0_D1 SOC_SPI_0_D0
<9> SOC_SPI_0_D0 TPM@
TPM_PIRQ#
<6> TPM_PIRQ#
<9> SOC_SPI_0_CLK
SOC_SPI_0_CLK SA0000AQ250 Security Classification Compal Secret Data Compal Electronics, Inc.
SOC_SPI_0_CS#2 2018/12/27 2019/12/27 Title
<9> SOC_SPI_0_CS#2 PLT_RST_R# Issued Date Deciphered Date
<11,51,52,68> PLT_RST_R#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM & FP
SA0000AQ230, S IC NPCT750AAAYX QFN 32P TPM (SPI interface) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 66 of 102
A B C D E
 1 2 3 4 5

SATA HDD G_INT2_R

+5VS +5VS_HDD

2
100mils RO29
1 2 0_0402_5%
RO3 0_0805_5%

10U_0402_6.3V6M

10U_0402_6.3V6M
1 GSEN@

1
1

1
CO16

CO12
CO13
0.1U_0201_10V6K
@

2
2
D D

add 1 cap for MLCC downsize

HDD FFC Type

JHDD1
14
+5VS_HDD 13 GND
GND
+5VS_HDD 12
DVT modify 11 12
10 11
G_INT2 RO4 1 @ 2 0_0402_5% G_INT2_R 9 10
<66> G_INT2 9
RO30 1 @ 2 0_0201_5% 8
<13> DEVSLP0 8
7
SATA_CRX_DTX_P0 CO4 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P0 6 7
<13> SATA_CRX_DTX_P0 SATA_CRX_DTX_N0 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_N0 5 6
CO3
<13> SATA_CRX_DTX_N0 4 5
SATA Port 0 SATA_CTX_DRX_N0 SATA_CTX_C_DRX_N0 4
CO2 1 2 0.01U_0402_16V7K 3
<13> SATA_CTX_DRX_N0 SATA_CTX_DRX_P0 SATA_CTX_C_DRX_P0 3
CO1 1 2 0.01U_0402_16V7K 2
<13> SATA_CTX_DRX_P0 1 2
close to CONN. 1
ACES_51625-01201-001
CONN@
SP010028W00

C C

https://vinafix.com
SATA ODD
+5VS +5VS_ODD

B B
1 2
100mils
RO26 0_0805_5% change ODD pin define
10U_0402_6.3V6M

10U_0402_6.3V6M
ODD@

1@

1
ODD FFC Type
1

CO23

CO22

CO21
0.1U_0201_10V6K +5VS_ODD
@
2

2 +5VS_ODD 1
2 1
3 2
4 3
add 1 cap for MLCC downsize 5 4
6 5
7 6
8 7
9 8
10 9
11 10
SATA_CRX_DTX_P1 ODD@ CO20 1 2 0.01U_0402_16V7K SATA_CRX_C_DTX_P1 12 11
<13> SATA_CRX_DTX_P1 SATA_CRX_DTX_N1 SATA_CRX_C_DTX_N1 12
ODD@ CO18 1 2 0.01U_0402_16V7K 13
<13> SATA_CRX_DTX_N1 14 13
SATA_CTX_DRX_N1 ODD@ CO19 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N1 15 14
<13> SATA_CTX_DRX_N1 SATA_CTX_DRX_P1 SATA_CTX_C_DRX_P1 15
<13> SATA_CTX_DRX_P1 ODD@ CO17 1 2 0.01U_0402_16V7K 16
16
close to CONN. 17
18 GND17
GND18
JODD1
ACES_51625-01601-001
SP01002OK00
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 67 of 102
1 2 3 4 5
 A B C D E

mSATA/SSD reserve for RDT3, DVT modify

+3VS

1
@
CM17 UM2 @
1U_0201_6.3V6M 1
2 2 VIN1 +3VS_SSD_NGFF
VIN2
1
+3VS DVT modify +3VS_SSD_NGFF +5VALW 7 6 1
VIN thermal VOUT
0_0603_5% CM16 2 @1 3 1
RM9 1 2 0.1U_0201_10V6K VBIAS @
RM13 1 @ 2 0_0201_5% 4 5 CM18
<12> SOC_NGFF_PW REN ON GND
0.1U_0201_10V6K

10U_0402_6.3V6M
10U_0402_6.3V6M
2 1

1
2

CM30

CM14
+ CM29 EM5201V_DFN8_3X3
2 150U_B2_6.3VM_R35M S IC EM5202DV DFN3X3 8P LOAD SWITCH

2
1 CM13 SGA00009M00
2 SA00009CW00
0.1U_0201_10V6K use EM5201 Footprint
add 1 cap for MLCC downsize 0_0201_5% 2 1 RS266

+3VS

5
VCC
1
<11,51,52,66> PLT_RST_R# IN B SSD_RST#_R
4
2 OUT Y

GND
<7> SOC_GPP_H0 IN A
1
UM3 @
NL17SZ08DFT2G_SC70-5 CM36

3
@ 0.01U_0402_16V7K
2 2 2

KEY M
JSSD1

https://vinafix.com
DVT modify 1 2 +3VS_SSD_NGFF
3 GND 3P3VAUX 4
PCIE_CRX_DTX_N8 5 GND 3P3VAUX 6
<13> PCIE_CRX_DTX_N8 PERn3 NC
PCIE_CRX_DTX_P8 7 8
<13> PCIE_CRX_DTX_P8 PERp3 NC
9 10 SSD_LED#
GND DAS/DSS# @ T245
PCIE_CTX_DRX_N8 CS125 1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_N8 11 12
<13> PCIE_CTX_DRX_N8 PCIE_CTX_DRX_P8 CS126 PETn3 3P3VAUX
1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_P8 13 14
<13> PCIE_CTX_DRX_P8 PETp3 3P3VAUX
15 16
PCIE_CRX_DTX_N7 17 GND 3P3VAUX 18
<13> PCIE_CRX_DTX_N7 PERn2 3P3VAUX
PCIE_CRX_DTX_P7 19 20
<13> PCIE_CRX_DTX_P7 PERp2 NC
21 22
PCIE X4 <13> PCIE_CTX_DRX_N7
PCIE_CTX_DRX_N7 CS127 1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_N7 23 GND NC 24
PCIE_CTX_DRX_P7 CS128 1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_P7 25 PETn2 NC 26
<13> PCIE_CTX_DRX_P7 PETp2 NC
(link to PICE Port 5~8) 27 28
PCIE_CRX_DTX_N6 29 GND NC 30
<13> PCIE_CRX_DTX_N6 PERn1 NC
PCIE_CRX_DTX_P6 31 32
<13> PCIE_CRX_DTX_P6 PERp1 NC
33 34
3 PCIE_CTX_DRX_N6 CS129 1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_N6 35 GND NC 36 3
<13> PCIE_CTX_DRX_N6 PCIE_CTX_DRX_P6 CS130 PETn1 NC
1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_P6 37 38
<13> PCIE_CTX_DRX_P6 PETp1 DEVSLP
39 40
PCIE_CRX_DTX_N5 41 GND NC 42
<13> PCIE_CRX_DTX_N5 PERn0/SATA-B+ NC
PCIE_CRX_DTX_P5 43 44 CM31 1 2 EMC@ DVT modify
<13> PCIE_CRX_DTX_P5 PERp0/SATA-B- NC
45 46 100P_0201_50V8J DVR change from 1000p to 100p
PCIE_CTX_DRX_N5 CS131 1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_N5 47 GND NC 48
<13> PCIE_CTX_DRX_N5 PCIE_CTX_DRX_P5 CS132 PETn0/SATA-A- NC
1 2 0.22U_0402_10V6K PCIE_CTX_C_DRX_P5 49 50 SSD_RST#_R
<13> PCIE_CTX_DRX_P5 PETp0/SATA-A+ PERST# CLKREQ_PCIE#1
51 52 CLKREQ_PCIE#1 <11>
CLK_PCIE_N1 53 GND CLKREQ# 54
<11> CLK_PCIE_N1 CLK_PCIE_P1 REFCLKN PEWake#
55 56
PCIE CLK <11> CLK_PCIE_P1
57 REFCLKP NC 58
GND NC

(From PCH CLKOUT1)

59 60 SUSCLK_SSD
NC SUSCLK(32kHz) @ T246
61 62
0104 remove NGFF_SSD_PEDET 63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
GND 3P3VAUX
for Lily_TGL and Iris_TGL not support auto detect function 65
67 GND 3P3VAUX
66 +3VS_SSD_NGFF
GND 68
NGFF_SSD_PEDET (SATA_GP0) GND1 69
GND2
SATA Device 0
BELLW _80159-3221
PCIE Device 1--PU on CPU side CONN@

SP070018L00
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF SSD(KEY M)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 68 of 102
A B C D E
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve eMMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 69 of 102
5 4 3 2 1
 A B C D E

1 1

2 2

https://vinafix.com

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5227S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 70 of 102
A B C D E
 1 2 3 4 5

MB_USB3.1 Type-A Conn.

DVT modify DVT modify 900mA

I (Max) : 0.9 A(+5VALW_USBA)
CT236 1 2 0.22U_0402_10V6K USB3_CTX_C_DRX_N3 1 @ 2 RT246 USB3_CTX_L_DRX_N3 +5VALW_USBA
RDS(Typ) : 70 mohm <13> USB3_CTX_DRX_N3
V drop : 0.063 V JUSB1
EN: Active High 0_0201_5% USB3_CTX_L_DRX_P3 9
CT237 1 2 0.22U_0402_10V6K USB3_CTX_C_DRX_P3 1 @ 2 RT233 USB3_CTX_L_DRX_P3 1 SSTX+
+5VALW <13> USB3_CTX_DRX_P3 USB3_CTX_L_DRX_N3 VBUS
8
UT10 +5VALW_USBA USB20_P3_R 3 SSTX-
A 80mil 0_0201_5% 7 D+ A
5 1 USB20_N3_R 2 GND 10
IN OUT USB3_CRX_L_DTX_P3 6 D- GND 11
2 4 SSRX+ GND 12
1 GND GND GND
USB3_CRX_DTX_N3 USB3_CRX_L_DTX_N3 USB3_CRX_L_DTX_N3

150U_B2_6.3VM_R35M
CT239 0_0201_5% 1 @ 2 RT235 5 13
EC_USB_EN USB_OC2# <13> USB3_CRX_DTX_N3 SSRX- GND
1U_0201_6.3V6M 4 3 1
EN OC

0.1U_0201_10V6K
1 ACON_TARBA-9U1393
2 USB3_CRX_DTX_P3 USB3_CRX_L_DTX_P3

CT513

CT241
+ 0_0201_5% 1 @ 2 RT236 CONN@
<13> USB3_CRX_DTX_P3
SY6288C20AAC_SOT23-5 LTCX008KB00
2 2
Symbol:DC23300N800
<58,72> EC_USB_EN
compatible: DC23300TT00

DT29
USB3_CRX_L_DTX_N3 1 1 10 9 USB3_CRX_L_DTX_N3

LT10 EMC@ USB3_CRX_L_DTX_P3 2 2 9 8 USB3_CRX_L_DTX_P3

USB_OC2# <6> USB20_P3 USB20_P3_R
4 3
<13> USB20_P3 4 3 USB3_CTX_L_DRX_N3 USB3_CTX_L_DRX_N3
4 4 7 7
USB20_N3 1 2 USB20_N3_R USB3_CTX_L_DRX_P3 5 5 6 6 USB3_CTX_L_DRX_P3
<13> USB20_N3 1 2
DLM0NSN900HY2D_4P 3 3
SM070005U00
DT30
8
6 3 USB20_N3_R
AZ1045-04F_DFN2510P10E-10-9 I/O4 I/O2
EMC@

+5VALW_USBA 5 2
VDD GND

4 1 USB20_P3_R
I/O3 I/O1

B AZC099-04S.R7G_SOT23-6 B
EMC@
SC300001G00

MB_USB3.1 Type-A Conn. 900mA +5VALW_USBB

(Charge Port)
1

150U_B2_6.3VM_R35M
USB Host Charger

CT514
DVT modify DVT modify + JUSB2
USB3_CTX_L_DRX_P4 9

https://vinafix.com
CT242 1 2 0.22U_0402_10V6K USB3_CTX_C_DRX_N4 1 @ 2 RT239 USB3_CTX_L_DRX_N4 1 SSTX+
<13> USB3_CTX_DRX_N4 2 USB3_CTX_L_DRX_N4 VBUS
8
0_0201_5% U2DP4_R 3 SSTX-
CT243 1 2 0.22U_0402_10V6K USB3_CTX_C_DRX_P4 1 @ 2 RT240 USB3_CTX_L_DRX_P4 7 D+
<13> USB3_CTX_DRX_P4 U2DN4_R GND
2 10
0_0201_5% USB3_CRX_L_DTX_P4 6 D- GND 11
4 SSRX+ GND 12
USB3_CRX_L_DTX_N4 5 GND GND 13
SSRX- GND
+5VALW ACON_TARBA-9U1393
@ CONN@
+5VALW_USBB USB3_CRX_DTX_N4 RT242 1 2 0_0201_5% USB3_CRX_L_DTX_N4
RS267 1 @ 2 0_1206_5% <13> USB3_CRX_DTX_N4 LTCX008KB00
USB3_CRX_DTX_P4 RT243 1 @ 2 0_0201_5% USB3_CRX_L_DTX_P4 Symbol:DC23300N800
<13> USB3_CRX_DTX_P4
1
22U_0603_6.3V6M

.1U_0402_16V7K

1@ 1
CHG@ RS268 compatible: DC23300TT00
CS9

CS7

@ 0_1206_5%
2 2 US12
2

CHG@
+5VALW_CHG 1 12 +USB3VCCA_CHG
VIN VOUT
2
<13> USB20_N4 DM_OUT
C RS11 3 C
<13> USB20_P4 DP_OUT
0_0402_5% 10 U2DP4
USB_OC1# 2 @ 1 13 DP_IN 11 U2DN4
<6> USB_OC1# FAULT# DM_IN
CHG_ILMSEL 4
1 <58> CHG_ILMSEL ILIM_SEL DT31
CS8 CHG_EN 5 15 LT12 EMC@ USB3_CRX_L_DTX_N4 1 1 10 9 USB3_CRX_L_DTX_N4
<58> CHG_EN EN ILIM_L U2DP4_R
0.1U_0201_10V6K 16 U2DP4 4 3
2 ILIM_HI 4 3 USB3_CRX_L_DTX_P4 2 2 USB3_CRX_L_DTX_P4
@ 9 8
1

CHG_CTL1 6
<58> CHG_CTL1 CHG_CTL2 CTL1 U2DN4_R USB3_CTX_L_DRX_N4 USB3_CTX_L_DRX_N4
22.1K_0402_1%

39K_0402_1%

7 9 U2DN4 1 2 4 4 7 7
CHG_CTL3 CTL2 NC 1 2
RS12

RS13

8 14
<58> CHG_CTL3 CTL3 GND USB3_CTX_L_DRX_P4 USB3_CTX_L_DRX_P4
17 DLM0NSN900HY2D_4P 5 5 6 6
Thermal Pad CHG@ @ SM070005U00
2

3 3
SLGC55544CVTR_TQFN16_3X3
8

AZ1045-04F_DFN2510P10E-10-9
DT32
EMC@
0831 Reserve ILIM_L R as vendor recommend 6 3 U2DN4_R
I/O4 I/O2

ILM R vaule
Ios(mA)=50250/R(Kohm) +5VALW_USBB
5
VDD GND
2

+5VALW ILIM_Hi=2273mA
ILIM_L=1288mA(reserve) 4 1 U2DP4_R
CHG@ I/O3 I/O1
RS14 1 2 10K_0402_5% CHG_CTL2
AZC099-04S.R7G_SOT23-6
@ EMC@
RS15 1 2 10K_0402_5% CHG_ILMSEL
SC300001G00

0911 Rerserve PU, vendor

suggest to EC control if
D D
future need support SDP2

USB Host Charger Truth Table

CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note
www.teknisi-indonesia.com
Setting
0 0 1 0 1 SDP1-OFF ILIM_H Port power off
1 0 1 0 1 SDP1 ILIM_H Data Lines Connected Security Classification Compal Secret Data Compal Electronics, Inc.
1 0 1 1 1 DCP ILIM_H Data Lines Disconnected Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title
Auto
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2/USB3 TYPEA1&2
1 1 1 1 1 CDP ILIM_H Data Lines Connected AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 71 of 102
1 2 3 4 5
 5 4 3 2 1

JIO1
+5VALW +3VLP
D D
1
HPOUT_L_1 2 1
<56> HPOUT_L_1 2
HPOUT_R_1 3
<56> HPOUT_R_1 3
<56> SLEEVE SLEEVE 4
RING2 5 4
<56> RING2 5
HP_PLUG# 6
<56> HP_PLUG# 6
7
LID_SW # 8 7
<58,63> LID_SW # 8 GNDA
9
PW R_SUSP_LED# 10 9
<58> PW R_SUSP_LED# 10
11
PW R_LED# 12 11
<58> PW R_LED# 12
13
14 13
15 14
15
Co-lay Dopey IO/B
16
17 16
18 17
19 18
<58,71> EC_USB_EN 19
DVT modify
<56> SPK_R+ 20
JIO1 21 20
pin8/pin9 swap, 22 21
pin11/pin12 swap, <56> SPK_R- 22
23
pin19/pin25 swap 23
24
25 24
26 25
BATT_BLUE_LED# 27 26
<58> BATT_BLUE_LED# 27
BATT_AMB_LED# 28
<58> BATT_AMB_LED# 28
C 29 C
USB20_L_P5 30 29
USB20_L_N5 31 30
32 31
32

33
34 G1
USB2 I/O G2

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RS157 1 @ 2 0_0402_5% USB20_L_P5 ACES_51569-03201-P01
<13> USB20_P5
SP01001SX00
RS158 1 @ 2 0_0402_5% USB20_L_N5
<13> USB20_N5 I/O Borad (USB2 /LED / Speaker-RCH)

Reserved CMC on SUB/B side

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve USB2/USB3 TYPEA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 72 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve USB2/USB3 DB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 73 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for Dock
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 74 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 75 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 76 of 102
5 4 3 2 1
 A B C D E

FAN1 Conn Screw Hole

+5VS
40mil H10 H8 H9 H12 H13 H14
RF1 1 2 0_0603_5% +VCC_FAN1 H_3P0N H_2P0-G H_3P0-G H_4P0X4P5-G H_3P0X2P0-G H_3P0-G
1 2
1 FD1 FD2 1
XEMC@ CF2 CF1 @ @ @

1
1000P_0402_50V7K 4.7U_0402_6.3V6M
2 1 @ @ @

1
@ @ FIDUCIAL_C40M80 FIDUCIAL_C40M80

FD3 FD4

H15
H7 H_3P8 @ @

1
h_2p0x2p7N
+3VS FIDUCIAL_C40M80 FIDUCIAL_C40M80
@

1
@

1
1

RF2
10K_0402_5%
40mil JFAN1
2

+VCC_FAN1 1
FAN_SPEED1 2 1
<58> FAN_SPEED1 FAN_PWM1 3 2
1
<58> FAN_PWM1 4 3 CPU STAND OFF
4 H1 H2 H3 H4
5 H_3P3 H_3P3 H_3P3 H_3P2
CF3 6 GND
2 1000P_0402_50V7K GND
XEMC@ CVILU_CI4204M2HR0-NH

1
CONN@
SP020012X00
2 @ @ @ @ 2

Reset Circuit
https://vinafix.com +3VLP

RG1 1 @ 2 0_0402_5%
MAINPWON <58,83,85>

2
RG3 RG2 1 2 0_0402_5%
EC_RST# <58>
10K_0402_5%

6
D
BI_GATE# 2
G 2N7002KDW_SOT363-6
BI_GATE PH to +RTCVCC at PWR side QG1A

3
D 1 S

1
BI_GATE 5
3 <83> BI_GATE G C70 3
QG1B 0.1U_0201_10V6K
2N7002KDW_SOT363-6 S 2

4
Reset Button
MP modify

SWG2
BI_GATE 1 2 BI_GATE

3 4

TS-A45U-2-S085_4P

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & Reset
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 77 of 102
A B C D E
 A B C D E

+3VS
+3VALW

@ JPQ2
+3VALW TO +3VS 1
1 2
2

1U_0201_6.3V6M
C150
1
+5VALW
I (Max) : 6.89 A(+3VS)
RON(Max) : 21 mohm JUMP_43X118
RV98 1 @ 2 0_0201_5% 1
<9> SOC_TS_PWR_EN V drop : 0.145 V

0.1U_0201_10V6K
@
2

1U_0201_6.3V6M
C152

C151
1 DVT modify,
RV99 1 2 0_0201_5% U20 Main use SE00000TG00 S CER CAP 1000P
<58> EC_TS_PWR_EN 1 14 50V K X7R 0201 2
2 VIN1 VOUT1 13 2nd use SE170102K80 S CER CAP 1000P
1 2 VIN1 VOUT1 25V K X7R 0201 1
EN_3VS_5VS 3 12 1 2
EN1 SS1 C153
4 11 1000P_0201_50V7K
VBIAS GND
+5VS +3VS 5 10 1 2
EN2 SS2 C154 +TS_PWR
RV361 1 2 0_0603_5% 6 9 1000P_0201_50V7K
RV362 1 @ 2 0_0603_5% 7 VIN2 VOUT2 8
VIN2 VOUT2
15 R3986 1 2 0_0603_5%
Thermal pad
1

0.1U_0201_10V6K
JW7110DFNC-TRPBF_DFN14_3X2

C3890
1U_0201_6.3V6M
C3889
1 2

@
2

+5VALW

+5VALW TO +5VS

1U_0201_6.3V6M
C155
1
+5VS

@ @ JPQ3
2 2 1 2 2
1 2
JUMP_43X118 1
U21
1 14 C156
DVT modify 2 VIN1 VOUT1 13 0.1U_0201_25V6K
+5VALW VIN1 VOUT1 2
R230 1 @ 2 0_0201_5% EN_3VS_5VS 3 12 1 2
<16,58,84,86> SUSP# EN1 SS1 C160
4 11 1000P_0201_50V7K
VBIAS GND DVT modify,
SUSP# R232 1 @ 2 0_0201_5% EN_1.8VS 5 10 1 2 Main use SE00000TG00 S CER CAP 1000P
EN2 SS2 50V K X7R 0201
1U_0201_6.3V6M
C159

1 C161
6 9 1000P_0201_50V7K 2nd use SE170102K80 S CER CAP 1000P
VIN2 VOUT2 25V K X7R 0201
7 8

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+1.8VALW_PRIM VIN2 VOUT2 +1.8VS_R +1.8VS
2 15
Thermal pad
JW7110DFNC-TRPBF_DFN14_3X2 1 @ 2

1U_0201_6.3V6M
C162
1 R290 1
0_0402_5%
C163
@ I (Max) : 0.591 A (+1.8VS) 0.1U_0201_10V6K
2 2
RON(Max) : 21 mohm
V drop : 0.012 V

+1.8VALW_PRIM TO +1.8VS

3 3

DIS(1.8VSDGPU_AON and +1.8VSDGPU_MAIN), remove

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface & Sequence Logic
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 78 of 102
A B C D E
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
XDP/CMC/APS Debug Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 79 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

https://vinafix.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/09/20 Deciphered Date 2020/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FIP Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 80 of 102
5 4 3 2 1
 5 4 3 2 1

D D

PWR-Reserve Page C

https://vinafix.com

B B

A A

Title
<Title>

Size Document Number Rev

A LA-K091P 0.1

Date: Wednesday, July 08, 2020 Sheet 81 of 102

5 4 3 2 1
 A B C D E

1 1

+19V_ADPIN 5A_Z120_25M_0805_2P
EMI@ PL101
+19V_VIN
@ PJP101
1 1 2
1 2
2 3
3

+19V_VIN

1
4
G1

1
5 EMI@ PC104
G2 EMI@ PC105 PC102 EMI@ 1000P_0402_50V7K

2
ACES_30706-11702-001 1000P_0402_50V7K 100P_0201_50V8J

1
ADAPDET
PR102
499K_0402_1% ACDET <84>

2
2 2

1
PQ101 D
ADAPDET 2
G

S
L2N7002SWT1G_SOT323-3

3
1
@
PR103
PR101
215K_0402_1%
1 2
+3VLP +CHGRTC

2
0_0402_5%

https://vinafix.com

3 3

4 4

Security Classification
2018/12/27
Compal Secret Data
2019/12/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / Pre-charge
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K092P
Date: Wednesday, July 08, 2020 Sheet 82 of 102
A B C D E
 A B C D E

+3VLP

1
OTP@
PC205

1
1 0.1U_0402_25V7K 1

2
OTP@
PR214
10K_0402_1%

1
PR207 100_0402_1% OTP@
MB:Battery Con Put TOP Side

2
1 2 PR213 OTP@
EC_SMB_DA1 <58,84> 100K_0402_1%
PR205 100_0402_1% PU201
1 2 1 8

100K_0402_1%_NCP15WF104F03RC
EC_SMB_CK1 <58,84> VCC TMSNS1

2
2 7 2 1
GND RHYST1
Battery Bot Side PR202 MAINPWON 1 2 MAINPWON_G718 3 6 PR216
<58,77,85> MAINPWON OT1 TMSNS2

1
200K_0402_1% PR218 47K_0402_1%
1 2 4 5 OTP@ OTP@
PIN1 GND @ PJP201 +3VLP 0_0402_5% OT2 RHYST2 PH202
1 OTP@ G718TM1U_SOT23-8
PIN2 GND 1 2 1 2
BATT_TEMP <58,84>

2
2 3
PIN3 SMD 3 4
EC_SMB_DA1-1
EC_SMB_CK1-1 PR203 1K_0402_1%
PIN4 SMC 4 5
5 6
BATT_TS
BATT_B/I
PIN5 TEMP 6 7
7 8
PIN6 BI 8 9 +RTCVCC
PIN7 Batt+ GND 10
GND
PIN8 Batt+ CVILU_CI9908M2HR0-NH
2016/11/16 update

1
PR212
100K_0402_5%
PQ201 Change to SB00000QO00, For KB9022
sense 20mΩ Active Recovery
SB501380010(BSS138LT1G Del)

2
2 2

1
D
<77> BI_GATE 2 PQ201
G LBSS139LT1G 1N SOT-23-3 45W PR206 58.5W,1V Active=recovery
+12.6V_BATT+ S
2.32K ohm

3
EMI@ PL201

2
5A_Z120_25M_0805_2P @
1 2 PR217
change PL201, PL202 +12.6V_BATT 0_0402_5%
65W PR206 84.5W,1V
PL202
SM01000C000 to comm 7.87K ohm Active=recovery
1 2
part SM01000P200

1
https://vinafix.com
5A_Z120_25M_0805_2P
EMI@ 90W PR20K __W,__V
ohm Active=recovery
1

EMI@ PC201 EMI@ PC202

1000P_0402_50V7K 0.01U_0402_50V7K PH1 under CPU botten side :
2

PH1 2V 1V CPU thermal protection at 89 +-3 degree C

Recovery at 56 +-3 degree C
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
3 +3VLP_ECA 3

ADP_I <58,84>
+19VB_5V
VAL50/ZAL20 Battery is 3-cell NVDC design.

1
B+=9V PR204
Change PR12=50k if Battery is 2-cell NVDC design 16.9K_0402_1%
45W@ PR206
B+=6V
1

2.32K_0402_1%

2
PR209 65W@
VCIN0_PH <58>
750K_0402_1%
@ PR206
7.87K_0402_1%
PR210
2

1
1
1 2
VCIN1_BATT_DROP <58> PC203 must close to EC pin

2
PH201
VCIN1_ADP_PROCHOT <58>
@ PC203
0_0402_5% 100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6

1
1

1
2
2

PC204 PR211 PR208

0.1U_0402_25V6 150K_0402_1%
T202 T201 must close to PH201
T202@ 10K_0402_1%
1

2
T201@

ECAGND <58>

4 4

Security Classification
2018/12/27
Compal Secret Data
2019/12/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 83 of 102
A B C D E
 A B C D E

PRB1 PQB2

1
D AON7506_DFN33-8-5
1M_0402_1%
2 1 2
PQB1 +19VB 1
G L2N7002SW T1G_SOT323-3 2 +12.6V_BATT_CHG
PRB2 S 5 3

3
2 1
+19V_P1 +19V_P2
PQB3 3M_0402_5% PQB4

4
EMB04N03H_EDFN5X6-8-5 AON7506_DFN33-8-5
1 1
PRB3
0.01_1206_1% EMI@ PLB1
+19V_CHG
2 2 HCB2012KF-121T50_0805
5 3 3 5 1 4 1 2
+19V_VIN
2 3

10U_0603_25V6M

PCB8 @ 10U_0603_25V6M
0.047U_0603_25V7M
4

4
1 1
PCB2

10U_0603_25V6M
1000P_0402_50V7K

2200P_0402_50V7K
1 2
1

1
PCB1

PCB3

PCB4
ACP ACN

68P_0402_50V8J

0.1U_0402_25V6

0.1U_0402_25V6
1

1
@EMI@ PCB5

EMI@ PCB6

PCB9

EMI@ PCB10
0.022U_0603_25V7K

2
4.7_0603_1%

4.02K_0402_1%
2

10_0402_1%
PRB4
PCB12
PCB11

1
1

2
+19V_VIN 0.1U_0402_25V6 PCB13

PRB5

PRB6
EMI@
2 1 1 2 1 2

PCB7
1 0.01U_0402_50V7K

2
ACDRV_CHGR_R 0.1U_0402_25V7K
PRB37 ACFET MDU1512 SB00000SY00
1

PRB7
0_0402_5%
Rds(on):4.2~5m Ohm 4.02K_0402_1% BATDRV_CHGR
Vgs=20V 1 2 ACDRV_CHGR

1
Vds=30V @ PRB8 @ PRB9
ID= 24.2A (Ta=70C) 0_0402_5% 0_0402_5%
1 2

2 1CMSRC_CHGR BATSRC_CHGR
PRB38 PRB10

2
0_0402_5%
4.02K_0402_1%

ACN_CHGR
ACP_CHGR
2

PDB1 PRB12 @ PCB15

S SCH DIO BAS40CW SOT-323 10_1206_5% 1000P_0402_50V7K 2016/03/13 SE158225K80 X1
+19V_VIN
3 1 2 down size SE00000WP00 S
1

1 2 1
PRB11 +19VB 2 ACDRV_CHGR CER CAP 2.2U 25V K X5R 0603 PQB5
422K_0402_1% PCB16 1U_0603_25V6K +6V_CHG_REGN
2 1 PCB18
2.2U_0603_16V6K
2

5
2 ACDET PUB1 2

AON7506_DFN33-8-5
<82> ACDET 1 2 Choke 4.7uH SH00000YC00 (Common Part)

ACDRV

ACP

ACN
28
VCC PRB14
(Size:6.6 x 7.3 x 3 mm)
66.5K_0402_1%

(DCR:28m~33m)
1

CMSRC_CHGR 3 24 0_0603_5%
CMSRC REGN
1

2DH_CHGR_R 4
PRB13

@ PCB19 1
6 PRB16
PCB17 0.047U_0603_25V7M
2200P_0402_50V7K ACDET 25 BST_CHGR1 2BST_CHGR_R 1 2
2

11 BTST
<58,83> EC_SMB_DA1 +12.6V_BATT
2

SDA

3
2
1
12 26 UG_CHGR 0_0603_5% PRB19
<58,83> EC_SMB_CK1 SCL HIDRV PLB2 0.01_1206_1%
1

https://vinafix.com
ACPRN_CHGR 5 4.7UH_PCMB063T-4R7MS_8A_20%
PRB39 <58,83> ADP_I PCB20 ACOK 27 LX_CHGR 1 2 1 4
0_0402_5% 1 2 PRB18 1 2 0_0402_5% 7 PHASE
IADP 2 3

1
100P_0201_50V8J IDCHG 8 23 LG_CHGR PQB6

4.7_1206_5%
2

IDCHG LODRV

EMI@ PRB20
1 2 9

10U_0603_25V6M

10U_0603_25V6M
PMON

AON7506_DFN33-8-5
@ PCB21 10 22 PRB22 316K_0402_1% SRP SRN

1SNUB_CHGR 2
/PROCHOT GND

1
1 2

PCB22

PCB23
100P_0402_50V8J
@ +3VLP 4
<58> IDCHG PRB24 78.7K_0402_1%
PRB23

2
13 21 ILIM_CHGR 1 2
1 2 GND ILIM PRB25

680P_0402_50V7K
<7,58> H_PROCHOT# 14 10_0402_1%

3
2
1
NC 20 SRP_CHGR 1 2

EMI@ PCB24
@
0_0402_5% PRB26 SRP
1 2 15 19 SRN_CHGR 1 2
20160601 colay BQ24781

2
/BATPRES SRN
3 PRB27 3
0_0402_5% 16 18 BATDRV_CHGR 10_0402_1% PCB25
/TB_STAT BATDRV 0.1U_0402_25V6
29 17 BATSRC_CHGR 1 2
PWPD BATSRC
For 4S per cell 4.35V battery <58,83> BATT_TEMP
CHG_TB_STAT BQ24800_W QFN28_4X4
+6V_CHG_REGN
ACDET 3.3*100/(316+100)=0.79 H/L Side AON7506 SB000010A00

0.1U_0402_25V6

0.1U_0402_25V6
@ PRB36
ICHG= 0.79 /(20*0.01)=3.95A Rds(on):13~15.8mohm

1
PCB26

PCB27
10K_0402_1%
1 2 Vgs=20V
1

4S_BATT@ 3.3*78.7/(316+78.7)=0.66 Vds=30V

2
PRB28 ICHG= 0.66 /(20*0.01)=3.28A ID= 10.5A (Ta=70C)
2M_0402_1%

+6V_CHG_REGN
1 2

4S_BATT@
PRB31
0_0402_5%

1
PRB32
2

10K_0402_1%
PRB34
1

4S_BATT@ 10K_0402_1%

2
PQB7 1 2 ACPRN_CHGR
4S_BATT@ PRB33 LTC015EUBFS8TL_UMT3F <58> AC_IN 1
100K_0402_1%
1 2 2 PRB35
<58> BATT_4S
4 12K_0402_1% 4
2

4S_BATT@
3
1

PQB9 D
2
<16,58,78,86> SUSP# G

L2N7002SW T1G_SOT323-3S
Security Classification Compal Secret Data Compal Electronics, Inc.
3

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 84 of 102
A B C D E
 A B C D E

PR302
499K_0402_1%
ENLDO_3V 1 2
EN1 and EN2 dont't floating
+19VB

1
150K_0402_1%
+19VB

PR303
EMI@ PL301 @ PC302
PR304
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1 +19VB_3V BST_3V 1
1 2 1 2 1 2

2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M

2
EMI@ PC301

@EMI@ PC303

EMI@ PC304
0.1U_0402_25V6

0.1U_0402_25V6
1

1
0_0603_5%

@ PC305

PC306

1
PU301

2
PL302

BS
IN

IN

IN

IN
1.5UH_6A_20%_5X5X3_M
LX_3V 6 20 LX_3V 1 2
LX LX +3VALWP
7 19
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
8 18
+3VALWP GND GND

@ PC307

PC308

PC309

@ PC310

PC311

PC312
SY8286BRAC_QFN20_3X3 @EMI@
SPOK_3V 9 17 PR305
+3VLP

2
PG LDO 4.7_1206_5%

1 3V_SN
10 16

2
NC NC

1
PC313

OUT
EN2

EN1
21 4.7U_0402_6.3V6M

NC
FF

2
PR301 GND @EMI@
100K_0402_5% PC314

11

12

13

14

15
680P_0402_50V7K

2
Vout is 3.234V~3.366V
<58,87> SPOK_3V
3.3V LDO 150mA~300mA

ENLDO_3V PC315 PR306

1000P_0402_50V7K 1K_0402_5%
3V_FB 1 2 1 2
<58> 3V_EN

@ PJ301
+3VALWP 1 2 +3VALW
1 2
keep short pad, JUMP_43X118
2 snubber is for EMI only. 2

+19VB_5V
+19VB EMI@ PL501 @ PC502
PR502
FBMA-L11-201209-800LMA50T 0.1U_0402_25V7K
1 2 +19VB_5V 1BST_5V 2 BST_5V_R 1 2
Choke 1.5uH SH00000II00, SH000008800, SH000019B00
2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6

0_0402_5% (Size:6.8 x 6.47 x 3 mm)

10U_0603_25V6M

10U_0603_25V6M

PU501

1
SY8288CRAC_QFN20_3X3 (DCR:14m~15m Ohm)
1

1
@EMI@ PC501

PC503

PC504

EMI@ PC505

@EMI@ PC506

BS
IN

IN

IN

IN
PL502
LX_5V 6 20 1.5UH_MMD-06CZ-1R5M-V1_9A_20%
2

LX LX
7 19 LX_5V 1 2
GND LX +5VALWP
8 18

https://vinafix.com
GND GND

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
+3VLP

1
1

1
9 17 VCC_5V 1 2
PG VCC

PC509

PC511

PC513
PR503

PC508

PC510

PC512
4.7_1206_5%
@EMI@
10 16 PC507

2
2

2
NC NC
1

2.2U_0402_6.3V6M
OUT

LDO
EN2

EN1

21 @
FF

PR501 GND

2
100K_0402_5%
11

12

13

14

15
2

15V_SN

680P_0402_50V7K
<58> SPOK_5V +5VLP

@EMI@
ENLDO_5V

PC514
5V LDO 150mA~300mA
4.7U_0402_6.3V6M

2
1

PC515

PR504
2.2K_0402_5% 5V_3V_EN
2

1 2 Iocp=12A
<58> EC_ON PR505
@
1 2 EN1 and EN2 dont't be floating.
3
<58,77,83> MAINPWON EN :H>0.8V ; L<0.4V PC516 PR506 @ PJ501
3
1000P_0402_50V7K 1K_0402_1% +5VALWP 1 2 +5VALW
0_0402_5% 5V_FB 1 2 5V_FB_1 1 2 1 2
Fsw : 600K Hz
JUMP_43X118
5V_3V_EN
1M_0402_1%
1

1
PR507

PC517
4.7U_0402_6.3V6M
2
2

PR509
499K_0402_1%
ENLDO_5V 1 2
+19VB
1
150K_0402_1%
PR508

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 85 of 102
A B C D E
 A B C D E

Pin19 need pull separate from +1.35VP.

+19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
@ PJM1 you can change from +1.35VP to +1.35VS. TDC 0.7A
JUMP_43X79
1
1 2 +19VB_1.2VP PRM1 Peak Current 1A 1

+19VB 1 2 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
+1.2VP

1
EMI@ PCM2

PCM4
@EMI@ PCM1

PCM3
UG_1.2VP +0.6VSP

2
PQM1
AON7408L_DFN8-5
LX_1.2VP

10U_0402_6.3V6M

10U_0402_6.3V6M
5

1
PCM5

1
PCM6

PCM7
0.1U_0402_25V7K

16

17

18

19

20
2

2
VLDOIN
PHASE

UGATE

BOOT

VTT
4 21
PAD
LG_1.2VP 15 1
LGATE VTTGND
PLM1

1
2
3
14 2
1UH_11A_20%_7X7X3_M PRM2 PGND VTTSNS
11K_0402_1% PUM1
1 2LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PCM8 CS RT8207PGQW _W QFN20_3X3 GND

1
1U_0402_10V6K

5
1 2 12 4 VTTREF_1.2VP
@EMI@ PRM3 PRM4 VDDP VTTREF
2 4.7_1206_5% 5.1_0603_5% 2
1 2 VDD_1.2VP 11 5
+5VALW +1.2VP

1 2
VDD VDDQ

1
PGOOD
PCM12
22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

TON
1
PCM9

PCM14
PCM13

PCM10

PCM15

PCM16

@EMI@ PCM11 PCM17 0.033U_0402_16V7K

FB
S5

S3

2
1
680P_0402_50V7K
2

2 PQM2 1U_0402_10V6K

10

6
AON7506_DFN3X3-8-5 PRM5

1
2
3
2.2_0402_1%

FB_1.2VP
2

TON_1.2VP

EN_1.2VP
PRM6
+5VALW

EN_0.6VSP
6.19K_0402_1%

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PRM7 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2

1
PRM8 Vout=0.75V* (1+Rup/Rdown)
<58> SYSON
SYSON 1 2 PRM9 =0.75*(1+(6.19/10))
10K_0402_1%
=1.21V

2
0_0402_5%

1
EMI@ PCM25 @ PCM18
+5VALW 33P_0201_50V8J 0.1U_0402_10V7K

2
+3VALW @ PRM10
0_0402_5%
1 2
<16,58,78,84> SUSP#
@ PJM2
3 JUMP_43X39 @ @ PJM3 3
PRM11
1

1 2 VIN_2.5V PCM19 JUMP_43X118

1 2 1U_0402_6.3V6K 1 2 1 2
+1.2VP +1.2V_VDDQ
<8> SM_PG_CTRL 1 2
2

0_0402_5%
1

1
@ PCM21 @ PJM4
PCM20 JUMP_43X39
4.7U_0402_6.3V6M 0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2

2
PUM2 1 2
G9661MF11U_SO8
@ 4 5
PRM12 VPP NC
3 6 MOSFET: 3x3 DFN
SYSON 1 2 EN_2.5V 2 VIN VO 7 +2.5VP
GND

1 VEN ADJ 8 H/S Rds(on): 27mohm(Typ), 32mohm(Max)

22U_0603_6.3V6M
0.01U_0402_50V7K

POK GND Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

1
0.1U_0402_16V7K

PCM23

0_0402_5% PRM14
9

1
1

PCM24
PCM22

PRM13
21.5K_0402_1%
Rup L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8% Idsm: 12A@Ta=25C, 10.5A@Ta=70C
2

1M_0402_5%
2

2
2

@ FB_2.5V Choke: 7x7x3

Rdc=14mohm(Typ), 15mohm(Max)
1

Mode Level +0.6VSP VTTREF_1.2V

PRM15
S5 L off off Switching Frequency: 538kHz
10K_0402_1%
Rdown S3 L off on Ipeak=7.5A
S0 H on on Iocp=Ipeak*1.2A
2

4
OVP: 110%~120% 4
@ PJM5 VFB=0.75V, Vout=1.365V
JUMP_43X39 Note: S3 - sleep ; S5 - power off
1 2 MOSFET footprint: SIS412DN
+2.5VP 1 2 +2.5V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: W ednesday, July 08, 2020 Sheet 86 of 102
A B C D E
 A B C D E

@ PJ1802
JUMP_43X39
1 2
+1.8VALWP 1 2 +1.8VALW_PRIM
1 1

Imax= 2A, Ipeak= 3A

FB=0.6V

PC1801
22U_0603_6.3V6M

1 2 PU1801 PL1801
@ PJ1801 SY8032IABC_SOT23-6
1UH_MLV-YT12N1R0M-C1L 4A_20%
+3VALW 1
JUMP_43X79
2 IN_1.8V 4 3 LX_1.8V 1 2
1 2 IN LX +1.8VALWP
1 2 5 2
+3VALW

68P_0402_50V8J
PR1801 100K_0402_5% PG GND

1
6 1

PC1802

22U_0603_6.3V6M

22U_0603_6.3V6M
FB EN

1
1

PC1803

PC1804
<91> 1.8VALW_PG

2
@EMI@ PR1802 PR1803

2
@ PR1804 0_0402_5% 4.7_0603_5% 20K_0402_1%
1 2 +1.8V_EN
<58,85> SPOK_3V

2
Rup

2
0.1U_0402_16V7K
1

PC1805
1
PR1807 0_0402_5% PR1805 FB_1.8V
1 2 1M_0402_1%
<58> EC_1.8V_EN

1
@
2

@EMI@ PC1806
680P_0402_50V7K PR1806

2
10K_0402_1%
Rdown

2
2
Note: 2
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
1.8 = 0.6*(1 + 20k/10k)

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3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/12/27 Deciphered Date 2019/12/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SY8032
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 87 of 102
A B C D E
 1 2 3 4 5

Module model information

RT3612EB_2Phase_V1A.mdd for IC portion
RT3612EB_2Phase_V1B.mdd for SW portion

A A

RT3612EBGQW-02 is MP part
+5VALW PUZ1
PRZ2 +19VB_VCCIN
6.8_0603_1% PRZ3 2.2_0805_5%
1 2 VCC_RT3612 10 22 VIN_RT3612 1 2
VCC VIN PCZ2 0.47U_0402_25V6K

2
1 2
PCZ1
4.7U_0402_6.3V6M

1
PRZ1 PRZ4 0_0402_5%
2.2_0603_1%
VRON
23 VRON_RT3612 1 2
VR_ON
High: > 0.7V
<11,58>
1 2 PVCC_RT3612 29 @ PCZ3 0.1U_0402_25V6
PVCC 1 2 Low: < 0.3V

2
PCZ4
Pull High in HW site. 4.7U_0402_6.3V6M 25
BST1_VCCIN <89>

1
BOOT1

<58> VR_HOT# PRZ5

75_0402_5% 26
VRHOT_RT3612 UGATE1 UG1_VCCIN <89>
1 2 2
VR_HOT
VREF06_RT3612 0.6V 27
VREF06_RT3612
PRZ6 PHASE1 LX1_VCCIN <89>
3.9_0402_1%
1 2 12 28
VREF06 LGATE1 LG1_VCCIN <89>

1
100K_0402_1%

105K_0402_1%
16.9K_0402_1%

PCZ5
1
1

8.2K_0402_1%
1

0.47U_0402_6.3V6K
PRZ8
PRZ7

PRZ9

PRZ10

2
B B

VR_HOT# 110 degreeC 1

2
2

BST2_VCCIN <89>
2

BOOT2
ALERT# 107 degreeC
442_0402_1%
1

PRZ15 41.2K_0402_1% 32
560_0402_1%
3.4K_0402_1%
90.9K_0402_1%

UGATE2 UG2_VCCIN <89>

1

1
1

1 2
PRZ14
PRZ11

PRZ13
PRZ12

Close to Phase1 MOS 31 LX2_VCCIN <89>

PHZ1 TSEN_RT3612 21 PHASE2
2

TSEN_RT3612_R 1 2 TSEN
2

2
2

30
LGATE2 LG2_VCCIN <89>
220K_0402_5%_B25/50 4700K
SET1_RT3612 8 PRZ16 2.61K_0603_1% PRZ17 2.1K_0603_1%
SET1 20 ISENSE1P_VCCIN_RR 1 2 ISENSE1P_VCCIN_R
1 2
ISEN1P ISENSE1P_VCCIN <89>

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SET2_RT3612 7
SET2

1
20K_0402_1%
1

15.8K_0402_1%

PRZ19
1

SET3_RT3612 6 PCZ6
4.53K_0402_1%
PRZ18

SET3
17.8K_0402_1% 510_0402_1%

+1.05V_VCCST 0.1U_0402_25V6
1
PRZ20

24K_0402_1%

2
1
PRZ21

19 ISENSE1N_VCCIN_R1 2
PRZ22

ISENSE1N_VCCIN <89>

2
ISEN1N PCZ7 0.1U_0402_25V6
2

PRZ23 681_0402_1%
2

1 2
1 2
1.5K_0402_1%
1
1

1 2

PRZ27 2.61K_0603_1% PRZ29 2.1K_0603_1%

1.5K_0402_1%

17 ISENSE2P_VCCIN_RR 1 2 ISENSE2P_VCCIN_R 1 2
PRZ25
PRZ24

ISEN2P ISENSE2P_VCCIN <89>

PRZ26

75K_0402_1%
100_0402_1%

45.3_0402_1%
1

1
1

1
PRZ30

PRZ28

PCZ8
0_0402_5%
2

0.1U_0402_25V6 PCZ9
PRZ32
PRZ31

PRZ33
2
2

0.1U_0402_25V6
2

4.53K_0402_1%

2
2

@ 18 ISENSE2N_VCCIN_R1 2
ISENSE2N_VCCIN <89>
2
2

2
ISEN2N PCZ10 0.1U_0402_25V6
1

PRZ34 681_0402_1%
PRZ35 0_0402_5% 1 2 +VCCIN
1 2 SVID_CLK_PWR_VCCIN 5
<15> SOC_SVID_CLK VCLK

2
C C

PRZ37 0_0402_5% PRZ36

1 2 SVID_DAT_PWR_VCCIN 4 100_0402_1%
<15> SOC_SVID_DAT VDIO

1
PRZ38 0_0402_5% 0_0402_5%
1 2 SVID_ALERT#_PWR_VCCIN 3 14 VSEN_VCCIN PRZ39 1 2
<15> SOC_SVID_ALERT# ALERT VSEN VCC_SENSE_VCCIN <15>
PCZ11 82P_0402_50V8J PCZ12 220P_0402_50V7K @ PCZ13
+3VS 15 COMP_VCCIN 1 2 1 2 1 2

0.082U_0402_16V7K
PRZ40 10K_0402_1% COMP
1 2 24 PRZ41 27.4K_0402_1% PRZ42 8.45K_0402_1% 330P_0402_50V7K

@ PCZ14
VR_READY

1
1 2 1 2

@ PCZ15
<58> VR_PWRGD LL=2m

2
0.47U_0402_6.3V6K 16 FB_VCCIN
1 2 FB
@PCZ16
1 2
PRZ43
16.2K_0402_1% 0.01UF_0402_25V7K
I_SYS PRZ44 0_0402_5%
Close to Phase1 Inductor 1 2 9
PSYS 13 RGND_VCCIN 1 2
RGND VSS_SENSE_VCCIN <15>
VREF06_RT3612 LL/IMON Compesation

1
PRZ45 PHZ2 PRZ46
2K_0402_1% 100K_0402_1%_B25/50 4250K 27K_0402_1% PRZ47
1 2 VCCIN_NTC1P 1 2 VCCIN_NTC1N 1 2 IMON_VCCIN 11 33 100_0402_1%
IMON GND

2
RT3612EBGQW-02_WQFN32_4X4
PRZ48
18.7K_0402_1%
1 2
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/05/15 Deciphered Date 2020/05/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCORE(RT3612EB)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
LA-K091P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 08, 2020 Sheet 88 of 102
1 2 3 4 5
 5 4 3 2 1

ICCMAX=54A
+VCCIN
TDC=25A
OCP=160% of Iccmax=86.4A
OVP=VID+0.35V=2.24V

330U_D2_2.5VY_R9M

330U_D2_2.5VY_R9M
1 1
Frequency 600KHz + +

PCZ17

PCZ18
@ 2 2
D D

+19VB_VCCIN
@
PJZ1
+19VB
<88> UG1_VCCIN
1 2
1 2

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K
JUMP_43X118

@EMI@ PCZ19

PCZ33

PCZ20

PCZ34
0.1U_0402_25V6
1 1

33U_25V_NC_6.3X4.5

33U_25V_NC_6.3X4.5
1

1
+ +

PCZ22

PCZ21
PRZ49

EMI@
2

2
2.2_0603_5% 2 2
1 2 BST1_VCCIN_R
<88> BST1_VCCIN

1
PCZ36 PQZ1

1
0.1U_0402_25V6
Rdc=0.98 mohm

D1

G1
2
+VCCIN
PLZ3
LX1_VCCIN 7 LX1_VCCIN 1 4
<88> LX1_VCCIN D2/S1
2 3

@EMI@ PRZ50
4.7_1206_5%
G2
S2

S2

S2

1
AONY36352 2N DFN5X6D
0.22UH_24A_20%_ 7X7X4_M

1 SNUB1_VCCIN 2
<88> LG1_VCCIN

ISENSE1N_VCCIN <88>

@EMI@ PCZ47
C C

680P_0402_50V7K
2
ISENSE1P_VCCIN <88>

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+19VB_VCCIN
<88> UG2_VCCIN
10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K
@EMI@ PCZ54

EMI@ PCZ55

PCZ56
0.1U_0402_25V6

PCZ57
1

PRZ51
2

2.2_0603_5%
1 2 BST2_VCCIN_R
<88> BST2_VCCIN
B B
1

PCZ58 PQZ2
2

0.1U_0402_25V6
Rdc=0.98 mohm
D1

G1
2

+VCCIN
PLZ4
LX2_VCCIN 7 LX2_VCCIN 1 4
<88> LX2_VCCIN D2/S1
2 3
@EMI@ PRZ52
4.7_1206_5%
G2
S2

S2

S2

AONY36352 2N DFN5X6D
0.22UH_24A_20%_ 7X7X4_M
3

1SNUB2_VCCIN 2

<88> LG2_VCCIN
@EMI@ PCZ59

ISENSE2N_VCCIN <88>
680P_0402_50V7K
2

ISENSE2P_VCCIN <88>

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/05/15 Deciphered Date 2020/05/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power stage-VCCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-K091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 08, 2020 Sheet 89 of 102
5 4 3 2 1
 A

D
5

5
+VCCIN
2 1 2 1

@
PCZ37 PCZ24
22U_0603_6.3V6M 22U_0603_6.3V6M
4

4
+VCCIN

2 1 2 1

PCZ38 PCZ25
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2 1
PCZ39 PCZ26
PCZ48 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ40 PCZ27
PCZ49 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ41 PCZ28
PCZ50 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
@

PCZ42 PCZ29
3

3
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PCZ51 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ43 PCZ30
PCZ52 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ44 PCZ31
PCZ53 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
+VCCIN
Date:

Size

Title

PCZ45 PCZ32
A

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
2 1
LA-K091P
Document Number

<Title>

@RF@ PCZ46 PCZ35

PCZ60
Wednesday, July 08, 2020

22U_0603_6.3V6M 22U_0603_6.3V6M
12P_0402_50V8J
2

2
2 1 2 1
@RF@
@

PCZ61 PCZ66
1U_0201 *6
22U_0603 *18
330U_R9

12P_0402_50V8J 22U_0603_6.3V6M
2 1
2 1
@RF@
@

PCZ67
PCZ62 22U_0603_6.3V6M
12P_0402_50V8J 2 1

2 1
@

PCZ68
@RF@ 22U_0603_6.3V6M
Sheet

PCZ63
*1

12P_0402_50V8J

2 1
@RF@
90

PCZ64
12P_0402_50V8J
1

1
of

2 1
@RF@
PCZ65
102

12P_0402_50V8J
Rev
0.1

D
 A B C D E

Module model information

RT6543A_V1A.mdd for IC portion
RT6543A_V1B.mdd for SW portion

1 1

BST_AUX_R +19VB

1
PRG1
2.2_0603_5% PCG1 PRG2 AUX input cap need place 5pcs +19VB_AUX
0.1U_0402_25V6 0_0805_5%

2
+19VB

2
@ PJG1
OCP is Lowside MOSFET Rdson sense

2
1 2 ICCMAX=31A

BST_AUX
1 2
TDC=14A

10U_0603_25V6M
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K
226K x1.2 JUMP_43X118

PCG6
PCG5
0.1U_0402_25V6

0.1U_0402_25V6
1
DC LL=TBD

1
255K x1.4

1
PUG1

PCG2
10
RT6543AGQW_WQFN20_3X3 AC LL=4.5

EMI@
@EMI@
PCG3
PCG36

PCG35

PCG4
PRG3

2
BOOT
191K_0402_1%
1 2 CS_DSI_RT6543 1 20 VSYS_RT6543
CS_DIS VSYS UG_AUX
+5VALW
PRG5 0_0603_5% +VCCIN_AUX
1 2 PVCC_RT6543 15 11 UG_AUX
PVCC UGATE
PQG3

1
2 1
PCG7 1U_0402_6.3V6K
Rdc=0.98 mohm

D1

G1
PRG4 5.1_0603_5%
VCC_RT6543 LX_AUX PLG1
1 2 16 12
VCC PH 7 LX_AUX 1 4
2 1 D2/S1
PCG8 1U_0402_6.3V6K ISENSEP_AUX 2 3 ISENSEN_AUX
PRG6 100K_0402_1% VCC_AUX_PWRGD

G2
High > 1V

S2

S2

S2

1
1 2 4 13 LG_AUX AONY36352 2N DFN5X6D

@EMI@ PRG7
+3VALW

4.7_1206_5%

8.87K_0603_1%
PGOOD LGATE 0.22UH_24A_20%_ 7X7X4_M
Low <0.4V

PRG8
3

6
PRG9

1 AUX_SNUB
2

1ISENSEP_AUX_R 2
2<87> 1 2 EN_RT6543 19 14 2
1.8VALW_PG EN PGND
LG_AUX
1

0_0402_5% PCG9

0_0402_5%
0.1U_0402_25V6 PRG10 0_0402_5%

@EMI@ PCG10
680P_0402_50V7K
2

VCCIN_AUX_CORE_VID1_R 17 2 ISENSEP_RT6543 1 2 ISENSEP_RT6543_R

PRG11
@ <11,17> VCCIN_AUX_CORE_VID1_R VID1 ISENSEP

8.87K_0603_1%

2
PRG12 0_0402_5%
+3VALW VCCIN_AUX_CORE_VID0_R 18 3 ISENSEN_RT6543 1 2 ISENSEN_RT6543_R

PRG13
<11,17> VCCIN_AUX_CORE_VID0_R VID0 ISENSEN
PCG11 +VCCIN_AUX
1 2 PRG15 PRG18
@ PRG14
PRG16 PRG17

2
100K_0402_1% 0.1U_0402_25V6 1 2 1 2
1 2 FSWSEL_RT6543 9 8 VOUT_RT6543 1 2 0_0402_5% 2 1

ISENSEN_RT6543_R
+5VALW FSWSEL VOUT 1.24K_0402_1% 1.5K_0402_1%
1

PCG13 PRG22 100_0402_1% PHG1

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@PRG19 PRG21
100K_0402_1% PCG12 820PF_0402_50V7K 10K_0402_1% 390P_0402_50V7K 1.6K_0402_1% ISENSEN_AUX_NTC 1 2
1

5 COMP_RT6543 1 2 1 2 1 2 1 2
COMP
10K_0402_1%_B25/50 3370K
2

PRG20 PRG23

ISENSEP_RT6543_R
10K_0402_1% 10K_0402_1%
PCG14 15P_0402_50V8J
B=3435(B25/85)
PRG24 20K_0402_1%
2

VCCIN_AUX_CORE_VID0_R FB_RT6543
6 1 2 1 2
VCCIN_AUX_CORE_VID1_R
5V: 800KHz FB 1 2

1
Float: 600KHz PRG25 PCG15
GND: 400KHz 0_0402_5% 0.1U_0402_25V6
1

7
VSS_SENSE_VCCIN_AUX <17>
AGND

RGND
@ PRG26

2
@ PRG27
10K_0402_1% 10K_0402_1%

1
VCC_SENSE_VCCIN_AUX <17>
PRG29
2

21

1
100_0402_1%
PCG16
@ PCG17 0.1U_0402_25V6
2

2
1 2

0.082U_0402_16V7K
330P_0402_50V7K

@ PCG18
1
3 3

2
VCCIN_AUX VID Follow Intel PDG Rev0.71 @PCG19
1 2
330U_R9 *1
VID1 VID0 +VCCIN_AUX 0.01UF_0402_25V7K 22U_0603 *13
Voltage +VCCIN_AUX
0 0 0

0 1 1.1 +VCCIN_AUX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 0 1.65

1
1

1
1

1
PCG20

PCG21

PCG22

PCG24

PCG27
PCG23

PCG25

PCG26

PCG28

PCG29
1 1 1.8

2
2

2
2

2
330U 2.5V Y D2 LESR9M

330U 2.5V Y D2 LESR9M

1 1
+ +

PCG30

PCG31
2 2
@

+VCCIN_AUX

22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1
1
1

1
1

1
PCG46
PCG47
PCG32

PCG44

PCG43
PCG33

PCG34

PCG45
2
2
2

2
2

2
@RF@ @RF@ @RF@ @RF@
@RF@ @RF@
@ @ @ @ @
12P_0402_50V8J

12P_0402_50V8J

12P_0402_50V8J

12P_0402_50V8J
12P_0402_50V8J

12P_0402_50V8J
1

1
1

1
PCG42

PCG41

PCG40

PCG37
PCG39

PCG38
2

2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/05/15 Deciphered Date 2020/05/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCCIN_AUX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-K091P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 08, 2020 Sheet 91 of 102
A B C D E
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A <Doc> <RevCode>

Date: Wednesday, July 08, 2020 Sheet 92 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A <Doc> <RevCode>

Date: Wednesday, July 08, 2020 Sheet 93 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A <Doc> <RevCode>

Date: Wednesday, July 08, 2020 Sheet 94 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A <Doc> <RevCode>

Date: Wednesday, July 08, 2020 Sheet 95 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A LA-K092P 0.1

Date: Wednesday, July 08, 2020 Sheet 96 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A LA-K092P 0.1

Date: Wednesday, July 08, 2020 Sheet 97 of 102

5 4 3 2 1
 5 4 3 2 1

D D

PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A LA-K092P 0.1

Date: Wednesday, July 08, 2020 Sheet 98 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A LA-K092P 0.1

Date: Wednesday, July 08, 2020 Sheet 99 of 102

5 4 3 2 1
 5 4 3 2 1

D D

C
PWR-Reserve Page C

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B B

A A

Title
<Title>

Size Document Number Rev

A LA-K092P 0.1

Date: Wednesday, July 08, 2020 Sheet 100 of 102

5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for

PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
New version charger p84 Change PUB1 from BQ24781(SA0000A6B00) to BQ24800(SA000D7R00) 02/10 Pre-EVT
01
Change PCG12 from 820P 25V K X7R 0402(SE000008980) to 820PF 50V K X7R 0402(SE000003W00)
sourcer request p91 p84 Change PCB18 from 2.2U 25V K X5R 0603(SE00000WP00) to 2.2U 16V K X5R 0603(SE000006S80) 04/10 EVT
D 02 p82 p86 Change PC102 from 100P 50V J NPO 0402(SE071101J80) to 100P 50V J NPO 0201(SE00000SE00)
D

p83 Change PCM25 from 33P 50V J NPO 0402(SE071330J80) to 33P 50V J NPO 0201(SE00000TB00)
Change PCM23,PCB13,PC202 from .01U 25V K X7R 0402(SE075103K80) to .01U 50V K X7R 0402(SE074103K80)

p88
03 CPU transient test Change PRZ14 from 1.74K +-1% 0402(SD034174180) to 442_0402_1%(SD034442080) 04/10 EVT
Change PRZ28 from 15K +-1% 0402(SD034150280) to 75K +-1% 0402(SD034750280)
Change PRZ46 from 30.9K +-1% 0402(SD034309280) to 27K +-1% 0402(SD034270280)
CPU transient test p88 Change PRZ9 from 750_0402_1% 0402(SD034750080) to 105K_0402_1%(SD034105380) DVT
Change PRZ26 from 680 +-1% 0402 (SD034680080) to 17.8K +-1% 0402(SD034178280) 06/09
Change PCZ12 from 330P 50V K X7R 0402(SE074331K80) to 220P 50V K X7R 0402(SE074221K80)
04
05 0 ohm shortpad p86 88 89 PRG9,PRM8,PRZ4 depop 06/09 DVT
1.8v Enable control , HW comfirm use PR1807
06 Del PR1804 p87 Pop PR1807, Depop PR1804 06/16 PVT

07

08
C C

09

10
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11

B B
12
13

14
15

16
17

18

A A

19

Security Classification
2018/12/27
Compal Secret Data
2019/12/27 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K091P
Date: Wednesday, July 08, 2020 Sheet 101 of 102
5 4 3 2 1
 5 4 3 2 1

D D

C C

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B B

A A

Title
<Title>

Size Document Number Rev

A LA-K091P 0.1

Date: Wednesday, July 08, 2020 Sheet 102 of 102

5 4 3 2 1