Microprocessor lectures Timing Diagram 9 lecture

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Timing Diagram
Lecture objectives: at the end of this lecture the student will able to:
1- Define the timing diagram.
2- Study and representation of the clock signal.
3- Determine the types of 8085 machine cycles.
9.1 Some of Definitions:
9.1.1 Timing Diagram: Timing diagram is the display of initiation of read/write and
transfer of data operations under the control of 3-status signals
IO / M , S1, and S0.
9.1.2 Instruction Cycle: It is fetching, decoding and executing of a single instruction,
which consists of one to five read or writing operations
between processor and memory or IO devices.
9.1.3 Machine Cycle: It is the one cycle that required to move one byte of data in or
out of the microprocessor. Each one machine cycle consists 3 to
6 clock period, referred to as T-state.

9.1.4 T-state: It is the time of one clock period which depends on operating
frequency. Another definition of the T-state is a portion of an operation
carried out in one system clock period.
There are seven different types of machine cycles in 8085A. Table 9.1 show these types
which its identified depend on status signals IO / M , S 1, and S0. These signals are
generated at the beginning of each machine cycle and remained valid for the duration of
the cycle.
9.2 Clock Signal:
The 8085 divide the clock frequency provided by X1 and X2 inputs by 2 which is
called operating frequency. Ideally, the clock signals should be square wave with zero
rise time and fall time, but practically, cannot get zero rise time and fall time. Therefore,
the clock and other signals are always shown with finite rise and fall times see Fig. 9.1.

Table 9.1: Machine cycle status and control signals.

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(a) (b)
Figure 9.1: Clock signal representation; a)ideal, b) Practical

9.2.1 Single and group of signals:

Single signal is represented by a line. It may have status either logic 0 or
logic 1 or tri-state as in Fig. 9.2. While, group of signals is also called a bus e.g.
address bus and data bus. To avoid complications in the timing diagram these
signal are grouped and shown in the form of block as shown in Fig. 9.3.

Figure 9.2: Single signal representation.

Figure 9.3: Group of signals representation.

9.2.2 Signal Timing:

In 8085 microprocessor, signals are activated at specific instant for specific
time period. Once we understand this, it is very easy to draw timing diagram.
Examples below explain ALE signals activation and what period they remain in
active state.
Ex.1/ALE is active high signal. It is activated in the beginning of T1 state of machine
cycle, except bus idle machine cycle, and it remain active in T1 state only as shown in
Fig. 9.4

Figure 9.4: ALE activation and its period.

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Ex.2/ A0-A7 (Lower Byte Address) is available on the multiplexed address/data bus
(AD0-AD7) during T1 state of machine cycle, except bus idle machine cycle as shown in
Fig. 9.5. below:

Figure 9.5: Lower address on the multiplexed bus.

Ex.3/ D0-D7 (Data Bus) it used to transfer the data from IO devices or memory to
microprocessor or from microprocessor to IO device or memory during T 2 and T3 states.
It is important to note that through reading data operation, the data will appear on the data
bus during the later part of the T2 state. while, in writing data operation the data will
appear on data bus at the beginning of T2 state, see Fig. (9.6 a & b).

Figure 9.6: Data bus status; a) through reading operation, b) through writing operation.
Why there are difference in appearing of data on data bus through reading and writing
operation.

Ex.4/ A8-A15 (Higher Byte Address) is available on the address bus during T1, T2, and T3
states of each machine cycle, except bus idle machine cycle s shown in Fig. 9.7. below:

Figure 9.7: Higher byte address status.

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Ex.5/ IO/M, S1, S2 signals are called status signals. They determine the type of machine
cycle to be executed. They are activated at beginning of T1-state of each machine cycle
and remain active till the end of the machine cycle as shown in Fig. 9.8.

Figure 9.8: Status signals timing diagram.

Ex.6/ RD and WR are determine the direction of data follow between microprocessor and
IO devices or memory locations. As we noted that these signals activated through T2 & T3
states of machine cycle. Both signals are never active at a time. The Fig. 9.9 shows the
timing diagram of RD and WR signals.

Figure 9.9: Read and write signals timing diagram.

9.3 8085 Machine Cycles and their Timings:
The 8085 has seven machine cycle. These are:
1. Opcode fetch.
2. Memory read.
3. Memory write.
4. I/O read.
5. I/O write.

9.3.1 Opcode Fetch Cycle:

The first machine cycle of every instruction is opcode fetch cycle in which
the 8085 finds the nature of the instruction to be executed. In this machine cycle,
the microprocessor places the contents of PC on the address bus then by reading
operation it reads the opcod of an instruction from determined memory location.
The length of this cycle is not fixed. Steps below explain opcode fetch cycle in

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more details. Figure 9.10 shows the timing diagram and data flow of opcod fetch
cycle.

 Step1: (T1 state) The 8085 processor places the contents of program
counter on the address bus, activate the ALE and send the status signals
IO/M, S1, and S0 with logical status (0 1 1) respectively.
 Step 2: (T2 state) The low order address disappears from AD0-AD7 lines.
Also, 8085 processor activates the RD signals to enable the addressed
memory location which places its contents on the data bus (AD0-AD7).
 Step 3: (T3 state) The processor loads the contents of data bus on its
Instruction Register and deactivates the RD signal to disables the memory
devices.
 Step4: (T4 state) the processor decode the opcode, and on the basis of the
instruction received, it decides whether to enter T5 or to enter T1 of new
machine cycle. One byte instructions those operate on eight bit data (8 bit
operand) are executed in T4. for example: MOV C,B- ANA E- ADD B-
INR C- RAR …etc.
 Step5: (T5 & T6 states) the processor performs stack write, internal 16
bits, or conditional return operations depending upon the type of
instruction. One byte instructions those operate on 16 bit data are executed
in T5 & T6. For example DCX H, PCHL, SPHL, INX H, etc.

Figure 9.10: details of opcode machine cycle.

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9.3.2 Memory read cycle:

The microprocessor executes the memory read cycle to read the data from
RAM or ROM memory. 8085 processor executes this machine cycle in 3 T-states.
Steps below show the details of this machine cycle:

 Step1 (T1 state): processor places the address on the address lines from SP,
Rp, or PC and activates ALE in order to latch low-order of address. Also, it
sends the status signals with logical status (0 1 0) for memory read machine
cycle.

 Step2 (T2 state): , 8085 processor activates the RD signals to enable the
addressed memory location which places its contents on the data bus (AD0-
AD7).

 Step 3: (T3 state) The processor loads the contents of data bus on specified
register (F, A, B, C, D, E, H, and L) and deactivates the RD signal to disables
the memory devices.

Figure 9.11 shows the timing diagram and data follow for read memory
machine cycle.

Figure 9.11: details of memory read machine cycle.

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9.3.3 Memory write cycle:

The microprocessor executes the memory write cycle to store the data into
RAM or stack memory. 8085 processor executes this machine cycle in 3 T-states.
Steps below show the details of this machine cycle:

 Step1 (T1 state): processor places the address on the address lines from SP or
Rp and activates ALE in order to latch low-order of address. Also, it sends
the status signals with logical status (0 0 1) for memory write machine cycle.

 Step2 (T2 state): , 8085 processor places tha data on data bus and activates
the WR signal to writing data into addressed memory location.

 Step 3: (T3 state) The processor deactivates the WR signal which disables
the memory device and terminates the write operation.

Figure 9.12 shows the timing diagram and data follow for memory write machine
cycle.

Figure 9.12: details of memory write machine cycle.

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9.3.4 IO read cycle:

The microprocessor executes the IO read cycle to read the data from input
device. 8085 processor executes this machine cycle in 3 T-states. Steps below show
the details of this machine cycle:

 Step1 (T1 state): processor places the address on the address lines from SP,
Rp, or PC and activates ALE in order to latch low-order of address. Also, it
sends the status signals with logical status (1 1 0) for IO read machine cycle.

 Step2 (T2 state): , 8085 processor activates the RD signals to enable the
addressed input device which places its contents on the data bus (AD0-AD7).

 Step 3: (T3 state) The processor loads the contents of data bus on specified
register (F, A, B, C, D, E, H, and L) and deactivates the RD signal to disables
the input device.

Figure 9.13 shows the timing diagram and data follow for IO read machine
cycle.

Figure 9.13: details of IO read machine cycle.

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9.3.5 IO write cycle:

The microprocessor executes the IO write cycle to store the data into output
device. 8085 processor executes this machine cycle in 3 T-states. Steps below show
the details of this machine cycle:

 Step1 (T1 state): processor places the address on the address lines from SP or
Rp and activates ALE in order to latch low-order of address. Also, it sends
the status signals with logical status (1 0 1) for IO write machine cycle.

 Step2 (T2 state): , 8085 processor places the data on data bus and activates
the WR signal to writing data into addressed output device.

 Step 3: (T3 state) The processor deactivates the WR signal which disables
the output device and terminates the writing operation.

Figure 9.14 shows the timing diagram and data follow for IO write machine cycle.

Figure 9.14: details of IO write machine cycle.

.
Draw and explain the timing diagram of MOV B,C instruction.

T1 : The 1st clock of 1st machine cycle (M1) makes ALE high indicating address latch
enabled which loads low-order address (00 H) on AD7 ⇔ AD0 and high-order
address (10 H) simultaneously on A15 ⇔ A8. The address 00H is latched in T1.
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T2 : During T2 clock, the microprocessor issues RD control signal to enable the memory
and memory places 41H from 1000H location on the data bus.

T3 : During T3, the 41H is placed in the instruction register and RD = 1 (high) disables
signal. It means the memory is disabled in T3 clock cycle. The opcode cycle is
completed by end of T3 clock cycle.

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T4 : The opcode is decoded in T4 clock and the action as per 41H is taken accordingly. In
other word, the content of C-register is copied in B-register as shown in Fig.9.18
below. Execution time for opcode 41H is:
Clock frequency of 8085 = 3.125 MHz
Time (T) for one clock = 1/3.125 MHz = 0.32 μS
Execution time for opcode fetch = 4T = 4*0.32 μS = 1.28 μS.

Figure 9.18: Timing diagram for MOV B,C instruction.

Example2:
The MVI B,05H instruction requires 2-machine cycles (M1 and M2). M1 requires 4-
states and M2 requires 3-states, total of 7-states as shown in Fig. 9.19. Status signals
IO/M, S1 and S0 specifies the 1st machine cycle as the op-code fetch.
T1: The high order address {10H} is placed on the bus A15 ⇔ A8 and low-order
address {00H} on the bus AD7 ⇔ AD0 and ALE = 1.
T2: The RD line goes low, and the data 06H from memory location 1000H are placed on
the data bus. The fetch cycle becomes complete in.
T3: The instruction is decoded.
T4: During T4-state, the contents of the bus are unknown.

With the change in the status signal, IO/M = 0, S1 = 1 and S0 = 0, the 2nd machine cycle
is identified as the memory read. The address is 1001H and the data byte [05H] is fetched
via the data bus. Both M1 and M2 perform memory read operation, but the M1 is called
op-code fetch i.e., the 1st machine cycle of each instruction is identified as the opcode
fetch cycle. Execution time for MVI B,05H i.e., instruction cycle time is:

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Clock frequency of 8085 = 3.125 MHz

Time ( T ) for one clock = 1/3.125 MHz = 0.32 μS.
Time for Opcode Fetch = 4T = 4*0.320 μS = 1.28 μS.
Time for Memory Read = 3T = 3*0.320 μS = 0.96 μS.
Total Execution time for Instruction = 1.28 +0.96 = 2.24 μS.

Figure 9.19: Timing diagram for MVI B,05 instruction.

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