COUNTERS 12.1. INTRODUCTION A digital counter is a set of flip-flops (FFs) whose states change in response to pulses applied at the input to the counter. The FFS are interconnected such that their combined state at any time is the binary equivalent of the total number of pulses that have occurred up to that time. Thus, as its name implies, a counter is used to count pulses. A counter can also be used as a frequency divider to ~~ obtain waveforms with frequencies that are specific fractions of the clock frequency. They are also used to perform the timing function as in digital watches, to cr me delays, to produce non-sequential binary counts, to generate pulse trains, and to act as frequency counters, etc. Counters may be asynchronous counters or synchronous counters. Asynchronous counters are also called ripple counters. The ripple counter is the simplest type of countér, the easiest to. design and requires the least amount of hardware. In ripple counters, the FFs within the counter are not made to change the states at exactly the same time. This is because the FFs are not triggered simultaneously. The clock does not directly control the time at which every stage changes state. An asynchronous counter uses TEES to perform a counting function. The actual hardware used is usually J-K FFs connected fn toggle mode, i.e. with Js and Ks connected to logic 1. Even D FFs may be used here. ‘The asynchronous counter has a disadvantage, in so far as the unwanted spikes are concerned. This limitation is overcome in parallel counters. The asynchronous counter is called ripple counter. V~ because when the counter, for example, goes from 1111 to 0000, the first stage causes the second to flip, the second causes the third to flip, and the third causes the fourth to flip, and so on. In other 527ast stage. In doing So, many int, rough to the last stage any in twill AND during any state, a brief spike watt 1 to 0000. Ripple counters are a the 528 FUNDAMENTALS OF DIGITAL CIRCUITS he first stage ripples th .d. If there is a gate thal / me the counter goes from 111 words, the transition of th stages are briefly entere: . seen at the gate output every ti called serial or series counters. Synchronous ¢ unters are clocked such that each FF in / iL c -s. Synchronous cot the se series 's triggered at the same “This is accomplished by connecting the clock line to each stage of, igge s accomplished by ¢| "Unter i ihe same time. ° oY coun er. Synchronous counters are faster than asynchronous counters, because the prop; i d is less. — delay involved i Ie yrqnous and asynchronous counters is given #8 Tale 121 ‘Table 12.1. Synchronous versus asynchronous counters ‘Asynchronous counters Synchronous counters 1. In this type of counter there is no connectigg between the output of first FF and clock inp of next FF and so on. 1. In this type of counter FFs are connected in such a way that the output of first FF drives the clock for the second FF, the output of the second the clock of the third and so on. 2. All the FFs are not clocked simultaneously. 3. Design and implementation is very simple even for more number of states. All the FFs are clocked simultaneously, . Design and implementation becomes and complex as the number of states i Since clock is applied to all the FFs simultaneously the total propagation delay js ‘equal to the propagation delay of only one Hence they are faster. 4. Main drawback of these counters is their low 4: speed as the clock is propagated through a number of FFs before it reaches the last FF. rg} ‘Acounter may be an up-counter or a down-counter. An up-counter is a counter which cou in the upward direction, i.€ 0, T, 2, W_A down-counter is a counter which counts in the downward direction, i.e. N,N 1, N—2,N—3, ..., 1, 0. Each of the counts of the counter is ca the state of the counter. The number of states through which the counter passes before returning: the starfig state is called the modulus of the counter. Hence, the modulus of a counter is equal to the total number of distinct states (counts) including zero that a counter can store. Jn other wor the number of inpui pulses that causes the counter to reset to its initial count is called the mod of the counter. Since a 2-bit counter has 4 states, it is called a mod-4 counter. It divides the i clock signal frequency by 4, therefore, it is also called a divide-by-4 counter. It requires two _ASimilarly, a 3-bit counter uses 3 FFs and has 2° = 8 states. It divides the input clock frequency 23, i.e. 8. In general, an n-bit counter will have n FFs and 2" states, and divides the input freq by 2". Hence, it is a divide-by-2” counter. A counter may have a shortened modulus. This type of counter does not utilize all the possi states. Some of the states are unutilized, i.e. invalid. The number of FFs required to construct mod-N counter equals the smallest for which NS 2". A mod-N counter divides the input trequeney_ by N, hence, it is called a divide-by-N-counter In an asynchronous counter, the invalid states are bypassed by providing a suitable feedback. In a synchronous counter, the invalid states are taken care of by treating the corresponding excitations as don’t cares. The least Significant bit (LSB) of any counter is that bit which changes most often. In ripple counters, the LSB is the Q output of the FF to which the external clock is applied. =COUNTERS 529 Acounter which Boes through all the possible states before restarting is called the full modulus | counter. A counter in which the maximum number of states can be changed is called the variable ues. counter. The final state of the counter sequence is called the terminal count. ck-out: In shortened-modulus counters, there may occur the problem of lock-out. Sometimes 7 when the counter is switched on, or any time during counting, because of noise spikes, the counter ‘g may find itself in some unused (invalid) state. Subse, uulses may cause the counter to move from one unused state to another unused state and the counter may never come to a valid state. So, the counter becomes useless. A counter whose unused states have this feature is said to suffer from the problem of lock-out. To ensure that, at ‘start-up’ the counter is in its initial state, external logic circuitry is provided which properly resets each FF. The logic circuitry for presetting the counter to its initial state can be provided either by obtaining an expression for reset/preset for the FFs or by modifying the design such that the counter goes from each invalid state to the init state after the clock pulse. So, no don’t cares are permitted in this d 2<2 Combination of modulo counters: A single FF is a mod-2 countr, We can have a counter of any modulus by choosing an appropriate number of FFs and providing proper feedback. Counters of different mods can be combined to get another mod counter. For example, a mod-2 counter and amod-5 counter can be combined to get a mod-10 counter; a mod-5 counter and a mod-4 counter can be combined to get a mod-20 counter, and so on. The connection between the individual counters may be a ripple connection, or the counters may be operated in synchronism with one another independently of whether the individual counters are ripple or synchronous. Further, we are at liberty to choose the order of the individual counters in a chain of counters. Such permutations will not change the modulus of the composite counter but may well make a substantive difference in the code in which the counter state is to be read. SEE Wed 4D C243" | Qo bE er 2 12.2 ASYNCHRONOUS COUNTERS ts a CUS) ay 2 12.2.1 Two-bit Ripple Up-counter Using Negative Edge-triggered Flip-Flops — The 2-bit up-counter counts in the order 0, 1, 2, 3, 0, 1, .... ie. 00, O1, 10, 11, 00, O1,.... ete. Figure 12.1 shows a 2-bit ripple up-counter, using negative edge-triggered J-K FFs, and its timing diagram. The counter is initially reset to 00. When the first clock pulse is applied, FF, toggles at the negative-going edge of this pulse, therefore, Q, goes from LOW to HIGH. This becomes a positive- going signal at the clock input of FF, So, FF, is not affected, and hence, the state of the counter after one clock pulse is Q, = | and Q, = 0, ie. O1. At the negative-going edge of the second clock pulse, FF, toggles. So, Q, changes from HIGH to LOW and this negative-going signal applied to CLK of “FP, activates FF,, and hence, Q, goes from LOW to HIGH. Therefore, Q, = 0 and Q, = I, ie, 10s the Slate of the counter after the second clock pulse. At the negative-going edge of the third clock pulse, FF, toggles. So Q, changes from a 0 to a 1. This becomes a positive-going signal to FF, hence, FF, is not affected. Therefore, Q, = 1 and Q, = I, ie. 11 is the state of the counter after the third clock Pulse. At the negative-going edge of the fourth clock pulse, FF, toggles. So, Q, goes from a 1 t0.a0. This negative-going signal at Q, toggles FF,, hence, Q, also changes from a I to a 0. Therefore, Q = and Q, =0, ie. 00 is the state of the counter after the fourth clock pulse. For subsequent clock pulses, the counter goes through the same sequence of states. So, it acts as a mod-4 counter with Q, as the LSB and Q, as the MSB. The counting sequence is thus 00, 01, 10, 11, 00, 01,.... ete. ee Seay? OE 530 atts orpiciraccincurrs (7 a, "®.o §) 1D) (b) Timing diagram A 2-bit down-counter counts in the order 0, 3, 2, 1, 0, 3,.... ie. 00, 11, 10,0 M dt Figure 12:2 shows a 2-bit ripple down-counter, using negative-edge triggered J- Shop rr, Hop Fe, a kK, at | K. ab Q, Oe. OD. ea oI @c (@) Logic diagram pom \\ 7102 445 9) Timing diagram ae Figure 12.2 Asynchronous 2-bit down-counter using negative edge-triggered flip-flops. For down counting, Q, of FF, is connected to the clock of FF,. Let initially all'the reset, ie, let the count be 00. At the negative-going edge of the first clock pulse, FF goes from a 0 to a 1 and Q, goes from a | to a 0. This ne; clock input of FF,, toggles FF, and, therefore, Q, goes fr Q = 1 and Q, = 1, i.e. the state of the counter is 11. At the pulse, Q, changes from a 1 to a0 and Q from aOtoal, affect FF, and, therefore, Q, remains at a 1. Hence, pulse is 10. At the negative-going edge of the third toa 1 and Q, froma | toa0. This negative-going si; a1 toa 0. Hence, the state of the counter after th edge of the fourth clock pulse, FF, toggles. So, Q, positive-going signal at Q, does not affect FF,. counter after the fourth clock pulse is 00. For su same sequence of states, i.e. the counter counts in 1 gative-going signal at Q, applie ‘om a 0 to a 1. So, after one clocl negative-going edge of the's This positive-going signal at Q, the state of the counter after the clock pulse, FF, toggles, So, Q, goes ignal at Q, toggles FF, and, so, Q, chaig ¢ third clock pulse is 01. At the negative 1, 80es from a 1 to a0 and Q, from a 0to So, Q, remains at a 0. Hence, the s! a ‘quent clock pulses the counter goes th the order 00, 11, 10, 01, 00, and Ite 12.2.3 Two-X \YV counters 531 red to choose the direction ora bidirectional counter, So, a control signal or a mode signal M is re then M = 0 for down of count. When M = 1 for up counting, Q, is transmitfed to clock of FF, and w ¢ transmitted to clock of FF}. This is achieved by using two AND gates and one OR counting, Q, is an gate as shown in Figure 12.3. The external clock signal is applied to FF,. Clock signal to FF, = (Q, Up) #(@, : Down) = QM + O,M ) Ole 42 1 oe OTF r! 0: be \ Yr" at Je > FF, it clk ‘ LoS Figure 12.3 Asynchronous 2-bit up-down!counter using negative edge-triggered flip-flops. bit Ripple Up-counter Using Positive Edge-triggered Flip-Flops ve edge-triggered J-K FFs, and its timing diagram are shown in Figure 12.4. The Q, output of the first FF is ‘connected to the clock of FF,. The external Glock signal is applied to the first flip-flop FF,. The FF, toggles at the positive-going edge of each clock pulse and FF, toggles whenever Q, changes froma 0 toa 1. State transitions occur at the positive-going edges of the clock pulses. The counting sequence is 00, 01, 10, 11, 00, O1, ete. Invgiod tape es d! 7 12.2.4 Two-l ‘A 2-bit ripple up-counter, using pos 1 9 a 1 Toa | 5, oh cu] tL ge 8 k, al ym |G (a) Logic diagram Figure 12.4 Asynchronous 2-bit up-coun pown-counter Using Positive Edge-triggered Flip-Flops edge-triggered J-K FFs, and its timing diagram are ‘st FF is connected to the clock of FF,, The external he positive-going edge of each clock pulse. The 1. The counting sequence is 00, 11, 10, 01, 00, ter using positive-edge tfiggered J-K flip-flops. 12.2.5 Two-bit Ripple er, using positive Q, output of the fir 'F,. The FF, toggles att m a0 toa A 2-bit ripple down-count shown in Figure 12.5. The clock signal is applied to Fi FF, toggles whenever Q, changes fro IL... etc.532 FUNDAMENTALS OF DIGITAL Cll » 1 AMours cLK ye taal Q, FF, celal w &E Q, 0 (a) Logic diagram Figure 12.5 Asynchronous 2-bit down-counter using positive edge 12.2.6 Two-bit Ripple Up/Down Counter Using Positive Edge-triggered Flip-Flop, Figure 12.6 shows a 2-bit ripple up/down counter using positive edge-triggered J-K FFs. ¥ M = 1 for up counting, Q, is transmitted to the clock of FF, and when M = 0 for down counting. is transmitted to the clock of FF. This is achieved by using two AND gates and one OR shown in Figure 12.6. . : Clock signal to FF, = (Q, - Up) + (Q, - Down) = QM+Q,M . yp mole A 1 1 o oe ° ° V7 Hs, Q, He Qf- CLK oO FF, Ky + dd Figure 12.6 Logic diagram of a two-bit ripple up/down counter usi ts rooees r using positive edge-trigger oon ) 12.3 DESIGN OF ASYNCHRONOUS COUNTERS ens aot To design an asynchronous‘counter, first write the counting sequence, then tabulate the values reset signal R for various states of the counter and obtain the minimal expression for R or Rus K-map or any oth ethod. i a R mee 'y othér method. Provide a feedback such that R or R resets ail the FFs after the d 12.3.1 Design of a Mod-6 Asynchronous Counter Using T FFs A mod-6 counter has six stable states 000, 001, 010, O11, 100, and 101. When the sixth pulse is applied, the counter temporarily goes to 110 state, but immediately resets to 000 becaus of the feedback provided, It is a ‘diyide-by-6 counter’, in the sense that it divides the input clock frequency by 6. It requires three FFs, because the smallest val isfyi ndit Restscney by Gilt requis . e alue of 7 satisfying the conditi NE 2] is n = 3; three FFs can have eight possible states, out of which only six are utilized the Femaining two states 110 and 111, are invalid. If initially the counter is in 000 state,