Digital Logic Design

Chapter 6

Counters
 Introduction: Counters
 Counters are circuits that cycle through a specified
number of states.
 Two types of counters:
• synchronous (parallel) counters
• asynchronous (ripple) counters
 Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.
 Synchronous counters apply the same clock to all
flip-flops.
 Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not change states at
exactly the same time as they do not have a common clock
pulse.
 Also known as ripple counters, as the input clock pulse
“ripples” through the counter – cumulative delay is a
drawback.
 n flip-flops  a MOD (modulus) 2n counter. (Note: A MOD-
x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input clock
frequency by the MOD number of the counter, hence a
counter is also a frequency divider.
 Asynchronous (Ripple) Counters
Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock input of the
next more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K
FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00  01  10  11  00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0
Asynchronous (Ripple) Counters
Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
 Asynchronous (Ripple) Counters
Example: 4-bit ripple binary counter (negative-edge triggered).

HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3
Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (ripple-clocked)
binary counter.
 If the accumulated delay is greater than the clock pulse,
some counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
Example

• A flip‐flop has a 3ns delay from the time the clock edge occurs
to the time the output is complemented.
a. What is the maximum delay in a 10‐bit binary ripple counter
that uses these flip‐flops?
b. What is the maximum frequency of the first clock at which
the 10‐bit binary ripple counter can operate reliably?

Solution
a. The worst case is when all 10 flip-flops are complemented.
The maximum delay is 10 x 3ns = 30 ns.
1
b. The maximum frequency is 𝑓 = = 33.3𝑀𝐻𝑧
30𝑛𝑠
 n
Asyn. Counters with MOD no. < 2
 States may be skipped resulting in a truncated sequence.
 Technique: force counter to recycle before going through all of
the states in the binary sequence.
 Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)

Q J Q J Q J
All J, K C CLK B CLK A CLK
inputs are 1 Q K Q K Q K
CLR CLR CLR
(HIGH).
B
C
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs are Q K Q K Q K
CLR CLR CLR
1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by clearing
B (a MOD-8 binary
counter) when count
C
of six (110) occurs.
NAND 1
Output 0
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d): Counting sequence of circuit (in CBA
order).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 0 0
C 0 0 0 0 1 1 0 0
NAND 1
Output 0

111 000
Temporary 001
state
Counter is a MOD-6
110 010 counter.

101 011
100
 n
Asyn. Counters with MOD no. < 2
 Decade counters (or BCD counters) are counters with
10 states (modulus-10) in their sequence.
 They are commonly used in daily life
 Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR
 n
Asyn. Counters with MOD no. < 2
 Asynchronous decade/BCD counter (cont’d).

HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D 0
0 1 0 1 0 1 0 1 0 1
C 0 0 1 1 0 0 1 1 0 0 0

B 0 0 0 0 1 1 1 1 0 0 0

A 0 0 0 0 0 0 0 0 1 1 0

NAND
output
 Asynchronous Down Counters
 So far we are dealing with up counters. Down counters, on
the other hand, count downward from a maximum value
to zero, and repeat.
 Example: A 3-bit binary (MOD-23) down counter.
1
Q0 Q1 Q2 3-bit binary
J Q J Q J Q
CLK C C C up counter
K Q' K Q' K Q'

1
Q0 Q1 Q2 3-bit binary
J Q J Q J Q
CLK C C C down counter
K Q' K Q' K Q'
Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.
000
001 111
1
Q0 Q1 Q2
J Q J Q J Q 010 110
CLK C C C
K Q' K Q' K Q'
011 101
100

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2 0 1 1 1 1 0 0 0 0
 Cascading Asynchronous Counters
 Larger asynchronous (ripple) counter can be constructed
by cascading smaller ripple counters.
 Connect last-stage output of one counter to the clock input
of next counter so as to achieve higher-modulus operation.
 Example: A modulus-32 ripple counter constructed from a
modulus-4 counter and a modulus-8 counter.

Q0 Q1 Q2 Q3 Q4

J J J J J
Q Q Q Q Q
CLK C C C C C
Q' Q' Q' Q' Q'
K K K K K

Modulus-4 counter Modulus-8 counter

Cascading Asynchronous Counters
 Example: A 6-bit binary counter (counts from 0 to 63)
constructed from two 3-bit counters.
A0 A1 A2 A3 A4 A5

Count 3-bit 3-bit

binary counter binary counter
pulse

A5 A4 A3 A2 A1 A0
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 : : :
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 0 1
: : : : : :
 Cascading Asynchronous Counters
• Multiple decade counters can be constructed by connecting
BCD counters in cascade, one for each decade.
• A three‐decade counter is shown below .
 Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are clocked at
the same time by a common clock pulse.
 We can design these counters using the sequential logic
design process.
 In a synchronous binary counter, the flip‐flop in the least
significant position is complemented with every pulse.
 A flip‐flop in any other position is complemented when all
the bits in the lower significant positions are equal to 1.
00 01

11 10
 Synchronous (Parallel) Counters
 Note that in a binary counter, since the output of the first flip flop is
complemented every clock cycle J0 and K0 becomes 1.
 The nth bit (shown underlined) is always complemented whenever the
previous flip flops output becomes 1
011…11  100…00
or 111…11  000…00
 Hence, Xn is complemented whenever
Xn-1Xn-2 ... X1X0 = 11…11.
 As a result, if T flip-flops are used, then
TXn = Xn-1 . Xn-2 . ... . X1 . X0
 Synchronous (Parallel) Counters
 Example 1: 2-bit synchronous binary counter (using T flip-
flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
state state inputs
A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1 TA1 = A0
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1
1

A0 J A1
J Q Q
C C
K Q' K Q'

CLK
Synchronous (Parallel) Counters
 Example 2: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 k TA1 = A0 TA0 = 1

1
CP

J K J K J K
Q Q Q

A0
 Synchronous (Parallel) Counters
 Example 3: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1
A1.A0
1 A2.A1.A0

A0 A1 A2 A3
J Q J Q J Q J Q
C C C C
Q' Q' Q' Q'
K K K K

CLK
 General Counter Design
 For binary counter it is easy to design. The next flip flop
output will complement if all the previous flip flop output
becomes 1. But for irregular counter(counting like
2764 and back to 2) it becomes complicate to
determine the flip flops input.

 Here are the general steps to design a counter:

1. Determine the type and number of flip flop.
2. Write the excitation table of the flip flop
3. Determine the state diagram
4. Determine the state table.
5. Determine the simplified Boolean equations to the the inputs
of the flip flops.
6. Draw the logic circuit.
 General Counter Design
• Example 1: Design synchronous counter that counts
01  3  2  6  7  5  4 and back to 0 using JK Flip flop.
Solution:
Step 1: Type of flip flop: JK
Number of flip flops required: 3 since it is MOD 8 counter.
MOD=2n where n is number of flip flop
and it can count from 0 up to Mod-1
Step 2: Excitation table of JK Flip flop:

Output Transition Flip flop Input

Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
 General Counter Design
• Step 3: State diagram of the counter

000

110 011
 General Counter Design
• Step 4: State transition table of the counter

State Transition Flip Flop Input

Present state Next state FF2 FF1 FF0
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
 General Counter Design
 Step 5: Determine the simplified Boolean equations to the inputs
of the flip flops.
 General Counter Design

From the key map in step 5 you will find the simplified
Boolean equation of the flip flop inputs as below
 General Counter Design
• Step 6: Draw the logic diagram

Q0 Q1 Q2
 General Counter Design
• Example 2: Design synchronous counter that counts
1  2  5 7 and back to 1 using JK Flip flop .
Take unused state as don’t care
Solution:
Type of flip flop: JK
Number of flip flops required: 3

Excitation table of JK Flip flop

State diagram of the counter
Output Flip flop Input
Transition
Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
 General Counter Design
• State transition table of the counter

State Transition Flip Flop Input

Present state Next state FF2 FF1 FF0
Q2 Q1 Q0 Q2+ Q1+ Q0+ J2 K2 J1 K1 J0 K0
0 0 0 X X X X X X X X X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 1 0 1 1 X X 1 1 X
0 1 1 X X X X X X X X X
1 0 0 X X X X X X X X X
1 0 1 1 1 1 X 0 1 X X 0
1 1 0 X X X X X X X X X
1 1 1 0 0 1 X 1 X 1 X 0
 General Counter Design
 Simplified Boolean equations for the flip flop inputs:

! Draw the logic ckt by urself

 General Counter Design
Unlike the previous example someone can ask you that the unused state will go to
specific state instead of taking as don’t care. In that case ur design might
becomes different.
Let us assume all the unused state will go to state 1 (001).
The state diagram and state transition table will becomes:
State diagram of the counter Present state Next state
Q2 Q1 Q0 Q2+ Q1+ Q0+
100 011
110 0 0 0 0 0 1
000
0 0 1 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 0 0 1
1 0 1 1 1 1
1 1 0 0 0 1
! Draw the simplified logic circuit 1 1 1 0 0 1
Synchronous (Parallel) Counters
 Example 3: Synchronous decade/BCD counter.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0 T0 = 1
1 0 0 0 1 T1 = Q3'.Q0
2 0 0 1 0 T2 = Q1.Q0
3 0 0 1 1 T3 = Q2.Q1.Q0 + Q3.Q0
4 0 1 0 0
5 0 1 0 1
Check the Boolean
6 0 1 1 0
equation by following all
7 0 1 1 1
8 1 0 0 0 the steps in example 1
9 1 0 0 1
10 (recycle) 0 0 0 0
 Synchronous (Parallel) Counters
 Example 3: Synchronous decade/BCD counter
(cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T Q T Q Q1 T Q Q2 T Q Q3
C C C C
Q' Q' Q' Q'

CLK
 General Counter Design
Example 4: Design of a Mod-11 synchronous binary
counter using T FF.
• Mod-11 counter means it count from 0 to 10 which in binary
from 0000 to 1010.
• The other binary inputs (1011,1100,1101,1110 and 111)
becomes don’t care.
• Follow all the 6 steps and you will finally arrive at the design
as below.
Q0 Q1 Q2 Q3

AC

T Q T Q T Q T Q
1 D 2 C 3 B 4 A
C Q C Q C Q C Q
 Up/Down Synchronous Counters
• A synchronous countdown binary counter goes through the
binary states in reverse order, from 1111 down to 0000 and
back to 1111 to repeat the count.
• The bit in the least significant position is complemented with
each pulse.
• A bit in any other position is complemented if all lower
significant bits are equal to 0.
• For example, the next state of 0100 is 0011.
– The least significant bit is always complemented.
– The second significant bit is complemented because the first
bit is 0.
– The third significant bit is complemented because the first two
bits are equal to 0.
– But the fourth bit does not change, because not all lower
significant bits are equal to 0.
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous
binary counter.
Clock pulse Up Q2 Q1 Q0 Down
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' ) TQ1 = Q0 TQ1 = Q0’
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’
Up/Down Synchronous Counters
 Example: A 3-bit up/down synchronous
binary counter (cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T Q T Q T Q Q2
Up C C C
Q' Q' Q'

CLK
A 4-bit up/down synchronous binary counter
 Shift Register Counters
 Shift register counter: a shift register with the
serial output connected back to the serial input.
 They are classified as counters because they give a
specified sequence of states.
 Two common types: the Johnson counter and the
Ring counter.
 Ring Counters
 One flip-flop (stage) for each state in the sequence.
 The output of the last stage is connected to the D input
of the first stage.
 An n-bit ring counter cycles through n states.

100000

000001 010000

000010 001000

000100
 Ring Counters
 Example: A 6-bit (MOD-6) ring counter.
PRE
Q0 Q1 Q2 Q3 Q4 Q5
D Q D Q D Q D Q D Q D Q

CLR
CLK

Clock Q0 Q1 Q2 Q3 Q4 Q5 100000
0 1 0 0 0 0 0
000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0
3 0 0 0 1 0 0 000010 001000
4 0 0 0 0 1 0
5 0 0 0 0 0 1 000100
 Johnson Counters
 The complement of the output of the last stage is
connected back to the D input of the first stage.
 Also called the twisted-ring counter.
 Require fewer flip-flops than ring counters but more
flip-flops than binary counters.
 An n-bit Johnson counter cycles through 2n states.
 Johnson Counters
 Example: A 4-bit (MOD-8) Johnson counter.
Q0 Q1 Q2 Clock Q0 Q1 Q2 Q3
D Q D Q D Q D Q 0 0 0 0 0
Q' 1 1 0 0 0
Q3' 2 1 1 0 0
CLR 3 1 1 1 0
CLK 4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
Timing Diagrams of 4-bit counter
0000
0001 1000

0011 1100

0111 1110
1111
 Exercise
1. Design a sequential circuit with two D flip-flops and one
input X with the conditions when:-
i. X=0, the state of the circuit remains the same
ii. X=1, the circuit goes through state transitions from
00 01 11 10 back to 00 and repeats.
2. Design a counter with the irregular binary count sequence
shown in the state diagram using JK flip flop.
1

7 2

5
 Exercise
3. Design the circuit represented by the diagram below. Treat
unused states as don’t cares. Use JK flip-flops.
0/0

1/1 001 0/0

100 1/0
0/0 0/0 011
1/1
010
1/1 0/0
1/1

000
 Exercise
4. Design a synchronous sequential circuit whose state diagram
is as follows. ( use JK flip-flops)
0

00
1 1
0
1 01 11
0
0 1
10
•Digital clock
•Digital IC for Library