Spartan-6 FPGA

Development Kit
USER GUIDE
 Table of Contents
Introduction ............................................................................................... 4

Block Diagram ........................................................................................... 5

Board overview .......................................................................................... 6

Clock Source and Reset ............................................................................ 7

Expansion Connectors and Boards ......................................................... 8

Pinout for A1 Expansion Connector ............................................................................. 8
Pinout for B1 Expansion Connector ............................................................................. 9

On Board Communications.................................................................... 10
UART RS422/RS485 ................................................................................................. 10
UART RS232 ............................................................................................................. 10
USB (Universal serial Bus) ........................................................................................ 11
On chip UART......................................................................................................... 11
On Chip High speed SPI FT1248 ............................................................................ 12

JTAG Programming/Debugging Ports ................................................. 13

Platform Flash Configuration Storage .................................................. 14

Double-Data-Rate SDRAM .................................................................... 15

Power Distribution .................................................................................. 17

Enpirion EP5368QI .................................................................................................... 17
Enpirion EP5368QI .................................................................................................... 17

Board Schematics .................................................................................... 18

Reference Material for Major ................................................................ 22

UGS6DEVK V1.0 www.avench.com 2

About This Guide
This user guide describes the components and operation of the Spartan-6 FPGA Development
Board.

Guide Contents
This manual contains the following chapters:

 Introduction

 Block Diagram

 Clock Source and Reset

 Expansion Connectors and Boards

 On Board Communications

 JTAG Programming/Debugging Ports

 Platform Flash Configuration Storage

 Power Distribution

 Board Schematics

 Reference Material for Major

UGS6DEVK V1.0 www.avench.com 3

Introduction
The Spartan-6 family provides leading system integration capabilities with the lowest total cost
for high-volume applications.

 The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic
cells, with half the power consumption of previous Spartan families, and faster, more com-
prehensive connectivity.
 Built on a mature 45 nm low-power copper process technology that delivers the optimal bal-
ance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, du-
al-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks.
 Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented
DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the program-
mable silicon foundation for Targeted Design Platforms that deliver integrated software and
hardware components that enable designers to focus on innovation as soon as their devel-
opment cycle begins

Key Components and Features

Spartan-6 LX FPGA: Logic optimized
 Spartan-6 LXT FPGA: High-speed serial connectivity
 Designed for low cost
 Low static and dynamic power
 Multi-voltage, multi-standard Select I/O interface banks
 High-speed GTP serial transceivers in the LXT FPGAs
 Integrated Endpoint block for PCI Express designs (LXT)
 Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification.
 Efficient DSP48A1 slices
 Integrated Memory Controller blocks
 Abundant logic resources with increased logic capacity
 Block RAM with a wide range of granularity
 Clock Management Tile (CMT) for enhanced performance
 Simplified configuration, supports low-cost standards
 Enhanced security for design protection
 Faster embedded processing with enhanced, low cost, MicroBlaze soft processor
 Industry-leading IP and reference designs

UGS6DEVK V1.0 www.avench.com 4

 Block Diagram

POWER SUPPLY POWER SUPPLY POWER SUPPLY

1V2 Input 3V3 Input 2V5 Input

EP5368QI EP5368QI EP5368QI

5V

RS485/422 RJ45

3V3/2V5

JUMBER BERG HDR

RS232
CONFIGURABLE

CLOCK/100Mhz
FXO-HC526R-100 5V
USB MICRO
USB-UART

FT232H

40 PIN CONNECTOR
FPGA XC6SLX9-2TQG144C
30 1/O's

EXP B

RESET
TLV803RDBZR/OD

40 PIN CONNECTOR

30 1/O's

EXP A

FPGA CONFIG/SPI FLASH

DDR SDRAM

M45PE80
HYB25D128800CE-6

Figure 1: Block Diagram

UGS6DEVK V1.0 www.avench.com 5

 Board overview

JTAG (Programming/
Debugging)
Expansion
Header B
Slew rate
selection

RS 422/485

Jumper Settings
(communica-
I/O Bank
tion)
Voltage
Selection RS232
FPGA(Xilinx Header
Spartan6)
USB
DDR2
Memory
Power Supply
(5V)

Reset Switch

Figure 2: Board overview

Power LED
Flash Memory
(SPI)
Crystal Oscillator
Expansion
Header A

UGS6DEVK V1.0 www.avench.com 6

Clock Source and Reset
System clock: - Abracon ASDMB-50.000MHZ-LC-T MEMS Oscillators feature low power con-
sumption at <10mA and exceptional stability at +/- 10ppm Over Temp. at -40 to +105°C and +/-
5ppm over -40 to +85°C. Abracon MEMS Oscillators are available in 30kG shock resistance con-
figuration Applications include computers and peripherals, portable electronics, consumer elec-
tronics, and military and automotive electronics.

No Pin Terminal
1 Standby#
2 GND
3 Output
4 VDD
More about Abracon ASDMB-50.000MHZ-LC-T: http://www.mouser.in/pdfdocs/Abracon_MEMS.pdf

System reset: - The TLV803 family of supervisory circuits provides circuit initialization and tim-
ing supervision, primarily for DSPs and processor-based systems

More about TI TLV803ZDBZR: http://www.mouser.in/pdfdocs/Abracon_MEMS.pdf

connection FPGA Pin

Sys_clk (50 MHz) 92
Reset_n 67

UGS6DEVK V1.0 www.avench.com 7

 Expansion Connectors and Boards
Pinout for A1 Expansion Connector

Schematic Name FPGA Pin Connector FPGA Pin Schematic Name

VCCO_B3_2 1 2 VCC_3V3
EXPA24 IO_L14P_D11_2 (58) 3 4 IO_L13N_D10_2 (59) EXPA22
EXPA26 IO_L14N_D12_2 (57) 5 6 IO_L12N_D2_MISO3_2 (61) EXPA20
EXPA28 IO_L30P_GCLK1_D13_2 (56) 7 8 IO_L12P_D1_MISO2_2 (62) EXPA18
IO_L30N_GCLK0_USERCCLK_2
EXPA27 9 10 IO_L2N_CMPMOSI_2 (66) EXPA9
(55)
GND 11 12 GND
EXPA25 IO_L1P_3 (35) 13 14 IO_L74P_AWAKE_1 (75) EXPA6
IO_L74N_DOUT_BUSY_1
EXPA21 IO_L2P_3 (33) 15 16 EXPA0
(74)
EXPA23 IO_L1N_VREF_3 (34) 17 18 IO_L47N_1 (78) EXPA14
IO_L3P_D0_DIN_MISO_MISO1_2
EXPA12_SPI_MISO 19 20 IO_L47P_1 (79) EXPA19
(65)
GND 21 22 GND
IO_L3N_MOSI_CSI_B_MISO0_2
EXPA11_SPI_MOSI 23 24 IO_L13P_M1_2 (60) EXPA8_M1
(64)
EXPA16_SPI_CLK IO_L1P_CCLK_2 (70) 25 26 IO_L2P_CMPCLK_2 (67) EXPA29_SYSRST_N
EXPA15_M0 IO_L1N_M0_CMPMISO_2 (69) 27 28 SUSPEND (73) EXPA17_SUSPEND
GND 29 30 GND
EXPA7 IO_L42P_GCLK7_1 (88) 31 32 IO_L46N_1 (80) EXPA10
EXPA13 IO_L42N_GCLK6_TRDY1_1 (87) 33 34 IO_L46P_1 (81) EXPA5
EXPA1 IO_L43P_GCLK5_1 (85) 35 36 IO_L45N_1 (82) EXPA4
EXPA2 IO_L43N_GCLK4_1 (84) 37 38 IO_L45P_1 (83) EXPA3
+5V 39 40 +5V

Table 1: A1 Expansion Connector

UGS6DEVK V1.0 www.avench.com 8

 Pinout for B1 Expansion Connector

Schematic Schematic
FPGA Pin Connector FPGA Pin
Name Name
VCC_3V3 1 2 VCC_3V3
EXPB1 IO_L66N_SCP0_0 (111) 3 4 IO_L66P_SCP1_0 (112) EXPB0
EXPB3 IO_L1P_1 (105) 5 6 IO_L65N_SCP2_0 (114) EXPB2
EXPB5 IO_L1N_VREF_1 (104) 7 8 IO_L65P_SCP3_0 (115) EXPB4
EXPB7 IO_L32P_1 (102) 9 10 IO_L64N_SCP4_0 (116) EXPB6
GND 11 12 GND
EXPB9 IO_L32N_1 (101) 13 14 IO_L64P_SCP5_0 (117) EXPB8
EXPB11 IO_L1P_HSWAPEN_0 (144) 15 16 IO_L63N_SCP6_0 (118) EXPB10
EXPB13 IO_L1N_VREF_0 (143) 17 18 IO_L63P_SCP7_0 (119) EXPB12
EXPB15 IO_L2P_0 (142) 19 20 IO_L62N_VREF_0 (120) EXPB14
GND 21 22 GND
EXPB17 IO_L2N_0 (141) 23 24 IO_L62P_0 (121) EXPB16
EXPB19 IO_L3P_0 (140) 25 26 IO_L37N_GCLK12_0 (123) EXPB18
EXPB21 IO_L3N_0 (139) 27 28 IO_L37P_GCLK13_0 (124) EXPB20
GND 29 30 GND
EXPB23 IO_L4P_0 (138) 31 32 IO_L36N_GCLK14_0 (126) EXPB22
EXPB25 IO_L4N_0 (137) 33 34 IO_L36P_GCLK15_0 (127) EXPB24
EXPB27 IO_L34P_GCLK19_0 (134) 35 36 IO_L35N_GCLK16_0 (131) EXPB26
EXPB29 IO_L34N_GCLK18_0 (133) 37 38 IO_L35P_GCLK17_0 (132) EXPB28
+5V 39 40 +5V

Table 2: B1 Expansion connector

UGS6DEVK V1.0 www.avench.com 9

On Board Communications
UART RS422/RS485
Jumper Settings

Connectors FPGA Pin 1 2 3

RS_422/485 Rx 95 J18

RS_422/485 Tx 94 J19
RS_422/485 DE 93
J20

J21

More about MAX3079E:-

http://datasheets.maximintegrated.com/en/ds/MAX3070E-MAX3079E.pdf

UART RS232
Jumper Settings

Connectors FPGA Pin

1 2 3
RS232_Rx 95
RS232_Tx 94 J18

J19

More about ST3232_16P:- J20

J21
http://www.datasheetarchive.com/dl/Datasheet-039/DSA0086517.pdf

UGS6DEVK V1.0 www.avench.com 10

USB (Universal serial Bus)
The FT232H is a single channel USB 2.0 Hi-Speed (480Mb/s) to UART/FIFO IC. It has the capability of be-
ing configured in a variety of industry standard serial or parallel interfaces.

1. UART
2. FT1248(4 bit mode)

The device is also configured in external EEPROM for the FT232H Configuration of the EEPROM
can be done with the free utility FT_PROG.

http://www.ftdichip.com/Support/Utilities/FT_Prog_v1.12.zip

On chip UART

Connectors FPGA Pin

USB_UART_RXD_D1 99
USB_UART_TXD_D0 100

UGS6DEVK V1.0 www.avench.com 11

On Chip High speed SPI FT1248

Figure 3: FT1248 4 bit mode interconnect

The device is configured in FT1248 mode is via an EEPROM setting (external EEPROM for the
FT232H). Configuration of the EEPROM can be done with the free utility FT_PROG.
http://www.ftdichip.com/Support/Utilities/FT_Prog_v1.12.zip

Jumper settings

Connectors FPGA Pin

1 2 3

FT1248_D3 97
J18
FT1248_D2 98
J19
FT1248_D1 99
FT1248_D0 100 J20

USB_FT1248_SCLK 95 J21
USB_FT1248_SS_N 94
USB_FT1248_MISO 93

UGS6DEVK V1.0 www.avench.com 12

JTAG Programming/Debugging Ports

The Spartan-6 FPGA development Kit board includes a JTAG programming and debugging chain.
JTAG headers for driving the JTAG signals from various supported JTAG download and debug-
ging cables.

JTAG (Programming/
Debugging)

JTAG Programmer

Figure 4: JTAG programming/debugging

UGS6DEVK V1.0 www.avench.com 13

Platform Flash Configuration Storage
Flash memory (SPI) is interfaced with the FPGA in the hardware itself. It can be programmed by
creating MCS file using Xilinx impact tool.

Flash memory (SPI)

Figure 5: SPI Flash

Features
 SPI bus-compatible serial interface
 75 MHz clock frequency (MAX)
 2.7–3.6V single supply voltage
 8Mb of page-erasable Flash memory

More about M45PE80:-

www.micron.com/~/media/documents/products/data.../m45pe80.pdf

UGS6DEVK V1.0 www.avench.com 14

Double-Data-Rate SDRAM
The 128-Mbit Double-Data-Rate SDRAM uses a double data- rate architecture to achieve high-
speed operation. The double data rate architecture is essentially a 2n pre-fetch architecture
with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the 128-Mbit Double-Data-Rate SDRAM effectively consists of a single
2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.

Features:-

• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing
Data at the receiver
• DQS is edge-aligned with data for reads and is center-aligned with data for writes
• Differential clock inputs
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges
Of DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: 2, 2.5, 3
• Auto Pre-charge option for each burst access
• Auto Refresh and Self Refresh Modes
• RAS-lockout supported tRAP=tRCD
• 7.8μs Maximum Average Periodic Refresh Interval
• 2.5 V (SSTL_2 compatible) I/O
• VDDQ = 2.5 V ± 0.2 V (DDR266A, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400)
• VDD = 2.5 V ± 0.2 V (DDR266A, DDR333); VDD = 2.6 V ± 0.1 V (DDR400)
• P(G)-TFBGA-60 package with 3 depopulated rows (8 × 12 mm2)
• P(G)-TSOPII-66 package

UGS6DEVK V1.0 www.avench.com 15

 Jumper Settings
Note: - If DDR memory is used, Bank 1 and 2 should
j7
be powered by 2.5V.
2.5v 3.3v

Address Bit FPGA Pin

A0 21
A1 17
A2 16
A3 15
A4 5
A5 6
A6 7
A7 8
A8 9
A9 10
A10/AP 22
A11 11
NC/A12 12
NC/A13 32
BA0 24
BA1 23
CK 2
CK ' 1
CAS’ 29
CKE 14
DM 39
RAS’ 27
WE’ 30
CS’ 26
DQ0 44
DQ1 43
DQ2 41
DQ3 40
DQ4 45
DQ5 46
DQ6 48
DQ7 50
DQS 51
UGS6DEVK V1.0 www.avench.com 16
Power Distribution
Voltage Regulators

Voltage Source Supplies

+5V DC 5v power supply Pin 39,40 on A1, B1 expansion

connectors
3.3 V regulator
EP5368QI 600mA Synchronous Buck Regu- VCCO supply input for FPGA
+3.3V DC lator With Integrated Inductor 3mm x 3mm I/O banks
x 1.1mm Package Pin 1 and 2 on A1, B1 expan-
sion connectors
Enpirion EP5368QI VCCO supply input to FPGA
+2.5V DC
I/O Banks

Enpirion EP5368QI
+1.2V DC FPGA core Input supply

UGS6DEVK V1.0 www.avench.com 17

Board Schematics

UGS6DEVK V1.0 www.avench.com 18

UGS6DEVK V1.0 www.avench.com 19
UGS6DEVK V1.0 www.avench.com 20
UGS6DEVK V1.0 www.avench.com 21
Reference Material for Major
Components

Device Vendor Part Number Description/Data Sheet Link

Crystal http://www.mouser.in/pdfdocs/Abracon_ME
oscilltor Abracon ASDMB-50.000MHZ-LC-T MS.pdf
Maxim http://datasheets.maximintegrated.com/en/
RS422/485 integraed MAX3079E ds/MAX3070E-MAX3079E.pdf
STmicro http://www.datasheetarchive.com/dl/Datash
RS232 Electronics ST3232_16P eet-039/DSA0086517.pdf
http://www.ftdichip.com/Support/Utilities/FT
USB FTDI FT232H _Prog_v1.12.zip
Buck http://www.altera.com/literature/ds/EP5368
converter Enpirion EP5368QI QI_03260.pdf
http://www.xilinx.com/support/documentati
FPGA Xilinx Xc6slx9 on/data_sheets/ds160.pdf
Qimonda http://datasheet.octopart.com/HYB25D1288
DDR2 HYB25D128800CE-6 00CE-6-Qimonda-datasheet-8329955.pdf
Texas
Reset Instruments TLV803ZDBZR http://www.ti.com/lit/ds/symlink/tlv803z.pdf
Flash www.micron.com/~/media/documents/p
memeory Micron M45pe80 roducts/data.../m45pe80.pdf

UGS6DEVK V1.0 www.avench.com 22