Contents

Revision History
Contents
1. Basic Specifications
1.1 Display Specifications
1.2 Mechanical Specifications
1.3 Active Area / Memory Mapping & Pixel Construction
1.4 Mechanical Drawing
1.5 Pin Definition
2. Absolute Maximum Ratings
3. Optics & Electrical Characteristics
3.1 Optics Characteristics
3.2 DC Characteristics
3.3 AC Characteristics
3.3.1 68XX-Series MPU Parallel Interface Characteristics
3.3.2 80XX-Series MPU Parallel Interface Characteristics
3.3.3 Serial Interface Characteristics (4-wire SPI)
3.3.4 Serial Interface Characteristics (3-wire SPI)
3.3.5 I2C Interface Characteristics
4. Functional Specification
4.1 Commands
4.2 Power down and Power up Sequence
4.2.1 Power up Sequence
4.2.2 Power down Sequence
4.3 Reset Circuit
4.4 Actual Application Example
4.4.1 VCC Supplied Externally
4.4.2 VCC Generated by Internal DC/DC Circuit
5. Reliability
5.1 Contents of Reliability Tests
5.2 Failure Check Standard
6. Outgoing Quality Control Specifications
6.1 Environment Required
6.2 Sampling Plan
6.3 Criteria & Acceptable Quality Level
6.3.1 Cosmetic Check (Display Off) in Non-Active Area
6.3.2 Cosmetic Check (Display Off) in Active Area
6.3.3 Pattern Check (Display On) in Active Area
7. Package Specifications
8. Precautions When Using These OEL Display Modules
8.1 Handling Precautions
8.2 Storage Precautions
8.3 Designing Precautions
8.4 Precautions when disposing of the OEL display modules
8.5 Other Precautions
Warranty
Notice
1. Basic Specifications

1.1 Display Specifications

1) Display Mode: Passive Matrix
2) Display Color: Monochrome (White)
3) Drive Duty: 1/64 Duty

1.2 Mechanical Specifications

1) Outline Drawing: According to the annexed outline drawing
2) Number of Pixels: 128  64
3) Panel Size: 34.5  23.0  1.4 (mm)
4) Active Area: 29.42  14.7 (mm)
5) Pixel Pitch: 0.23  0.23(mm)
6) Pixel Size: 0.21  0.21(mm)
7) Weight: 2.18 (g)

1.3 Active Area / Memory Mapping & Pixel Construction

P0.23x128-0.02=29.42

"A"
0.23
P0.23x64-0.02=14.7

0.21
0.21
0.23

Detail "A"
Scale (10:1)
Segment 129 Segment 2
( Column 1 ) ( Column 128 )

Common 1 Common 0
( Row 63 ) ( Row 64 )
Common 63 Common 62
( Row 1 ) ( Row 2 )
 Item Date Remark
A 20130619 Original Drawing
1.4

34.5± 0.2 (Panel Size)

34.5± 0.2 (Cap Size)
0.5± 0.5 33.5± 0.2 (Polarizer)
(1.54) 31.42± 0.2 (V/A) P0.23x128-0.02=29.42
(2.54) 29.42± 0.2 (A/A)
10 5 1.4± 0.1 "A"

0.5± 0.5
(1.1)
(2.1)
t=0.15mm Max
Remove Tape

6
P0.23x64-0.02=14.7
Active Area 1.3"
Mechanical Drawing

128 x 64 Pixels

Polarizer
t=0.2mm

16.7± 0.2 (V/A)

14.7± 0.2 (A/A)
Segment 129 Segment 2

19.2± 0.2 (Cap Size)

18.2± 0.2 (Polarizer)
( Column 1 ) ( Column 128 )

23± 0.2 (Panel Size)

Common 1 Common 0
( Row 63 ) ( Row 64 )

(35)
Common 63 Common 62
( Row 1 ) ( Row 2 )

Glue
Pin Symbol
1 N.C. (GND)
2 C2P
3 C2N
4 C1P

2-R0.4± 0.05
5 C1N
12± 0.2 6 VBAT

11
7 VSS

15x8x0.05mm

12± 0.3
Protective Tape
8 VSS
9 VDD
1 30 10 BS0

6.887
Contact Side

D0
D2
D4
D6

4
NC

C2P
C1P
V SS
BS2
BS1

VCC
11

IR EF

R ES#
R /W#

V BAT

4.75
0.23

N .C . (G ND)
12 BS2

N .C . (G ND)
C2N
C1N
V SS
VDD
BS1
CS#
D /C#
E /RD#
D1
D3
D5
D7
V COMH
NC
0.21 13 CS#
14 RES#
15 D/C#
16 R/W#
17 E/RD#

2± 0.3
0.1± 0.03 18 D0
16± 0.1 (Alignment Mark) 19 D1
0.21
0.23

20 D2
P0.70x(30-1)=20.3± 0.05(W0.40± 0.03) 21 D3

Contact Side
22 D4
0.85± 0.1 23 D5
24 D6
(6.25) 22± 0.2 25 D7
26 IREF
Detail "A" 27 VCOMH
Notes: 28 VCC
Scale (10:1) 29 NC
30 N.C. (GND)
1. Color: White
2. Driver IC: SSD1106G
Customer Approval Drawing Number Rev.
3. FPC Number: QT1106P07
4. Interface: Signature
Allvision Technology Inc. QG-2864KSWLG01 A
8-bit 68XX/80XX Parallel, 3/4-wire SPI, I2 C Unless Otherwise Specified Material
5. General Tolerance: ± 0.30 Unit mm Title
General Roughness Soda Lime / Polyimide
Tolerance Drawn E.E. Panel / E. P.M.
Dimension ± 0.3 By Scale Sheet Size
Angle ±1 Date 1:1 1 of 1 A3
1.5 Pin Definition

Pin Number Symbol I/O Function

Power Supply
Power Supply for Logic
9 VDD P This is a voltage supply pin. It must be connected to external source.
Ground of Logic Circuit
8 VSS P This is a ground pin. It acts as a reference for the logic pins. It must be
connected to external ground.
Power Supply for OEL Panel
This is the most positive voltage supply pin of the chip. A stabilization capacitor
28 VCC P should be connected between this pin and V SS when the converter is used. It
must be connected to external source when the converter is not used.
Ground of Analog Circuit
29 VLSS P This is an analog ground pin. It should be connected to V SS externally.

Driver
Current Reference for Brightness Adjustment
26 IREF I This pin is segment current reference pin. A resistor should be connected
between this pin and V SS . Set the current at 12.5A maximum.
Voltage Output High Level for COM Signal
27 VCOMH O This pin is the input pin for the voltage output high level for COM signals. A
capacitor should be connected between this pin and V SS .

DC/DC Converter
Power Supply for DC/DC Converter Circuit
This is the power supply pin for the internal buffer of the DC/DC voltage converter.
6 VBAT P It must be connected to external source when the converter is used. It should be
connected to V DD when the converter is not used.
P o s i t i v e T e r m i n a l o f t h e F l y i n g I n v e r ti n g C a p a c i t o r
4/5 C1P / C1N Negative Terminal of the Flying Boost Capacitor
I
2/3 C2P / C2N The charge-pump capacitors are required between the terminals. They must be
floated when the converter is not used.

Interface
Communicating Protocol Select
These pins are MCU interface selection input. See the following table:
BS0 BS1 BS2
10 BS0
I2C 0 1 0
11 BS1 I 3-wire SPI 1 0 0
12 BS2 4-wire SPI 0 0 0
8-bit 68XX Parallel 0 0 1
8-bit 80XX Parallel 0 1 1
Power Reset for Controller and Driver
14 RES# I This pin is reset signal input. When the pin is low, initialization of the chip is
executed. Keep this pin pull high during normal operation.
Chip Select
13 CS# I This pin is the chip select input. The chip is enabled for MCU communication only
when CS# is pulled low.
Data/Command Control
This pin is Data/Command control pin. When the pin is pulled high, the input at
D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0
will be transferred to the command register.
When the pin is pulled high and serial interface mode is selected, the data at SDIN
15 D/C# I will be interpreted as data. When it is pulled low, the data at SDIN will be
transferred to the command register. In I2C mode, this pin acts as SA0 for slave
address selection.
For detail relationship to MCU interface signals, please refer to the Timing
Characteristics Diagrams.
Read/Write Enable or Read
This pin is MCU interface input. When interfacing to a 68XX-series
microprocessor, this pin will be used as the Enable (E) signal. Read/write operation
is initiated when this pin is pulled high and the CS# is pulled low.
17 E/RD# I When connecting to an 80XX-microprocessor, this pin receives the Read (RD#)
signal. Data read operation is initiated when this pin is pulled low and CS# is
pulled low.
When serial or I2C mode is selected, this pin must be connected to V SS .
1.5 Pin Definition (Continued)

Pin Number Symbol I/O Function

Interface (Continued)
Read/Write Select or Write
This pin is MCU interface input. When interfacing to a 68XX-series
microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull
this pin to “High” for read mode and pull it to “Low” for write mode.
16 R/W# I When 80XX interface mode is selected, this pin will be the Write (WR#) input.
Data write operation is initiated when this pin is pulled low and the CS# is pulled
low.
When serial or I2C mode is selected, this pin must be connected to V SS .
Host Data Input/Output Bus
These pins are 8-bit bi-directional data bus to be connected to the
microprocessor’s data bus. When serial mode is selected, D1 will be the serial
18~25 D0~D7 I/O data input SDIN and D0 will be the serial clock input SCLK. When I2C mode is
selected, D2 & D1 should be tired together and serve as SDA out & SDA in in
application and D0 is the serial clock input SCL.
Unused pins must be connected to V SS except for D2 in serial mode.

Reserve
Reserved Pin
7 N.C. - The N.C. pin between function pins are reserved for compatible and flexible
design.
Reserved Pin (Supporting Pin)
1, 30 N.C. (GND) - The supporting pins can reduce the influences from stresses on the function pins.
These pins must be connected to external ground as the ESD protection circuit.
2. Absolute Maximum Ratings
Parameter Symbol Min Max Unit Notes
Supply Voltage for Logic V DD -0.3 4 V 1, 2
Supply Voltage for Display V CC 0 14 V 1, 2
Supply Voltage for DC/DC V BAT -0.3 5 V 1, 2
Operating Temperature T OP -40 85 C
Storage Temperature T STG -40 85 C 3
Life Time (120 cd/m2) 10,000 - hour 4
2
Life Time (80 cd/m ) 30,000 - hour 4
Life Time (60 cd/m2) 50,000 - hour 4
Note 1: All the above voltages are on the basis of “V SS = 0V”.
Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the
module may occur. Also, for normal operations, it is desirable to use this module under the
conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used
beyond these conditions, malfunctioning of the module can occur and the reliability of the module
may deteriorate.
Note 3: The defined temperature ranges do not include the polarizer. The maximum withstood
temperature of the polarizer should be 80C.
Note 4: V CC = 12.0V, T a = 25°C, 50% Checkerboard.
Software configuration follows Section 4.4 Initialization.
End of lifetime is specified as 50% of initial brightness reached. The average operating lifetime at
room temperature is estimated by the accelerated operation at high temperature conditions.
3. Optics & Electrical Characteristics

3.1 Optics Characteristics

Characteristics Symbol Conditions Min Typ Max Unit

Brightness
L br Note 5 120 - - cd/m2
(V CC Supplied Externally)
Brightness
L br Note 6 100 150 - cd/m2
(V CC Generated by Internal DC/DC)
(x) 0.28 0.32 0.36
C.I.E. (White) C.I.E. 1931
(y) 0.31 0.35 0.39
Dark Room Contrast CR - 2000:1 -
Viewing Angle - Free - degree
* Optical measurement taken at V DD = 2.8V, V CC = 12V & 7.25V.
Software configuration follows Section 4.4 Initialization.

3.2 DC Characteristics

Characteristics Symbol Conditions Min Typ Max Unit

Supply Voltage for Logic V DD 1.65 2.8 3.3 V
Supply Voltage for Display Note 5
V CC - 12.0 - V
(Supplied Externally) (Internal DC/DC Disable)
Supply Voltage for DC/DC V BAT Internal DC/DC Enable 3.5 - 4.2 V
Supply Voltage for Display Note 6
V CC 6.4 - 9 V
(Generated by Internal DC/DC) (Internal DC/DC Enable)
High Level Input V IH I OUT = 100μA, 3.3MHz 0.8V DD - V DD V
Low Level Input V IL I OUT = 100μA, 3.3MHz 0 - 0.2V DD V
High Level Output V OH I OUT = 100μA, 3.3MHz 0.9V DD - V DD V
Low Level Output V OL I OUT = 100μA, 3.3MHz 0 - 0.1V DD V
Operating Current for V DD I DD - 180 300 μA

Operating Current for V CC

I CC Note 7 - 23 32 mA
(V CC Supplied Externally)

Operating Current for V BAT

I BAT Note 8 - 45 50 mA
(V CC Generated by Internal DC/DC)

Sleep Mode Current for V DD I DD, SLEEP - 1 5 μA

Sleep Mode Current for V CC I CC, SLEEP - 2 10 μA
Note 5 & 6: Brightness (L br ) and Supply Voltage for Display (V CC ) are subject to the change of the panel
characteristics and the customer’s request.
Note 7: V DD = 2.8V, V CC = 12V, IREF=910K 100% Display Area Turn on.
Note 8: V DD = 2.8V, V CC = 8V, IREF=560K 100% Display Area Turn on.
* Software configuration follows Section 4.4 Initialization.
3.3 AC Characteristics
[Link] 68XX-Series MPU Parallel Interface Timing Characteristics:

Symbol Description Min Max Unit

t cycle Clock Cycle Time 300 - ns
t AS Address Setup Time 5 - ns
t AH Address Hold Time 0 - ns
t DSW Write Data Setup Time 40 - ns
t DHW Write Data Hold Time 7 - ns
t DHR Read Data Hold Time 20 - ns
t OH Output Disable Time - 70 ns
t ACC Access Time - 140 ns
Chip Select Low Pulse Width (Read) 120
PW CSL - ns
Chip Select Low Pulse width (Write) 60
Chip Select High Pulse Width (Read) 60
PW CSH - ns
Chip Select High Pulse Width (Write) 60
tR Rise Time - 40 ns
tF Fall Time - 40 ns
* (V DD - V SS = 1.65V to 3.3V, T a = 25°C)
[Link] 68XX-Series MPU Parallel Interface with Internal Charge Pump

68xx parallel interface

Vin 1 N.C. (GND)

R2 2
S C2P
C2 3
D C2N
G Q1 4
G Q2 C1P
D C1 5 C1N
GPIO S 6 VBAT
R3 C6 7 N.C.
8 VSS
VDD 9 VDD
C5 10 BS0
11 BS1
12 BS2
CS# 13 CS#
RES# 14 RES#
D/C# 15 D/C#
R/W# 16 R/W#
E 17 E/RD#
D[7:0] 18 D0
19 D1
20 D2
21 D3
22 D4
23 D5
24 D6
25 D7
R1 26 IREF
C4 27 VCOMH
C3 28 VCC
29 VLSS
30 N.C. (GND)

GND

Recommended Components:
C1, C2: 1μF / 16V, X5R
C3: 2.2μF
C4: 4.7μF / 16V, X7R
C5, C6: 1μF
R1: 560kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3: 47kΩ
Q1: FDN338P
Q2: FDN335N
Notes:
VDD: 1.65~3.3V, it should be equal to MPU I/O voltage.
Vin: 3.5~4.2V
* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.
[Link] 80XX-Series MPU Parallel Interface Timing Characteristics:

Symbol Description Min Max Unit

t cycle Clock Cycle Time 300 - ns
t AS Address Setup Time 10 - ns
t AH Address Hold Time 0 - ns
t DSW Write Data Setup Time 40 - ns
t DHW Write Data Hold Time 7 - ns
t DHR Read Data Hold Time 20 - ns
t OH Output Disable Time - 70 ns
t ACC Access Time - 140 ns
t PWLR Read Low Time 120 - ns
t PWLW Write Low Time 60 - ns
t PWHR Read High Time 60 - ns
t PWHW Write High Time 60 - ns
t CS Chip Select Setup Time 0 - ns
t CSH Chip Select Hold Time to Read Signal 0 - ns
t CSF Chip Select Hold Time 20 - ns
tR Rise Time - 40 ns
tF Fall Time - 40 ns
* (V DD - V SS = 1.65V to 3.3V, T a = 25°C)

( Read Timing )

( Write Timing )
 [Link] 80XX-Series MPU Parallel Interface with Internal Charge Pump

80xx parallel interface

Vin 1 N.C. (GND)

R2 2
S C2P
C2 3
D C2N
G Q1 4
G Q2 C1P
D C1 5 C1N
GPIO S 6 VBAT
R3 C6 7 N.C.
8 VSS
VDD 9 VDD
C5 10 BS0
11 BS1
12 BS2
CS# 13 CS#
RES# 14 RES#
D/C# 15 D/C#
WR# 16 R/W#
RD# 17 E/RD#
D[7:0] 18 D0
19 D1
20 D2
21 D3
22 D4
23 D5
24 D6
25 D7
R1 26 IREF
C4 27 VCOMH
C3 28 VCC
29 VLSS
30 N.C. (GND)

GND

Recommended Components:
C1, C2: 1μF / 16V, X5R
C3: 2.2μF
C4: 4.7μF / 16V, X7R
C5, C6: 1μF
R1: 560kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3: 47kΩ
Q1: FDN338P
Q2: FDN335N
Notes:
VDD: 1.65~3.3V, it should be equal to MPU I/O voltage.
Vin: 3.5~4.2V
* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.
[Link] Serial Interface Timing Characteristics: (4-wire SPI)

Symbol Description Min Max Unit

t cycle Clock Cycle Time 100 - ns
t AS Address Setup Time 15 - ns
t AH Address Hold Time 15 - ns
t CSS Chip Select Setup Time 20 - ns
t CSH Chip Select Hold Time 10 - ns
t DSW Write Data Setup Time 15 - ns
t DHW Write Data Hold Time 15 - ns
t CLKL Clock Low Time 20 - ns
t CLKH Clock High Time 20 - ns
tR Rise Time - 40 ns
tF Fall Time - 40 ns
* (V DD - V SS = 1.65V to 3.3V, T a = 25°C)
[Link] 4-wire Serial Interface with Internal Charge Pump
4-w ire serial interface

V in 1 N .C . (G N D )
R2 2
S C 2P
C2 3
D C 2N
G Q1 4
G Q2 C 1P
D C1 5 C 1N
G PIO S 6 VDDB
R3 7 N .C .
8 V SS
VDD 9 VDD
10 B S0
C6

C5

11 B S1
12 B S2
C S# 13 CS#
R E S# 14 RES#
D /C # 15 D /C #
R4 16 R /W #
R5 17 E /R D #
SCLK 18 D0
S D IN 19 D1
20 D2
21 D3
22 D4
23 D5
24 D6
25 D7
R1 26 IR E F
C4 27 VCOM H
C3 28 VCC
29 V LSS
30 N .C . (G N D )

GND

Recommended Components:
C1, C2: 1μF / 16V, X5R
C3: 2.2μF
C4: 4.7μF / 16V, X7R
C5, C6: 1μF
R1: 560kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3: 47kΩ
R4, R5: 4.7kΩ
Q1: FDN338P
Q2: FDN335N
Notes:
VDD: 1.65~3.3V, it should be equal to MPU I/O voltage.
Vin: 3.5~4.2V
* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.
[Link] Serial Interface Timing Characteristics: (3-wire SPI)

Symbol Description Min Max Unit

t cycle Clock Cycle Time 100 - ns
t CSS Chip Select Setup Time 20 - ns
t CSH Chip Select Hold Time 10 - ns
t DSW Write Data Setup Time 15 - ns
t DHW Write Data Hold Time 15 - ns
t CLKL Clock Low Time 20 - ns
t CLKH Clock High Time 20 - ns
tR Rise Time - 40 ns
tF Fall Time - 40 ns
* (V DD - V SS = 1.65V to 3.3V, T a = 25°C)
[Link] 3-wire Serial Interface with Internal Charge Pump
3-wire serial interface

Vin 1 N.C. (GND)

R2 2
S C2P
C2 3
D C2N
G Q1 4
G Q2 C1P
D C1 5 C1N
GPIO S 6 VDDB
R3 7 N.C.
8 VSS
VDD 9 VDD
10 BS0
C6

C5

11 BS1
12 BS2
CS# 13 CS#
RES# 14 RES#
15 D/C#
R4 16 R/W#
R5 17 E/RD#
SCLK 18 D0
SDIN 19 D1
20 D2
21 D3
22 D4
23 D5
24 D6
25 D7
R1 26 IREF
C4 27 VCOMH
C3 28 VCC
29 VLSS
30 N.C. (GND)

GND

Recommended Components:
C1, C2: 1μF / 16V, X5R
C3: 2.2UF/16V
C4: 4.7μF / 16V, X7R
C5, C6: 1μF/16V
R1: 560kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3: 47kΩ
R4, R5: 4.7kΩ
Q1: FDN338P
Q2: FDN335N
Notes:
VDD: 1.65~3.3V, it should be equal to MPU I/O voltage.
Vin: 3.5~4.2V
* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.
[Link] I2C Interface Timing Characteristics:

Symbol Description Min Max Unit

t cycle Clock Cycle Time 2.5 - μs
t HSTART Start Condition Hold Time 0.6 - μs
Data Hold Time (for “SDA OUT ” Pin) 0
t HD - ns
Data Hold Time (for “SDA IN ” Pin) 300
t SD Data Setup Time 100 - ns
Start Condition Setup Time
t SSTART 0.6 - μs
(Only relevant for a repeated Start condition)
t SSTOP Stop Condition Setup Time 0.6 - μs
tR Rise Time for Data and Clock Pin 300 ns
tF Fall Time for Data and Clock Pin 300 ns
t IDLE Idle Time before a New Transmission can Start 1.3 - μs
* (V DD - V SS = 1.65V to 3.3V, T a = 25°C)
 [Link] I2C Interface with Internal Charge Pump

I 2 C in te r f a c e

V in 1 N .C . ( G N D )
R2 2
S C 2P
C2 3
D C 2N
G Q1 4
G Q2 C 1P
D C1 5 C 1N
G P IO S 6 VDDB
R3 7 N .C .
8 V SS
VDD 9 VDD
10 BS0
C6

C5

11 BS1
12 BS2
13 CS#
RES# 14 RES#
15 D /C #
R4 16 R /W #
R5 17 E /R D #
SCL 18 D0
SDA 19 D1
20 D2
21 D3
22 D4
23 D5
24 D6
25 D7
R1 26 IR E F
C4 27 VCOM H
C3 28 VCC
29 V LSS
30 N .C . ( G N D )

GND

Recommended Components:
C1, C2: 1μF / 16V, X5R
C3: 2.2μF
C4: 4.7μF / 16V, X7R
C5, C6: 1μF
R1: 560kΩ, R1 = (Voltage at IREF - VSS) / IREF
R2, R3: 47kΩ
R4, R5: 4.7kΩ
Q1: FDN338P
Q2: FDN335N
Notes:
VDD: 1.65~3.3V, it should be equal to MPU I/O voltage.
Vin: 3.5~4.2V
The I2C slave address is 0111100b’. If the customer ties D/C# (pin 15) to VDD, the I2C slave address
will be 0111101b’.
* VBAT will be connected to VDD when VCC be connected to external source (12V), R1 should be
replaced as 910 kΩ.
4. Functional Specification
4.1 Commands
Refer to the Technical Manual for the SH1106

4.2 Power down and Power up Sequence

To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include
a delay period between high voltage and low voltage power sources during turn on/off. It gives the
OEL panel enough time to complete the action of charge and discharge before/after the operation.

4.2.1 Power up Sequence: V DD on

V CC /VBAT on
1. Power up V DD
Display on
2. Send Display off command
3. Initialization V CC
4. Clear Screen
5. Power up V CC / V BAT V DD
6. Delay 100ms
V SS /Ground
(When V CC is stable)
7. Send Display on command
Display off
4.2.2 Power down Sequence: V CC / V BAT off
V DD off
1. Send Display off command
2. Power down V CC / V BAT V CC /V BAT
3. Delay 100ms
(When V CC / V BAT is reach 0 and panel is V DD
completely discharges)
V SS /Ground
4. Power down V DD

Note 13:
1) Since an ESD protection circuit is connected between V DD and V CC inside the driver IC, V CC
becomes lower than V DD whenever V DD is ON and V CC is OFF.
2) V CC / V BAT should be kept float (disable) when it is OFF.
3) Power Pins (V DD , V CC , V BAT ) can never be pulled to ground under any circumstance.
4) V DD should not be power down before V CC / V BAT power down.

4.3 Reset Circuit

When RES# input is low, the chip is initialized with the following status:
1. Display is OFF
2. 12864 Display Mode
3. Normal segment and display data column and row address mapping (SEG0 mapped to column
address 00h and COM0 mapped to row address 00h)
4. Shift register data clear in serial interface
5. Display start line is set at display RAM address 0
6. Column address counter is set at 0
7. Normal scan direction of the COM outputs
8. Contrast control register is set at 7Fh
9. Normal display mode (Equivalent to A4h command)
4.4 Actual Application Example
Command usage and explanation of an actual example

4.4.1 V CC Supplied Externally

<Power up Sequence>

Set Display Offset set VPP

V DD /V CC off State
0xD3, 0x00 0x32

Power up V DD Set Display Start Line Set Normal/Inverse Display

(RES# as Low State) 0x40 0xA6

Power Stabilized Set Charge Pump

Clear Screen
(Delay Recommended) 0xad, 0x8b

Set RES# as High Set Segment Re-Map Power up V CC & Stabilized

(3μs Delay Minimum) 0xA1 (Delay Recommended)

Initialized State Set COM Output Scan Direction Set Display On

(Parameters as Default) 0xC8 0xAF

Set Display Off Set COM Pins Hardware Configuration

(100ms Delay Recommended)
0xAE 0xDA, 0x12

Initial Settings Set Contrast Control

Display Data Sent
Configuration 0x81, 0XBF

Set Display Clock Divide Ratio/Oscillator Frequency Set Pre-Charge Period

0xD5, 0x80 0xD9, 0X22

Set Multiplex Ratio Set VCOMH Deselect Level

0xA8, 0x3F 0xDB, 0x40

If the noise is accidentally occurred at the displaying window during the operation, please reset
the display in order to recover the display function.
 <Power down Sequence>

Power down V CC
Normal Operation V DD /V CC off State
(100ms Delay Recommended)

Set Display Off

Power down V DD
0xAE

<Entering Sleep Mode>

Normal Operation Power down V CC

Set Display Off

Sleep Mode
0xAE

<Exiting Sleep Mode>

Set Display On
Sleep Mode Normal Operation
0xAF

Power up V CC & Stabilized

(100ms Delay Recommended)
(Delay Recommended)

External setting
{
RES=1;
delay(1000);
RES=0;
delay(1000);
RES=1;
delay(1000);
write_i(0xAE); /*display off*/

write_i(0x02); /*set lower column address*/

write_i(0x10); /*set higher column address*/

write_i(0x40); /*set display start line*/

write_i(0xB0); /*set page address*/

 write_i(0x81); /*contract control*/
write_i(0xBF); /*128*/

write_i(0xA1); /*set segment remap*/

write_i(0xA6); /*normal / reverse*/

write_i(0xA8); /*multiplex ratio*/

write_i(0x3F); /*duty = 1/64*/

write_i(0xad); /*set charge pump enable*/

write_i(0x8a); /* 0x8a 外供 VCC */

write_i(0x32); /*0X30---0X33 set VPP 8V */

write_i(0xC8); /*Com scan direction*/

write_i(0xD3); /*set display offset*/

write_i(0x00); /* 0x20 */

write_i(0xD5); /*set osc division*/

write_i(0x80);

write_i(0xD9); /*set pre-charge period*/

write_i(0x22); /*0x22*/

write_i(0xDA); /*set COM pins*/

write_i(0x12);

write_i(0xdb); /*set vcomh*/

write_i(0x40);

write_i(0xAF); /*display ON*/

}

void write_i(unsigned char ins)

{

DC=0;
CS=0;
WR=1;
P1=ins; /*inst*/
WR=0;
WR=1;
CS=1;
}

void write_d(unsigned char dat)

{
DC=1;
CS=0;
WR=1;
P1=dat; /*data*/
WR=0;
WR=1;
CS=1;
}

void delay(unsigned int i)

{
while(i>0)
{
i--;
}
}
4.4.2 V CC Generated by Internal DC/DC Circuit
<Power up Sequence>

Set Display Offset set VPP

V DD /V CC off State
0xD3, 0x00 0x33

Power up V DD Set Display Start Line Set Normal/Inverse Display

(RES# as Low State) 0x40 0xA6

Power Stabilized Set Charge Pump

Clear Screen
(Delay Recommended) 0xad, 0x8a

Set RES# as High Set Segment Re-Map Power up V CC & Stabilized

(3μs Delay Minimum) 0xA1 (Delay Recommended)

Initialized State Set COM Output Scan Direction Set Display On

(Parameters as Default) 0xC8 0xAF

Set Display Off Set COM Pins Hardware Configuration

(100ms Delay Recommended)
0xAE 0xDA, 0x12

Initial Settings Set Contrast Control

Display Data Sent
Configuration 0x81, 0Xff

Set Display Clock Divide Ratio/Oscillator Frequency Set Pre-Charge Period

0xD5, 0x80 0xD9, 0X1f

Set Multiplex Ratio Set VCOMH Deselect Level

0xA8, 0x3F 0xDB, 0x40

If the noise is accidentally occurred at the displaying window during the operation, please reset
the display in order to recover the display function.
 <Power down Sequence>

Power Stabilized
Normal Operation V DD /V BAT off State
(100ms Delay Recommended)

Set Display Off Power down V BAT

0xAE (50ms Delay Recommended)

Set Charge Pump

Power down V DD
0x8D, 0x10

<Entering Sleep Mode>

Set Charge Pump

Normal Operation Sleep Mode
0xad, 0x8b

Set Display Off

Power down V BAT
0xAE

<Exiting Sleep Mode>

Set Charge Pump Power Stabilized

Sleep Mode
0xaD, 0x8a (100ms Delay Recommended)

Power up V BAT Set Display On

Normal Operation
(100ms Delay Recommended) 0xAF

Internal setting（Charge pump）

{
RES=1;
delay(1000);
RES=0;
delay(1000);
RES=1;
delay(1000);
write_i(0xAE); /*display off*/

write_i(0x02); /*set lower column address*/

write_i(0x10); /*set higher column address*/
 write_i(0x40); /*set display start line*/

write_i(0xB0); /*set page address*/

write_i(0x81); /*contract control*/

write_i(0xff); /*128*/

write_i(0xA1); /*set segment remap*/

write_i(0xA6); /*normal / reverse*/

write_i(0xA8); /*multiplex ratio*/

write_i(0x3F); /*duty = 1/64*/

write_i(0xad); /*set charge pump enable*/

write_i(0x8b); /* 0x8B 内供 VCC */

write_i(0x33); /*0X30---0X33 set VPP 9V */

write_i(0xC8); /*Com scan direction*/

write_i(0xD3); /*set display offset*/

write_i(0x00); /* 0x20 */

write_i(0xD5); /*set osc division*/

write_i(0x80);

write_i(0xD9); /*set pre-charge period*/

write_i(0x1f); /*0x22*/

write_i(0xDA); /*set COM pins*/

write_i(0x12);

write_i(0xdb); /*set vcomh*/

write_i(0x40);

write_i(0xAF); /*display ON*/

}

void write_i(unsigned char ins)

{

DC=0;
CS=0;
WR=1;
P1=ins; /*inst*/
WR=0;
 WR=1;
CS=1;
}

void write_d(unsigned char dat)

{
DC=1;
CS=0;
WR=1;
P1=dat; /*data*/
WR=0;
WR=1;
CS=1;
}

void delay(unsigned int i)

{
while(i>0)
{
i--;
}
}
5. Reliability

5.1 Contents of Reliability Tests

Item Conditions Criteria

High Temperature Operation 70C, 240 hrs
Low Temperature Operation -40C, 240 hrs
High Temperature Storage 85C, 240 hrs
The operational
Low Temperature Storage -40C, 240 hrs functions work.
High Temperature/Humidity Operation 60C, 90% RH, 120 hrs
-40C  85C, 24 cycles
Thermal Shock
60 mins dwell
* The samples used for the above tests do not include polarizer.
* No moisture condensation is observed during tests.

5.2 Failure Check Standard

After the completion of the described reliability test, the samples were left at room temperature for 2
hrs prior to conducting the failure test at 235C; 5515% RH.
6. Outgoing Quality Control Specifications

6.1 Environment Required

Customer’s test & measurement are required to be conducted under the following conditions:
Temperature: 23  5C
Humidity: 55  15% RH
Fluorescent Lamp: 30W
Distance between the Panel & Lamp: ≥ 50cm
Distance between the Panel & Eyes of the Inspector: ≥ 30cm
Finger glove (or finger cover) must be worn by the inspector.
Inspection table or jig must be anti-electrostatic.

6.2 Sampling Plan

Level II, Normal Inspection, Single Sampling, MIL-STD-105E

6.3 Criteria & Acceptable Quality Level

Partition AQL Definition

Major 0.65 Defects in Pattern Check (Display On)
Minor 1.0 Defects in Cosmetic Check (Display Off)

6.3.1 Cosmetic Check (Display Off) in Non-Active Area

Check Item Classification Criteria

X > 6 mm (Along with Edge)

Y > 1 mm (Perpendicular to edge)
X

Y
Panel General Chipping Minor

Y
6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued)

Check Item Classification Criteria

Any crack is not allowable.

Panel Crack Minor

Copper Exposed
Minor Not Allowable by Naked Eye Inspection
(Even Pin or Film)

Film or Trace Damage Minor

Terminal Lead Prober Mark Acceptable

Glue or Contamination on Pin

Minor
(Couldn’t Be Removed by Alcohol)

Ink Marking on Back Side of panel

Acceptable Ignore for Any
(Exclude on Film)
6.3.2 Cosmetic Check (Display Off) in Active Area
It is recommended to execute in clear room environment (class 10k) if actual in necessary.
Check Item Classification Criteria
Any Dirt & Scratch on Polarizer’s
Acceptable Ignore for not Affect the Polarizer
Protective Film
W ≤ 0.1 Ignore
Scratches, Fiber, Line-Shape Defect W > 0.1
Minor
(On Polarizer) L≤2 n≤1
L>2 n=0
Φ ≤ 0.1 Ignore
Dirt, Black Spot, Foreign Material,
Minor 0.1 < Φ ≤ 0.25 n≤1
(On Polarizer)
0.25 < Φ n=0
Φ ≤ 0.5
 Ignore if no Influence on Display
0.5 < Φ n=0

Dent, Bubbles, White spot

Minor
(Any Transparent Spot on Polarizer)

Fingerprint, Flow Mark

Minor Not Allowable
(On Polarizer)
* Protective film should not be tear off when cosmetic check.
** Definition of W & L & Φ (Unit: mm): Φ = (a + b) / 2

b: Minor Axis
W

a: Major Axis
6.3.3 Pattern Check (Display On) in Active Area

Check Item Classification Criteria

No Display Major

Missing Line Major

Pixel Short Major

Darker Pixel Major

Wrong Display Major

Un-uniform Major
7. Package Specifications
EPE COVER FOAM 351x212x1,
ANTISTATIC x 1 Pcs
x 1 pcs (Empty)

1B6 Pcs Tray Vacuum packing

Module
EPE PROTECTTIVE
A pcs
x 15
Staggered Stacking

Tray 420x285 mm
T=0.8mm

Exsiccator x 2 pcs

Primary Box
Brimary Box C4 SET
SET
Wrapped with adhesive tape
B pcs
x 16

Vacuum packing bag

EPE PROTECTTIVE
370mm x 280mm x 20mm

CARTON BOX

Label

Primary L450mm x W296 x H110, B wave

x C4Pcs
Univision Technology Inc.

Part ID :
Label
Lot ID :

Q'ty :

QC :

Carton Box L464mm x W313mm x H472mm, AB wave

(Major / Maximum)

Item Quantity
Module 810 per Primary Box
Holding Trays (A) 15 per Primary Box
Total Trays (B) 16 per Primary Box (Including 1 Empty Tray)
Primary Box (C) 1~4 per Carton (4 as Major / Maximum)
8. Precautions When Using These OEL Display Modules

8.1 Handling Precautions

1) Since the display panel is being made of glass, do not apply mechanical impacts such us dropping
from a high position.
2) If the display panel is broken by some accident and the internal organic substance leaks out, be
careful not to inhale nor lick the organic substance.
3) If pressure is applied to the display surface or its neighborhood of the OEL display module, the cell
structure may be damaged and be careful not to apply pressure to these sections.
4) The polarizer covering the surface of the OEL display module is soft and easily scratched. Please
be careful when handling the OEL display module.
5) When the surface of the polarizer of the OEL display module has soil, clean the surface. It takes
advantage of by using following adhesion tape.
* Scotch Mending Tape No. 810 or an equivalent
Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent
such as ethyl alcohol, since the surface of the polarizer will become cloudy.
Also, pay attention that the following liquid and solvent may spoil the polarizer:
* Water
* Ketone
* Aromatic Solvents
6) Hold OEL display module very carefully when placing OEL display module into the system housing.
Do not apply excessive stress or pressure to OEL display module. And, do not over bend the film
with electrode pattern layouts. These stresses will influence the display performance. Also,
secure sufficient rigidity for the outer cases.

7) Do not apply stress to the driver IC and the surrounding molded sections.
8) Do not disassemble nor modify the OEL display module.
9) Do not apply input signals while the logic power is off.
10) Pay sufficient attention to the working environments when handing OEL display modules to prevent
occurrence of element breakage accidents by static electricity.
* Be sure to make human body grounding when handling OEL display modules.
* Be sure to ground tools to use or assembly such as soldering irons.
* To suppress generation of static electricity, avoid carrying out assembly work under dry
environments.
* Protective film is being applied to the surface of the display panel of the OEL display module.
Be careful since static electricity may be generated when exfoliating the protective film.
11) Protection film is being applied to the surface of the display panel and removes the protection film
before assembling it. At this time, if the OEL display module has been stored for a long period of
time, residue adhesive material of the protection film may remain on the surface of the display
panel after removed of the film. In such case, remove the residue material by the method
introduced in the above Section 5).
12) If electric current is applied when the OEL display module is being dewed or when it is placed under
high humidity environments, the electrodes may be corroded and be careful to avoid the above.
8.2 Storage Precautions
1) When storing OEL display modules, put them in static electricity preventive bags avoiding exposure
to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and high
humidity environment or low temperature (less than 0C) environments. (We recommend you to
store these modules in the packaged state when they were shipped from Allvision technology Inc.)
At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur
with them.
2) If electric current is applied when water drops are adhering to the surface of the OEL display
module, when the OEL display module is being dewed or when it is placed under high humidity
environments, the electrodes may be corroded and be careful about the above.

8.3 Designing Precautions

1) The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module,
and if these values are exceeded, panel damage may be happen.
2) To prevent occurrence of malfunctioning by noise, pay attention to satisfy the V IL and V IH
specifications and, at the same time, to make the signal line cable as short as possible.
3) We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (V DD ).
(Recommend value: 0.5A)
4) Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring
devices.
5) As for EMI, take necessary measures on the equipment side basically.
6) When fastening the OEL display module, fasten the external plastic housing section.
7) If power supply to the OEL display module is forcibly shut down by such errors as taking out the
main battery while the OEL display panel is in operation, we cannot guarantee the quality of this
OEL display module.
8) The electric potential to be connected to the rear face of the IC chip should be as follows: SSD1306
* Connection (contact) to any other potential than the above may lead to rupture of the IC.

8.4 Precautions when disposing of the OEL display modules

1) Request the qualified companies to handle industrial wastes when disposing of the OEL display
modules. Or, when burning them, be sure to observe the environmental and hygienic laws and
regulations.

8.5 Other Precautions

1) When an OEL display module is operated for a long of time with fixed pattern may remain as an
after image or slight contrast deviation may occur.
Nonetheless, if the operation is interrupted and left unused for a while, normal state can be
restored. Also, there will be no problem in the reliability of the module.
2) To protect OEL display modules from performance drops by static electricity rapture, etc., do not
touch the following sections whenever possible while handling the OEL display modules.
* Pins and electrodes
* Pattern layouts such as the FPC
3) With this OEL display module, the OEL driver is being exposed. Generally speaking,
semiconductor elements change their characteristics when light is radiated according to the
principle of the solar battery. Consequently, if this OEL driver is exposed to light, malfunctioning
may occur.
* Design the product and installation method so that the OEL driver may be shielded from light in
actual usage.
* Design the product and installation method so that the OEL driver may be shielded from light
during the inspection processes.
4) Although this OEL display module stores the operation state data by the commands and the
indication data, when excessive external noise, etc. enters into the module, the internal status may
 be changed. It therefore is necessary to take appropriate measures to suppress noise generation
or to protect from influences of noise on the system design.
5) We recommend you to construct its software to make periodical refreshment of the operation
statuses (re-setting of the commands and re-transference of the display data) to cope with
catastrophic noise.

Warranty:

The warranty period shall last twelve (12) months from the date of delivery. Buyer shall be completed to
assemble all the processes within the effective twelve (12) months. WiseChip Semiconductor Inc. shall be
liable for replacing any products which contain defective material or process which do not conform to the
product specification, applicable drawings and specifications during the warranty period. All products must be
preserved, handled and appearance to permit efficient handling during warranty period. The warranty
coverage would be exclusive while the returned goods are out of the terms above.

Notice:

No part of this material may be reproduces or duplicated in any form or by any means without the written
permission of Allvision technology Inc. Allvision technology Inc. reserves the right to make changes to this
material without notice. Allvision technology Inc. does not assume any liability of any kind arising out of any
inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there
is no representation that this material is applicable to products requiring high level reliability, such as, medical
products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and
there is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party. This material or portions thereof may contain technology or
the subject relating to strategic products under the control of Foreign Exchange and Foreign Trade Law of
Taiwan and may require an export license from the Ministry of International Trade and Industry or other
approval from another government agency.