VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design
Introduction & Motivation

Dr. Johannes Wolkerstorfer

IAIK Graz University of Technology [email protected] www.iaik.tugraz.at

Dr. Johannes Wolkerstorfer

01_introduction

VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Contact
Newsgroup: tu-graz.lv.vlsi-design Email: [email protected] E il J h W lk t f @i ik t t Slides: http://www.iaik.tugraz.at/ Office: room F2.10, IAIK Office hours: any time Telephone: +43 316 873-5515

Dr. Johannes Wolkerstorfer

01_introduction

VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design General overview

Introduction Arithmetic Methodology Design flow CMOS l i logic Subsystems High speed architecture High speed circuit Low power Nanotechnology Testing T ti Best practice

Dr. Johannes Wolkerstorfer

01_introduction

VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Literature
Slides http://www.iaik.tugraz.at/content/teaching/ master_courses/vlsi_design/downloads/ Hubert Kslin, Digital Integrated Circuits, Cambridge Press, ISBN 978-0521882675 2008 Press 978-0521882675, 2008. Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective,Prentice Hall Electronics and VLSI Series,
2nd edition ISBN 978 0130909961, 2003 edition, 978-0130909961 2003.
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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Literature Architecture & Arithmetic

Computer Organization and Design: The Hardware/Software Interface,
D. Patterson and J. Hennessy, Second Edition, Morgan Kaufmann Publishers, 1998 Publishers 1998.

Computer Arithmetic Algorithms and Hardware Designs,

Behrooz Parhami, Oxford University Press, 2000, ISBN 0-19-512583-5.

Dr. Johannes Wolkerstorfer

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Literature Tools
The designer's guide to VHDL,
Peter J Ashenden Morgan J. Ashenden, Kaufmann Publishers, May 2001.

Software Manuals
PDF files of installed software Links work in StudentNet under Linux only More about in KU

Dr. Johannes Wolkerstorfer

01_introduction

VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Overview
Motivation
Application of integrated circuits

Challenges of VLSI design

How to cope with complexity

Hardware-Software interaction CMOS process t h l technology CMOS logic basics

Dr. Johannes Wolkerstorfer

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design Opportunities pp

Efficient h d Effi i t hardware
New applications
Wireless computing UMTS, MP3 UMTS MP3, PDA

Higher Hi h complexity l it
Voice recognition

Dr. Johannes Wolkerstorfer

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design State of the art

System-on-Chip
Single chip solution
Digital
P Processor Memory

Analog
Wireless IO

Software

Picture Tality
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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design Complex p p processor

Pentium
trans.: Die size: CMOS: Frequ.: Frequ : Dissip: Volt:

3,
28, , 105, 0.18, 1.0, 10 35, 1.65,

4
42 mio 146 mm 0.13 m 2.2 2 2 GHz 55 Watt 1.5 Volt

Picture Intel Corp.

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design Design g p g gap

Silicon technology
Exponential growth
+ Transistors - Feature size - Cost
log

GAPs
Silicon Sili opportunity gates transistor mask
1960 1970 1980

SoC synthesis

Design Automation
To T cope with complexity ith l it Lags behind technology

Design productivity
1990 2000

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design Design automation g

The dream
Push-button solution Automated design flow
From high-level description To physical implementation

The reality
Automation mostly on low level
Logic synthesis Standard-cell layout

Automated optimization
High speed Low power Low die size Time to market

Straight-forward solution
Tools yield average results only Most optimization by engineers

Do what I mean
Dr. Johannes Wolkerstorfer 01_introduction 12

VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design How to handle complexity p y

Design flow
Top down Verification

Design principles
Hierarchy y
Divide & conquer

Regularity
Reusability

Modularity
System y

Well-defined interfaces

Algorithm Architecture Implementation

Locality
Abstraction

Abstraction is the key to handle compexity! y p y

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

VLSI Design Complex system p y

Complex systems contain software!
Software i t S ft interacts with hardware t ith h d

Picture Siemens Corp.

Application A li ti RTOS Iteration Driver

DSP

Analog g

DMA Processor Memory

Software

Hardware

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Hardware Software Interface

Hardware influences software ( (and vice versa) )
Hardware-Software codesign

HW-SW similarities
Multiple layers M lti l l Hierarchy Abstraction

so oftware e har rdware e

Software interacts with hardware

Application OS Device driver Firmware Instruction set

Datapath/control

Module Gate Transistor

Instruction set is the interface between HW and SW

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Instruction set Categories g

CISC: complex instruction set computer
Comprehensive instruction set Variable instruction length 80x86, 68000, Pentium

RISC: d RISC reduced i t ti set computer d instruction t t

Sparse instruction set DEC Alpha, SUN Sparc, MIPS

VLIW: very long instruction word EPIC: explicitly parallel instruction Computer
Multiple RISC instruction per word Fixed instruction length IA-64, Crusoe

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Instruction set Operations p

Load, Store Computational
add, sub, mul

(43%)

mov, push, pop ,p ,p p

OP Simple operations

data

Jump and b J d branch (23%) h

Unconditional: goto Conditional: jnz, j j , jz

IO, Coprocessor Special

Used most often Most impact on performance

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Instruction set Execution

Fetch & Execute Pipelining
Overlap fetch & execute Throughput increased More resources required Complexity increased
Instruction fetch Instruction decode Operand fetch Execute E t Result store

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology Complexity p y

Transistor count
Exponential E ti l growth Doubles every 18 months
16,000 x in 20 years
Picture Intel

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology Clock frequency q y

Performance
Exponential E ti l growth Doubles every 3 years

Picture IBM

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology
Complementary Metal Oxide Semiconductor
NMOS transistor
ON when gate at VDD g
Gate Source PMOS Drain Gate NMOS Source

PMOS transistor
ON when gate at GND

Interconnect
Metal (Al, Cu)

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology Transistors as switches

NMOS transistor
G Good switch for GND G

PMOS transistor
Good switch for VDD

GND

VDD - Vt

Threshold voltage Vt
Cut-off: VGS < VT => ID = 0
Reduced output voltage
NMOS switching VDD PMOS switching GND

VDD
V

GND + Vt
V

Good

Bad

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology Chip p p production

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology Process steps p

Picture Intel

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS technology Cross section

NMOS transistor: in substrate PMOS transistor: in n-well n well
Substrate Source Drain Gate Wires

NMOS Transistor

PMOS Transistor

Picture Prentice Hall

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics

Why is knowledge of circuits important? Isn t Isnt the circuit level automated today?
Redesign of cell libraries for new technologies Automated design good for straight-forward solution straight forward High speed and low power require more design parameters (logic style) Tools support traditional design methods only Humans do better optimization than tools today Electrical problems (clock and power distribution)

Know and understand VLSI effects! K d d t d ff t !

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics Digital systems g y

Synchronous logic
S Standard design technique g q Global clock controls flip-flops Static CMOS logic

Combinational logic

clk

Efficient implementation Keep system level and circuit level in mind!

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics Logic g

Static CMOS logic
Complementary
Pull-up network Pull-down network
a b q

Inverting
Otherwise additional Inverter
a q

Logic levels: LO (GND) HI (VDD) (GND),

Intermediate voltages abstracted

No static power consumption

b

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics Inverter

Simpelst CMOS g p gate: q = !a Insulating output from input Amplification: restoring levels Explanation model for
Performance
Time to charge CL
a CL q a CL q

Power consumption
Energy to charge CL

Inverter is the key to understand CMOS logic!

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics Transistor

L

Gates voltage
Modulates h M d l t channel conductivity l d ti it
n+
(Drain)

W
(Gate)

poly n+

SiO2

(Gate Oxid)

Source-drain voltage
Specifies drain current

p
(Bulk)

(Source)

Designer influences characteristics

By modification of geometry
Ids max ds,max Linearity by width W y by length L

Ids

Pictures Volker Schindler

Manufacturer determines
Geometry limits: Lmin, Wmin And other parameters: tox

linear Saturation Vgs4 Vgs3 g Vgs2 Vgs1

Vds
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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics Performance

Performance determined by
Propagation delay P ti d l
Size of load capacitor CL
Fanout: number of connected gates Interconnect: length of wires
a CL q

Current driving capability

Process technology: Transistor geometry: Supply voltage: Lmin W VDD < > >
a CL q

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

CMOS logic basics Power dissipation p

Power consumption determined by
Charging f Ch i of capacitor it
Size of load capacitor CL
Fanout Interconnect
a CL q

Supply Voltage VDD

a q CL

Power dissipation is a major concern!

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VLSI

Institute for Applied Information Processing and Communications (IAIK) VLSI & Security

Conclusion
Complex VLSI systems
Hardware and Software Abstraction to cope with complexity

C OS p ocess technology CMOS process tec o ogy

Short innovation cycles High integration (Moores law) (System-on-Chip)

CMOS inverter
To explain basic effects of integrated circuits

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