EC806 DDFPGA
Modeling of Digital Systems
Dr Sumam David S.
EC806
Objectives
• At the end of the lecture the student
must be able to
– Appreciate top-down design methodology,
need for HDL, and choose level of
abstraction for modeling a digital system
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EC806 DDFPGA
FPGA based Design Flow
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What is inside an ASIC or an FPGA?
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What is inside an ASIC or an FPGA?
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What is inside an ASIC or an FPGA?
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What is inside an ASIC or an FPGA?
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What is inside an ASIC or an FPGA?
You are writing HDL code to get this image automatically using the tools
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Different Tools?
• Cadence
• Synopsys
• Mentor Graphics
• Xilinx
• Intel Altera – Quartus
• Open source tools
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Fabrication facilities
• SCL Chandigarh – under ISRO
• UMC
• TSMC
• Global foundries
• Intel
• Samsung ….etc.
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FPGA
Logic blocks
Implement combinational
and sequential logic
Interconnect
Wires to connect inputs
and outputs to logic
blocks
I/O blocks
Special logic blocks at
periphery of device for
external connections
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Modeling digital systems
• Model
– Represents info that is relevant and abstracts away details
– Context dependent
• Reasons for modeling
– Requirements specification
– Documentation
– Testing using simulation
– Formal verification
– Synthesis
– Design reuse
• Goal
– Most reliable design process, with minimum cost and time
– Avoid design errors!
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Domains
• Digital systems modeled in 3 principal domains and
at different levels of abstraction
• Behavioral
– What does it do?
– Truth table, state diagram, waveform, algo
• Structural
– What are the components and how are they connected ?
– Schematic, net list
• Physical
– Where are the components located on Si/PCB ?
– Placement & routing
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Behavioural view
• What the system does
• Info on how this will be achieved is hidden
• Inputs and outputs are defined along with
the relationship between them
• Examples
– Truth table
A
– State diagram B
Y=A+B Y
– Waveform
– Algorithm
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Structural
• What the design is
– What components are used
– How are they interconnected
• No info on what the system does nor how it will be
made
• Example
– Schematic
– Net list
• The components may be defined using behavioral or
structural description
– hierarchical description
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Physical
• How the design is made
• Placement & routing or Manufacturing info
• No info on what components are being made nor on how they
behave
• PCB manufacture
– GERBER files
• Etching tracks, drilling holes
• IC layout
– GDS2 files
• Mask layout: diffusion, metal …
• PLDs
– JEDEC files
• Define internal connections
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Example
• Controller for a temperature
measurement system with data input
and display output
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Domains and Levels of Modeling
Structural Behavioral
high level of
abstraction
low level of
abstraction
Physical “Y-chart” due to
Gajski & Kahn
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Domains and Levels of
Modeling
Structural Behavioral
Algorithm
(behavioral)
Register-Transfer
Language
Boolean Equation
Differential Equation
Physical “Y-chart” due to
Gajski & Kahn
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Behavioral domain - levels
• Algorithm
– The set of operations to be performed
• Register Transfer Language
– How data will be moved and stored
• Boolean Equations
– How individual signals are manipulated
• Differential equations
– How currents and voltages in the transistors
behave
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Domains and Levels of
Modeling
Structural Behavioral
Processor-Memory
Switch
Register-Transfer
Gate
Transistor
Physical “Y-chart” due to
Gajski & Kahn
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Levels of abstraction
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Domains and Levels of
Modeling
Structural Behavioral
Polygons
Sticks
Standard Cells
Floor Plan
Physical “Y-chart” due to
Gajski & Kahn
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Adv…
• Automatic synthesis
• Testing & verification using simulation
• Formal verification
• Max reliability for min cost & design
time
• Design reuse
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RTL (dataflow) descriptions
• Describes system in terms of units of data
storage and transformation
• Datapath
– Data storage registers and data
transfer between these units
– Implemented by registers and logic
• Control path
• Sequences operations of the datapath components
• Implemented by FSM
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RTL description
Data in Data out
Data path
Control Status
External External
Control path
Control in Control out
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Datapath
CL R Data Data CL Data
Data in
out in out
Control Load
• storage of data and constants
Data in CL R Data • data transfer
out • data transformations
Control Load
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Control path
inputs outputs
CL
Present next state
state
FSM
• activates operations in data path via control signals
• uses status & external control signals for decision making
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RTL Design method
• Specify the behavior of the system
• Design the data path
• Design the control path
• Implement the data and control path
– Specify the interface between datapath
and control path in terms of explicit signals
– structural model
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Example - Serial Adder
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