Implementation, Characterization and Application of Path

Changing Switch based Arbiter PUF on FPGA as a

lightweight Security Primitive for IoT

MAHABUB HASAN MAHALAT, SURAJ MANDAL, ANINDAN MONDAL, and

BIBHASH SEN, National Institute of Technology Durgapur, India
RAJAT SUBHRA CHAKRABORTY, Indian Institute of Technology Kharagpur, India

Secure authentication of any Internet-of-Things (IoT) device becomes the utmost necessity due to the lack
of specifically designed IoT standards and intrinsic vulnerabilities with limited resources and heterogeneous
technologies. Despite the suitability of arbiter physically unclonable function (APUF) among other PUF
variants for the IoT applications, implementing it on field-programmable gate arrays (FPGAs) is challeng-
ing. This work presents the complete characterization of the path changing switch (PCS)1 based APUF on
two different families of FPGA, like Spartan-3E (90 nm CMOS) and Artix-7 (28 nm CMOS). A comprehen-
sive study of the existing tuning concept for programmable delay logic (PDL) based APUF implemented
on FPGA is presented, leading to establishment of its practical infeasibility. We investigate the entropy, ran-
domness properties of the PCS based APUF suitable for practical applications, and the effect of temperature
variation signifying the adequate tolerance against environmental variation. The XOR composition of PCS
based APUF is introduced to boost performance and security. The robustness of the PCS based APUF against
machine learning based modeling attack is evaluated, showing similar characteristics as the conventional
APUF. Experimental results validate the efficacy of PCS based APUF with a little hardware footprint remov-
ing the paucity of lightweight security primitive for IoT.
CCS Concepts: • Security and privacy → Hardware security implementation;
Additional Key Words and Phrases: Path changing switch (PCS), physically unclonable function (PUF), arbiter
PUF (APUF), IoT, FPGA, programmable delay line (PDL)

1 This is an extended version of the article that appeared in IEEE SOCC 2019 [28]. For the convenience of the reviewers, we

have attached the conference paper with this submission. We have also provided a list of additional contributions of this
submitted version with respect to the conference version.

This work is sponsored by DST-SERB under core research scheme (Formerly EMR) through grant No. EMR/2017/003206,
WBDHESTB through the grant number ST/P/S&T/6G-04/2017 and Young Faculty Research Fellowship of Visvesvaraya
PhD scheme through the grant number MLA/MUM/GA/10(37)B.
Authors’ addresses: M. H. Mahalat, S. Mandal, A. Mondal, and B. Sen, Department of Computer Science and Engineer-
ing, National Institute of Technology Durgapur, Durgapur, West Bengal, India, 713209; emails: {mahabubhasan.mahalat,
surajcse71, anindanmondal14}@gmail.com, [email protected]; R. S. Chakraborty, Department of Computer
Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India, 721302; email:
[email protected].
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee
provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and
the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored.
26
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prior specific permission and/or a fee. Request permissions from [email protected].
© 2021 Association for Computing Machinery.
1084-4309/2021/11-ART26 $15.00
https://doi.org/10.1145/3491212

ACM Transactions on Design Automation of Electronic Systems, Vol. 27, No. 3, Article 26. Pub. date: November 2021.
26:2 M. H. Mahalat et al.

ACM Reference format:

Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen, and Rajat Subhra Chakraborty. 2021.
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a
lightweight Security Primitive for IoT. ACM Trans. Des. Autom. Electron. Syst. 27, 3, Article 26 (November 2021),
26 pages.
https://doi.org/10.1145/3491212

1 INTRODUCTION
The fast pace advancement of internet technology and its key feature of the connected envi-
ronment propel the growth of the Internet-of-Things (IoT) which connects billions of devices,
swiftly driving smart life experience of all users. It is forecasted that by 2025 there will be 75 billion
connected devices [53]. However, the resource constrained IoT devices face several challenges in
ensuring security. In most IoT devices, resources like CPU, power and memory, are limited. Thus,
the standard cryptographic algorithms having prohibitive resource demand, are not feasible to
use in low-cost IoT devices. Also, the secret key used in classical cryptographic protocols is gen-
erally stored in non-volatile memory, which is itself vulnerable to potential threats. Moreover, the
standard cryptographic protocols are not sufficient to prevent physical attacks (i.e. tampering, side-
channel analysis, fault injection) on their own [43]. A single compromised IoT device may have
a profound impact on the IoT network and may cause catastrophic damage to the whole IoT net-
work [7]. Besides, the IoT devices are mostly deployed in an un-monitored environment, which
escalates the potential security threats. In fact, IoT devices are more susceptible to physical attacks
[7, 34].
Towards this direction, Physically Unclonable Function (PUF) has emerged as a promising se-
curity primitive that can provide low-cost security from the root of the hardware [4, 11, 22, 35, 51].
PUF has the ability to harvest the uncontrollable inherent randomness of a device to provide it
a unique identity. PUF generates a response (output) against a challenge (input), where the rela-
tion between the challenge and response depends on the inevitable fabrication variation of the
device embodies PUF. The unique features of PUF include unclonability, tamper-evident property,
and non-volatile key generation [11, 50]. Major variants of PUF are arbiter PUF (APUF), ring
oscillator PUF (RO PUF), SRAM PUF, RS Latch PUF, etc. [11, 16, 17, 50]. Among other PUF
variants, APUF is considered to be one of the most promising for IoT applications due to its re-
markably lightweight and regular structure. APUF is able to generate an exponential number of
challenge-response pairs (CRPs) using relatively low hardware resources which makes it a suit-
able candidate for IoT. However, the rigid fabric of FPGA is an obstacle to implement a high-quality
APUF on it. The conventional APUF implemented on FPGA suffers from low uniqueness which
is an essential property of PUF [18, 19, 26, 29, 47]. On the other hand, FPGAs can easily interface
with the outside world and provide low power and low latency determinism which make them
a primary driving force of the IoT. Indeed, recently FPGAs are being adopted in different IoT ap-
plications including smart city, smart grid, industry 4.0, health care, connected care, data center,
etc. [37, 39]. Hence, implementing a high-quality APUF on FPGA will be extremely beneficial for
providing low-cost security to IoT.
To date, programmable delay logic (PDL) is the most adopted primitive to alleviate the im-
plementation issues of APUF on FPGA [30, 44]. However, even the PDL based APUF designs can-
not provide the desired uniqueness without using fine-tuning, which additionally increases the
hardware overhead [30, 46]. Also, PDL-based APUF requires the FPGA CAD tool to support the
“hard-macro” feature for implementation, which makes the design less flexible as well as restricts
the free resources (inside a CLB) to be used by other logic. Nevertheless, in this paper, we have

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:3

investigated that the use of fine-tuning for unbiasing the PUF is not feasible practically. Tuning
(using PDL) can only reduce the delay bias if it is performed separately on individual PUF instances
which is a tedious task and will increase the device cost. Hence, it may not be suitable for low-cost
IoT devices. Also, it will violate the PUF property. We have proposed the path changing switch
(PCS) as a primitive to implement APUF on FPGA, which can overcome the limitations of the
existing PUFs. The PCS is a switching structure consists of inverters and multiplexers which can
be implemented on FPGA without using the hard macro. The main advantage of the PCS based
APUF is that it can achieve the required PUF property without the need for additional fine-tuning.
Furthermore, in the PCS based APUF, the delay paths are implemented symmetrically utilizing the
less restrictive directed routing constraints feature of the CAD tool, which improves flexibility.
In this paper, we have performed an in-depth analysis of the PCS based APUF to deploy it in
IoT practically. We have characterized the PCS based APUF in two different FPGA technologies
a) Spartan-3E (90 nm CMOS) b) Artix-7 (28 nm CMOS). It is an absolute necessity to compare the
PUF performance in different technology, as the process variations also change depending on the
fabrication process. Also, the flexibility of the PCS based APUF needs to be verified across different
technology. In addition to the characterization of the PCS based APUF, we have analyzed its secu-
rity in terms of entropy and randomness test which are essential criterion to prevent cryptanalysis
attacks. Also, modeling robustness of the PCS based APUF is verified through Artificial Neural
Network (ANN) based modeling attack. Further, we have characterized and investigated the XOR
composition of the PCS based APUF to boost its performance and robustness to modeling attack.
The increase of robustness of the XOR-PUF based on PCS based APUF follows the same trend as
that of the XOR-PUF constituted of conventional APUF. The contributions of this paper can be
summarized as below:
• Feasibility analysis of the fine-tuning concept of PDL based APUF for FPGA.
• Characterization of the PCS based APUF on Spartan-3E (90 nm CMOS) and Artix-7 (28 nm
CMOS) FPGA.
• Security analysis of the implemented PCS based PUF in terms of randomness and entropy.
• Performance improvement of the PCS based APUF through its XOR-composition and ana-
lyze its security.
• Analysis of the modeling robustness of the PCS based APUF and its XOR composition by
ANN based machine learning attack.
The rest of the paper is structured as follows: In the following section we briefly describe the basic
APUF and the structure of PDL. The limitations of the PDL are explained in Section 3. Section 4
describes the design of the PCS based APUF and shows the implementation of PCS based APUF
on Spartan-3E and Artix-7 FPGA. Section 5 presents the characterization metrics of the PCS based
APUF. Section 6 presents the results of the performance evaluation of the PCS based APUF and
compares the performance with other APUF designs. Performance improvement of the PCS based
APUF through the XOR composition and the corresponding results are discussed in Section 7.
Modeling robustness of the proposed PCS based PUF and the discussion in the context of IoT is
reported in Section 8. Finally, Section 9 concludes the paper.

2 BACKGROUND
2.1 Basic Arbiter PUF
An Arbiter PUF (APUF) generates a response by comparing the travel time of a signal propa-
gating through two structurally symmetric paths [6]. The response relies on the intrinsic physical
variation of these delay paths. An APUF consists of several path swapping switches and an arbiter,

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26:4 M. H. Mahalat et al.

Fig. 1. Structure of a basic APUF.

Fig. 2. PDL using a three input LUT.

as shown in Figure 1. The signal inside a switch follows either the direct or the crossed path de-
pending on the challenge bit Ci . The arbiter gives 0 or 1 as the response (R) bit based on the arrival
time of the signal at its two inputs. If the signal of the top delay path reaches first, the arbiter
produces 1 as the response bit otherwise produces 0 as the response. An APUF, with a challenge
length of n bits, is able to generate 2n different challenge-response pairs.

2.2 Programmable Delay Logic (PDL) on FPGA

The rigid fabric of the FPGA makes it hard to place the delay paths on an FPGA symmetrically.
Programmable delay logic (PDL) is introduced as a switching structure to implement APUF on
FPGA. Construction of the PDL using the lookup table (LUT) of an FPGA is introduced in [30].
PDL leverages the delay variation of the internal delay paths of a LUT. PDL using a three-input LUT
is shown in Figure 2. A PDL can be constructed using the LUT by configuring it (the LUT) as an
inverter. In Figure 2, S 1 is the inverter input and S 2 , S 3 are redundant inputs. Although, the output
(i.e. 0 or 1) of inverter is independent of S 2 and S 3 , from Figure 2, it can be observed that the signal
propagation path inside the LUT depends on S 2 and S 3 . For instance, the signal propagates through
the path denoted by a solid line (red) or dotted line when S 2S 3 = 11 or S 2S 3 = 00, respectively. Thus,
different propagation paths can be selected using S 2S 3 . The propagation paths may have different
lengths, so the propagation delay depends on the value of S 2S 3 . These select lines of the PDL (i.e.
S 2S 3 ) are used as the challenge bits in the PDL based APUFs. However, the PDL based APUFs
cannot achieve the essential PUF properties without additional tuning. The tuning using PDL and
its feasibility are discussed in the following section.

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:5

Fig. 3. Ring Oscillator (RO) circuit used for delay measurement.

3 LIMITATIONS OF PDL FOR TUNING THE DELAY BIAS

The PDL based APUFs presented in the literature [30, 44], are biased and cannot achieve the unique-
ness, which is a fundamental property of the PUF. To solve this problem, additional PDLs are in-
serted as the tuning elements in both the top and bottom delay paths. For instance, if the top path
of the APUF has less systematic delay compared to the bottom path due to routing asymmetry,
then the select lines of the tuning elements in the top and bottom path are configured to maximize
and minimize the delay, respectively. Once the tuning bits are determined, they should be fixed
for all the APUF instances (across all the devices). Here “tuning bit” and “select line” are used al-
ternatively. According to the definition of PUF, all the PUF instances should be symmetric, so it is
required to use the same tuning bits in all the APUF instances [30]. However, the same tuning bits
will be applicable (i.e. to reduce the delay bias) for all the PUF instances only if the internal prop-
agation paths selected by the same tuning bits in the symmetric LUTs (in different devices) have
similar delay characteristics. To investigate it further, we have characterized the delay properties
of different propagation paths of a LUT in Artix-7 and Spartan-3E FPGA. Artix-7 and Spartan-3E
FPGA consists of six and four input LUTs, respectively. Thus, in Artix-7, a PDL with five tuning
bits (i.e. 25 = 32 different combinations) can be implemented whereas in Spartan-3E, a PDL with
three tuning bits (i.e. 23 = 8 different combinations) can be implemented.
We have analyzed the impact of the tuning bits on delay variation of PDL, considering multiple
FPGAs on multiple boards. To measure the delay, we have used a ring oscillator (RO) circuit
shown in Figure 3. The counter at the end of RO measures the relative frequency of the RO with
reference to the clock frequency of the FPGA device. The delay can be obtained from the measured
frequency of the RO by knowing the clock frequency of the FPGA. We have measured the RO
frequency 10 times, and then taken the average value to minimize the measurement error. Here,
the measured delay denotes the delay of the entire circuit containing one AND gate, two inverters
and one PDL. However, finding the delay variations caused by the tuning bits in different devices
(or different LUTs) are of our interest not the actual delay. So it will not affect our analysis. The
delay variation (caused by different tuning bits) measured in Artix-7 and Spartan-3E FPGA are
shown in Figure 4 and Figure 5, respectively.
The key observations made from Figure 4 and 5 are as follows:
• The same tuning bits in different devices (or in different LUTs of the same device) may have
the opposite effect on the delay. For instance, consider Artix-7 (1) in Figure 4(a), tuning bit
3 has more delay compared to tuning bit 0 in board 4 whereas in other two boards tuning
bit 3 has less delay compared to tuning bit 0. (2) in Figure 4(b), tuning bit 3 of CLB X49Y101
has less delay than tuning bit 0 whereas in the other two CLBs tuning bit 3 have more delay
than tuning bit 0. Similar effects are also observed in Spartan-3E (Figure 5).
• The delay differs by a different amount in similar LUT of different devices (or different LUTs
of the same device), i.e., consider Figure 4(a), in board 4 tuning bit 12 and 15 has a delay
difference of ≈ 0.7ps whereas in board 7 it is ≈ 0ps.

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26:6 M. H. Mahalat et al.

Fig. 4. Delay variations caused by different tuning bits in Artix-7 FPGA (a) same LUT of different boards,
(b) symmetric LUT of different CLBs.

Fig. 5. Delay variations caused by different tuning bits in Spartan-3E FPGA (a) same LUT of different boards
(b) symmetric LUT of different CLBs.

From the above discussion, it is evident that using the same tuning bits to reduce the delay
bias in different PUF instances might not always work. Furthermore, a situation appears where
a tuning bit increases the delay (compared to another tuning bit) in one device but decreases the
delay in another device, which will worsen the delay bias. Hence, applying the same tuning bits
on different PUF instances to mitigate the delay bias is not feasible practically.

4 DESIGN AND IMPLEMENTATION OF THE PCS BASED APUF

The most remarkable feature of the PCS based APUF is that it can achieve the desired PUF proper-
ties without using additional tuning. The delay paths of the PCS based APUF can be made closely
symmetric on FPGA, which minimizes the delay bias. Hence the PCS based APUF can achieve
desired PUF properties without requiring tuning.

4.1 Design of the PCS based APUF

The PCS based APUF is constructed by using PCS as the basic building block. A PCS is a switch-
ing structure which consists of four inverters and three multiplexers (MUX). The inverters are
considered as the primary delay-elements where the multiplexers select one inverter among the
four different inverters. The structure of a PCS is shown in Figure 6(a). The select lines of the mul-
tiplexers (C 2i−1 and C 2i ) are used as the PUF challenge. In PCS, unlike PDL, the inverters (which

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:7

Fig. 6. Construction of the PCS based APUF.

are implemented using LUT) are the main delay elements. The top and bottom delay paths of the
PCS based APUF are constructed independently. The structure of the PCS based APUF is shown
in Figure 6(b). The enable comprises three registers namely primary, top and bottom enable to
trigger the delay paths simultaneously. This structure of the enable logic helps to place it on FPGA
symmetrically. The SR latch based arbiter captures the delay variation between the top and bottom
delay paths and produces 1 or 0 as the response bit. The use of a dedicated D-latch of FPGA as the
arbiter introduces delay bias so the SR latch is adopted instead [44].

4.2 Analysis of the PCS based APUF

The PCS based APUF, unlike the conventional APUF design, uses two independent delay paths
which are not cross-coupled. This structure of the PCS based APUF facilitates the design to
implement the delay paths symmetrically on FPGA. In previous studies, it has been observed that
it is difficult to symmetrically implement the cross-coupled switches of the conventional APUF on
FPGA [30, 44]. However, the PCS based APUF generates the response by racing a signal through
two symmetric delay paths, principally similar to the conventional APUF.
A challenge bit Ci in the PCS based APUF selects a symmetric delay-element (i.e. inverter along
with the attached circuitry) in both the top and bottom paths to propagate the signal. Let the delay
of the delay-elements selected by Ci = 1, is ti and bi , in the top and bottom path respectively. The
delay difference i between the delay-elements selected by Ci = 1 can be obtained as:
i = ti − bi (1)
Similarly, the delay difference i  for Ci = 0 can be computed as:
i  = ti − bi (2)
Where ti, bi are the delay of the selected delay-elements in the top and bottom path, respectively
for Ci = 0. The cumulative sum of all the delay differences (considering all the challenge bits)
defines the final response bit R of PCS based APUF. Let the total delay difference between the top
and bottom paths of the PCS based APUF is D n .

n
Dn = (i)Ci .(i  ) 1−Ci (3)
i=1

Where, n is the number of challenge bits. Final response R can be evaluated as:
⎧
⎪ 1, if D n > 0
R=⎨
⎪ 0, Otherwise (4)
⎩

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Fig. 7. A PCS (i.e. i t h PCS) inside a CLB of Spartan-3E FPGA.

In previous works, delay of a delay-element has been commonly represented by a Gaussian dis-
tribution with mean μ and standard deviation σ as N (μ, σ 2 ) [24, 31]. The delay difference i (or
i ), without losing generality can be represented by Gaussian distribution with zero mean as N (0,
2σ 2 ). Summation of mutually independent Gaussian random variables also follows a Gaussian dis-
tribution [31]. So, the delay difference D n can be expressed (assuming independence of the top and
bottom paths) as:
 n 
n
Dn = (i)Ci .(i  ) 1−Ci = N (0, 2σ 2 ) = N (0, 2nσ 2 ) (5)
i=1 i=1
From Equation (5), it can be observed that the PCS based APUF has similar delay characteristic
as the conventional APUF [24]. Thus, the PUF properties of the PCS based APUF can be analyzed
similarly to the conventional APUF. A statistical analysis of the properties of APUF and its variants
can be found in [24].

4.3 Implementation of the PCS based APUF on Spartan-3E FPGA

Here, the implementation technique of the PCS based APUF on Spartan-3E FPGA is discussed
briefly to perform a fair comparison with the implementation on Artix-7 FPGA. For more details
of the implementation technique, the readers are referred to [28].
A CLB of Xilinx Spartan-3E FPGA (90 nm CMOS) is composed of four slices, i.e. two Slice L and
two Slice M. Each Slice contains two 4-input LUTs; thus a CLB contains a total of 8 LUTs. A PCS
can be implemented by using a single CLB. Implementation of a PCS inside a CLB is shown in
Figure 7. Here it should be noted that among three multiplexers, two are implemented using LUT,
which can also be implemented using the F5MUX, but that will increase the routing asymmetry.
A delay path is implemented using the user constraint file (UCF) and the source code of a PCS
as the basic unit. The two delay paths are made symmetric to each other with the help of BEL,
LOC (i.e. placement constraints) and directed routing constraint (DRC) feature of the CAD tool.
For the symmetric implementation of the delay paths, the DRC feature of the CAD tool is utilized
instead of the hard macro as using hard-macro will prevent the remaining resources of a CLB from
being used by other logic. Few device-dependent constraints are applied to minimize the routing
asymmetry and the delay bias, which are as follows:
• The top and bottom delay-paths are placed parallel to each other vertically in the FPGA
device.
• A dedicated D flip-flop is used to implement the primary enable. The top and bottom enable
are implemented utilizing the LUT F and LUT G of symmetric slices, respectively.

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:9

Fig. 8. A PCS based APUF implemented on Spartan-3E FPGA (Xilinx FPGA editor view (90o rotated
clockwise)).

Fig. 9. Routing asymmetries of the PCS based APUF implemented on Spartan-3E FPGA (a) routing asym-
metry at the beginning (b) routing asymmetry at the end.

• The last PCS (i.e. nt h PCS) of both the delay paths are implemented using two slice L and
one Slice M whereas rest of the PCSes are implemented using two Slice M and one Slice L.
Figure 8 shows the implementation of the PCS based APUF on Spartan-3E FPGA. It can be observed
that the top and bottom delay paths follow exact symmetric routing except the beginning and the
end. The routing asymmetries of the implemented PCS based APUF are highlighted in Figure 9.
However, following the FPGA editor tool, at the beginning, the delay difference between the top
and bottom path is 12ps (Figure 9(a)) and it is −12ps at the end (Figure 9(b)), which almost nullify
the effect of routing asymmetry.

4.4 Implementation of the PCS based APUF on Artix-7 FPGA

A CLB of an Artix 7 FPGA (28 nm CMOS) contains two slices, i.e. both are Slice L or one Slice L and
one Slice M. Each slice contains four 6-input LUTs, thus a CLB contains a total of 8 LUTs. A PCS can
be implemented inside a single CLB using six LUTs and one dedicated F7MUX. Implementation of
a PCS is shown in Figure 10. It can be seen that implementation of a PCS on the Artix-7 is similar
to the implementation on Spartan-3E FPGA.
A delay path is implemented using PCS as the basic unit by applying the same technique adopted
for Spartan-3E. However, the placements of the delay paths are different from Spartan-3E to con-
nect the arbiter and the enable logic symmetrically. Here, the delay paths are placed parallel to
each other row by row like a chain. Like Spartan-3E, here also the placement of the last PCS (nt h

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Fig. 10. A PCS (i th PCS) implemented using a CLB of Artix-7 FPGA.

Fig. 11. The PCS based APUF implemented on Artix-7 (a) Enable logic and the beginning of the delay paths
(b) Arbiter and the ending of the delay paths.

PCS) differs from others i.e. the multiplexers are implemented using A6LUT, B6LUT and F7AMUX.
The implemented PCS based APUF on Artix-7 is shown in Figure 11. The top and bottom enables
are implemented using C6LUT and F7BMUX of two symmetric slices L. The primary enable is im-
plemented using C6LUT and F7BMUX of a Slice M. It can be noted that the implemented design is
exactly symmetric except the ending. The wire which connects the top delay path with the Arbiter
is not precisely symmetric to the wire connecting the bottom delay path and the Arbiter. However,
in the FPGA editor, we have checked that the delay difference is only 1ps which can be ignored.

5 METRICS FOR CHARACTERIZATION OF THE PCS BASED APUF

In this section, we have introduced the metrics used for the characterization of the PCS based
APUF. Reliability, uniqueness, and uniformity are the primary metrics used to evaluate the PUF
property [29]. Besides these, entropy and randomness are the desired properties that need to be
satisfied by PUF to deploy it as a security primitive practically [21, 23].

5.1 Uniqueness
Uniqueness (U), which denotes the ability of PUF to identify two similar PUF instances uniquely
is measured by the difference between the response of two similar PUF instances against the same

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challenge. Uniqueness is evaluated using the following equation:

2 
I −1 I
H D(Pi , Pj )
U= × 100% (6)
I (I − 1) i=1 j=i+1 n
where I is the number of PUF instances, H D (Pi , Pj ) denotes the Hamming distance between the
response (against the same challenge) of the PUF instance Pi and Pj and n is the number of re-
sponse bits. In other words, uniqueness measures the average Hamming distance of the responses
of similar PUF instances against the same challenge. The optimal value of uniqueness is 50%.

5.2 Reliability
A PUF instance is expected to produce the same response against a challenge C always. Reliability
(R) measures the ability of PUF to generate the same response considering a constant challenge.
It is calculated as: r 
1  H D Pj , Pj
K i

R = 1 −
× 100% (7)
K i=1 n
 
where K denotes the number of times response is measured, r Pj is the response of the PUF in-
stance P j measured at the nominal environmental condition and i Pj is the response during i t h
measurement. The optimal value of reliability is 100%.

5.3 Uniformity
Uniformity (Un) denotes the generation of 0 or 1 as the response bit (of a PUF instance) with the
same probability. It measures the proportion of 0 and 1 in the PUF response. Uniformity of a PUF
instance is obtained using the following equation:
1
n
Un = (r i × 100%) (8)
n i=1

where n is the number of response bits and r i denotes the i t h response bit. The ideal uniformity is
50%.

5.4 Entropy
The entropy test is used to measure the impact of a challenge bit of the APUF on its security.
Here, the conditional Shannon entropy based approach presented in [23] is utilized to measure the
entropy.
Let C x is a challenge from a random set of challenge S, and C y is a neighboring challenge of C x ,
i.e. the Hamming distance between C x and C y , H D(C x , C y ) = 1. Thus, challenge C x will have n
neighbors (C y ) for a challenge length of n bits. Considering the PUF response as X and Y against
the challenge C x and C y respectively the conditional Shannon entropy (H (X | Y )) can be calculated
using the following equation:
  
p(x, y)
H (X | Y ) = − p(x, y) log2 , (9)
x ϵ X,yϵY
y

where p(x, y) and p(y) denote the probability of the event (x, y) and y, respectively, considering
the number of random challenges C x as the total events. H (X | Y ) is computed considering a
single (C x , C y ) pair at a time. Thus, for n bit challenge, n different H (X | Y ) needs to be computed.
H (X | Y ) can be 0 ≤ H (X | Y ) ≤ 1, where a higher value indicates a high degree of randomness
(i.e. high security) and a low value indicates the mutual information is very high (i.e. low security).

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26:12 M. H. Mahalat et al.

Table 1. Performance of a 64 bit PCS based APUF on Spartan-3E and Artix-7 FPGA

FPGA Uniqueness (%), (Std.) Uniformity (%) Reliability (%)

Technology — Max Min Average, (Std.) Max Min Average, (Std.)
Spartan-3E 49.81, (12.86) 90.17 10.54 49.77, (25.50) 99.11 97.75 98.19, (0.35)
Artix-7 51.34, (15.07) 99.39 3.11 57.64, (37.64) 99.75 97.73 97.57, (1.49)

5.5 Randomness Test

There is no specific metric to evaluate the randomness of a response vector of PUF. The NIST test
suite is originally designed to evaluate the performance of a random number generator, not the
PUF [41]. So, successful testing does not guarantee the randomness of the PUF response but failing
a test indicates a lack of randomness in the PUF response. In this work, we have used a subset of
the NIST test suite containing six tests, which was also adopted in [32], to check the randomness of
a response string of the PCS based APUF. The NIST tests are as follows: frequency test (T 1), block
frequency test (T 2), runs test (T 3), longest run test (T 4), approximate entropy test (T 5), cumulative
sums forward (T 6) and cumulative sums backward test (T 7). The selected subset of the NIST test
suite requires a string with a minimum length of 128 bits. So, we have used a randomly generated
response string of the PCS based APUF with length 128 bits as the input to the NIST suite.

6 PERFORMANCE EVALUATION OF THE PCS BASED APUF

6.1 Experimental Setup
The results presented in this section are based on a 64-bit PCS based APUF implemented on fifteen
Xilinx Spartan-3E and nine Artix-7 (Digilent Nexys-4) boards. The Microblaze MCS is utilized to
perform a serial communication between the FPGA board and the PC where challenge-response
pairs are extracted using Matlab. The response against a challenge is extracted seven times and
the majority of the generated response bit is considered as the final response for minimizing the
measurement error.

6.2 Evaluation of the Fundamental Quality Metrics

We have collected a set of 1,000 responses against 1,000 random challenges (in normal operating
condition) from each of the FPGA boards to evaluate the performance. The uniqueness, reliability
(calculated in normal temperature), and uniformity of the 64-bit PCS based APUF are shown in Ta-
ble 1. The reliability is calculated by performing 10 different measurements using a fixed challenge
set (in normal operating conditions) on each of the boards. It can be observed that the uniqueness
and reliability of the proposed PCS based APUF closely follow the ideal behavior in both FPGAs.
However, the average uniformity is close to the ideal value (i.e. 50%) but the standard deviation
(Std.) is high and the maximum and minimum uniformity differs from the ideal value. To give a
close look on the uniformity variation, we have further shown the uniformity deviation from the
ideal value (50%) on the individual FPGA boards in Figure 12. Uniformity deviation is obtained as
the difference between the measured uniformity (%) and the ideal uniformity of 50%. i.e. |measured
uniformity−50|. It can be observed that the uniformity deviates from the ideal value (50%) in some
of the boards. To be specific, in five out of fifteen Spartan-3E FPGA boards the value of uniformity
deviates by more than 30 (equivalent to 60% deviation from the ideal value). In case of Artix-7, only
four out of nine boards show a uniformity deviation of more than 30. Thus, the PCS based APUF
achieves desired uniqueness and reliability but slightly deviates from the ideal uniformity in some
of the individual PUF instances (boards). However, the PDL based APUFs cannot even achieve the
required uniqueness without using tuning.

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:13

Fig. 12. Uniformity deviation of the 64-bit PCS based APUF on individual FPGA boards (a) Uniformity devi-
ation on Spartan-3E FPGA (b) Uniformity deviation on Artix-7 FPGA.

Fig. 13. Impact of temperature on the reliability of the PCS based APUF (a) Reliability on Spartan-3E FPGA
(b) Reliability on Artix-7 FPGA.

The IoT devices are mostly placed in an uncontrolled environment. So, we have collected the
challenge-response pairs in a temperature range of 25o C to 65o C with an increment of 10o C to
investigate the effect of environmental variation on the reliability of PCS based APUF. The re-
liability in different temperatures with reference to the response set generated at nominal tem-
perature (25o C) is shown in Figure 13. We have shown the reliability of the FPGAs in which the
value of uniformity is very close to the ideal value of 50%. The PUF instances having very low
or high uniformity value possess better reliability. Hence, these are less affected by the environ-
mental variation. According to Figure 13, the lowest reliability measured in Spartan-3E is 94.1%
due to temperature variation, which deviates by 3.84% from the reliability at normal temperature
(i.e. 25o C). In Artix-7, the lowest reliability is 88.71% which deviates by 11.50% from the reliability
at normal temperature. Thus, it can be inferred from the experimental results of Spartan-3E and
Artix-7 FPGA that the worst-case reliability of the PCS based APUF does not deviate by more than
12% due to a variation of 40o C in the temperature (i.e. 25o C to 65o C). However, the impact of tem-
perature on the reliability is slightly higher on Artix-7 (28 nm technology) compared to Spartan-3E
(90 nm technology) FPGA.

6.3 Evaluation of Response String Randomness

We have collected a response string of length 12,800 from each of the boards by applying 12,800
random challenges to perform the randomness tests. The most widely used NIST randomness

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Table 2. Pass Rate of the Response Sequences

of Spartan-3E FPGA

Board No. T1 T2 T3 T4 T5 T6 T7
1 0 4 1 2 0 0 0
2 17 77 69 64 37 19 23
3 0 0 0 0 0 0 0
4 98 98 99 98 98 99 98
5 0 0 0 0 0 0 0
6 0 5 1 1 0 0 0
7 99 99 98 99 99 100 98
8 96 98 100 100 99 96 97
9 0 4 0 2 0 0 0
10 19 69 65 60 30 18 19
11 0 20 12 18 2 0 0
12 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0
15 90 99 97 97 92 93 95

Table 3. Pass Rate of the Response Sequences

of Artix-7 FPGA

Board No. T1 T2 T3 T4 T5 T6 T7
1 0 0 0 0 0 0 0
2 87 98 98 93 91 87 86
3 0 23 10 16 2 0 0
4 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0
6 97 100 100 100 99 96 97
7 39 92 90 80 63 40 41
8 0 0 0 0 0 0 0
9 86 99 99 94 94 87 88

tests (discussed in Section 5.5) are performed by partitioning a response string into 100 sequences
having 128 bit length. The results of the tests performed on Spartan-3E and Artix-7 are presented in
Table 2 and Table 3, respectively. The different tests are denoted by the columns T 1,T 2, . . . ,T 7 (i.e.
see Section 5.5). The number written inside a cell in the column T i (i.e. iϵ {1, 2, . . . 7}) denotes the
percentage of the sequences which pass test T i considering the board implied by the corresponding
row. The high pass rate denotes good randomness whereas the low pass rate indicates a lack of
randomness. In Spartan-3E, nine out of fifteen boards show a pass rate of zero in at least one of
the tests. In Artix-7, five boards out of nine boards have zero pass rate in at least one of the tests.
These mean that the response strings considerably lack in randomness in those PUF instances
(boards). However, comparing Table 2 and Table 3 with Figure 12(a) and 12(b), respectively, it can
be seen that the response of the boards in which uniformity deviates from the ideal value also lack
in randomness. On the other hand, the boards with close to ideal uniformity value possess better
randomness. This suggests that improving the uniformity of an individual PUF instance of the PCS
based APUF will eventually enhance the randomness of its response string.

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:15

Fig. 14. Entropy of 64-bit PCS based APUF implemented on Spartan-3E FPGA.

6.4 Evaluation of Entropy

We have performed the entropy calculation using 1,000 random challenges and their 1-bit neigh-
bors (i.e., total 1,000 ∗ (64 + 1) = 65,000 challenges). The calculated entropy of the PCS based APUF
on Spartan-3E and Artix-7 FPGA are shown in Figure 14 and Figure 15, respectively. For concise
analysis, we have shown the calculated entropy of three Spartan-3E and three Artix-7 FPGA boards
having lowest, moderate, and best entropy values. A challenge bit with the high entropy value (≈1)
indicates that it contributes more towards the security of the PUF, whereas the low entropy (≈0)
denotes less contribution on the PUF security. For effective security of PUF, all the challenge bits
should have high and uniform entropy value. Though the PUF instance on board 13 of Spartan-3E
(Figure 14) and board 5 of Artix-7 (Figure 15) have low entropy, the entropy of different challenge
bits are random and do not follow a specific pattern. Hence, by observing the entropy values of an
instance of the PCS based APUF an adversary cannot extract any information about the responses
of another PUF instance. It is worth to mention that the PUF instances with low entropy values
also significantly deviate from the ideal uniformity (Figure 12).

6.5 Hardware Overhead

The resources used by a 64 bit PCS based APUF implemented on Spartan-3E (Spartan-3E
XC3S500E) and Artix-7 ( XC7A100T) FPGA are shown in Table 4 and Table 5, respectively. It can
be noticed that the implemented PCS based APUF incurs negligible hardware foot-print on the
FPGAs. In Spartan-3E, the PCS based APUF incurs only 3.70% of the total LUTs and 4.20% of the
total slices, respectively. Furthermore, in Artix-7, it uses less than 1% of total LUTs and Slices. It
is to be noted that the hard macro feature is not used during implementation (except the Arbiter)
of the PCS based APUF. The hard macro restricts the leftover resources of a CLB to be utilized by
other logic which eventually increases the hardware overhead. Thus, the leftover resources of the

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26:16 M. H. Mahalat et al.

Fig. 15. Entropy of 64-bit PCS based APUF implemented on Artix-7 FPGA.

Table 4. Resources Used by a 64 Bit PCS based APUF

Implemented on Spartan-3E FPGA

Component LUTs Slices F5 MUXes Latches

Delay Paths 384 192 64 —
Enable Logic 2 3 — 1
Arbiter 2 1 — —
Entire APUF 388 196 64 1
Resources used w.r.t
3.70% 4.20% 1.37% 0.01%
resources in FPGA

Table 5. Resources Used by a 64 Bit PCS based APUF

Implemented on Artix-7 FPGA

Component LUTs Slices F7BMUXes Latches

Delay Paths 384 128 64 —
Enable Logic 3 3 2 —
Arbiter 2 1 — —
Entire APUF 389 132 66 —
Resources used w.r.t
0.61% 0.83% 0.41% —
resources in FPGA

CLBs of the implemented PCS based APUF are available to be used by any other logic which also
improves the hardware utilization.
It is difficult to perform a direct comparison among various APUF designs implemented on dif-
ferent FPGA technology. However, Table 6 compares the performance of the PCS based APUF with

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:17

Table 6. Performance Comparison of Different APUFs on FPGA

Uniqueness Uniformity Reliability Challenge Hardware

APUF Design Technology
(%) (%) (%) Length Consumption
APUF [19, 29] Virtex-5 7.2 55.69 99.76 64 129 Slices
32 LUTs +
APUF [47] Spartan-3 8.1 37.3 99.7 16
1 Filp-flop
APUF [18] Artix-7 9.42 64 129 Slices
APUF [26, 27] Virtex-5 4.7 54.78 99.32 64 130 Slices
2-1 Double
Virtex-5 46.37 45.74 90.31 64 303 Slices
APUF [25, 27]
PDL APUF without
Spartan-3 28 43.38 96.66 90
tuning [44]
PDL APUF
Spartan-3 45.25 48.09 95.93 90
with tuning [44]
Modified APUF [14] Artix-7 20 96.64 64 128 Slices
FF APUF [13, 15] Artix-7 41.53 97.1 64 128 Slices
Xilinx 266 Slices+128
MMPUF [5] 40.6 96 64
7-series Weak PUFs
PCS Spartan-3E 49.81 49.77 98.19 64 196 Slices
based APUF Artix-7 51.34 57.64 97.57 64 132 Slices

previous APUFs implemented on FPGA to give the reader an idea about the performance of the
PCS based APUF. It can be observed that the conventional APUF design [18, 19, 26, 27, 29, 47]
significantly lacks in uniqueness on FPGA although exhibits close to the desired (average) unifor-
mity and (average) reliability. The conventional APUF can only achieve the uniqueness as high as
9.42% [18]. The modified APUF [14] compares two independent delay paths composed of flip-flops
and multiplexers to generate a response bit. The FF-APUF [13, 15] also generates a response bit
by comparing two independent delay paths consisting of asynchronous elements. The uniqueness
of the modified APUF and the FF APUF is 20% and 41.53%, respectively which show notable im-
provement over the conventional APUF but still lack from the ideal uniqueness (50%). The double
APUF [25, 27] utilizes redundant APUFs to improve the uniqueness. It enhances the uniqueness
to 46.37% but worsens the reliability and incurs significant hardware (i.e., takes 303 slices). The
MMPUF [5] achieves a uniqueness of 40.6%. However, a 64 bit MMPUF is composed of a 64 bit
APUF and 128 weak PUFs, which also increases hardware overhead. The PDL APUF [44] exhibits
an improved uniqueness of 45.35% with the penalty of low reliability (95.93%) and additional tun-
ing circuit. The hardware overhead of the PDL APUF is not mentioned explicitly in the related
literature. From the reported details in [44], it can be observed that two PDLs are implemented in-
side a CLB utilizing the hard-macro feature. One disadvantage of the hard-macro is that it makes
the leftover resources inside the CLB in which it is located, unavailable for usage by other logic.
Based on this observation, in practice, the PDL APUF with 90 challenge bits occupies ≈32 CLBs or
≈32 ∗ 4 = 128, slices in Spartan-3 FPGA. Also, the authors used eight additional PDLs for tuning,
taking four CLBs or 16 slices (assuming two PDLs in a CLB). However, as discussed earlier, tuning
using PDL is not feasible practically. The PCS based APUF shows a higher uniqueness of 49.81%
and 51.34% in Spartan-3E and Artix-7 FPGA, respectively, while maintaining a modest reliability
of 98.19% and 97.57% in Spartan-3E and Artix-7, respectively. The PCS based APUF almost utilized
the same hardware resources like the conventional APUF design. It is to be noted that, in Spartan-
3E, each CLB contains four slices and each slice contains two LUTs, whereas a CLB of Virtex-5
and Artix-7 contains two slices and four LUTs per slice. Thus, although the PCS based APUF on

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26:18 M. H. Mahalat et al.

Table 7. Performance of a 3-XOR Composition of 64 Bit PCS based APUF

FPGA Uniqueness (%), (Std.) Uniformity (%) Reliability (%)

Technology – Max Min Average, (Std.) Max Min Average, (Std.)
Spartan-3E 50.11, (2.43) 70.62 23.94 47.79, (10.55) 97.23 93.75 96.03, (1.09)
Artix-7 50.36, (2.25) 68.87 43.68 53.68, (9.56) 95.44 91.71 93.88, (1.46)

Spartan-3E consumes more slices than Artix-7 but has a similar hardware overhead as on Artix-7
(Table 4 and Table 5).

7 PERFORMANCE IMPROVEMENT OF THE PCS BASED APUF

The key facts observed from the performance evaluation of the PCS based APUF are as follows:
• The PCS based APUF shows a satisfactory level of uniqueness and reliability on Spartan-3E
(90 nm technology) as well as on Artix-7 (28 nm technology) FPGA.
• Few limited individual instances of the PCS based APUF deviate from the desired uniformity,
randomness, or entropy both in the case of Spartan-3E and Artix-7 FPGA.
• Only those instances of the PCS based APUF deviate from the desired level of entropy or
randomness which significantly deviate from the ideal value of uniformity.
Thus, the overall performance of the PCS based APUF can be further boosted by improving the
uniformity of the individual PUF instances. One way to improve the uniformity is through the
XOR composition of the PCS based APUF. XOR function has the property that, it will produce
the output with uniform zero and one if at least one of its inputs maintains the uniformity [45].
N
An XOR composition of the PCS based APUF can be mathematically written as i=1 Ii , where Ii
denotes an instance of the PCS based APUF and N is the number of instances in the composition.
The responses of the PUF instances (Ii ) are used as the inputs to the XOR and the output of the
XOR is finally considered as the PUF response. Theoretically, increasing the value of N (number
of instances in the XOR composition) also increases the probability of the response of the XOR
function to be ideally uniform. However, the unreliability of each of the PUF instances in the
XOR composition cumulatively increases the unreliability of the final response. Additionally, the
hardware overhead increases with increasing value of N. Hence, the value of N cannot be increased
arbitrarily. Here, we have experimented with an XOR composition of 3 PCS based APUF (i.e. N = 3)
to check the improvement in performance. It is to be noted that the hardware overhead of N XOR
composition is almost N times the resources of a basic PCS based APUF which is still significantly
low for N = 3.

7.1 Performance Evaluation of the XOR Composition of PCS based APUF

To evaluate the performance of the 3-XOR composition, we have implemented three instances of
the PCS based APUF (i.e. N = 3) on an FPGA board. It is to be noted that, for fair analysis, the
same instance of the PCS based APUF used earlier (for the performance analysis of basic PCS based
APUF) is considered as one of the basic components in the construction of the 3-XOR composition.
The other instances are implemented parallel to the instance of the basic PCS based APUF. The
same challenge vector is applied to all these three PUF instances and the responses are XORed
to produce the final response. Like the basic PCS based APUF, here, we have applied a challenge
seven times and considered the majority of the response (i.e. global response) as the final response.
The uniqueness, uniformity, and reliability (obtained in the normal operating condition) of the
3-XOR composition of 64 bit PCS based APUF implemented on Spartan-3E and Artix-7 FPGA are
shown in Table 7. It can be observed that the XOR composition almost has a similar uniqueness

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:19

Fig. 16. Comparison of the uniformity deviation of the 3 XOR composition of 64-bit PCS based APUF and
the basic PCS based APUF on individual FPGA board (a) Uniformity deviation on 15 different Spartan-3E
FPGA (b) Uniformity deviation on 9 different Artix-7 FPGA.

profile (with an improvement in the standard deviation) as the basic PCS based APUF but the
reliability decreases slightly. However, the maximum and minimum uniformity and the standard
deviation (considering uniformity) of the XOR composition are improved from the basic PCS based
APUF. In Figure 16, we have shown the uniformity deviation of the XOR composition calculated
on individual FPGA boards compared to the uniformity deviation of the basic PCS based APUF.
The uniformity of the XOR composition measured on individual FPGA boards is remarkably better
than the basic PCS based APUF. The improvement is more noteworthy on Artix-7 FPGA, where
uniformity deviation of the XOR composition measured on individual boards is in between the
range ≈(4−20).
Again, we have performed the NIST randomness tests following the same convention used for
the basic PCS based APUF to remark on the randomness of the response string. The results of
the tests on Spartan-3E and Artix-7 FPGA are presented in Table 8 and Table 9, respectively. In
Spartan-3E, only 1 out of 15 boards shows a pass rate of zero in at least one of the tests, and in
Artix-7 none of the boards shows a pass rate of zero in any of the tests, which are a remarkable
improvement over the basic PCS based APUF. Finally, we have performed the entropy calculation
on the XOR composition to check gain over basic PCS based APUF. The results of the entropy
calculation on Spartan-3E and Artix-7 FPGA are shown in Figure 17 and Figure 18, respectively.
For fair assessment, here we have presented the entropy of the same boards reported for the basic
PCS based APUF (i.e. Figure 14 and 15). The XOR composition shows reasonably better entropy
(i.e. close to 1) over the basic PCS based APUF. Also, the improvement is more prominent on the
boards in which the basic PCS based APUF has very low entropy.
Thus, it is evident from the experimental results that the XOR composition of PCS based APUF
achieves better uniformity, randomness, and entropy over the basic variant with a negligible loss
of reliability.

8 ROBUSTNESS TO MACHINE LEARNING BASED MODELING ATTACK

Modeling robustness denotes the difficulty of making a mathematical model of a PUF using its
challenge-response pairs (CRPs). In conventional APUF, flipping a challenge bit changes the
competing delay paths to propagate the signal. Thus, the applied challenge is converted to feature
vector using the linear additive delay model to perform a modeling attack in such APUF [40].
However, unlike the conventional APUF, the applied challenge can be directly used for modeling
PCS based APUF.

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26:20 M. H. Mahalat et al.

Table 8. Pass Rate of the Response Sequences Considering

the 3-XOR Composition of 64 - bit PCS based APUF on
Spartan-3E FPGA

Board No. T1 T2 T3 T4 T5 T6 T7
1 79 99 98 92 92 77 82
2 39 89 91 78 64 44 43
3 100 99 99 100 98 99 100
4 97 100 100 98 97 97 97
5 95 99 99 97 97 97 95
6 99 99 100 97 100 99 100
7 100 99 99 99 99 99 100
8 93 100 100 98 97 93 93
9 38 92 91 87 67 38 39
10 100 100 98 100 99 100 100
11 6 49 36 44 12 7 6
12 0 3 2 2 1 0 0
13 98 99 99 100 99 99 99
14 98 99 100 97 97 99 98
15 93 97 100 97 96 94 94

Table 9. Pass rate of the Response Sequences

Considering the 3-XOR Composition of 64 - bit PCS
based APUF on Artix-7 FPGA

Board No. T1 T2 T3 T4 T5 T6 T7
1 97 99 97 99 97 98 98
2 92 99 97 95 96 93 96
3 83 96 97 92 92 85 84
4 24 81 73 62 43 25 23
5 52 95 94 89 77 54 52
6 92 100 100 96 97 92 95
7 85 99 99 94 95 87 87
8 4 49 35 33 13 6 7
9 93 98 99 96 94 94 93

It is noteworthy that artificial neural network (ANN) has been extensively used for finding the
mathematical model of APUF and its variants [20, 49]. So, we have performed the ANN-based
modeling attack to verify the modeling robustness of the PCS based APUF.
We have generated a dataset consisting 2 ∗ 105 random CRPs from an instance of the standalone
and the XOR compositions of the PCS based APUF to perform the attack. The attack has been
performed using the CRPs obtained from Board 7 of Spartan-3E and Board 6 of Artix-7 FPGA
at normal temperature. We have chosen these boards deliberately as the PUF instance (i.e., the
instance of the basic PCS based APUF) on these boards possess closely similar characteristics (i.e.
uniformity and reliability) as the conventional APUF implemented on ASIC [20] to provide a fair
analysis. The sklearn library of Python is used to implement the ANN based modeling attack [36].
The attack with different number of CRPs is performed by taking 70% as training and 30% as testing
data. The modeling accuracy has been estimated using the five-fold cross-validation method. The

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:21

Fig. 17. Entropy of 3 XOR composition of 64-bit PCS based APUF implemented on Spartan-3E FPGA.

Table 10. Modeling Robustness of PCS based APUF and its XOR Composition
FPGA Modeling Activation No. of No. of Neurons in
PUF Reliability CRP
Technology Accuracy Function Hidden layers Hidden Layer
PCS
97.75% 94.82% 6 ∗ 104 tanh 2 (64, 64)
based APUF
3-XOR Composition 96.33% 94.18% 17 ∗ 104 tanh 3 (64, 64, 64)
Spartan-3E
4-XOR Composition 94.57% 92.44% 20 ∗ 104 tanh 3 (64, 64, 64)
5-XOR Composition 92.77% 90.03% 17 ∗ 104 tanh 3 (64, 64, 64)
6-XOR Composition 91.32% 84.61% 19 ∗ 104 relu 3 (64, 64, 64)
PCS
95.40% 93.99% 6 ∗ 104 relu 1 64
based APUF
3-XOR Composition 91.97% 90.45% 10 ∗ 104 tanh 3 (64,64,64)
Artix-7
4-XOR Composition 91.84% 90.41% 14 ∗ 104 tanh 3 (64, 64, 64)
5-XOR Composition 91.67% 89.31% 16 ∗ 104 tanh 3 (64, 64, 64)
6-XOR Composition 89.07% 86.13% 20 ∗ 104 tanh 3 (64, 64, 64)

best parameters and modeling accuracy are shown in Table 10. The lower modeling accuracy or an
increase in the number of required CRPs (to achieve the same accuracy) indicates more robustness
against modeling attacks. It can be noted that the modeling robustness of the basic PCS based
APUF is at least as good as the conventional APUF (implemented on ASIC or evaluated using
simulation) reported in previous literature [20, 42]. However, the modeling accuracy is bounded
by the reliability as the reliability indicates the ratio of noise-free bits. Similar to the conventional
APUF, the XOR composition of PCS based APUF improves the robustness against modeling attack.
For concise analysis, we have also reported the modeling robustness of 4, 5, and 6-XOR composition
of the PCS based APUF. It is evident that the modeling accuracy degrades as the number of PCS
based APUF (i.e. N ) increases in the XOR composition. Our result trends are consistent with a

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26:22 M. H. Mahalat et al.

Fig. 18. Entropy of 3 XOR composition of 64-bit PCS based APUF implemented on Artix-7 FPGA.

recently published work which applies advanced deep learning to obtain close to 100% modeling
accuracy, while reducing the computational cost [48]. Also, we have performed the modeling attack
using Support Vector Machine (SVM). However, The training time of SVM becomes impractical
for a very large dataset, so we have considered a dataset consisting 105 random CRPS. SVM shows
poor modeling accuracy except for the basic PCS based APUF. So, we do not report the modeling
accuracy using SVM here. The modeling accuracy of PCS based APUF using SVM is available
online at [1].

8.1 Discussion
Energy and hardware resource are the primary concern to implement security primitive in an IoT
device. On the other hand, FPGAs, due to their true flexibility and reconfigurability became a pri-
mary driving force for the development of IoT. We have shown that the PCS based APUF requires
negligible hardware resources to implement it on FPGA. Also, PCS based APUF follows the same
principle as the primitive APUF, which has a significantly low power requirement compared to
the FPGA friendly RO PUF. Moreover, it can generate an exponential number of CRPs which is
essential for the authentication of the IoT devices. Besides, the PCS based APUF has considerable
robustness against temperature (environmental) variation which supports the characteristics of
IoT devices to be deployed in an uncontrolled environment. The PCS based APUF has (at least)
similar modeling robustness as the conventional APUF (i.e. implemented on ASIC or simulation).
However, it is worth mentioning that the conventional APUF implemented on FPGA (reported in
previous literature) failed to achieve the required PUF properties (Table 6). All these characteristics
make the PCS based APUF suitable security primitive to implement on FPGA for the low-cost IoT
applications. Further, we have investigated the XOR composition of the PCS based APUF, which

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Implementation, Characterization and Application of PCS based Arbiter PUF 26:23

shows enhanced PUF characteristics and security with only three component PCS based APUF.
Experimental results suggest that, in general, the XOR composition of the PCS based APUF en-
sures good uniformity in all the PUF instances. However, considering the uniformity, the XOR
composition or the basic PCS based APUF can be used depending on the requirement, as most of
the PUF instances show acceptable uniformity even without applying XOR composition.
The robustness to modeling attack of the PCS based APUF can be improved by increasing the
number of component PCS based APUF in the XOR composition with the penalty of reliability.
However, 100% reliability is not a requirement for authentication and identification of an IoT de-
vice. Moreover, if required, an error correction mechanism can be used on the authentication server
instead of the IoT device utilizing a lightweight authentication protocol to retain the constraints
of IoT. Besides, the modeling attack can be avoided by utilizing a suitable protocol that does not
leak a CRP explicitly [12, 38]. Also, a lightweight obfuscation mechanism can be used to prevent
modeling attacks [52]. As a proof-of-concept, we have applied the lightweight set-based obfusca-
tion scheme proposed in [52], on the PCS based PUF and then performed the ANN based model
building attack. The set-based obfuscation scheme uses a set of random numbers to obfuscate
the challenge and response, where the response strings of the PUF itself are served as random
numbers. An adversary can only access the challenge set and the obfuscated response bits. The
experiment is conducted on the same boards shown in Table 10, with up to 2 ∗ 105 CRPs. After
the obfuscation, ANN shows a maximum modeling accuracy of 50.69% and 57.28% considering the
standalone PCS based APUF implemented on Spartan-3E and Artix-7 FPGA, respectively, with a
set of only two random numbers (i.e. response string). These modeling accuracy values are close
to that corresponding to the ideal modeling robustness of the proposed PUF (i.e. 50%). Also, from
the results, it is obvious that using the XOR composition or increasing the random numbers in the
set can increase the modeling robustness further.
Side channel analysis attack is another concern for the security of a PUF. However, unlike the
ring oscillator (RO) PUF, the PCS based APUF has a significantly low hardware footprint, which
makes it harder to perform electromagnetic emission based side channel analysis attacks [33]. The
power analysis and fault injection based side channel attacks may be a threat to APUF [3]. The
power consumption of the PCS APUF (which is basically an APUF) is relatively low as the trigger
signal only propagates through two delay paths without any oscillation or glitch. Nevertheless, if
necessary, lightweight masking can be utilized to prevent any side channel analysis attack or a
combination of side channel analysis and machine learning attack [2].
Probably approximately correct (PAC) learning attack is another kind of attack worth men-
tioning for the security of PUF [9]. PAC learning frameworks are provable approaches used to find
vulnerability against machine learning based modeling attacks. Fourier analysis based attack [10]
is an extension of PAC learning which considers noisy PUF response. However, empirical machine
learning based methods show similar modeling accuracy as predicted by the provable approaches
[8]. In this work, we have performed an extensive ANN based model building attack to validate
the security of the PCS based APUF. Investigating all the possible attacks is out of the scope of the
current work. However, evaluating the robustness of the proposed PUF to some of these attacks
would be definitely part of our future work. Furthermore, We have made all the data sets of the
PCS based APUF available online at [1] to encourage further research on the PCS based APUF.

9 CONCLUSION
In this paper, the path changing switch (PCS) based APUF is implemented on Spartan-3E (90
nm CMOS) and Artix-7 (28 nm CMOS) FPGA eradicating the concept of fine-tuning used in ex-
isting models. In Spartan-3E FPGA, the PCS based APUF exhibits an average uniqueness, uni-
formity, and reliability of 49.81%, 49.77% and 98.19%, respectively. In Artix-7 FPGA, the average

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26:24 M. H. Mahalat et al.

uniqueness, uniformity and reliability are 51.34%, 57.64% and 97.57%, respectively. The results
show the superiority of the PCS based APUF over the other APUFs implemented on FPGA. Also,
the PCS based APUF is considerably robust against temperature variation. Moreover, the PCS based
APUF requires significantly low hardware resources (4.20% and 0.83% of Slices in Spartan-3E and
Artix-7, respectively) for implementation. Also, we have performed the NIST randomness and en-
tropy calculation on the PCS based APUF. It shows that few individual PUF instances which signif-
icantly deviate from the ideal uniformity also lack randomness and entropy. An XOR composition
of PCS based APUF is developed, which remarkably improves the uniformity of the individual PUF
instances as well as the randomness and entropy with little loss in reliability. The maximum and
minimum uniformity of a 3-XOR composition computed on Artix-7 FPGA is 68.87% and 43.68%,
respectively, compared to the 99.39% and 3.11% of standard PCS based APUF. Further, we have an-
alyzed the modeling robustness which depicts the resilience of the PCS based APUF against model
building attacks. Also, it is observed that the XOR composition improves its modeling robustness.
Hence, the PCS based APUF or its XOR composition (depending on the requirement) can be used
as a low-cost and reliable security primitive to implement on FPGA for the IoT applications.

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Received March 2021; revised September 2021; accepted October 2021

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