MITSUBISHI ELECTRIC

MELSEC System Q

Programmable Logic Controllers

User's Manual
(Functioning and Programming)

CPU Modules
Q CPU (Q Mode)

Art. no.: 130022

01 06 2003
SH(NA)-080038 MITSUBISHI ELECTRIC INDUSTRIAL AUTOMATION
Version F
 • SAFETY INSTRUCTIONS •
(Always read these instructions before using this equipment.)

When using Mitsubishi equipment, thoroughly read this manual and the associated manuals introduced in
this manual. Also pay careful attention to safety and handle the module properly.
These SAFETY PRECAUTIONS classify the safety precautions into two categories: "DANGER" and
"CAUTION".

Indicates that incorrect handling may cause hazardous conditions,

! DANGER resulting in death or severe injury.

Indicates that incorrect handling may cause hazardous conditions,

! CAUTION resulting in medium or slight personal injury or physical damage.

Note that the ! CAUTION level may lead to a serious consequence according to the circumstances.
Always follow the instructions of both levels because they are important to personal safety.

Please save this manual to make it accessible when required and always forward it to the end user.

[Design Precautions]
! DANGER
• Install a safety circuit external to the PLC that keeps the entire system safe even when there are
problems with the external power supply or the PLC module. Otherwise, trouble could result
from erroneous output or erroneous operation.
(1) Outside the PLC, construct mechanical damage preventing interlock circuits such as
emergency stop, protective circuits, positioning upper and lower limits switches and
interlocking forward/reverse operations.
(2) When the PLC detects the following problems, it will stop calculation and turn off all output in
the case of (a). In the case of (b), it will stop calculation and hold or turn off all output
according to the parameter setting.
(a) The power supply module has over current protection equipment and over voltage
protection equipment.
(b) The PLC CPUs self-diagnosis functions, such as the Watch dog timer error, detect
problems.
In addition, all output will be turned on when there are problems that the PLC CPU cannot
detect, such as in the I/O controller. Build a fail safe circuit exterior to the PLC that will make
sure the equipment operates safely at such times. Refer to " LOADING AND
INSTALLATION" in High Performance model QCPU (Q Mode) User's Manual (Hardware
Design, Maintenance and Inspection) for example fail safe circuits.
(3) Output could be left on or off when there is trouble in the output module relay or transistor.
So build an external monitoring circuit that will monitor any single outputs that could cause
serious trouble.

A-1 A-1
[Design Precautions]
! DANGER
• When overcurrent which exceeds the rating or caused by short-circuited load flows in the output
module for a long time, it may cause smoke or fire. To prevent this, configure an external safety
circuit, such as fuse.

• Build a circuit that turns on the external power supply when the PLC main module power is
turned on. If the external power supply is turned on first, it could result in erroneous output or
erroneous operation.

• When there are communication problems with the data link, refer to the corresponding data link
manual for the operating status of each station.
Not doing so could result in erroneous output or erroneous operation.

• When connecting a peripheral device to the CPU module or connecting a personal computer or
the like to the intelligent function module to exercise control (data change) on the running PLC,
configure up an interlock circuit in the sequence program to ensure that the whole system will
always operate safely.
Also before exercising other control (program change, operating status change (status control))
on the running PLC, read the manual carefully and fully confirm safety.
Especially for the above control on the remote PLC from an external device, an immediate
action may not be taken for PLC trouble due to a data communication fault.
In addition to configuring up the interlock circuit in the sequence program, corrective and other
actions to be taken as a system for the occurrence of a data communication fault should be
predetermined between the external device and PLC CPU.

! CAUTION
• Do not bunch the control wires or communication cables with the main circuit or power wires, or
install them close to each other. They should be installed 100 mm (3.94 inch) or more from each
other.
Not doing so could result in noise that would cause erroneous operation.

• When controlling items like lamp load, heater or solenoid valve using an output module, large
current (approximately ten times greater than that present in normal circumstances) may flow
when the output is turned OFF to ON.
Take measures such as replacing the module with one having sufficient rated current.

A-2 A-2
[Installation Precautions]

! CAUTION
• Use the PLC in an environment that meets the general specifications contained in High
Performance model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and
Inspection). Using this PLC in an environment outside the range of the general specifications
could result in electric shock, fire, erroneous operation, and damage to or deterioration of the
product.

• Hold down the module loading lever at the module bottom, and securely insert the module fixing
latch into the fixing hole in the base unit. Incorrect loading of the module can cause a
malfunction, failure or drop.
When using the PLC in the environment of much vibration, tighten the module with a screw.
Tighten the screw in the specified torque range.
Undertightening can cause a drop, short circuit or malfunction.
Overtightening can cause a drop, short circuit or malfunction due to damage to the screw or
module.

• When installing more cables, be sure that the base unit and the module connectors are installed
correctly.
After installation, check them for looseness.
Poor connections could cause an input or output failure.

• Securely load the memory card into the memory card loading connector.
After installation, check for lifting.
Poor connections could cause an operation fault.

• Completely turn off the external power supply before loading or unloading the module.
Not doing so could result in electric shock or damage to the product.

• Do not directly touch the module's conductive parts or electronic components.

Touching the conductive parts could cause an operation failure or give damage to the module.

[Wiring Precautions]

! DANGER
• Completely turn off the external power supply when installing or placing wiring.
Not completely turning off all power could result in electric shock or damage to the product.

• When turning on the power supply or operating the module after installation or wiring work, be
sure that the module's terminal covers are correctly attached.
Not attaching the terminal cover could result in electric shock.

A-3 A-3
[Wiring Precautions]
! CAUTION
• Be sure to ground the FG terminals and LG terminals to the protective ground conductor. Not
doing so could result in electric shock or erroneous operation.

• When wiring in the PLC, be sure that it is done correctly by checking the product's rated voltage
and the terminal layout.
Connecting a power supply that is different from the rating or incorrectly wiring the product could
result in fire or damage.

• External connections shall be crimped or pressure welded with the specified tools, or correctly
soldered.
Imperfect connections could result in short circuit, fires, or erroneous operation.

• Tighten the terminal screws with the specified torque.

If the terminal screws are loose, it could result in short circuits, fire, or erroneous operation.
Tightening the terminal screws too far may cause damages to the screws and/or the module,
resulting in fallout, short circuits, or malfunction.

• Be sure there are no foreign substances such as sawdust or wiring debris inside the module.
Such debris could cause fires, damage, or erroneous operation.

• The module has an ingress prevention label on its top to prevent foreign matter, such as wire
offcuts, from entering the module during wiring.
Do not peel this label during wiring.
Before starting system operation, be sure to peel this label because of heat dissipation.

[Startup and Maintenance precautions]

! DANGER
• Do not touch the terminals while power is on.
Doing so could cause shock or erroneous operation.

• Correctly connect the battery. Also, do not charge, disassemble, heat, place in fire, short circuit,
or solder the battery.
Mishandling of battery can cause overheating or cracks which could result in injury and fires.

• Switch all phases of the external power supply off when cleaning the module or retightening the
terminal or module mounting screws. Not doing so could result in electric shock.
Undertightening of terminal screws can cause a short circuit or malfunction.
Overtightening of screws can cause damages to the screws and/or the module, resulting in
fallout, short circuits, or malfunction.

A-4 A-4
[Startup and Maintenance precautions]
! CAUTION
• The online operations conducted for the CPU module being operated, connecting the peripheral
device (especially, when changing data or operation status), shall be conducted after the
manual has been carefully read and a sufficient check of safety has been conducted.
Operation mistakes could cause damage or problems with of the module.

• Do not disassemble or modify the modules.

Doing so could cause trouble, erroneous operation, injury, or fire.

• Use a cellular phone or PHS more than 25cm (9.85 inch) away from the PLC.
Not doing so can cause a malfunction.

• Switch all phases of the external power supply off before mounting or removing the module.
If you do not switch off the external power supply, it will cause failure or malfunction of the
module.

• Do not drop or give an impact to the battery mounted to the module.

Doing so may damage the battery, causing the battery fluid to leak inside the battery.
If the battery is dropped or given an impact, dispose of it without using.

• Before touching the module, always touch grounded metal, etc. to discharge static electricity
from human body, etc.
Not doing so can cause the module to fail or malfunction.

[Disposal Precautions]
! CAUTION
• When disposing of this product, treat it as industrial waste.

[Transportation Precautions]
! CAUTION
• When transporting lithium batteries, make sure to treat them based on the transport regulations.
(Refer to Appendix 5 for details of the controlled models.)

A-5 A-5
REVISIONS
The manual number is given on the bottom left of the back cover.
Print Date * Manual Number Revision
Dec., 1999 SH (NA)-080038-A First edition
Dec., 2000 SH (NA)-080038-B Add the Q33B type main base unit and Q63B type extension base unit.
Change Chapter 11 (1) to (3) to Section 11.1 to 11.3.
Unify the name from the software package (GPP function, ladder logic test
tool function, GPPW, etc) to the product name (GX Developer, GX
Configurator).
Add the explanation of the following functions of which serial number's upper
five digits were added in 02092 (02092 -A)
• Automatic write to standard ROM
• Forced ON/OFF correspondence for external I/O
• Remote password setting
• Increment of Q12HCPU and Q25HCPU standard RAM capacity
• MELSECNET/H remote I/O network correspondence
• Interrupt module (QI60) correspondence
Correction
Section 1.1, Section 2.1, 2.2, Chapter 3, Section 4.2, 4.2.1, 4.2.2, 4.2.3, 4.6,
Section 5.2, 5.3, Section 6.1, 6.9.3, Section 7.3 (3) (4), 7.6.5, 7.8, 7.14, 7.18,
7.19.1, 7.20.1, Chapter 9, Section 10.2, 10.10, Section 11.3, Appendix 1,2
Addition
Section 2.3, Section 4.1.3, 4.2.5, Section 5.4, 5.5.2, 5.6.2, Section 6.6, 6.6.2,
6.7, Section 7.6.3, 7.7.2, 7.7.3, 7.9.1, 7.9.3, 7.16, 7.17, 7.17.2, 7.20.1,
Section 10.10
Jun., 2001 SH (NA)-080038-C The explanation of the multiple PLC system added to the function version B
of the QCPU was added to Chapters 13 to 19.
General name for QCPU was changed to the High Performance model
QCPU.
The Q52B and Q55B extension base units and PC CPU module were added.
Overall correction

Apr., 2002 SH (NA)-080038-D Addition of the high speed interrupt function (Section 7.20) added to the serial
No. whose upper 5 digits are 04012 (04012 ) and the
description of the Q2MEM-2MBS SRAM card
Overall correction

Mar., 2003 SH (NA)-080038-E

Additon model
Q32SB, Q33SB, Q35SB, Q61SP
Correction
SAFETY PRECAUTIONS, About Manuals, Chapters 1, Section 1.2, 1.3,
Section 2.1, 2.2, 2.3, Chapters 3, Section 4.2.2, 4.3.1, 4.4, 4.8.4, Section
5.6.1, 5.8, Chapters 6, Section 6.1, 6.2, 6.3, 6.5, 6.7, 6.8, 6.9.1, 6.9.2, 6.9.3,
Section 7.1, 7.12, 7.12.1, 7.13, 7.14, 7.15.2, 7.17, 7.17.2, 7.19.2, 7.21.1,
7.21.2, 7.22.2, Chapters 9, Section 10.1, 10.13.2, Section 11.2, Section 14.1,
14.2.4, Section 15.2, Section 16.2, Section 17.2, Appendix 1, 2, 4.2, 4.3
Addition
Section 6.9.4, Section 7.8, 7.9

A-6 A-6
Print Date * Manual Number Revision
Jul., 2003 SH (NA)-080038-F
Correction
SAFETY PRECAUTIONS, Section 2.1, Section 6.2, 6.7, Section 10.2.11,
Section 13.1, 13.3, Section 14.1, Chapters 16, Section 16.3.2, Appendix 2
Addition
Appendix 5, 5.1, 5.2

Japanese Manual Version SH-080020-J

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent
licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property
rights which may occur as a result of using the contents noted in this manual.
 1999 MITSUBISHI ELECTRIC CORPORATION

A-7 A-7
 INTRODUCTION

Thank you for choosing the Mitsubishi MELSEC-Q Series of General Purpose Programmable Controllers.
Please read this manual carefully so that equipment is used to its optimum.

CONTENTS
SAFETY INSTRUCTIONS ...........................................................................................................................................A- 1
REVISIONS ....................................................................................................................................................................A- 6
CONTENTS....................................................................................................................................................................A- 8
Manuals...........................................................................................................................................................................A-19
How to Use This Manual ...............................................................................................................................................A-20
Generic Terms and Abbreviations................................................................................................................................A-21

1 OVERVIEW 1 – 1 to 1 - 11

1.1 Features..................................................................................................................................................................... 1- 2
1.2 Programs ................................................................................................................................................................... 1- 5
1.3 Convenient Programming Devices and Instructions ............................................................................................ 1- 8

2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM 2- 1 to 2- 8

2.1 System Configuration.............................................................................................................................................. 2- 1

2.2 Precaution on System Configuration..................................................................................................................... 2- 6
2.3 Confirming the Serial No. and Function Versions................................................................................................ 2- 8

3 PERFORMANCE SPECIFICATION 3- 1 to 3- 3

4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION CONDITIONS 4- 1 to 4-53

4.1 Sequence Program ................................................................................................................................................. 4- 1

4.1.1 Main routine program ........................................................................................................................ 4- 3
4.1.2 Sub-routine programs ....................................................................................................................... 4- 4
4.1.3 Interrupt programs............................................................................................................................. 4- 6
4.2 Program Execute Type ...........................................................................................................................................4-10
4.2.1 Initial execution type program ........................................................................................................... 4-16
4.2.2 Scan execution type program ........................................................................................................... 4-18
4.2.3 Low speed execution type program ................................................................................................. 4-20
4.2.4 Stand-by type program ..................................................................................................................... 4-26
4.2.5 Fixed scan execution type program.................................................................................................. 4-32
4.3 Operation Processing..............................................................................................................................................4-35
4.3.1 Initial processing................................................................................................................................ 4-35
4.3.2 I/O refresh (I/O module refresh processing)..................................................................................... 4-35
4.3.3 Automatic refresh of the intelligent function module ........................................................................ 4-36
4.3.4 END processing ................................................................................................................................ 4-36
4.4 RUN, STOP, PAUSE Operation Processing........................................................................................................4-37
4.5 Operation Processing during Momentary Power Failure....................................................................................4-38

A-8 A-8
4.6 Data Clear Processing ............................................................................................................................................4-39
4.7 I/O Processing and Response Lag........................................................................................................................4-40
4.7.1 Refresh mode.................................................................................................................................... 4-40
4.7.2 Direct mode ....................................................................................................................................... 4-43
4.8 Numeric Values which Can Be Used in Sequence Programs ...........................................................................4-45
4.8.1 BIN (Binary code) .............................................................................................................................. 4-47
4.8.2 HEX (Hexadecimal)........................................................................................................................... 4-48
4.8.3 BCD (Binary Coded Decimal) ........................................................................................................... 4-49
4.8.4 Real numbers (floating decimal point data)...................................................................................... 4-50
4.9 Character String Data..............................................................................................................................................4-53

5 ASSIGNMENT OF I/O NUMBERS 5- 1 to 5-19

5.1 Relationship Between the Number of Stages and Slots of the Extension Base Unit ...................................... 5- 1
5.2 Installing Extension Base Units and Setting the Number of Stages .................................................................. 5- 2
5.3 Base Unit Assignment (Base Mode) .................................................................................................................... 5- 3
5.4 What are I/O Numbers?.......................................................................................................................................... 5- 7
5.5 Concept of I/O Number Assignment...................................................................................................................... 5- 8
5.5.1 I/O numbers of main base unit, Slim type base unit and extension base unit ................................ 5- 8
5.5.2 Remote station I/O number............................................................................................................... 5-10
5.6 I/O Assignment by GX Developer..........................................................................................................................5-11
5.6.1 Purpose of I/O assignment by GX Developer .................................................................................. 5-11
5.6.2 Concept of I/O assignment using GX Developer ............................................................................. 5-13
5.7 Examples of I/O Number Assignment...................................................................................................................5-16
5.8 Checking the I/O Numbers .....................................................................................................................................5-19

6 MEMORIES AND FILES HANDLED BY HIGH PERFORMANCE MODEL QCPU 6- 1 to 6-28

6.1 About the High Performance model QCPU's Memory........................................................................................ 6- 3

6.2 Program Memory..................................................................................................................................................... 6- 6
6.3 About the Standard ROM ....................................................................................................................................... 6- 8
6.4 About the Standard RAM........................................................................................................................................ 6- 9
6.5 Memory Card ...........................................................................................................................................................6-11
6.6 Writing Data to the Standard ROM or the Flash Card.........................................................................................6-13
6.6.1 Writing Data to the standard ROM or to the Flash card using GX Developer ................................ 6-13
6.6.2 Automatic write to standard ROM
(Auto Download all Data from Memory card to standard ROM) ..................................................... 6-15
6.7 Executing Standard ROM/Memory Card Programs (Boot Run)........................................................................6-18
6.8 Program File Configuration.....................................................................................................................................6-21
6.9 GX Developer File Operation and File Handling Precautions ............................................................................6-23
6.9.1 File operation..................................................................................................................................... 6-23
6.9.2 File handling precautions .................................................................................................................. 6-24
6.9.3 File capacity....................................................................................................................................... 6-25
6.9.4 Memory capacity for files .................................................................................................................. 6-26

7 FUNCTION 7- 1 to 7-94

7.1 Function List ............................................................................................................................................................. 7- 1

7.2 Constant Scan.......................................................................................................................................................... 7- 2
7.3 Latch Functions........................................................................................................................................................ 7- 5
A-9 A-9
7.4 Setting the Output (Y) Status when Changing from/to STOP Status to/from RUN Status ............................. 7- 7
7.5 Clock Function ......................................................................................................................................................... 7- 9
7.6 Remote Operation ...................................................................................................................................................7-12
7.6.1 Remote RUN/STOP.......................................................................................................................... 7-12
7.6.2 Remote PAUSE................................................................................................................................. 7-15
7.6.3 Remote RESET................................................................................................................................. 7-17
7.6.4 Remote latch clear ............................................................................................................................ 7-19
7.6.5 Relationship of the remote operation and High Performance model QCPU RUN/STOP switch... 7-20
7.7 Selecting the Input Response Time of the Q Series Module (I/O Response Time) ........................................7-21
7.7.1 Selecting the response time of the input module ............................................................................. 7-21
7.7.2 Selecting the response time of the high speed input module.......................................................... 7-22
7.7.3 Selecting the response time of the interrupt module ....................................................................... 7-23
7.8 Error-time Output Mode Setting .............................................................................................................................7-24
7.9 Hardware Error-time CPU Operation Mode Setting ............................................................................................7-25
7.10 Setting the Switches of the Intelligent Function Module....................................................................................7-26
7.11 Monitoring Function...............................................................................................................................................7-27
7.11.1 Monitor condition setting ................................................................................................................. 7-27
7.11.2 Monitoring test for local device ....................................................................................................... 7-31
7.11.3 Enforced ON/OFF for external I/O.................................................................................................. 7-33
7.12 Writing in Program during High Performance model QCPU RUN ..................................................................7-37
7.12.1 Writing data in the circuit mode during RUN .................................................................................. 7-37
7.12.2 Writing a batch of files during RUN ................................................................................................ 7-40
7.13 Execution Time Measurement.............................................................................................................................7-42
7.13.1 Program monitor list ........................................................................................................................ 7-42
7.13.2 Interrupt program monitor list ......................................................................................................... 7-46
7.13.3 Scan time measurement ................................................................................................................. 7-47
7.14 Sampling Trace Function......................................................................................................................................7-49
7.15 Debug Function with Multiple Users....................................................................................................................7-58
7.15.1 Multiple-user monitoring function.................................................................................................... 7-59
7.15.2 Multiple-user RUN write function .................................................................................................... 7-60
7.16 Watch Dog Timer (WDT)......................................................................................................................................7-62
7.17 Self-Diagnosis Function........................................................................................................................................7-64
7.17.1 Interrupt due to error occurrence.................................................................................................... 7-67
7.17.2 LED display when error occurs....................................................................................................... 7-67
7.17.3 Error caucellation ............................................................................................................................ 7-68
7.18 Failure History ........................................................................................................................................................7-69
7.19 System Protect.......................................................................................................................................................7-70
7.19.1 Password registration...................................................................................................................... 7-70
7.19.2 Remote password ........................................................................................................................... 7-72
7.20 Monitoring High Performance model QCPU System Status from GX Developer (System Monitor) ..........7-75
7.21 LED Display............................................................................................................................................................7-79
7.21.1 LED display ..................................................................................................................................... 7-79
7.21.2 Priority setting.................................................................................................................................. 7-81
7.22 High Speed Interrupt Function .............................................................................................................................7-83
7.22.1 High speed interrupt program execution ........................................................................................ 7-85
7.22.2 High speed I/O refresh, high speed buffer transfer........................................................................ 7-86
7.22.3 Processing time............................................................................................................................... 7-88
7.22.4 Restrictions...................................................................................................................................... 7-90
7.23 Module Service Interval Time Reading ..............................................................................................................7-93

A - 10 A - 10
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL FUNCTION MODULE
8- 1 to 8- 9

8.1 Communication Between High Performance model QCPU and Q-series Intelligent Function Modules...... 8- 1
8.1.1 Initial setting and automatic refresh setting using GX Configurator ................................................ 8- 2
8.1.2 Communication using device initial value......................................................................................... 8- 3
8.1.3 Communication using FROM/TO instruction ................................................................................... 8- 4
8.1.4 Communication using the intelligent function module device.......................................................... 8- 4
8.1.5 Communication using the instructions dedicated for intelligent function modules.......................... 8- 5
8.2 Request from Intelligent Function Module to High Performance model QCPU ............................................... 8- 6
8.2.1 Interrupt from the intelligent function module ................................................................................... 8- 6
8.3 Communication Between High Performance model QCPU and AnS Series Special Function Modules..... 8- 7
8.3.1 Communication using device initial value......................................................................................... 8- 7
8.3.2 Communication using FROM/TO instruction ................................................................................... 8- 8
8.3.3 Communication using the intelligent function module device.......................................................... 8- 8
8.3.4 Effects of quicker access to the special function module and countermeasures against them ..... 8- 9

9 PARAMETER LIST 9- 1 to 9-12

10 EXPLANTION OF DEVICES 10- 1 to 10-72

10.1 Device List ............................................................................................................................................................10- 1

10.2 Internal User Devices..........................................................................................................................................10- 3
10.2.1 Inputs (X) ....................................................................................................................................... 10- 5
10.2.2 Outputs (Y) .................................................................................................................................... 10- 8
10.2.3 Internal relays (M) ......................................................................................................................... 10-10
10.2.4 Latch relays (L).............................................................................................................................. 10-11
10.2.5 Anunciators (F).............................................................................................................................. 10-12
10.2.6 Edge relay (V) ............................................................................................................................... 10-16
10.2.7 Link relays (B)................................................................................................................................ 10-17
10.2.8 Link special relays (SB) ................................................................................................................ 10-18
10.2.9 Step relays (S)............................................................................................................................... 10-18
10.2.10 Timers (T) .................................................................................................................................... 10-19
10.2.11 Counters (C)................................................................................................................................ 10-24
10.2.12 Data registers (D) ........................................................................................................................ 10-29
10.2.13 Link registers (W) ........................................................................................................................ 10-30
10.2.14 Link special registers (SW) ......................................................................................................... 10-31
10.3 Internal System Devices .....................................................................................................................................10-32
10.3.1 Function devices (FX, FY, FD) ..................................................................................................... 10-32
10.3.2 Special relays (SM) ....................................................................................................................... 10-34
10.3.3 Special registers (SD) ................................................................................................................... 10-35
10.4 Link Direct Devices (J \ ) ...............................................................................................................................10-36
10.5 Intelligent Function Module Devices (U \G ) ...............................................................................................10-39

A - 11 A - 11
10.6 Index Registers (Z) ..............................................................................................................................................10-40
10.6.1 Switching between scan execution type programs and low speed execution type programs ... 10-41
10.6.2 Switching between scan/low speed execution type programs and interrupt/
fixed scan execution type programs ............................................................................................ 10-42
10.7 File Registers (R).................................................................................................................................................10-44
10.7.1 File register capacity ..................................................................................................................... 10-45
10.7.2 Differences in memory card access method by memory card type ............................................ 10-45
10.7.3 Registering the file registers ......................................................................................................... 10-46
10.7.4 File register designation method .................................................................................................. 10-50
10.7.5 Precautions in using file registers ................................................................................................. 10-51
10.8 Nesting (N) ...........................................................................................................................................................10-53
10.9 Pointers (P)...........................................................................................................................................................10-54
10.9.1 Local pointers ................................................................................................................................ 10-54
10.9.2 Common pointers.......................................................................................................................... 10-55
10.10 Interrupt Pointers (I)...........................................................................................................................................10-57
10.11 Other Devices ....................................................................................................................................................10-59
10.11.1 SFC block device (BL) ................................................................................................................ 10-59
10.11.2 SFC transition device (TR) ......................................................................................................... 10-59
10.11.3 Network No. designation device (J)............................................................................................ 10-59
10.11.4 I/O No. designation device (U).................................................................................................... 10-60
10.11.5 Macro instruction argument device (VD).................................................................................... 10-61
10.12 Constants ...........................................................................................................................................................10-62
10.12.1 Decimal constants (K)................................................................................................................. 10-62
10.12.2 Hexadecimal constants (H)......................................................................................................... 10-62
10.12.3 Real numbers (E) ........................................................................................................................ 10-63
10.12.4 Character string ( " " )................................................................................................................ 10-63
10.13 Convenient Uses for Devices...........................................................................................................................10-64
10.13.1 Global devices and local devices ............................................................................................... 10-64
10.13.2 Device initial values..................................................................................................................... 10-70

11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME 11- 1 to 11- 4

11.1 Reading High Performance model QCPU's Scan Time................................................................................11- 1

11.2 Factors Responsible for Extended Scan Time ...............................................................................................11- 2
11.3 Factors Responsible for Shortened Scan Time..............................................................................................11- 4

12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE MODEL QCPU 12- 1 to-12- 8

12.1 Writing Procedure for 1 Program......................................................................................................................12- 1

12.1.1 Items to consider when creating one program............................................................................ 12- 1
12.1.2 Procedure for writing programs to the High Performance model QCPU ................................... 12- 2
12.2 Procedure for Multiple Programs......................................................................................................................12- 5
12.2.1 Items to consider when creating multiple programs ................................................................... 12- 5
12.2.2 Procedure for writing programs to the High Performance model QCPU ................................... 12- 6

A - 12 A - 12
13 OUTLINE OF MULTIPLE CPU SYSTEM 13- 1 to 13- 6

13.1 Features...............................................................................................................................................................13- 1
13.2 Outline of Multiple CPU System .......................................................................................................................13- 3
13.3 Differences with Single CPU System ..............................................................................................................13- 5

14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM 14- 1 to 14- 21

14.1 System Configuration.........................................................................................................................................14- 1

14.2 Precautions For Multiple CPU System Configuration ....................................................................................14- 5
14.2.1 Function versions of High Performance model QCPU , motion CPUs and
PC CPU module that can be used, and their mounting positions............................................... 14- 5
14.2.2 Precautions when using Q series corresponding I/O modules and intelligent function
modules......................................................................................................................................... 14- 9
14.2.3 Limitations when mounting AnS series corresponding I/O modules and special function
modules......................................................................................................................................... 14-10
14.2.4 Modules that have mounting restrictions..................................................................................... 14-12
14.2.5 Compatible GX Developers and GX Configurators .................................................................... 14-13
14.2.6 Parameters that enable the use of multiple CPU system........................................................... 14-14
14.2.7 Resetting the multiple CPU system............................................................................................. 14-18
14.2.8 Processing when High Performance model QCPU stop errors occur ....................................... 14-19
14.2.9 Reducing the time required for multiple CPU system processing .............................................. 14-21

15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS 15- 1 to 15- 3

15.1 Concept behind Allocating I/O Numbers .........................................................................................................15- 1

15.1.1 I/O modules and intelligent function module I/O numbers.......................................................... 15- 1
15.1.2 I/O number of High Performance model QCPU, Motion CPU and PC CPU module ................ 15- 2
15.2 Setting of Control CPUs with GX Developer ....................................................................................................15- 3

16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM 16- 1 t o 16-15

16.1 Automatic Refresh of CPU Shared Memory ...................................................................................................16- 2

16.2 Communication with Multiple CPU Dedicated Instructions and Intelligent Function Module Devices..16- 9
16.3 Interactive Communications between The High Performance model QCPU and Motion CPU ...............16-11
16.3.1 Control commands from the High Performance model QCPU to the Motion CPU ................... 16-11
16.3.2 Reading and writing device data ................................................................................................. 16-12
16.4 CPU Shared Memory..........................................................................................................................................16-13

17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND

INTELLIGENT FUNCTION MODULES 17- 1 to 17- 5

17.1 Range of Control CPU Communications.........................................................................................................17- 1

17.2 Range of Non-control CPU Communications .................................................................................................17- 1

A - 13 A - 13
18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM HIGH PERFORMANCE MODEL
QCPUs 18- 1 to 18- 3

18.1 Concept behind CPU Scanning Time..............................................................................................................18- 1

18.2 Factor to Prolong the Scan Time......................................................................................................................18- 2

19 STARTING UP THE MULTIPLE CPU SYSTEM 19- 1 to 19- 9

19.1 Flow-chart for Starting Up the Multiple CPU System .....................................................................................19- 1

19.2 Setting Up the Multiple CPU System Parameters (Multiple CPU Settings, Control CPU Settings) .........19- 3
19.2.1 System configuration.................................................................................................................... 19- 3
19.2.2 Creating new systems.................................................................................................................. 19- 4
19.2.3 Using existing preset multiple CPU settings and I/O allocations................................................ 19- 7

APPENDICES App- 1 to App-60

APPENDIX 1 Special Relay List.............................................................................................................................. App- 1

APPENDIX 2 Special Register List ......................................................................................................................... App-22
APPENDIX 3 List of Interrupt Pointer Nos. & Interrupt Factors ........................................................................... App-58
APPENDIX 4 Enhancement of the High Performance Model QCPU Functions .............................................. App-59
APPENDIX 4.1 Specification Comparison ............................................................................................App-59
APPENDIX 4.2 Function Comparison ...................................................................................................App-59
APPENDIX 4.3 Usability of Added Functions Depending on GX Developer Version .........................App-60
APPENDIX 5 Transportation Precautions.............................................................................................................. App-61
APPENDIX 5.1 Controlled models.........................................................................................................App-61
APPENDIX 5.2 Transport guidelines.....................................................................................................App-61

INDEX Index- 1 to Index- 3

A - 14 A - 14
 (Related manual)..................................................................High Performance Model QCPU (Q Mode) User's Manual
(Hardware Design, Maintenance and Inspection)
CONTENTS

1. OVERVIEW

1.1 Features

2. SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM

2.1 System Configuration

2.2 Precaution on System Configuration
2.3 Comfirming Serial Number and Function Version

3. GENERAL SPECIFICATIONS

4. HARDWARE SPECIFICATION OF THE CPU MODULE

4.1 Performance Specification

4.2 Part Names and Settings
4.3 Switch Operation After Writing in Program
4.4 Latch Clear Operation
4.5 Executing automatic Write to standard ROM

5. POWER SUPPLY MODULE

5.1 Specification
5.1.1 Power supply module specifications
5.1.2 Selecting the power supply module
5.1.3 Precaution when connecting the uninterruptive power supply
5.2 Names of Parts and Settings

6. BASE UNIT AND EXTENSION CABLE

6.1 Base Unit Specification Table

6.2 Extension Cable Specification Table
6.3 Parts Names of Base Unit
6.4 Setting the Extension Base Unit
6.5 Guideline for Use of Extension Base Units (Q5 B)

A - 15 A - 15
7. MEMORY CARD AND BATTERY

7.1 Memory Card Specifications

7.2 Battery Specifications (For CPU Module and SRAM Card)
7.3 Handling the Memory Card
7.4 The Names of The Parts of The Memory Card
7.5 Memory Card Loading/Unloading Procedures
7.6 Installation of Battery (for CPU Module and Memory Card)

8. EMC AND LOW VOLTAGE DIRECTIVE

8.1 Requirements for Conformance to EMC Directive

8.1.1 Standards applicable to the EMC Directive
8.1.2 Installation instructions for EMC Directive
8.1.3 Cables
8.1.4 Power supply module
8.1.5 When using Q1AS6 B type base unit
8.1.6 Others
8.2 Requirement to Conform to the Low Voltage Directive
8.2.1 Standard applied for MELSEC-Q series PLC
8.2.2 MELSEC-Q series PLC selection
8.2.3 Power supply
8.2.4 Control box
8.2.5 Grounding
8.2.6 External wiring

9. LOADING AND INSTALLATION

9.1 General Safety Requirements

9.2 Calculating Heat Generation by PLC
9.3 Module Installation
9.3.1 Precaution on installation
9.3.2 Instructions for mounting the base unit
9.3.3 Installation and removal of module
9.4 How to set Stage Numbers for the Extension Base Unit
9.5 Connection and Disconnection of Extension Cable
9.6 Wiring
9.6.1 The precautions on the wiring
9.6.2 Connecting to the power supply module

10. MAINTENANCE AND INSPECTION

10.1 Daily Inspection

10.2 Periodic Inspection
10.3 Battery Replacement
10.3.1 Battery service life
10.3.2 Battery replacement procedure
10.4 When Resuming Operation after Storage of PLC without Battery
10.5 When Resuming PLC Operation after Storage of PLC with Battery Gone Flat
A - 16 A - 16
11. TROUBLESHOOTING

11.1 Troubleshooting Basics

11.2 Troubleshooting
11.2.1 Troubleshooting flowchart
11.2.2 Flowchart for when "MODE" LED is not turned on
11.2.3 Flowchart for when "MODE" LED is flickering
11.2.4 Flowchart for when "POWER" LED is turned off
11.2.5 Flowchart for when the "RUN" LED is turned off
11.2.6 When the "RUN" LED is flickering
11.2.7 Flowchart for when "ERR." LED is on/flickering
11.2.8 When "USER" LED is turned on
11.2.9 When "BAT." LED is turned on
11.2.10 Flowchart for when "BOOT" LED is flickering
11.2.11 Flowchart for when output module LED is not turned on
11.2.12 Flowchart for when output load of output module does not turn on
11.2.13 Flowchart for when unable to read a program
11.2.14 Flowchart for when unable to write a program
11.2.15 Flowchart for when it is unable to perform boot operation from memory card
11.2.16 Flowchart for when UNIT VERIFY ERR. occurs
11.2.17 Flowchart for when CONTROL BUS ERR. occurs
11.3 Error Code List
11.3.1 Procedure for reading error codes
11.3.2 Error code list
11.4 Canceling of Errors
11.5 I/O Module Troubleshooting
11.5.1 Input circuit troubleshooting
11.5.2 Onput circuit troubleshooting
11.6 Special Relay List
11.7 Special Register List

APPENDICES

APPENDIX 1 Error Code Return to Origin During General Data Processing

APPENDIX 1.1 Error code overall explanation
APPENDIX 1.2 Description of the errors of the error codes (4000H to 4FFFH)
APPENDIX 2 External Dimensions Diagram
APPENDIX 2.1 CPU module
APPENDIX 2.2 Power supply module
APPENDIX 2.3 Main base unit
APPENDIX 2.4 Slim type main base unit
APPENDIX 2.5 Extension base unit
APPENDIX 3 Upgraded Functions of High Performance model QCPU
APPENDIX 3.1 Specification comparison
APPENDIX 3.2 Function comparison
APPENDIX 3.3 Usability of added functions depending on GX Developer version

A - 17 A - 17
APPENDIX 4 Transportation Precautions
APPENDIX 4.1 Controlled models
APPENDIX 4.2 Transport guidelines

INDEX

A - 18 A - 18
Manuals

The following manuals are also related to this product.

In necessary, order them by quoting the details in the tables below.

Related Manuals

Manual Number
Manual Name
(Model Code)
High Performance Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance
and Inspection) SH-080037
This manual provides the specifications of the CPU modules, power supply modules, base units, (13JL97)
extension cables, memory cards and others. (Sold separately)

QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)

SH-080039
This manual describes how to use the sequence instructions and application instructions.
(13JF58)
(Sold separately)

QCPU (Q Mode)/QnACPU Programming Manual (PID Control Instructions) SH-080040

This manual describes the dedicated instructions used to exercise PID control. (Sold separately) (13JF59)

QCPU (Q Mode)/QnACPU Programming Manual (SFC)

SH-080041
This manual explains the system configuration, performance specifications, functions, programming,
(13JF60)
debugging, error codes and others of MELSAP3. (Sold separately)

QCPU (Q Mode)/QnACPU Programming Manual (MELSAP-L)

SH-080076
This manual describes the programming methods, specifications functions, and so on that are necessary
(13JF61)
to create the MELSAP-L type SFC program. (Sold separately)

QCPU (Q Mode) Programming Manual (Structured Text) SH-080366E

This manual describes the structured text language programming methods. (Sold separately) (13JF68)

A - 19 A - 19
How to Use This Manual

This manual is prepared for users to understand memory map, functions, programs and devices of the CPU
module when you use MELSEC-Q Series PLCs.

The manual is classified roughly into three sections as shown below.

(1) Chapters 1 and 2 Describe the outline of the CPU module and the system
configuration. The feature of CPU module and the basics
of the system configuration of CPU module are described.

(2) Chapters 3 to 6 Describe the performance specifications, executable

program, I/O No. and memory of the CPU module.

(3) Chapter 7 Describes the functions of the CPU modules.

(4) Chapter 8 Describes communication with intelligent function modules.

(5) Chapters 9 and 10 Describe parameters and devices used in the CPU
modules.

(6) Chapter 11 Describes the CPU module processing time.

(7) Chapter 12 Describes the procedure for writing parameters and

programs created at the GX Developer to the CPU module.

(8) Chapters 13 to 19 Describes an overview of the multiple PLC system, the

system configuration, the I/O numbers, communications
between CPU modules, and communications between I/O
modules and intelligent function modules.

REMARK
This manual does not explain the functions of power supply modules, base units,
extension cables, memory cards and batteries of CPU module.
For these functions, refer to the manual shown below.
• High Performance Model QCPU (Q Mode) User's Manual (Hardware Design,
Maintenance and Inspection)

A - 20 A - 20
Generic Terms and Abbreviations

The following abbreviations and general names for Q02CPU, Q02HCPU, Q06HCPU Q12HCPU, and
Q25HCPU are used in the manual.

Generic Term/Abbreviation Description

General name for Q02CPU, Q02HCPU, Q06HCPU Q12HCPU and Q25HCPU
High Performance model QCPU
modules.
Q Series Abbreviation for Mitsubishi MELSEC-Q Series Programmable Logic Controller.
Abbreviation for small types of Mitsubishi MELSEC-A Series Programmable Logic
AnS Series
Controller.
General product name for SWnD5C-GPPW-E, SWnD5C-GPPW-A-E, SWnD5C-
GX Developer GPPW-V-E and SWnD5C-GPPW-VA-E.
For QCPU, version 4 or later can be used.
General name for Q33B, Q35B, Q38B and Q312B type main base units that accept
Q3 B High Performance model QCPU, Q series power supply module, input/output modules
and intelligent function modules.
General name for Q32SB, Q33SB and Q35SB type slim type main base units that
Q3 SB accept High Performance model QCPU, slim type power supply module, input/output
modules and intelligent function modules.
General name for Q52B and Q55B that accept the Q Series I/O and intelligent
Q5 B
function modules.
General name for Q63B, Q65B, Q68B and Q612B type extension base unit with Q
Q6 B
Series power supply module, I/O module, intelligent function module attachable.
General name for QA1S65B and QA1S68B type extension base unit with AnS Series
QA1S6 B
power supply module, I/O module, special function module attachable.
QnCPU General name for Q02CPU.
QnHCPU General name for Q02HCPU, Q06HCPU Q12HCPU and Q25HCPU
General name for Q33B, Q35B, Q38 and Q312B type main base unit with Q Series
Main base unit
power supply module, I/O module, intelligent function module attachable.
General name for Q32SB, Q33SB and Q35SB type slim type main base units that
Slim type main base unit accept High Performance model QCPU, slim type power supply module, input/output
modules and intelligent function modules.
Extension base unit General name for Q5 B, Q6 B and QA1S6 B.
Base unit General name for main base unit and extension base unit.
General name for QC05B, QC06B, QC12B, QC30B, QC50B and QC100B type
Extension cable
extension cable.
General name for Q61P-A1, Q61P-A2, Q62P, Q63P, Q64P, A1S61PN, A1S62P and
Power supply module
A1S63P type power supply module.
Slim type power supply module General name for Q61SP type slim type power supply module.
General name for battery for Q6BAT and Q7BAT type CPU module and Q2MEM-BAT
Battery
type SRAM card.
SRAM card Abbreviation for Q2MEM-1MBS and Q2MEM-2MBS type SRAM card.
Flash card General name for Q2MEM-2MBF and Q2MEM-4MBF type Flash card.
ATA card General name for Q2MEM-8MBA, Q2MEM-16MBA and Q2MEM-32MBA type ATA card.
Memory card General name for SRAM card, Flash card and ATA card.
CPU slot Slot on the right of the power supply module of the main base unit.
High Performance model QCPU/motion CPU that controls any of the I/O and
intelligent function modules mounted on the main or extension base unit. For
Control CPU
example, when the module mounted on slot 3 is controlled by the CPU No. 2, the
CPU No. 2 is the control CPU of the module on slot 3.
I/O or intelligent function module other than the controlled module. For example, when
Non-controlled module
the module mounted on slot 3 is controlled by the CPU No. 2, the module on slot 3 is
(Non-group module)
the non-controlled module of the CPU Nos. 1, 3 and 4.

A - 21 A - 21
 Generic Term/Abbreviation Description
I/O or intelligent function module controlled by the control CPU. For example, when
Controlled module the module mounted on slot 3 is controlled by the CPU No. 2, the module on slot 3 is
the controlled module of the CPU No. 2.
Numbers assigned to differentiate between the High Performance model QCPU and
motion CPU mounted in a multi CPU system. The CPU on the CPU slot is the CPU
CPU numbers
No. 1, the one on slot 0 is the CPU No. 2, the one on slot 1 is the CPU No. 3, and the
one on slot 2 is the CPU No. 4.
System mounted with the High Performance model QCPU on the CPU slot to exercise
Single CPU system
control.
PC CPU module MELSEC-Q Series corresponding PC CPU module
High Performance model QCPUs and/or Motion CPUs other than the control CPU.
Non-control CPUs For example, when the module mounted on slot 3 is controlled by the CPU No. 2, the
CPU Nos. 1, 3 and 4 are the non-control CPU of the module on slot 3.
System mounted with up to four High Performance model QCPU, Motion CPU and PC
Multiple CPU system
CPU module on the main base unit to exercise control.

A - 22 A - 22
MEMO

A - 23 A - 23
 1 OVERVIEW
MELSEC-Q

1. OVERVIEW
1 This manual describes the functions, programs and devices of the High Performance
model QCPU.

Refer to the following manual for the specifications, etc. of the power supply modules,
base units, extension cables, memory cards and battery.
High Performance Model QCPU (Q Mode) User's Manual (Hardware Design,
Maintenance and Inspection)

Functions are added when the High Performance model QCPU is updated.
The added functions can be discriminated by the function version/serial number of the
CPU module.
Table 1.1 gives the added functions and the corresponding GX Developer versions.
When using the added function, confirm the function version/serial number and the GX
Developer version.

Table 1.1 List of Functions Added to High Performance Model QCPU and Function
Versions/Serial Numbers
Update Details of High Performance Model QCPU
Corresponding
Function
Serial No. Added functions GX Developer
version
• Automatic write to standard ROM
• Enforced ON/OFF for external I/O
• Remote password setting
• Increased standard RAM capacity of
A "02092" or later Version 6 or later
Q12HCPU, Q25HCPU
• Compatibility with MELSECNET/H remote
I/O network
• Interrupt module (QI60) compatibility
— • Compatibility with the multiple PLC system Version 6 or later
• Installation of PC CPU module into the
"03051" or later multiple PLC system
Version 7 or later
• High speed interrupt function
• Compatibility with index modification for
module designation of dedicated instruction
• Selection of refresh item for COM
Version 7.10L
"04012" or later instruction
or later
• Extended life battery of SRAM card
B • Compatibility with 2Mbyte SRAM card
• Increased standard RAM capacity of
Q02HCPU, Q06HCPU
• SFC program online batch change
"04122" or later • File memory capacity change
Version 8 or later
• CC-Link remote network additional mode
• Incomplete derivative PID operation
Version 8.03D or
"05032" or later function
later
• Floating-point comparison instruction
speedup

POINT
(1) Refer to Section 2.3 for the serial No. and function version of the High
Performance model QCPU.
(2) Refer to Appendix 4 for details.

1-1 1-1
1 OVERVIEW
MELSEC-Q

1.1 Features

High Performance model QCPU has the following new features: 1

(1) Controllable multiple I/O points
All High Performance model QCPUs support 4096 points (X/Y0 to FFF) as the
number of actual I/O points capable of getting access to the I/O module installed
on the base unit.
They also support 8192 points max. (X/YO to 1FFF) as the number of I/O
devices which can be used in the remote I/O stations such as MELSECNET/H
remote I/O NET, CC-Link data link and MELSECNET/MINI-S3 data link.

(2) Lineup according to program capacity

The optimum CPU module for the program capacity to be used can be selected.
Q02CPU, Q02HCPU : 28k step
Q06HCPU : 60k step
Q12HCPU : 124k step
Q25HCPU : 252k step

(3) Realised high speed processing

Depending on the type of the sequencer, high speed processing has been
realized.(Example: when LD instruction is used)
Q02CPU : 0.079 s
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU : 0.034 s

In addition, an access to the intelligent function module or an increase in speed

of the link refresh of the network have been realized by the connection system
(System bus connection) of the newly developed base unit.
Access to the intelligent function module : 20 s /word (approx. 7 times) 1
MELSECNET/H link refresh processing : 4.6ms/8k word (approx. 4.3 times) 1
1: Where Q02HCPU is compared with Q2ASHCPU-S1.

(4) Increase in debugging efficiency through high speed

communication with GX Developer
In the High Performance model QCPU, a time required for writing/reading of a
program or monitoring has been reduced through the high speed communication
at a speed of 115.2kbps max. by the RS-232, and a communication time
efficiency at the time of debugging has been increased.
In the Q02HCPU, Q06HCPU, Q12HCPU, and Q25HCPU, a high speed
communication at a speed of 12Mbps is allowed through the USB.

26k step program transfer time

Q25HCPU(USB) 12

Q25HCPU(RS-232) 30

Q2ASHCPU 86

A2USHCPU-S1 94

0 10 20 30 40 50 60 70 80 90 100 (Unit:s)

(5) AnS series I/O module or special function module are available.
For Q series, if an appropriate module is not available, the AnS series I/O
module or special function module can also be used for the High Performance
model QCPU through the use of the QA1S65B/QA1S68B extension base unit.

1-2 1-2
1 OVERVIEW
MELSEC-Q

(6) Saved space by a reduction in size

The installation space for Q series has been reduced by approx. 60 % of the
space for AnS series.
Comparison of installation space
1SX10 1SY50 1SX41 1SY41 1SX81 1SY81 1SX42 1SY42

98mm
(3.86
inch) PULL

5 Slot Basic Base Unit 245mm(9.65inch) (depth:98mm(3.86inch))

8 Slot Basic Base Unit 328mm(12.92inch)
12 Slot Basic Base Unit 439mm(17.30inch)

(7) Connection of up to seven extension base units.

(a) The High Performance model QCPU can connect to seven extension base
units (eight base units including the main) and accept up to 64 modules.
(b) The overall distance of the extension cables is up to 13.2m to ensure high
degree of extension base unit arrangement.

(8) Memory extension by memory card

The High Performance model QCPU is provided with a memory card installation
connector to which a memory card of 32 Mbyte max. can be connected (32
Mbyte is available when a ATA card is used).
When a memory card of large capacity is installed, a large capacity of file can be
controlled, comments to all data devices can be set up, and the programs in the
past can be stored in the memory as they are in the form of the corrected
histories.
If a memory card is not installed, a program can be stored onto the standard
ROM built in the CPU module, and file registers can be handled by the standard
RAM.

REMARK
• The number of file registers that can be handled changes depending on the
function version/serial number of the CPU module used.
CPU Module Type Number of File Registers
Q02CPU 32k points
Q02HCPU First 5 digits of serial number are "04011" or earlier 32k points
Q06HCPU First 5 digits of serial number are "04012" or later 64k points
Q12HCPU First 5 digits of serial number are "02091" or earlier 32k points
Q25HCPU First 5 digits of serial number are "02092" or later 128k points
Refer to Section 2.3 to confirm the function version and serial number of the High
Performance model QCPU.

1-3 1-3
1 OVERVIEW
MELSEC-Q

(9) Data can be written automatically to standard ROM

You need not use GX Developer to write parameters/programs on a memory
card to the standard ROM of the High Performance model QCPU.
When the standard ROM is used to perform ROM operation, you can load a
memory card into the High Performance model QCPU and write
parameters/programs on the memory card to the standard ROM. Hence, you
need not carry GX Developer (personal computer) to rewrite the
parameters/programs.
(10) External I/O can be turned ON/OFF forcibly
If the High Performance model QCPU is in the RUN mode, you can operate GX
Developer to turn external inputs/outputs ON/OFF forcibly, independently of the
program execution status.
You need not put the High Performance model QCPU in the STOP mode to
perform wiring/operation tests by forced ON/OFF of outputs.
(11) Remote password can be set
When access to an Ethernet module or serial communication module is made
externally, whether access to the High Performance model QCPU can be made
or not can be selected with a remote password.
(12) Remote I/O network of MELSECNET/H can be configured
You can load the remote master station of the MELSECNET/H to configure an
MELSECNET/H remote I/O system.
(13) PC CPU module compatibility in multiple CPU system configuration
The High Performance model QCPU, Motion CPU and PC CPU module can
configure a multiple CPU system.
(14) Ease of handling CC-Link system
When one master module for CC-Link system is used, I/O signals for up to 64
remote I/O stations can be controlled without parameter setting.
The remote I/O stations can be controlled as if I/O modules on the base unit are
controlled.
(15) File password for blocking illegal access
The file password can be used to set the access level (read disable, write
disable) of a program to prevent program file, device initial value file and device
comment file changes due to illegal access.

REMARK
1) Features (9) to (12) are functions added to the High Performance model QCPU
whose serial number is "02092" or later in its upper 5 digits.
2) The remote password facility can be executed when the Ethernet module or
serial communication module of function version B and GX Developer Version 6
or later are used.
3) In addition to the remote password, there are the following protection facilities for
the High Performance model QCPU.
Protection of the whole CPU module by making system settings of the High
Performance model QCPU
Protection of the memory card by setting the write protect switch of the memory
card
File-by-file protection using password
4) The MELSECNET/H remote I/O network facility can be executed when the
MELSECNET/H network module of function version B and GX Developer
(Version 6 or later) are used.
5) The feature in (13) is the function added to the High Performance model QCPU
whose first five digits of serial No. are "03051" or later.

1-4 1-4
1 OVERVIEW
MELSEC-Q

1.2 Programs

(1) Program management by memory card

(a) Programs created with GX Developer can be stored in the QCPU's program
memory, standard ROM or memory card.

High Performance model QCPU

Program memory
Parameter

Program Memory
card
Standard ROM 1 RAM
Parameter Parameter
Program Program
File register File register
(only read process
is enabled) ROM
Parameter
Standard RAM 2
Program
File register
File register
When Flash card
is used, only read
process is enabled

1: The standard ROM is used when parameters and programs are written
to ROM.
2: The standard RAM is used when access to the file register need to
speed up.

(b) The QCPU processes programs stored in the program memory.

High Performance model QCPU
Program memory Execution of program
Parameter in program memory

Program

1-5 1-5
1 OVERVIEW
MELSEC-Q

Programs stored in the standard ROM/memory card are executed after they
are booted to (read to) the QCPU program memory. (Programs to be booted
to the QCPU are designated on the “(PLC) Parameter" dialog box, and the
parameter drive is designated by a DIP switch setting at the QCPU.)
High Performance model QCPU
Program memory
Execution of program booted
Parameter from the standard ROM or memory
card to the program memory.
Program

Boot
Memory card Standard ROM
Parameter Parameter

Program Program

(2) Program construction

Programs are stored in a file format in the program memory, standard ROM or
memory card.
Multiple programs can therefore be stored in the program memory, standard
ROM or memory card by using different file names.
Multiple program writing
is enabled by using
different file names.
File name: ABC File name: ABC File name: DEF
Device
Parameter Program Program
comments High
GX
Performance
Developer
Writing from GX Developer to QCPU model QCPU

Therefore, the program creation can be split among several designers so that
they control and manage the programs by process or function.
Only the relevant programs should be modified or debugged when the
specifications are changed.

(a) Example of program creation split among several designers:

High Performance model QCPU
Program memory
/ Standard ROM / Memory card

Designer A Program A
Programs A to C
Designer B Program B are executed in
sequence. 1
Designer C Program C

REMARK
1: See Section 4.2 for details on the execution sequence.

1-6 1-6
1 OVERVIEW
MELSEC-Q

(b) Example of programs split by process: 1

High Performance model QCPU
Program memory
/ Standard ROM / Memory card

Ship in Program A

Split Manufacturing Program B Programs A to D

by are executed in
process Assembly Program C sequence. 2

Ship out Program D

(c) Example of programs split by function:

High Performance model QCPU
Program memory
/ Standard ROM / Memory card

Initial processing Program A The execution

sequence and
Split Main processing Program B execution
by conditions can
function Communication processing Program C be set to conform
to programs
Error processing Program D A to D. 2

REMARK
1: Programs split by process can be further split by function.
2: See Section 4.2 for details on the execution sequence and execution conditions.

1-7 1-7
1 OVERVIEW
MELSEC-Q

1.3 Convenient Programming Devices and Instructions

The QCPU features devices and instructions which facilitate program creation. Some
of them are described below.

(1) Flexible device designation

(a) Word device bits can be designated to serve as contacts or coils.
[In the case of High Performance model QCPU] [In the case of AnS]
Bit designation of
X0 D0.5 word device X0
D0.A MOV D0 K4M0

Switches b10 M5
of D0 ON and M10
The 1/0 status OFF (1/0).
of b5 of D0 is used
as ON/OFF data.
MOV K4M0 D0

: D0.5
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Bit designation
D0 1/0 1/0 Word device designation

(b) Direct processing in 1-point units is permitted within a program simply by

using direct access inputs (DX ) and direct access outputs (DY ).
[In the case of High Performance model QCPU]
[In the case of AnS]
Direct access input
M0 DX10 M9036
DY100 SET M9052
(Always ON)
Output to output M9036
module at SEG K1X10 K1B0
instruction execution (X10 to X13 refresh)
Read from input M0 X10
Y100
module at
instruction
execution M9036
SEG K1Y100 K1B0
(Y100 to Y103 refresh)

(c) Differential contacts ( / ) eliminate the need of converting inputs to

pulses.
[In the case of High Performance model QCPU] [In the case of AnS]
Differential contact
X0 X1 X0
Y100 PLS M0

Y100 M0 X1
Y100

ON at leading Y100
edge of X0

1-8 1-8
1 OVERVIEW
MELSEC-Q

(d) The buffer memory of intelligent function module (e.g. Q64AD, Q62DA) can
be used in the same way as devices when programming.
[In the case of High Performance model QCPU] [In the case of AnS]
X0 X0
+P U4\G12 D0 FROMP H4 K12 D10 K1

Readout of Q64AD
buffer memory's
+P D10 D0
address 12 data
Power supply module

:U4\G12
Q64AD (16 points)
Q64AD (16 points)
Q62AD (16 points)
Output (16 points)
Output (16 points)
Input (16 points)
Input (16 points)
Input (16 points)

Buffer memory address

designation
QCPU

Intelligent function
module designation

I/O Nos.:X/Y40 to X/Y4f

POINT
By making the automatic refresh setting of the used intelligent function module
using GX Configurator, the corresponding data can be read/written from/to the
device memory of the CPU module without access being made directly to the buffer
memory.

(e) Direct access to link devices (LX, LY, LB, LW, SB, SW) of MELSECNET/H
network modules (e.g. QJ71LP21-25) is allowed without refresh settings.
X0
+P J5\W12 D0

Direct readout of the No.5 network module's

"LW12" link register
Power supply module

Q68AD (16 points)

Q68AD (16 points)
Q62AD (16 points)
Output (16 points)
Output (16 points)
Input (16 points)
Input (16 points)

:J5\W12
QJ71LP21-25

Link register designation

QCPU

Network No. designation

Network No.5

1-9 1-9
1 OVERVIEW
MELSEC-Q

(2) Edge relays simplify pulse conversion processing

(a) The use of a relay (V) that comes ON at the leading edge of the input
condition simplifies pulse processing when a contact index qualification has
been made.
[Circuit example]
M1000
RST Z1 Reset index register (Z1)

FOR K1000 Repetition (1000 times) designation

X0Z1 V0Z1
M0Z1 Pulsing M0 to M999

M1000
INC Z1 Increment Index Register (Z1) (+1)

NEXT Return to FOR instruction

[Timing chart]
ON
X0 OFF
ON
When Z1=0 V0 OFF
ON
M0 OFF
1 Scan

ON
X1 OFF
ON
When Z1=1 V1 OFF
ON
M1 OFF
1 Scan

(3) Simple data processing

(a) Real numbers (floating decimal point data) and character string constants
can be used in the programming as they are.
X0 Real number data Real number data Real number data
E+P E1.23 D0 R0 D0 R0
E1.23 + E3.45 E4.68
Real number ADD instruction D1 R1

$+P D5 "CPU" D10 Character Character Character

string data string data string data
Character string data LINK instruction
D5 "0" "Q" D10 "0" "Q"
+ "CPU"
D6 NUL "2" D11 "C" "2"
D12 "U" "P"
D13 NUL

REMARK
: NUL indicates "00H (character string END)".

1 - 10 1 - 10
1 OVERVIEW
MELSEC-Q

(b) Data processing instructions such as table processing instructions, etc.,

enable high speed processing of large amounts of data.
X0
FINSP D0 R0 K2 FIF0 table FIF0 table
Insertion Insertion Insertion position R0 3 R0 4
source designation R1 10 R1 10
Instruction for data insertion at table D0 15 R2 20 R2 15
R3 30 R3 20
R4 R4 30

(4) Easy shared use of sub-routine programs

(a) A common pointer can be used to call the same sub-routine program from
all sequence programs being executed.
Program A Common pointer Subroutine program
M0 P1000 call SM400 M0
0 CALLP P1000 P1000 MOV K4X0 R0
Always
ON
M0
MOV K4X20 R0

Program B
RET
M10 P1000 call
0 CALLP P1000

(b) The use of sub-routine call instructions with arguments simplifies the
creation of sub-routine programs which are called several times.
Sub-routine program
Argument designation Destination data
P0 call source data
M0 SM400 M0
0 CALLP P0 W0 K4X0 R0 P0 MOV FD0 FD2
Always
Argument from FD2
ON
Argument to FD1 M0
Argument to FD0 MOV FD1 FD2
Subroutine program
designation
Argument designation RET
M10 P0 call
100 CALLP P0 W10 K4X10 R10

Argument from FD2

Argument to FD1
Argument to FD0

REMARK
: For details on the argument I/O condition, see Section 10.3.1.

1 - 11 1 - 11
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

2. SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM

This section describes the system configuration of the High Performance model
QCPU, cautions on use of the system, and configured equipment.

2.1 System Configuration

The outline of the equipment configuration, configuration with peripheral devices, and
system configuration in the High Performance model QCPU system is described
below. 2
(1) Equipment configuration
(a) When main base unit (Q3 B) is used

MITSUBISHI

MITSUBISHI
LITHIUM BATTERY

Memory card 1 High Performance model QCPU

(Q2MEM-1MBS,Q2MEM-2MBS, Battery
(Q02CPU,Q02HCPU,Q06HCPU,
Q2MEM-2MBF,Q2MEM-4MBF, (Q6BAT)
Q12HCPU,Q25HCPU)
Q2MEM-8MBA,Q2MEM-16MBA,
Q2MEM-32MBA)

MITSUBISHI
LITHIUM BATTERY

Battery
Battery holder
(Q7BAT)
Q7BAT-SET

Power supply module 4 ,

Main base unit
I/O module , Intelligent function
(Q33B, Q35B,Q38B,Q312B)
module of the Q Series
2
Extension of the AnS Series module Extension of the Q Series module

Q5 B extension base unit

Extension cable
QA1S6 extension base unit (Q52B, Q55B)
(QC05B,QC06B,QC12B,
(QA1S65B,QA1S68B) Q6 B extension base unit
QC30B, QC50B,QC100B)
(Q63B, Q65B,Q68B,Q612B)

Power supply module , Power supply module 3 4,

I/O module , Intelligent function I/O module , Intelligent function
module of the AnS Series module of the Q Series

POINTS
1: The number of memory cards to be installed is one sheet.
The memory card must be selected from SRAM, Flash, and ATA according to the
application and capacity.
With commercial memory cards, the Operation is not assured.
2: QA1S65B and QA1S68B extension base units are used for the power supply module, I/O
module, and special function module of the AnS series.
3: The Q series power supply module is not required for the Q5 B type extension base unit.
4: As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P.
The slim type power supply module (Q61SP) cannot be used.
2-1 2-1
 2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

(b) When slim type main base unit (Q3 SB) is used

MITSUBISHI

MITSUBISHI
LITHIUM BATTERY

Memory card *1
High Performance model QCPU
(Q2MEM-1MBS,Q2MEM-2MBS, Battery
(Q02CPU,Q02HCPU,Q06HCPU,
Q2MEM-2MBF,Q2MEM-4MBF, (Q6BAT)
2 Q2MEM-8MBA,Q2MEM-16MBA,
Q12HCPU,Q25HCPU)
Q2MEM-32MBA)

MITSUBISHI
LITHIUM BATTERY

Battery
Battery holder
(Q7BAT)
Q7BAT-SET

Slim type power supply module, *3

Slim type main base unit
I/O module ,
(Q32SB,Q33SB,Q35SB) *2
Intelligent function module

POINTS
1: One memory card is installed.
Select the memory card from the SRAM card, Flash card and ATA card according to the
application and capacity.
When the memory card available on the market is used, operation is not guaranteed.
2: The slim type main base unit does not have an extension cable connector. The extension
base or GOT cannot be connected.
3: As a power supply module, use the slim type power supply module (Q61SP).
The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply module.

2-2 2-2
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

(2) Configuration of peripheral devices

MITSUBISHI

Memory card 1 High Performance model QCPU USB cable 1

(To be procured yourself)
(Q2MEM-1MBS,Q2MEM-2MBS, (Q02CPU,Q02HCPU,Q06HCPU, Only Q02HCPU, Q06HCPU
Q2MEM-2MBF,Q2MEM-4MBF, Q12HCPU,Q25HCPU) Q12HCPU and Q25HCPU
Q2MEM-8MBA,Q2MEM-16MBA, can be used.
Q2MEM-32MBA)

RS-232 cable
(QC30R2)

Personal Computer
PC card adapter GX Developer Version 4 or later
(Q2MEM-ADP) (SW4D5C-GPPW-E)

1: For writing into memory card on GX Developer, and USB cable, refer to the
operating manual of the GX Developer.

2-3 2-3
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

(3) Outline of system configuration

(a) When main base unit (Q3 B) is used
Main base unit(Q312B)
Power supply module
0 1 2 3 4 5 6 7 8 9 10 11 Slot No.
00 20 40 60 80 A0 C0 E0 100 120 140 160
O C
Extension U
T P
cable U 1F 3F 5F 7F 9F BF DF FF 11F 13F 15F 17F

Extension base unit(Q612B)

1st extension Power supply module The figure shows the configuration
stage 12 13 14 15 16 17 18 19 20 21 22 23
180 1A0 1C0 1E0 200 220 240 260 280 2A0 2C0 2E0 when 32-I/O modules are
O
IU
loaded to each slot.
NT
19F 1BF 1DF 1FF 21F 23F 25F 27F 29F 2BF 2DF 2FF
Extension base unit(Q68B) Extension base unit(QA1S68B)
2nd extension Power supply module 5th extension Power supply module
stage 24 25 26 27 28 29 30 31 stage 45 46 47 48 49 50 51 52
300 320 340 360 380 3A0 3C0 3E0 5A0 5C0 5E0 600 620 640 660 680
System configuration O O
IU IU
NT NT
31F 33F 35F 37F 39F 3BF 3DF 3FF 5BF 5DF 5FF 61F 63F 65F 67F 69F
Extension base unit(Q68B) Extension base unit(QA1S68B)
3rd extension Power supply module 6th extension Power supply module
stage 32 33 34 35 36 37 38 39 stage 53 54 55 56 57 58 59 60
400 420 440 460 480 4A0 4C0 4E0 6A0 6C0 6E0 700 720 740 760 780
O O
IU IU
NT NT
41F 43F 45F 47F 49F 4BF 4DF 4FF 6BF 6DF 6FF 71F 73F 75F 77F 79F
Extension base unit(Q65B) Extension base unit(QA1S65B)
4th extension
Power supply module 7th extension Power supply module
stage 40 41 42 43 44 stage 61 62 63
500 520 540 560 580 7A0 7C0 7E0

Invalid
Invalid
O O
IU IU
NT NT
51F 53F 55F 57F 59F 7BF 7DF 7FF

Maximum number of
Seven Extension Stages
Extension Stages
Maximum number of
I/O modules to be 64 modules
installed
Maximum number of
4096
occupied I/O points
Main base unit Q33B, Q35B, Q38B, Q312B
Extension base unit Q52B, Q55B, Q63B, Q65B, Q68B, Q612B, QA1S65B, QA1S68B
Extension cable QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
(1) Extension bases unit of up to seven stages can be used.
(2) Do not use extension cable longer than an overall extension length of 13.2m(43.31ft.).
(3) When using an extension cable, do not bind it together with the main circuit (high voltage and heavy current)
line or do not lay down them closely to each other.
(4) When setting the No. of the expansion stages, set it in the ascending order so that the same No. is not set
simultaneously by two extension base units.
(5) When Q5 B, Q6 B and QA1S6 B types of extension base units are mixed, first connect the Q5 B,
Q6 B type and then connect the QA1S6 B type.
When setting the No. of the extension stages, set it from Q5 B/Q6 B in order.
Notes Although there are no particular restrictions in the order of the installation of the Q5 B and Q6 B, refer to
Section 6.6 for usability.
(6) Connect the extension cable from OUT of the extension cable connector of the base unit to IN of the
extension base unit on the next stage.
(7) If 65 or more modules are installed, an error will occur.
(8) When bus-connected, the GOT occupies one extension stage and one slot.
(9) The High Performance model QCPU processes the GOT as a 16-point intelligent function module. Hence,
connection of one GOT decreases the number of controllable points on base unit by 16 points.
(10) As a power supply module, the Q61SP cannot be used.
Use the Q61P-A1, Q61P-A2, Q62P or Q64P as a power supply module.
2-4 2-4
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

(b) When slim type main base unit (Q3 SB) is used
Slim type main base unit (Q35SB)
0 1 2 3 4 Slot No.

Power supply
00 20 40 60 80

CPU module
module
System configuration
1F 3F 5F 7F 9F

The above system assumes that each slot is loading with

a 32-point module.
Maximum number of
Extension not allowed
Extension Stages
Maximum number of
I/O modules to be 5 modules
installed
Maximum number of
4096
occupied I/O points
Slim type main base
Q32SB, Q33SB, Q35SB
unit type
Extension base unit Cannot be connected.
Extension cable Cannot be connected.
(1) The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply module.
Use the Q61SP as a power supply module.
Notes (2) The slim type main base unit does not have an extension cable connector.
The extension base or GOT cannot be connected.

2-5 2-5
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

2.2 Precaution on System Configuration

This section describes hardware and software packages compatible with QCPU.

(1) Hardware
(a) The number of modules to be installed and functions are limited depending on
the type of the modules.
Limit of number of modules
Applicable Module Type
to be installed
• QJ71LP21
• QJ71BR11
Q Series MELSECNET/10H
• QJ71LP21-25 Up to 4 units
network module
• QJ71LP21G
• QJ71LP21GE
• QJ71E71
Q series Ethernet interface
• QJ71E71-B2 Up to 4 units
module
• QJ71E71-100
Q series CC-Link system • QJ61BT11
No limit
master local module • QJ61BT11N
No limit
MELSECNET/MINI-S3 data • A1SJ71PT32-S3
(setting of automatic refresh
link module • A1SJ71T32-S3
function not allowed)
• A1SD51S
AnS series special function • A1SD21-S1
Total of 6 units
module shown on the right • A1SJ71J92-S3
(When GET/PUT service is used)
• A1SI61
Interrupt module One unit only
• QI60
: A maximum of 4 modules if the network parameters for CC-Link are set and
controlled by the GX Developer. There is no restriction in the number of modules
when the parameters are set by the special-purpose instructions for the CC-Link.
For details on the CC-Link System Master Local Unit that can set parameters with
the special-purpose instructions, refer to the user's manual for the CC-Link Master
Local module.

(b) When the AnS series special-function modules shown below are used, a
limitation is given to an accessible device range.
• A1SJ71J92-S3 type JEMANET interface module
• A1SD51S type intelligent communication

Device Accessible device range

Input (X), Output (Y) X/Y0 to 7FF
Internal relay (M), Latch relay (L) M0 to 8191
Link relay (B) B0 to FFF
Timer (T) T0 to 2047
Counter (C) C0 to 1023
Data register (D) D0 to 6143
Link register (W) W0 to FFF
Annunciator (F) F0 to 2047

(c) A graphic operation terminal can be used only for the GOT900 series (Basic
OS matching Q mode and communication driver must be installed).
The GOT800 series, A77GOT, and A64GOT cannot be used.

2-6 2-6
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

(d) The modules shown below cannot be used.

Module Name Type
MELSECNET/IO network A1SJ71LP21, A1SJ71BR11, A1SJ71QLP21,
module A1SJ71QLP21S, A1SJ71QLP21GE, A1SJ71QBR11
MELSECNET (II), /B data link
A1SJ71AP21, A1SJ71AR21, A1SJ71AT21B
module
A1SJ71QE71-B2-S3(-B5-S3),
Ethernet interface module
A1SJ71E71-B2-S3(-B5-S3)
Serial communication module,
A1SJ71QC24(N), A1SJ71UC24-R2(-R4/-PRF)
computer link module
CC-Link master-local module A1SJ61QBT11, A1SJ61BT11
Modem interface module A1SJ71CMO-S3
ME-NET interface module A1SJ71ME81

(e) A dedicated instruction for the next module which was present in the QnA/A
series program instruction cannot be used for the High Performance model
QCPU. Re-writing using FROM/TO instruction is required.
Module Name Type
High speed counter module A1SD61, A1SD62, A1SD62D(-S1), A1SD62E
MELSECNET/MINI-S3 A1SJ71PT32-S3, A1SJ71T32-S3
Positioning module A1SD75P1-S3(P2-S3/P3-S3)
ID module A1SJ71ID1-R4, A1SJ71ID2-R4

(f) Some system configurations and functions are restricted when writing the
parameter of the "High speed interrupt fixed scan interval" setting.
Refer to the following manual for the restrictions when the parameter of the
"High speed interrupt fixed scan interval" setting has been written.
• High Performance model QCPU (Q mode) User's Manual
(Function Explanation, Program Fundamentals)
Note that the above restrictions do not apply to the High Performance model
QCPU of serial number "04011" or earlier since it ignores the "High speed
interrupt fixed scan interval" setting.

(2) Software package

GX Developer that can use the functions added to the High Performance model
QCPU changes depending on the function version/serial number of the CPU
module.
Function Version Serial Number GX Developer
A — Version 4 (SW4D5C-GPPW-E) or later
— Functions added to "02092"
Version 6 (SW6D5C-GPPW-E) or later
B —
— Functions added to "03052" Version 7 (SW7D5C-GPPW-E) or later
Version 7.10L (SW7D5C-GPPW-E)
— Functions added to "04012"
or later
— Functions added to "04122 " Version 8 (SW8D5C-GPPW) or later
— Functions added to "05032 " Version 8.03D (SW8D5C-GPPW) or later

POINT
(1) Refer to Section 2.3 for the serial No. and function version of the High
Performance model QCPU.
(2) Refer to Appendix 4 for details.

2-7 2-7
2 SYSTEM CONFIGURATION FOR SINGLE CPU SYSTEM
MELSEC-Q

2.3 Confirming the Serial Number and Function Version

The CPU module serial No. can be confirmed on the rated plate and GX Developer's
system monitor.
(1) Confirming the serial No. on the rated plate

Function version

(2) Confirming the serial No. on the system monitor (list of product
information)
The CPU module serial No. and function version can be confirmed with the list of
product information on the GX Developer (Version 6 or later) system monitor.
Serial Nos. and function versions of the intelligent function module and CPU
module can also be confirmed.

Serial number Function version

2-8 2-8
3 PERFORMANCE SPECIFICATION
MELSEC-Q

3. Performance Specification
The table below shows the performance specifications of the CPU module.
Performance Specifications
Model
Item Remark
Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU
Control method Repetitive operation of stored program
Direct I/O is possible by
I/O control mode Refresh mode direct I/O specification
(DX , DY )
Relay symbol language, logic symbolic language,
Programming language
MELSAP3 (SFC), MELSAP-L, Function block,
(Sequence control dedicated language)
structured text (ST) 3
Processing speed LD X0 0.079 s 0.034 s
(Sequence instruction) MOV D0 D1 0.237 s 0.102 s
381
Total number of instructions
(excluding intelligent function module dedicated instructions)
Constant scan (ms)
Set parameter values to
(Function for setting the scan timer to fixed 0.5 to 2000 (configurable in increments of 0.5 ms)
specify
settings)
Program 2 Program memory
28k step 60k step 124k step 252k step See Section 6.2.
capacity (Drive 0)
Memory card (RAM)
Capacity of loading memory cards (2Mbyte max.) See Section 6.5.
(Drive 1)
Memory card (ROM) Installed memory card capacity
See Section 6.5.
(Drive 2) (Flash card: 4 Mbyte max., ATA card: 32 Mbyte max.)
Memory Standard RAM
64kbyte 128kbyte 5 256kbyte 3 See Section 6.4.
capacity (Drive 3)
Standard ROM
112 kbyte 240 kbyte 496 kbyte 1008 kbyte See Section 6.3.
(Drive 4)
CPU shared memory
8 kbyte See Section 14.2.4.
3
Program memory 28 60 124 252 1 See Section 6.2.
Memory card (RAM) 256 See Section 6.5.
Memory Flash card 288 See Section 6.5.
Maximum number card
ATA card 512 See Section 6.5.
of stored files (ROM)
Only one file register
Standard RAM 2
and one local device
Standard ROM 28 60 124 252 See Section 6.3.
Standard ROM number of writings Max. 100000 times
1: 124 is the maximum number of programs that can be executed on High Performance model QCPU. 125 or more programs cannot be
executed.
2: The maximum number of sequence steps (for one program) for which the parameters are stored in another drive and executed with the
High Performance model QCPU can be calculated with the following expression.
(Program size) - (File header size (default: 34 steps))
Refer to the High Performance model QCPU (Q Mode) User's Manual (Function Explanation, Program Fundamentals) for details on
the program size and file.
3: The memory capacity of the Q12HCPU or Q25HCPU whose first five digits of serial No. are "02091" or earlier is 64k bytes.
(Refer to Section 2.3 for the serial No. confirmation method.)
4: The CPU shared memory is not latched. The CPU shared memory is cleared when the power is turned on to the PLC or when the
CPU module is reset.
5: The memory capacity of the Q02HCPU or Q06HCPU whose first five digits of serial No. are "04011" or earlier is 64k bytes.
(Refer to Section 2.3 for the serial No. confirmation method.)

3-1 3-1
 3 PERFORMANCE SPECIFICATION
MELSEC-Q

Performance Specifications (continued)

Model
Item Remark
Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU
Number of devices
Number of I/O device points 8192 points (X/Y0 to 1FFF)
usable on program
Number of points
Number of occupied I/O points 4096 points (X/Y0 to FFF) accesible to actual I/O
modules
Internal relay [M] Default 8192 points (M0 to 8191)

Latch relay [L] Default 8192 points (L0 to 8191)

Link relay [B] Default 8192points (B0 to 1FFF)

3 Default 2048 points (T0 to 2047) (for low / high speed timer)
Select between low / high speed timer by instructions.
The measurement unit of the low / high speed timer is set with
Timer [T] parameters.
(Low speed timer : 1 to 1000ms, 1ms/unit, default 100ms)
(High speed timer : 0.1 to 100ms, 0.1ms/unit, default 10ms)
Default 0 point(for low / high speed retentive timer)
Switchover between the low / high speed retentive timer is set by
instructions. Number of use points
Retentive timer [ST] The measurement unit of the low /high speed retentive timer is set with is set with parameters.
parameters.
(Low speed retentive timer : 1 to 1000ms, 1ms/unit, default 100ms)
(High speed retentive timer : 0.1 to 100ms, 0.1ms/unit, default 10ms)
Number of device points

• Normal counter default 1024 points (C0 to 1023)

Counter [C] • Interrupt counter maximum 256 points
(default 0 point, set with parameters)
Data register [D] Default 12288 points (D0 to 12287)

Link register [W ] Default 8192 points (W0 to 1FFF)

Annunciator [F] Default 2048 points (F0 to 2047)

Edge relay [V] Default 2048 points (V0 to 2047)

• When a standard RAM is used: 32768 points (R0 to 32767)
• When a SRAM card is used:
The number of points of up to 1041408 points can be used by block
conversion in increments of 32768 points (R0 to 32767).
• When a Flash card (2Mbyte) is used:
[R] The number of points of up to 1041408 points can be used by block
When a Flash card is
conversion in increments of 32768 points (R0 to 32767).
• When a Flash card (4Mbyte) is used: used, read only is
File register The number of points of up to 1042432 points can be used by block possible.
conversion in increments of 32768 points (R0 to 32767).
The ATA card cannot
• When a standard RAM is used: 32768 points (ZR0 to 32767)
• When a SRAM card is used: be used.
1041408 points (ZR0 to 1041407), No block conversion necessary.
[ZR] • When a Flash card (2Mbyte) is used:
1041408 points (ZR0 to 1041407), No block conversion necessary.
• When a Flash card (4Mbyte) is used:
1042432 points (ZR0 to 1042431), No block conversion necessary.

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Performance Specifications (continued)

Model
Item Remark
Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU
Link special relay [SB] 2048 points (SB0 to 7FF)
Link special register [SW] 2048 points (SW0 to 7FF)
Step relay [S] 6 8192 points (S0 to 8191)
Index register [Z] 16 points (Z0 to 15)
4096 points (P0 to 4095), set parameter values to select usable range
Number of device points

Pointer [P]
of in-file pointer / shared pointers.
256 points (I0 to 255)
The number of device
The specified intervals of the system interrupt pointers I28 to I31 can
Interrupt pointer [ I ] points is fixed.
be set with parameters.(0.5 to 1000ms, 0.5 ms/unit)
Default I28 : 100ms I29 : 40ms I30 : 20ms I31 : 10ms
Special relay [SM] 2048 points (SM0 to 2047)
Special register [SD] 2048 points (SD0 to 2047)
Function input [FX] 16 points (FX0 to F)
Function output [FY] 16 points (FY0 to F) 7
Function register[FD] 5 points (FD0 to 4) 7
Device having a direct access to link device.
MELSECNET/10(H) use only.
Link direct device
Specified form : J \X ,J \Y ,J \W ,
J \B ,J \SW ,J \SB
Device having a direct access to the buffer memory of the intelligent
Intelligent function module device
function module. Specified form : U \G
L0 to 8191 (default)
Latch (power failure compensation) range
(Latch range can be set for B, F, V, T, ST, C, D, and W.) Set parameter values
RUN and PAUSE contacts can be set from among X0 to 1FFF, to specify
Remote RUN/PAUSE contact
respectively.
Year, month, day, hour, minute, second, day of the week
(leap year automatic distinction)
Clock function Accuracy -3.18 to +5.25s (TYP. +2.12s) /d at 0°C
Accuracy -3.93 to +5.25s(TYP. +1.90s)/d at 25°C
Accuracy -14.69 to +3.53s(TYP. -3.67s)/d at 55°C
Allowable momentary power failure period Varies according to the type of power supply module.
5VDC internal current consumption 0.60A 0.64A 0.64A 0.64A 0.64A
H 98mm (3.86inch)
External dimensions W 27.4mm (1.08inch)
D 89.3mm (3.52inch)
Weight 0.20kg 0.20kg 0.20kg 0.20kg 0.20kg
6: The step relays are devices for the SFC function.
7: In a program, only FX0 to FX4 and FY0 to FY4 can be used.

REMARK
For general specifications, refer to the High Performance Model QCPU (Q Mode)
User's Manual (Hardware Design, Maintenance and Inspection).

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4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION

CONDITIONS
Sequence programs and SFC programs can be executed at the High Performance
model QCPU.
This chapter describes the sequence program configuration and execution conditions.
SFC programs are not described in this manual.
For details on SFC programs, refer to the QCPU (Q mode)/QnACPU Programming
Manual (SFC).

4.1 Sequence Program

(1) Definition of sequence program

(a) A sequence program consists of sequence instructions, basic instructions,
and application instructions, etc.
Sequence instruction
4 X0 M0 K100
T0
T0
Y30
Basic instruction
X1
BIN K4X10 D0
Application instruction
X41
FROM H5 K0 D10 K1

(b) There are 3 types of sequence program: main routine programs, sub-routine
programs, and interrupt programs.
For details on these programs, see the following sections of this manual:
• Main routine programs : Section 4.1.1
• Sub-routine programs : Section 4.1.2
• Interrupt programs : Section 4.1.3
File A

Main routine
program

FEND
P0 Sub-routine
program

RET
I0 Interrupt
program

IRET

END

REMARK
For details on the sequence instructions, basic instructions, and application
instructions, refer to the " QCPU (Q Mode)/QnACPU Programming Manual
(Common Instructions)".

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(2) Sequence program writing format

Programming for sequence programs is enabled using either ladder mode or list
mode.

(a) Ladder mode

• The ladder mode is based on the relay control sequence ladder.
Programming expressions are similar to the relay control sequence ladder.
• Relay symbolic language programming occurs in ladder block units.
A ladder block is the smallest unit of sequence program operation, with
the ladder beginning from the left bus and ending at the right bus.
Left bus a contact b contact Coil (output)

X0 Right bus
0 Y20
X1 X2 X3
Step No. 2 Y21

Y22 Ladder blocks

Y23 4
X4 X5
8 Y24
Y24

X0 to X5 : Indicate inputs.
Y20 to Y24 : Indicate outputs.

Fig.4.1 Ladder Block

(b) List mode

The list mode uses dedicated instructions instead of the contact symbols,
coil symbols, etc., used in the ladder mode.
Contact a, contact b and coil instructions are as follows:
• a contact ............LD, AND, OR
• b contact ............LDI, ANI, ORI
• coil......................OUT

(3) Program operation

In sequence program, the instructions are executed in order beginning from step
0 and ending at the END/FEND.
With ladder mode, the instructions in a ladder block are executed in order
beginning from left bus to the right bus. When one ladder block is completed, the
next downward ladder block will be executed.
[Ladder mode] [List mode]
Left to right 0 LD X0 1)
1) 2) 7) 8) 9) 1 AND X1 2)
X0 X1 X5 X6 X7 10) 2 LD X2 3)
0 Y10 3 AND X3 4)
3) 4) Executed in 4 ORB 5)
5)
Top to X2 X3 order beginning 5 OR X4 6)
bottom 6) from step 0 to 6 AND X5 7)
X4 the END 7 AND X6 8)
instruction. 8 AND X7 9)
11) 9 OUT Y10 10)
10 END
10 END 11)
Number 1) to 11) indicate the operating
order of the sequence program. Step No.

Fig.4.2 Sequence Program Operation

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4.1.1 Main routine program

(1) Definition of main routine program

(a) A main routine program begins from step 0 and ends at the END/FEND
instruction. 1
(b) In the main routine program, the instructions are executed from step 0 to the
END/FEND.
1) If only one program is executed, the program is operated from step 0
again after the END/FEND instruction is executed and the END
instruction is processed.
Step 0
Program execution
Main routine
program

Returns to step 0 when only one

program is being executed.
END/FEND END/FEND

END processing

2) If multiple programs are being executed, each of them will be operated

according to the designated execution conditions after the END/FEND
instruction is processed.

(2) Execution conditions for main routine programs 2

If multiple programs are being executed, the following five types of execution
conditions can be designated by the program in the PLC parameters according to
the application.
• Initial execution program : See Section 4.2.1.
• Scan execution type program : See Section 4.2.2.
• Low speed execution type program : See Section 4.2.3.
• Stand-by type program : See Section 4.2.4.
• Fixed scan execution type program : See Section 4.2.5.

REMARK
1: For details on the END/FEND instruction, refer to the "QCPU (Q
mode)/QnACPU Programming Manual (Common Instructions)".
2: If only one program is executed, it is processed under the "scan execution type
program" condition without designation by the program in the PLC parameters.

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4.1.2 Sub-routine programs

(1) Definition of sub-routine program

(a) A sub-routine program begins from a pointer (P ) and ends at a RET
instruction.
(b) A sub-routine program is executed only when called by a CALL instruction
(e.g. CALL(P), FCALL(P)) from the main routine program.
(c) Sub-routine program application
1) The overall step count can be reduced by using a sub-routine program
as a program which is executed several times in one scan.
2) The step count of a constantly executed program can be reduced by
using a sub-routine program as a program which is executed only
when a given condition is satisfied.

(2) Sub-routine program management

Sub-routine programs are created after the main routine program (after FEND
instruction), and the combination of main and sub-routine programs can be
managed as one program.
(a) When created after the main routine program
• A sub-routine program is created between the main routine program's
FEND and END instructions.
• Because there are no restrictions on the order in which sub-routine
programs are created, it is not necessary to set the pointers in ascending
order when creating multiple sub-routine programs.
• Either a local pointer or a common pointer can be used.
High Performance model QCPU
Program A
Program memory / Standard
ROM / Memory card
Main routine
program Write File of
program A
FEND

P0 Y10

RET
Sub-routine
program P8 Y11

RET

P1 Y12

RET

END

REMARK
: See Section 10.9 for details on local and common pointers.
See Section 10.8 for details on sub-routine program nesting.

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(b) Using the sub-routine program as a separate program

Sub-routine programs can also be managed as separate, separate
programs (stand-by type programs). (See Section 4.2.4 for details on
stand-by type programs).

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4.1.3 Interrupt programs

(1) Definition of interrupt program

(a) An interrupt program begins from the interrupt pointer (I ), and ends at the
IRET instruction. 1
(b) Interrupt programs are executed only when an interrupt factor occurs. 1

POINT
The interrupt pointers include a pointer designed for only the high speed interrupt
function (I49).
When you have used I49, do not use interrupt programs, which use the other
interrupt pointers I0 to I48, I50 to I255, and fixed scan execution type programs.
If any fixed scan execution type program or the like is run, the interrupt program
using I49 cannot be executed at the preset interrupt cycle intervals.
See Section 7.20 for details on the high speed interrupt function.

REMARK
1: See Section 10.10 for details on interrupt factors and interrupt pointers.

(2) Interrupt program management

Interrupt programs are created after the main routine program (after the FEND
instruction), and the combination of main and sub-routine programs can be
managed as one program.
(a) When created after the main routine program
• An interrupt program is created between the main routine program's
FEND and END instructions.
• Because there are no restrictions on the order in which interrupt programs
are created, it is not necessary to set the interrupt pointers in ascending
order when creating multiple interrupt programs.
High Performance model QCPU
Program A
Program memory/ Standard
ROM / Memory card
Main routine
program Write File of
program A
FEND

I0 Y10

IRET
Interrupt
program
I32 Y11

IRET

I28 Y12

IRET

END

Interrupt pointer

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(b) Using the interrupt program as a separate program

Interrupt programs can also be managed as separate, discrete programs
(stand-by type programs). (See Section 4.2.4 for details on stand-by type
programs).
However, the same interrupt program pointer number cannot be used more
than once in the program being executed by the CPU module.

(3) Executing interrupt programs

(a) In order to execute an interrupt program with the interrupt pointer I32 to I47,
IMASK and EI instructions are required to obtain permission for the
interruption. 1
1) If an interrupt factor occurs prior to an interruption permitted status, the
interrupt program corresponding to the factor will be executed when
the "interruption permitted" status is established.
2) If an interrupt factor occurs during a STOP/PAUSE, the interrupt
program corresponding to the factor will be executed when the
"interruption permitted" status is established following a return to the
RUN status.
Interrupt program example Interrupt program execution Program execution
EI Interrupt program for
"I0" activated
Main routine
Interrupt program
program
for "I29" activated

End of main FEND

I0
routine program
FEND
Interrupt
I0 program
"I0" interrupt
program I29
IRET
Interrupt
I29 program
"I29" interrupt
program END
IRET

END

Fig.4.3 Interrupt Program Execution

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(b) When an interrupt factor occurs, the interrupt program with the interrupt
pointer number corresponding to that factor is executed.
However, interrupt program execution varies according to the condition at
that time.
1) If two or more interrupts occur at the same time:
The interrupt programs are executed, starting with the one
corresponding to an interrupt pointer number (I ) of the highest
priority. 2
The remaining interrupt programs remain on stand-by until processing
of the higher priority interrupt program is completed.
If the same interrupt factor as that being executed occurs before the
interrupt program is processed, the interrupt factor is stored in the
memory and, after the interrupt program has been processed, the
same interrupt program is executed again.
2) When an instruction is being executed:
The interrupt program may be executed by interrupting the execution
of an instruction in the main routine program. When the same device is
used in both the main routine program and interrupt program, device
data may be separated.
To prevent the separation of the device data, the following measures
must be taken.
(a) Do not specify the device, to which data will be written in the
interrupt program, directly in the main routine program, but use
another device by shifting the data with a transfer instruction, etc.
(b) If inconvenience is caused when the instruction is interrupted in the
main routine program, execute it after disabling the interruption
with the DI instruction.
However, since the interrupt program will not interrupt during access to
the device of each argument of the instruction, data separation will not
occur on an argument basis.
3) Interruption during a network refresh:
If an interrupt factor occurs during a network refresh operation, the
network refresh operation is suspended, and the interrupt program is
executed.
This means that "assurance of blocks in cyclic data at each station"
cannot be secured by using a device designated as a destination of
link refresh operation on the MELSECNET/H Network System. 3

10ms 10ms 10ms 10ms

Interrupt factor

Interrupt program
execution

Network refresh
execution

Network refresh operation is suspended,

and the interrupt program is executed.

Fig.4.4 Interruption during Network Refresh Operation

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4) Interruption during END processing:

If an interrupt factor occurs during an END processing waiting period
when constant scan is performed, the interrupt program corresponding
to the factor will be executed.

REMARK
1: For details on the IMASK and EI instructions, refer to the "QCPU (Q
mode)/QnACPU Programming Manual (Common Instructions).
To execute interrupt programs I0 through I31 and I48 through I255, use an EI
instruction to enter the interrupt programs into an interrupt enabled status.
2: See Section 10.10 for details on the priority ranking of interrupt programs.
3: For assurance of station unit blocks in cyclic data, see the "MELECNET/H
Network System Reference Manual."

(c) When the interrupt program is executed in the default setting of the High
Performance model QCPU, the save and restoration of the index register
value and the save and restoration of the file register block No. are
performed at the time of switching between the main routine program and
interrupt program.
Refer to Section 10.6.2 for details..

(4) High speed execution of an interrupt program and overhead time

By default, High Performance model QCPU performs the following process when
executing an interrupt program:
• To hide and restore an index register. (See section 10.6.2)
• To hide and restore the file name of a file register in use.
The above-listed processes are not performed if "Execute at a High Speed" is selected at
the "PLC System" tab screen in the “(PLC) Parameter" dialog box.
This will make it possible to shorten the duration of overhead time required for
execution of an interrupt program.
OVERHEAD TIME ( s)
CPU TYPE
High speed execution is not selected High speed execution is selected
Q02CPU 380 230
Q02HCPU, Q06HCPU,
165 100
Q12HCPU, Q25HCPU

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(5) Program creation restrictions

(a) A device which is switched ON by a PLS instruction in an interrupt program
will remain ON until that interrupt program is executed again.
X0 X0
PLS M0 PLS M0

END 0 IO IRET END 0 END 0 IO IRET END 0

ON

X0 OFF
ON

M0 OFF
Switched OFF by PLS M0 instruction
Switched ON by PLS M0 instruction at X0 leading edge (OFF to ON)

(b) A DI status (interruption prohibited) is established during execution of an

interrupt program.
Do not execute EI/DI instructions in the interrupt program.
(c) Timers cannot be used in interrupt programs.
As timers are used at OUT T instructions to update present values and
switch contacts ON and OFF, the use of a timer in the interrupt program
would make a normal time count impossible.
(d) The following commands cannot be used in the interrupt program.
• COM
• ZCOM
(e) When the interrupt program/fixed scan execution type program is executed
at a measuring time such as the scan time or execution time, the values of
the interrupt program/fixed scan execution type program are added to the
measured time.
Thus, if the interrupt program/ fixed scan execution type program is
executed, the values stored in the following special registers and
GX Developer monitor values will be longer than when the interrupt
program/ fixed scan execution type program is not executed.
1) Special registers
• SD520, SD521: Current scan time
• SD522, SD523: Initial scan time
• SD524, SD525: Minimum scan time
• SD526, SD527: Maximum scan time
• SD528, SD529: Current scan time for low speed
• SD532, SD533: Minimum scan time for low speed
• SD534, SD535: Maximum scan time for low speed
• SD540, SD541: END processing time
• SD542, SD543: Constant scan wait time
• SD544, SD545: Cumulative execution time for low speed execution
type programs
• SD546, SD547: Execution time for low speed execution type
programs
• SD548, SD549: Scan program execution time
• SD551, SD552: Service interval time
2) GX Developer monitor values
• Execution time measurement
• Scan time measurement
• Constant scan

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4.2 Program Execute Type

Programs executed by High Performance model QCPU can be stored in the High
Performance model QCPU's program memory, standard ROM or memory card.
Programs can be stored in the standard ROM or memory card as a single program, but
also as multiple programs by splitting them into separate programs for each control
function.
This permits the programming procedure to be split up among several program
designers, who can design separate programs for each operation and can store them
in the standard ROM or memory card.

When multiple programs are executed by High Performance model QCPU, "program
name (file name)" and "execute type" settings of the programs must be designated.
Control by one program Control by separating
into multiple programs
Program A

Control contents A Control contents A

Program B
Store by separating
Control contents B Control contents B
the code according
to control contents.

Program n

Control contents n Control contents n

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(1) Execute Type Setting

(a) To execute several programs, specify a "Program name" and "Execute
type" of each program at the "Program" tab screen in the “(PLC)
Parameter" dialog box.
High Performance model QCPU will execute the selected programs in the
order of specified Execute Type setting.

1)
2)

3)

4)

5)

6)

1) Program name
This column is used to specify a program name (file name) of the
program to be executed by High Performance model QCPU.
2) Execute type
This column is used to specify the execute type of the program defined
in the "Program name" column. See Section (b).
3) Fixed scan
This column is used to specify time intervals at which to an execution
type program.
The Fixed Scan setting range is determined by the units of time
intervals as follows:
• In the unit "ms": 0.5 to 999.5
• In the unit "s": 1 to 60
4) In units
This column is used to specify the units (ms/s) of fixed scan intervals.

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5) File Use Setting

Sets whether to use the data (file register, initial device value,
comment, local device) set at the “PLC file” tab screen in the “(PLC)
Parameter” dialog box, per program. The data is set for each program.
By default, the option "Use PLC file setting" is selected. If the option
"Not used" is selected, the File Use setting is made as listed below in the
table.
Setting item Processing when the option "Not used" is selected
File register File registers can not be used in the program.
The device initial value is not set when the program file name and
Initial device value
the device initial value is the same.
Comment file used in a
Comments can not be used in the program.
command
Local devices are not hidden or restored at the time of program
Local device
conversion.

6) I/O Refresh Setting

High Performance model QCPU uses the I/O Refresh setting to
update output and input from an I/O module and an intelligent function
module.
The I/O Refresh Setting button is used to update the range of selected
programs. Make the I/O Refresh setting for a scan execution type
program if you want to receive an input (X) or produce an output (Y)
before executing the fixed scan execution type program.

(b) There are following 5 execute types:

1) Initial execution (Initial)
This program type is executed once only at power ON or when STOP-
RUN switching occurs. (See Section 4.2.1)
2) Scan execution (Scan)
This program type is executed once per scan, beginning from the scan
which follows execution of the initial execution program. (See Section 4.2.2)
3) Low speed execution (Low speed)
This program type is executed only when a constant scan setting is
made or when a time is set for execution of low speed execution type
programs.
• When a constant scan setting is made, the program is executed
during the surplus time of a scan execution type program.
• When a time for execution of low speed execution type programs is
set, the program is executed during this set time. (See Section 4.2.3.)
4) Stand-by (Wait)
This program is executed only when its execution is requested. (See
Section 4.2.4.)
5) Fixed scan execution (Fixed scan)
Program that is executed at time intervals specified in the "Fixed scan"
and "In units" columns of the Program Setting sheet of the PLC
Parameter dialog box. (See Section 4.2.5.)
(c) Scantimes of programs being executed (except the fixed scan execution
type program) can be checked on the monitor of the program list. (See
Section 7.11.1.)
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(2) Flow of each program of High Performance model QCPU

The flow of each program after power-ON or STOP of the PLC to RUN switching
of the CPU module is shown below.
Power ON/STOP to RUN

Initial execution Executed only once at power ON

or STOP to RUN.
type program

Run only when "constant scan" or

Low speed execution "low speed program execution time"
type program
has been set.

END processing Fxied scan execution Program run at specified cyclic

time intervals
type program

Scan execution Stand-by type Run only when execution request

is given.
type program program

POINT
Not all execute types need to be set for the High Performance model QCPU.
Use the items marked with " " as needed, such as the Initial execution, low speed
execution, stand-by and fixed scan execution type programs.

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(3) Changing the Execute Type

(a) The Execute Type setting made at the "Program" tab screen in the “(PLC)
Parameter" dialog box can be changed at any time while a sequence
program is executed. To change the execute type of a program, use a
PSCAN, PLOW, PSTOP or POFF instruction.
PLOW

PSCAN PSCAN
Initial execution Scan execution Low speed execution
type program type program type program

PSTOP PSTOP PSTOP

POFF POFF POFF
PSCAN PLOW
PLOW PSCAN
1
PSTOP
Stand-by type POFF Fixed scan execution
program type program

(b) The following table shows the timing of changing the execute type of a
program by using a PSCAN, PLOW, PSTOP or POFF instruction.

Executed instruction
PSCAN PSTOP POFF PLOW
Execute type before change
No change - remains Output is turned OFF
Scan execution type
scan execution type. in the next scan.
Becomes stand-by
Becomes stand-by
type. Becomes low speed
Initial execution type type from the next
Becomes scan type.
scan after that.
execution type.
No change - remains
Stand-by type No processing.
stand-by type.
Low speed execution Low speed execution
type execution is Low speed execution type execution is
stopped: becomes type execution is stopped, and output is No change - remains
Low speed execution type scan executions from stopped: becomes turned OFF in the low speed
the next scan. stand-by type from the next scan. Becomes executions.
(Execution from step next scan. stand-by type from the
0.) next scan after that.
Output is turned OFF
in the next scan.
Becomes scan Becomes stand-by Becomes low speed
Fixed scan execution type Becomes stand-by
execution type. type. type.
type from the next
scan after that.

POINT
1: If the fixed scan execution type program is changed to another execution type,
you cannot return to the fixed scan execution type.

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4.2.1 Initial execution type program

(1) Definition of initial execution type program

(a) An initial execution type program is executed once only at power ON, or
when STOP to RUN switching occurs.
(b) This program's execute type is designated as "initial" in the program of the
PLC parameters.
(c) In the same manner as the initial processing for the intelligent function
module, the initial execution program is executed only once, and is not
required in subsequent scans.
An instruction that contains a complete device cannot be used for an initial
execution type program because the complete device needs several scans
to complete the execution.
Control with one program Using initial execution type program
Program A
Initial execution
Initial program
type program
Division into initial
execution type program
Program B and scan execution type
Program to execute Scan execution
at every scan type program

(2) Using multiple initial execution type programs

When multiple initial execution type programs are used, they are executed one
by one in ascending order of the program in the PLC parameters.

(3) END processing

END processing is performed when all initial execution type programs are
completed, and the "scan execution type program" is then executed from the
next scan.
Power supply ON/STOP to RUN

Initial execution
type program A

Initial execution Executed by program

1 Scan
type program B setting order.

Initial execution
type program n

END processing

Scan execution
type program

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(4) Initial scan time

(a) This is the execution time period for initial execution type programs.
If multiple initial execution type programs are executed, it is the execution
time period in which all those programs are executed.
When an interrupt program/fixed scan execution type program is executed
while an initial execution type program is running, the execution time of the
interrupt program/fixed scan execution type program will be added to the
initial execution type program.

(b) The High Performance model QCPU measures the initial scan time and
stores the result in special registers (SD522, SD523). 1
The initial scan time can be checked by monitoring the SD522 and SD523
special registers.
SD522 SD523

Stores less than 1 ms initial scan time (unit s)

Stores the initial scan time in 1 ms units.

If the SD522 value is 3, and the SD523 value is 400, the initial scan time is
3.4 ms.
POINT
1: The accuracy of the initial scan time stored at the special registers is ± 0.1 ms.
The initial scan time count will continue even if a watchdog time reset
instruction (WDT) is executed at the sequence program.

(5) Initial execution monitor time

(a) The execution period of the initial execution type program can be monitored
by this timer. The default value is not set.
When monitoring the execution time of the initial execution type program,
designate the initial execution monitor time within the range of 10 to 2000
ms range at the "PLC RAS" tab screen in the “(PLC) Parameter" dialog box.
(Setting unit: 10 ms)

(b) The low speed execution type program is executed after the execution of
the initial execution type program is completed.
To use the low speed execution type program, specify the time that is
longer than the sum of the initial scan time and the execution time of the
low speed execution type program.

(c) When the initial scan time exceeds the set initial execution monitor time,
"WDT ERROR (error code: 5000)" occurs, and High Performance model
QCPU operation is stopped.
POINT
When the initial execution monitor time is designated, there will be a 10 ms error in
the count value.
Therefore, a monitor time setting (t) of 10 ms will result in a "WDT ERROR" when
the initial scan time is in the range 10 ms < t < 20 ms.

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4.2.2 Scan execution type program

(1) Definition of scan execution type program

(a) Scan execution type programs are executed once per scan, beginning from
the scan which follows execution of the initial execution type program.
(b) Set the execute type to "scan" at the "Program" tab screen in the “(PLC)
Parameter" dialog box.

(2) Executing multiple scan execution type programs

When multiple scan execution type programs are used, they are executed one by
one in ascending order set at the "Program" tab screen in the “(PLC) Parameter"
dialog box.

(3) END processing

The first scan execution type program is executed again, when all scan execution
type programs are executed and the END processing is completed.
The END processing (network refresh) can be performed for each program while
several scan execution type programs are executed. To do this, include a COM
instruction at the end of each scan execution type program.
STOP to RUN
Power ON to RUN
First scan Second scan Third scan Forth scan

END processing

Initial execution type program

0 END 0 END 0 END

Scan execution type program A

0 END 0 END 0
Scan execution type program B

0 END 0 END
Scan execution type program C

Scan time

(4) Constant scan

Constant scan is a function that repeats the execution of a main routing program
at give intervals.
When constant scan is set, the scan execution program is executed at intervals
of the preset constant scan time.
Refer to Section 7.2 for details of constant scan.

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(5) Scan time

(a) The "scan time" is a total of following the execution time of the scan
execution type program and END processing.
If multiple scan execution type programs are used, the "scan time" is the
total time required to execute all the programs.
When an interrupt program/fixed scan execution type program is executed,
the value added to the interrupt program/fixed scan execution type
program's execution time will become the scan time.
(b) The scan time current value, minimum value, and maximum value are
measured at the High Performance model QCPU, and the results are
stored in special registers (SD520, SD521, and SD524 to SD527). 1
Therefore, the initial scan time can be checked by monitoring the SD520,
SD521, and SD524 to SD527 special registers.

Current value SD520 SD521

Minimum value SD524 SD525
Maximum value SD526 SD527

Stores less than 1 ms initial scan time (unit s)

Stores the initial scan time in 1 ms units.

If the SD520 value is 3, and the SD521 value is 400, the initial scan time is 3.4
ms.

POINT
1: The accuracy of the scan time stored at the special registers is ± 0.1 ms. The
scan time count will continue even if a watch dog timer reset instruction (WDT)
is executed at the sequence program.

(6) WDT (Watch dog timer)

This is the timer which monitors the scan time, and its default setting is 200 ms.
This WDT setting can be designated within the range of 10 to 2000 ms range at
the "PLC RAS" tab screen in the “(PLC) Parameter" dialog box.
(Setting units: 10 ms)
When using the low speed execution type program, set the WDT greater than the
scan time plus the execution time of the low speed execution type program.
If the scan time (execution time for scan execution type program + low speed
execution type program) exceeds the WDT setting value, a "WDT ERROR (error
code: 5000)" occurs, and High Performance model QCPU operation is stopped.

POINT
The WDT measurement error is 10 ms.
Therefore, a WDT setting (t) of 10 ms will result in a "WDT ERROR" if the scan
time is in the following range: 10 ms < t < 20 ms.

REMARK
Use the GX Developer's Program Monitor List to check the execution time of a
program being executed. See Section 7.11.1 for details on the GX Developer's
Program Monitor List.

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4.2.3 Low speed execution type program

(1) Definition of low speed execution type program

(a) Low speed execution type programs are executed only during "constant
scanning surplus time" or during the period designated for "low speed
program execution time".
1) For a constant scan time with enhanced control accuracy, designate a
constant scan time setting at the "PLC RAS" tab screen in the “(PLC)
Parameter".
(Setting range: 0.5 to 2000 ms, setting unit: 0.5 ms)
2) To secure execution time for low speed execution type programs at
each scan, designate a low speed program execution time in the "PLC
RAS" tab screen the (PLC) "Parameter".
(Setting range: 1 to 2000 ms, setting unit: 1 ms)
3) In order to execute a low speed execution type program, set either the
constant scan time or low speed program execution time.
(b) Set the execute type of the low speed program to "low speed" in the
program of the PLC parameters.
(c) The low speed execution type program is used for programs which do not
require execution in each scan, for example programs for printer output.

(2) Executing multiple low speed execution type programs

When multiple low speed execution type programs are used, they are executed
one by one in ascending number order of the program in the PLC parameters.

(3) Execution time of the Low speed execution type program to be

executed per scan
(a) If all the low speed execution type program operation is completed within
one scan and there is surplus time, the processing executed after that
depends on the ON/OFF status of special register SM330 and the
execution condition for low speed execution type programs.
1) Asynchronous method (SM330 = OFF)
Method in which low speed execution type program operation is
continued in the surplus time.
2) Synchronous method (SM330 = ON)
Method in which even if there is surplus time, low speed execution
type program operation is not continued, and operation starts again
from the next scan.
Operation method for low SM330 Execution condition for low speed execution type programs
speed execution type setting When constant scan time When low speed program
programs status is set execution time is set
The low speed execution
The low speed execution type
Asynchronous method OFF type program is re-
program is re-executed 2.
executed 1.
Constant scan waiting Scan execution type program
Synchronous method ON
time is generated 3. operation is started 4.

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1 If a constant scan time has been designated, the low speed execution
type program will be executed repeatedly during the constant scan's
surplus time.
Therefore, the low speed execution type program's execution time
varies from scan to scan.
As the low speed execution type program will not be executed at all if
the constant scan's surplus time is 0.5 ms or less, a constant scan time
setting should be designated which provides a surplus time of more
than 0.5 ms.
2 If a low speed program execution time has been designated, the low
speed execution type program will be executed repeatedly in
accordance with that time setting.
Therefore, the scan time will vary from scan to scan.
3 If a constant scan time has been designated, the surplus time after
completion of low speed END processing is waiting time, and execution
of a scan execution type program starts when the constant scan time
has elapsed.
This means that the scan time is constant in each scan.
However, if the surplus time after the constant scan is less than 0.5 ms,
low speed execution type programs cannot be executed. If using a low
speed execution type program, set the constant scan time so that the
surplus time is 0.5 ms or longer.
4 If a "low speed program execution time" has been designated, scan
execution type program operation is started ignoring the surplus time
after completion of low speed END processing.
This means that the scan time differs in each scan.

(b) If a low speed execution type program cannot be processed within constant
scan surplus time or within the low speed program execution time, program
execution is temporarily stopped and the remainder of the program is
executed in the next scan.

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1 : Asynchronous method
(1) Constant scan time setting
The low speed execution type program is operated under the following conditions as shown
below.
• Constant scan time : 8ms
• Total scan execution type program time : 4ms to 5ms
• Execution time of low speed execution type program A : 1ms
• Execution time of low speed execution type program B : 3ms
• END processing/low speed END processing : 0ms (0 ms is used to simplify the illustration)
END END END END
processing processing processing processing

0 8 16 24 (ms)

4ms 4.5ms 4ms 4ms

Scan execution type program

1ms 1ms 1ms 1ms

Low speed execution type program A

2.5ms 1.5ms 1.5ms 1ms 2ms 0.5ms

Low speed execution type program B
0.5ms
0.5ms 0.5ms 0.5ms
Constant scan wait time
Low speed Low speed Low speed
scan time scan time scan time
(13ms) (8.5ms) (8.5ms)

Low speed Low speed Low speed

END processing END processing END processing
execution execution execution
(2) Low speed program execution time setting
The low speed execution type program is operated under the following conditions as shown
below.
• Low speed program execution time : 3ms
• Total scan execution type program time : 4ms to 5ms
• Execution time of low speed execution type program A : 1ms
• Execution time of low speed execution type program B : 3ms
• END processing/low speed END processing : 0ms (0 ms is used to simplify the illustration)
END END END END END
processing processing processing processing processing

0 4 11.5 18.5 25.5 33.5 (ms)

4ms 4.5ms 4ms 4ms 5ms

Scan execution type program

1ms 1ms 1ms 1ms

Low speed execution type program A

2ms 1ms 1ms 2ms 3ms

Low speed execution type program B
Low speed scan time Low speed scan time Low speed scan time
(12.5ms) (8ms) (8ms)

Low speed END Low speed END Low speed END

processing execution processing execution processing execution

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2 : Synchronous method
(1) Constant scan time setting
The low speed execution type program is operated under the following conditions as shown
below.
• Constant scan time : 8ms
• Total scan execution type program time : 4ms to 5ms
• Execution time of low speed execution type program A : 1ms
• Execution time of low speed execution type program B : 3ms
• END processing/low speed END processing : 0ms (0 ms is used to simplify the illustration)
END END END END
processing processing processing processing

0 8 16 24 32 (ms)

4ms 4.5ms 4ms 4ms 5ms

Scan execution type program

1ms 1ms
Low speed execution type program A

2.5ms 0.5ms 2.5ms 0.5ms

Low speed execution type program B

0.5ms 3ms 0.5ms 3.5ms

Constant scan wait time
Low speed scan time Low speed scan time
(13ms) (15.5ms)

Low speed END Low speed END

processing execution processing execution
(2) Low speed program execution time setting
The low speed execution type program is operated under the following conditions as shown
below.
• Low speed program execution time : 3ms
• Total scan execution type program time : 4ms to 5ms
• Execution time of low speed execution type program A : 1ms
• Execution time of low speed execution type program B : 3ms
• END processing : 0ms (0 ms is used to simplify the illustration)
END END END END END
processing processing processing processing processing

0 4 11.5 16.5 23.5 29.5 (ms)

4ms 4.5ms 4ms 4ms 5ms

Scan execution type program

1ms 1ms 1ms

Low speed execution type program A

2ms 1ms 2ms 1ms 2ms

Low speed execution type program B
Low speed scan time Low speed scan time
(12.5ms) (12ms)

Low speed END Low speed END

processing execution processing execution

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(4) Precautions for creating Low speed execution type programs

(a) See Section 10.6.1 for details on index register processing when switching
from a scan execution type program to a low speed execution type
program.
(b) See Section 10.6.2 for details on index register processing when an
interrupt program/a fixed scan execution type program is executed during
execution of low speed execution type program.
(c) The low speed program execution time should be set so that sum of the
[scan time] + [low speed program execution time] sum is less than the WDT
setting value.
(d) The COM instruction can not be used in low speed execution type
programs.
(e) Low speed execution type programs can also be executed with scans that
execute the initial execution type programs.
Establish an interlock with SM402 and SM403 for the circuit that validates
the low speed execution type program's operation after the scan execution
type program has been executed.
(f) When the "constant scan time" and "low speed program execution time"
have been set, "PRO. TIME OVER (error code: 5010)" will occur if (surplus
time of constant scan) < (low speed program execution time).

(5) Low speed END processing

The low speed END processing is performed when all the low speed execution
type programs are executed.
The following processing is performed for the low speed END processing.
• Low speed program special relay/special register setting
• Low speed execution type program write during RUN
• Low speed scan time measurement
• Low speed execution type program watch dog timer reset
When the low speed END processing is completed, the low speed execution type
program is executed from the beginning again.
POINT
(1) During execution of low speed execution type programs, the constant scan
time may deviate by the amount of "the maximum instruction processing time +
low speed END processing time".

(6) Low speed scan time

(a) The low speed scan time is the total time required for low speed execution
type program execution and low speed END processing.
If multiple low speed execution type programs are executed, the low speed
scan time is the total time required to execute all the programs, plus the low
speed END processing time.
When an interrupt program/fixed scan execution type program is executed,
the value added with the interrupt program/fixed scan execution type
program's execution time will become the low speed scan time.

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(b) The low speed scan time is measured by the High Performance model
QCPU, and the result is stored in special registers (SD528 to SD535). 1
The low speed scan time can therefore be checked by monitoring the
SD528 to SD535 special registers.

Current value SD528 SD529

Minimum value SD532 SD533
Maximum value SD534 SD535

Stores less than 1 ms low-speed scan time (unit s)

Stores the low-speed scan time in 1 ms units.

If the SD528 value is 50, and the SD529 value is 400, the low speed scan
time is 50.4 ms.
POINT
1: The accuracy of the scan time stored at the special registers is ± 0.1 ms.
The scan time count will continue even if a watchdog time reset instruction
(WDT) is executed in the sequence program.

(7) Low speed execution monitor time

The execution time of the low speed execution type program can be monitored
by this timer. The default value is not set.
When monitoring the execution time of the low speed execution type program,
designate the low speed execution monitor time in a 10 to 2000 ms range at the
"PLC RAS" tab screen in the “(PLC) Parameter" dialog box. (Setting unit: 10 ms)
If the execution time of the low speed execution type program exceeds this timer
setting, a "PRG TIME OVER" error occurs.

POINT
The low speed execution time measurement occurs at low speed END processing.
Therefore a “PRG TIME OVER” error will occur if the low speed execution monitor
time (t) is designated as 100 ms, and the measured low speed scan time at low
speed END processing exceeds 100 ms.

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4.2.4 Stand-by type program

(1) Definition of stand-by type program

(a) Stand-by type programs are executed only when requested.
(b) Stand-by type programs are used for the following applications.
1) Placing programs in the library
Sub-routine and interrupt programs are converted to stand-by type
programs which are managed separately from the main program.
2) Changing the program setup
Main routing programs registered as stand-by type programs can
execute the programs required for control by converting them to scan
execution type programs.
They will be reconverted to stand-type programs after they completes
the program execution.

(2) Stand-by type program applications

(a) Placing programs in the library
1) This application is used to manage sub-routine and interrupt programs
separately from the main routine program.
Multiple sub-routine and interrupt programs can be created for a single
stand-by type program.
Scan execution type program Scan execution type program

Main routine Main routine

program program

P100 Sub-routine
program Stand-by type program

I0 Interrupt P100 Sub-routine

program program

I0 Interrupt
program

2) When stand-by type program execution is completed, the program,

which was active before the stand-by type program was executed, is
executed.
A stand-by type program's sub-routine and interrupt programs are
executed as shown below.
CALL P100 command execution Interrupt error factor occurred.
END processing END processing END processing

Scan execution type program

P100 RET
Sub-routine program

I0 IRET
Interrupt program

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(b) Changing the program setup

1) Create a program compatible with all programs and use it only to
execute necessary programs.
Programs designated as stand-by type programs in the “(PLC)
Parameter" dialog box can be converted to scan execution type
programs and executed in a sequence program.
Change the execution type in the High Performance model QCPU by
using PSCAN, PLOW, PSTOP, and POFF instructions. (See Section
4.2 3).)

(c) The following methods can be used to convert a program which is to be

executed.
1) Selecting the program to be executed from a single management
program:
• Convert a stand-by type program that meets the designated
conditions to a scan execution type program by using a constantly
executed scan execution type program as the management
program. Then execute the converted program.
Scan execution type programs which are not required can be
converted to stand-by type programs.
• Execute types of "ABC","DEF","GHI" and "JKL" stand-by type
programs are converted as shown below.
Scan execution type program
(Control program)
"PSCAN" is an instruction
M0
that switches the specified
PSCAN "ABC"
"ABC" program to a scan
When M0 is on, switch
M1 execution type program.
the "ABC" program from a
stand-by type program to a PSTOP "ABC" "PSTOP" is an instruction
scan execution type program. that switches the specified
"ABC" program to a stand-
PSCAN "DEF"
When M1 is on, switch by type program.
the "ABC" program from
a scan execution type PSTOP "DEF"
program to a stand-by
type program.

Stand-by Stand-by Stand-by Stand-by

type type type type
program program program program
: ABC : DEF : GHI : JKL

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2) When changing the execute type of the scan execution type programs
and stand-by type programs by the scan execution type programs
having the condition for switching the execution type.
• The scan execution type program being executed changes the next
program to be executed from a stand-by type program to a scan
execution type program.
• If the condition realizes when "ABC" and "GHI" programs have been
set to scan execution type, and "DEF" program to stand-by type, the
execute types of "ABC" and "DEF" programs are switched as shown
below.

[Before execution of PSCAN and PSTOP instructions]

Scan execution type program : ABC
• "PSCAN" is an instruction that switches
M0 the specified "DEF" program to a scan
PSCAN "DEF" type program.
• "PSTOP" is an instruction that switches
PSTOP "ABC"
the specified "ABC" program to a stand-
by type program.

Stand-by type program: DEF Scan execution type program : GHI

PSCAN "GHI" PSCAN "ABC"

PSTOP "DEF" PSTOP "GHI"

When M0 is on

[After execution of PSCAN and PSTOP instructions]

Stand-by type program: ABC

M0
PSCAN "DEF"

PSTOP "ABC"

Scan execution type program: DEF Scan execution type program : GHI

PSCAN "GHI" PSCAN "ABC"

PSTOP "DEF" PSTOP "GHI"

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(d) The execute type of program is switched at END processing. The program
execute type does not change while the program is being executed.
If different execute type is specified for a same program in a same scan,
the last-specified execute type becomes effective.
END processing END processing END processing
Execution program "GHI" "ABC" "GHI" "GHI" "DEF" "GHI"
name

PSTOP "ABC" execution Switches "DEF" to the scan

PSCAN "DEF" execution execution type and "ABC" to
the stand-by type program,
respectively.

REMARK
1) : The "GHI" and "DEF" programs are executed in the order as set at the
"Program" tab screen in the “(PLC) Parameter" dialog box.

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(3) Precautions for creating stand-by type programs

(a) Because current value is updated and contact ON/OFF is switched when
the OUT T instruction is executed, timers cannot be used in stand-by
type programs.

(b) Gathering sub-routine programs in a single program

1) Create the sub-routine programs in order beginning from step 0 of the
stand-by type program. An END instruction is required at the end of
the sub-routine program.
2) Because there are no restrictions on the order of creating sub-routine
programs, the pointer numbers need not be assigned in ascending
order when creating multiple sub-routine programs.
3) Use common pointers.
Sub-routine programs with common pointers can be called from all
programs executed by High Performance model QCPU.
(If local pointers are used, the stand-by type program's sub-routine
programs will not be executed.)
Program A High Performance model QCPU
Program memory / Standard
Main routine ROM / Memory card
program Write
Program A

Common pointer
Program B (Stand-by type program)
Program B

P500 Y10 Write

RET

P508 Y11

RET

P501 Y12

RET

END

Use a common pointer.

(This does not have to be created in order.)

4) See section 10.13.1 for execution of a sub-routine program that

contains local devices.

REMARK
: See Section 10.9 for details on common pointers and local pointers.

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(c) Gathering interrupt programs in a single program

1) Create the interrupt programs in order beginning from step 0 of the
stand-by type program.
An END instruction is required at the end of the interrupt program.
2) Because there are no restrictions on the order of creating interrupt
programs, the pointer numbers need not be assigned in ascending
order when creating multiple interrupt programs.
Program A High Performance model QCPU
Program memory / Standard
ROM / Memory card
Main routine
program
Write
Program A

Program B (Stand-by type program)

Program B

I0 Y10 Write

IRET
Interrupt
program
I32 Y11

IRET

I28 Y12

IRET

END

Interrupt pointer
(This does not have to be created in order.)

REMARK
: See Section 10.10 for details on interrupt pointers.

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4.2.5 Fixed scan execution type program

(1) Definition of fixed scan execution type program

(a) This program is executed at specified intervals.
Without describing an interrupt point and IRET instruction, a fixed scan
execution can be performed for each file.
(b) The type of execution is set to "Fixed Scan" at the "Program" tab screen in
the (PLC) parameter dialog box.

(2) Execution of fixed scan execution type program

(a) Fixed scan execution type programs are executed at specified cyclic time
intervals.
When multiple fixed scan execution type programs have reached there
simultaneously, they are executed in the ascending order set at the
"Program" tab screen in the “(PLC) Parameter" dialog box.
(b) Set the periodic interval at the "Program" setting tab screen in “(PLC)
Parameter" dialog box. The setting range varies with the set unit.
• When the unit is "ms": 0.5 to 999.5ms
• When the unit is "s": 1 to 60s
(c) When the specified times of fixed scan execution type programs and
interrupt programs (I28 to I31) have come simultaneously, the priority of
execution is given to the interrupt programs.
(d) Execution during network refreshing
When the execution conditions of fixed scan execution type programs are
established during the network refreshing, the network refresh is
suspended, and interrupt programs are executed.
Therefore, even if the "block assurance of cyclic data for each station" is
made in the MELSECNET/H network system, the above operation will not
be assured when a device set to be refreshed is used in the interrupt
programs. 1

10ms 10ms 10ms 10ms

Interrupt factor

Fixed scan
execution type
program execution
Link refresh
execution

Link refresh operation is suspended,

and the interrupt program is executed.

Fig. 4.5 Execution of Fixed Scan Execution Type Programs during Network Refreshing

REMARK
1: Refer to the following manual on the block assurace of cyclic data for each
station.
• Q-Corresponding MELSECNET/H Network System Reference Manual

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(e) Execution during END processing:

When the execution condition of fixed scan execution type programs are
established during the wait time of END instruction while the constant scan
is executed, the fixed scan execution type programs are executed.
(f) Perform the processing of the index register when the program is switched
from the scan execution type program to the fixed scan execution type
program by seeing Section 10.6.2.

(3) Setting of fixed scan execution type program for high speed
execution and overhead time
When fixed scan execution type programs are executed, the processing below is
performed.
• Save and return of index resister
• Save and return of file name of file resister in use
If "High Speed Execution" is selected from the interrupt program/fixed scan
execution type program at the "PLC system" tab screen in the “(PLC) Parameter"
dialog box, the processing above will not be performed.
As a result, the overhead time for the fixed scan execution type programs can be
reduced.
Overhead time
CPU type High speed execution is not High speed execution is
selected selected
Q02CPU 380 s 230 s
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 165 s 100 s

(4) Cautions on programming

(a) If a device is turned ON in a fixed scan execution type program by a PLS
instruction, it is kept ON until the same type of the fixed scan execution type
program is executed again.
Fixed scan execution X0 X0
type program execution PLS M0 PLS M0

END 0 0 END END 0 END 0 0 END END 0

ON

X0 OFF
ON
OFF
M0
Switched OFF by PLS M0 instruction
Switched ON by PLS M0 instruction at X0 leading edge (OFF to ON)

(b) During the execution of a fixed scan execution type program, interruption is
prohibited (DI). Therefore, do not execute EI/DI instructions during the
programming of the fixed scan execution type program.
(c) During the programming of a fixed scan execution type program, a timer
cannot be used.
Because the timer updates the current values and turns ON/OFF at the
time of execution of OUT T instruction, if the timer is used during the
programming in the fixed scan execution type program, the current values
will be updated only when the fixed scan execution type program is
executed, and normal measurement will be disabled.

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(d) The following commands cannot be used in the fixed scan execution type
program.
• COM
• ZCOM
(e) When a fixed scan execution type program is executed, an interruption must
be allowed by an EI instruction in the initial execution type program/scan
execution type program.
(f) When the interrupt program/fixed scan execution type program is executed
at a measuring time such as the scan time or execution time, the values of
the interrupt program/fix scan execution type program are added to the
measured time.
Thus, if the interrupt program/ fixed scan execution type program is
executed, the values stored in the following special registers and
GX Developer monitor values will become longer than when the interrupt
program/ fixed scan execution type program is not executed.
1) Special registers
• SD520, SD521: Current scan time
• SD522, SD523: Initial scan time
• SD524, SD525: Minimum scan time
• SD526, SD527: Maximum scan time
• SD528, SD529: Current scan time for low speed
• SD532, SD533: Minimum scan time for low speed
• SD534, SD535: Maximum scan time for low speed
• SD540, SD541: END processing time
• SD542, SD543: Constant scan wait time
• SD544, SD545: Cumulative execution time for low speed execution
type programs
• SD546, SD547: Low speed execution time
• SD548, SD549: Scan program execution time
• SD551, SD552: Service interval time
2) GX Developer monitor values
• Execution time measurement
• Scan time measurement
• Constant scan

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4.3 Operation Processing

4.3.1 Initial processing

This is a preprocessing for sequence operation execution, and is performed only once
as shown in the table below.
When the initial processing is completed, the High Performance model QCPU goes in
the RUN/STOP switch setting status. (See Section 4.4.)

High Performance model QCPU status

Initial processing item When the power When reset is When STOP
is turned on. executed. to RUN 1
The I/O module initialization
Boot from the standard ROM/memory card
PLC parameter check
Multiple CPU system parameter value equality
check
Device initialization of the range not latched
(bit device: OFF, word device: 0)
Automatic allocation of the I/O number of
installed modules
Start of the MELSECNET/H network information
setting and network communication
Switch setting of intelligent function module
CC-Link data setting
Ethernet data setting
Setting of device initialization values
: executed, : not executed

REMARK
1: Indicates that the parameter or program was changed in a STOP status and the
CPU was placed in a RUN status without being reset.
(Move the RUN/STOP switch from STOP to RUN (RUN LED flickers) to STOP
to RUN.)
Fully note in the above switch operation that normal operation may not be
performed since the previous data may not be maintained in the case of the
pulse conversion instruction (PLS, _P) depending on the program change.

4.3.2 I/O refresh (I/O module refresh processing)

In I/O refresh, an input (X) is received from the input module/intelligent function
module, and output (Y) of the High Performance model QCPU is sent to the output
module/intelligent function module.

The I/O refresh is executed before the sequence program operation starts.
During constant scan execution, the I/O refresh is executed after the constant scan
delay time has elapsed.
(The I/O refresh is executed at each constant scan cycle.)

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4.3.3 Automatic refresh of the intelligent function module

When automatic refresh of intelligent function modules is set, communication with the
intelligent function modules of the designated data is performed.
Refer to the manual of the intelligent function modules, for details on the automatic
refresh setting of intelligent function modules.

4.3.4 END processing

This is a post-processing to return the sequence program execution to step 0 after

completing the whole sequence program operation processing once.

(a) When a refresh request is made from the network module, refresh
processing is performed.

(b) When the trace point of the sampling trace is set at every scan (after END
instruction execution), the set device status is stored in the sampling trace
area.

POINT
(1) When the constant scan function (See Section 7.2) is set, END processing time
result is stored until when END processing is completed or the next scan starts.
(2) When executing the low speed execution type program, the low speed END
processing starts after the all low speed execution type programs are
completed.
See Section 4.2.3 for details on the low speed execution type program and low
speed END processing.

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4.4 RUN, STOP, PAUSE Operation Processing

The High Performance model QCPU has three types of operation status; RUN, STOP
and PAUSE status.
The High Performance model QCPU operation processing is explained below:
(1) RUN Status Operation Processing
(a) RUN status indicate that the sequence program operation is performed from
step 0 to END (FEND) instruction to step 0 repeatedly.
(b) When entering the RUN status, the output status saved at STOP status is
output by setting "Previous status" as "Output mode at STOP to RUN" at
the "PLC system" tab screen in the “(PLC) Parameter" dialog box.
(c) It usually takes 1 to 3 seconds to prepare for staring the sequence program
operation since STOP status is switched to RUN status, though it might be
longer depending on the system.
(2) STOP Status Operation Processing
(a) STOP status indicates that the sequence programs are stopped by
RUN/STOP switch or remote STOP function. (See 7.6.1 for details on
remote STOP function.)
High Performance model QCPU might enter STOP status when a stopping
error occurs.
(b) When entering the STOP status, save the output status and turn off all
output.
The device memory of other than the output (Y) is retained.
(3) PAUSE Status Operation Processing
(a) The PAUSE status indicates that the sequence program operations are
paused by remote PAUSE function while maintaining the output and device
memory status. (See Section 7.6.2 for details on remote PAUSE function.)
(4) High Performance model QCPU Operation Processing with
RUN/STOP Status
Operation Processing of
High Performance Sequence
Device memory
mdel QCPU program
External output
operation
RUN/STOP processing
status M, L, S, T, C, D Y

OS saves the status

Executes up to OS saves the status
Maintains the status immediately before
the END immediately before
RUN to STOP immediately before the the STOP status
instruction and the STOP status and
STOP status. and all points turn
stops. all points turn off.
off.
Starts executing the
operation from the status
Determined by the Determined by the
immediately before the
"STOP RUN-time "STOP RUN-time
STOP status. When the
STOP to RUN Starts at step 0. output mode" in the output mode" in the
device initial value function is
PLC parameter PLC parameter
designated, however, the
dialog box. dialog box.
device initial value is set or
the local devices are cleared.

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POINT
The High Performance model QCPU performs the following in any of RUN, STOP,
and PAUSE status:
• I/O module refresh processing
• Data communication with GX Developer and serial communication module
• Refresh process of MELSECNET/H and CC-Link
For this reason, I/O monitor and test operation using GX Developer, reading/writing
from the serial communication, communication with another station using
MELSECNET/H, and communication with a remote station over the CC-Link can
be made even in the STOP or PAUSE status.

4.5 Operation Processing during Momentary Power Failure

The High Performance model QCPU detects a momentary power failure when the
input power voltage supplied to the power supply module is lower than the regulated
ranges.
When the High Performance model QCPU detects a momentary power failure, the
following operation processing is performed:

(1) When momentary power failure occurs for a period shorter than the
permitted power failure time
(a) The output is maintained when the momentary power failure occurs, and file
name of the file accessed and error history are logged. Then the system
interrupts the operation processing. (The timer clock continues.)
(b) When there is an SFC continue specification, a system saving processing is
performed.
(c) When a momentary power failure ends, the operation processing is
resumed.
(d) Even if the operation is interrupted due to momentary power failure, the
watch dog timer (WDT) measurement continues. For example, if the GX
Developer PLC parameter mode WDT setting is set at 200 ms, when a
momentary failure of 15 ms occurs at scan time 190 ms, the watch dog
timer error is set.

Momentary power failure occurrence Power recovery

END 0 END END

QCPU interrupts the operation.

Fig.4.6 Operation Processing When Momentary Power Failure Occurs

(2) When a power failure occurs for a period longer than the permitted
power failure time
The High Performance model QCPU starts initially. (PLC power is turned on.)
The same operation processing as that after the following operation occurs.
• Power ON
• Resetting using RESET/L. CLR switch
• Remote setting using GX Developer

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4.6 Data Clear Processing

(1) Data clear

The High Performance model QCPU clears all data except for the following,
when a reset operation is performed with RESET/L.CLR switch, or power ON to
OFF to ON.
(a) Program memory data (except for when "clear program memory" is set at
boot specification.)
(b) Data in the memory card
(c) Device data with latch specification (latch clear valid)
(d) Device data with latch specification (latch clear invalid)
(e) File register data
(f) Failure history data (when special register SD storage)

Data in (c) is cleared by operating "latch clear" with the RESET/L.CLR switch, or
operating "remote latch clear" from GX Developer.
See Section 7.6.4 for details on the remote latch clear.

(2) Device latch specification

(a) Specify the device latch (latch range setting) for each device at the "Device"
tab screen in the “(PLC) Parameter" dialog box.
There are two types of latch range settings:
1) Valid latch clear key
Sets the latch range that can be cleared by operating "latch clear" with
the RESET/L.CLR switch and remote latch clear.
2) Invalid latch clear key
Sets the latch range that can not be cleared even by operating "latch
clear" with the RESET/L.CLR switch or operating "remote latch clear"
from GX Developer.

(b) The devices in which RESET/L.CLR switch is set to invalid can only be
cleared by an instruction or GX Developer.
1) Instruction to clear method
Reset with the RST instruction or send "0" with the MOV/FMOV
instruction.
2) GX Developer clear method
Clear all device memory in the online PLC memory clear (including
latch).
Refer to the GX Developer operating manual for details of the GX
Developer operation methods.
POINT
To clear file registers or local devices, use the RST instruction to perform a reset
operation, or use the MOV/FMOV instruction to transmit "0".

REMARK
Refer to following manual for the MOV/FMOV instruction.
• QCPU (Q mode)/QnACPU Programming Manual (Common instructions)

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4.7 I/O Processing and Response Lag

In the direct mode, the batch communication with I/O modules is performed before
sequence program operation starts.
By creating a sequence program with direct access I/O, I/O processing can be
performed in a direct mode to communicate with I/O module at execution of each
instruction in the sequence program.
For details on direct access I/O, see Section 10.2.1 and 10.2.2, respectively.

4.7.1 Refresh mode

(1) Definition of refresh mode

With the refresh mode, batch communication with the I/O modules is performed
before the sequence program operation starts.
(a) Batch reading of the input module ON/OFF information is executed in the
High Performance model QCPU's internal input device memory when
sequence program operation starts. This ON/OFF data (in the input device
memory) is then used for processing when a sequence program is
executed.
(b) The processing result of the output (Y) sequence program is output to the
High Performance model QCPU's internal output device memory, and
batch output of the ON/OFF data (in output device memory) to the output
module is executed when sequence program operation starts.

High Performance model QCPU

Remote input Network

refresh area module
CPU (operation processing area) 3
At input
Input (X) refresh
3) GX Developer Input
device
input area 1) module
X0 memory 1
1) At input Area for
refresh communication
with input module At output
4) 2
Output (Y) refresh Output
Y22 device
Y20 2) module
5)
memory

Network
module

• Input refresh:
Before start of the sequence program operation, input data are batch-read from the
input module (1) and ORed with the GX Developer input area or remote input refresh
area data, and the results are stored into the input (X) device memory.
• Output refresh:
Data in the output (Y) device memory is output in a batch 2) to the output module
before sequence program operation starts.
• When an input contact instruction has been executed:
Input information is read 3) from the input (X) device memory, and a sequence
program is executed.
• When an output contact instruction has been executed:
Output information is read 4) from the output (Y) device memory, and a sequence
program is executed.
• When an output OUT instruction has been executed:
The sequence program operation result 5) is stored in the output (Y) device memory.
Fig.4.7 I/O Information Flow in Refresh Mode

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REMARK
1: The peripheral device input area can be switched ON and OFF by the following:
• Test operation by the GX Developer
• A network refresh by the MELSECNET/H network system
• Writhing from a serial communication module
• CC-Link automatic refresh
2: The output (Y) device memory can be switched ON and OFF by the following:
• Test operation by GX Developer
• A network refresh by the MELSECNET/H network system
• Writhing from a serial communication module
• CC-Link automatic refresh
3: The remote I/O refresh area indicates the area used when automatic refresh
setting is made to the input (X) with MELSECNET/H and CC-Link.
Automatic refresh of the remote input refresh area is executed during END
processing.

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(2) Response lag

An output module lags max.2 scans behind an input module. (See Fig.4.8)

Ladder examples
X5 Ladder that turns the Y5E output
55 Y5E
ON when an X5 input turns ON.

When Y5E turns ON fastest

Input refresh Input refresh Output refresh
0 END 0 56 END 0

ON
OFF
External contact
ON
OFF
X5
QCPU ON
devices OFF
Y5E
ON
OFF
External load
Lag time

(Minimum 1 scan)

Y5E output turns on fastest if the external contact is turned ON immediately before
the refresh operation. Then X5 turns ON at the input refresh, Y5E turns ON at step
56, and the external load turns ON at the output refresh following execution of the
END instruction. In this case, the time lag between the external contact ON and the
external load ON is 1 scan.

When Y5E turns ON slowest

Input refresh Input refresh Output refresh
0 END 0 56 END 0

ON
OFF
External contact
ON
OFF
X5
QCPU ON
devices OFF
Y5E
ON
OFF
External load
Lag time
(Maximum 2 scan)

Y5E turns on slowest if the external contact is turned ON immediately after the
refresh operation. Then X5 turns ON at the input refresh, Y5E turns ON at step 56,
and the external load turns ON at the output refresh following execution of the END
instruction. In this case, the time lag between the external contact ON and the
external load ON is 2 scan.
Fig.4.8 Timing chart showing response of Output "Y" when Input "X" turns ON

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4.7.2 Direct mode

(1) Definition of direct mode

In the direct mode the communication with the I/O modules is performed when
executing sequence program instructions.
With High Performance model QCPU, direct mode I/O processing can be
performed by using direct access inputs (DX) and direct access outputs (DY).
For details on direct I/O, see Section 10.2.1 and 10.2.2, respectively.

High Performance model QCPU

Remote input Network

refresh area module
CPU (operation processing area) 3

1) Input
2) GX Developer
Input (X) input area module
3) 1
device
DX0 memory

4) 2
Output (Y)
Y20 Output
device
DY25 5) module
memory

• When an input contact instruction has been executed:

The input module's input information 1) is ORed with GX Developer input area's
input information 2) or remote input refresh area data, and the result is stored into
the input (X) device memory. Then this data is then used as input information 3) at
sequence program execution.
• When an output contact instruction has been executed:
Output information 4) is read from the output (Y) device memory, and a sequence
program is executed.
• When an output OUT instruction has been executed:
The sequence program's operation result 5) is output to the output module, and is
stored in the output (Y) device memory.
Fig.4.9 I/O Information Flow in Direct Mode

REMARK
1: The GX Developer input area can be turned ON and OFF by the following:
• Test operation by GX Developer
• Writing from a serial communication module
2: The output (Y) device memory can be turned ON and OFF by the following:
• Test operation by the GX Developer
• A network refresh by MELSECNET/H network system
• Writing from a serial communication module
• CC-Link automatic refresh
3: The remote input refresh area indicates the area used when automatic refresh
setting is made to the input (X) with MELSECNET/H and CC-Link.
Automatic refresh of the remote input refresh area is performed during END
processing.

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(2) Response lag

An output module lags max.1 scan behind an input module. (See Fig.4.10)

Ladder examples
DX5 Ladder that turns the DY5E output
55 DY5E
ON when an DX5 input turns ON.

When DY5E turns ON fastest

LD DX5
OUT DY5E
0 55 56

ON
OFF
DX5
ON
OFF
DY5E

DY5E output turns fastest ON if the DX5 input is turned ON immediately before the
step 55 operation. If DX5 is ON when step 55's LD DX5 is executed, DY5E will turn
ON within that scan.
Therefore, in this case, output DY5E lags minimally behind input DX5.

When DY5E turns ON slowest

LD DX5
OUT DY5E

0 55 56 END 0 55 56

ON
OFF
DX5
ON
OFF
DY5E
Lag time
(Maximum of 1 scan)

DY5E output turns ON slowest if the DX5 input is turned ON immediately after the
step 55 operation. In this case, the DY5E output will turn ON during the next scan.
In this case output DY5E lag max.1 scan behind input DX5.
Fig.4.10 Timing chart showing response of Output "Y" when Input "X" turns ON

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4.8 Numeric Values which Can Be Used in Sequence Programs

Numeric and alphabetic data are expressed by "0" (OFF) and "1" (ON) numerals in the
High Performance model QCPU.
This expression form is called "binary code" (BIN).
The hexadecimal (HEX) expression form in which BIN data are expressed in 4-bit
units, and the BCD (binary coded decimal) expression form are applicable to the High
Performance model QCPU.
Real numbers may also be used. (See Section 4.8.4)
The numeric expressions by BIN, HEX, BCD, and Decimal (DEC) notations are shown
in Table 4.1 below.

Table 4.1 BIN, HEX, BCD, and Decimal Numeric Expressions

BCD
DEC (Decimal) HEX (Hexadecimal) BIN (Binary)
(Binary Coded Decimal)
0 0 0 0
1 1 1 1
2 2 10 10
3 3 11 11
• • • •
• • • •
• • • •
9 9 1001 1001
10 A 1010 1 0000
11 B 1011 1 0001
12 C 1100 1 0010
13 D 1101 1 0011
14 E 1110 1 0100
15 F 1111 1 0101
16 10 1 0000 1 0110
17 11 1 0001 1 0111
• • • •
• • • •
• • • •
47 2F 10 1111 100 0111
• •
• •
• •
32766 7FFE 0111 1111 1111 1110 ——
32767 7FFF 0111 1111 1111 1111 ——
-32768 8000 1000 0000 0000 0000 1000 0000 0000 0000
-32767 8001 1000 0000 0000 0001 1000 0000 0000 0001
• •
• •
• •
-2 FFFE 1111 1111 1111 1110 ——
-1 FFFF 1111 1111 1111 1111 ——

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(1) External numeric inputs to High Performance model QCPU

When inputting numeric values to the High Performance model QCPU from an
external source (such as digital switch), use BCD (binary coded decimal) which
allows the same setting as decimal form.
However, the High Performance model QCPU handles the values as BIN data
since the operation is based on BIN form, if it uses values set in the BCD form as
they are.
Therefore, the High Performance model QCPU operates with numeric values that
are different from the set values.
A BIN instruction is provided to convert the BCD input data to the BIN data
compatible with the High Performance model QCPU.
A program which converts numeric data to BIN data can be created at the
sequence program to allow the settings of numeric values from an external
source without being conscious of the corresponding BIN values.
High Performance model QCPU
[Numeric data designation]
Digital switch BINP K4X0 D0

4 3 2 1
BCD input
XF X0
BIN data
BCD D5 K4Y30

Fig.4.11 Digital Switch Data Input to High Performance model QCPU

(2) External numeric outputs from High Performance model QCPU

A digital display can be used to display numeric data which is output from the
High Performance model QCPU.
However, BIN date cannot be displayed at the digital display as it is because the
High Performance model QCPU use it for operation.
Therefore BCD instruction is provided for the High Performance model QCPU to
convert the BIN data to BCD data. A program which converts BIN data to BCD
data can be created in the sequence program in order to display the output data
in the same manner as decimal data.
High Performance modle QCPU
[Numeric data designation]
BINP K4X0 D0 Digital display

Y3F Y30

BCD D5 K4Y30 BCD output

BIN data

Fig.4.12 Digital Display of Data from High Performance model QCPU

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4.8.1 BIN (Binary Code)

(1) Binary code

Binary date is represented by 0 (OFF) and 1 (ON).
Decimal notation uses the numerals 0 through 9. When counting beyond 9, a 1 is
placed in the 10s column and a 0 is placed in the 1s column to make the number
10.
In binary notation, the numerals 0 and 1 are used. A carry occurs after 1 and the
number becomes 10 (decimal 2).
Table 4.2 gives a comparison between binary and decimal notations.

Table 4.2 Comparison between Binary and Decimal Notations

DEC (Decimal) BIN (Binary)
0 0000
1 0001
Carry
2 0010
3 0011
Carry
4 0100
5 0101
6 0110
7 0111
Carry
8 1000
9 1001
10 1010
11 1011

(2) Binary numeric expression

(a) High Performance model QCPU registers (data registers, link registers, etc.)
n
consist of 16 bits, and a "2 " value is allocated to each of the register bits.
The most significant bit (initial bit) is used to discriminate between "positive"
and "negative".
1) When most significant bit is "0"...Positive
2) When most significant bit is "1"...Negative
The numeric expressions for the High Performance model QCPU registers
are shown in Fig.4.13 below.
Most significant bit (for positive/negative discrimination)
Bit name b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

2 15 2 14 2 13 2 12 2 11 2 10 2 9 28 27 26 25 24 23 22 2 1 20

Decimal value -32768 16384 81924096 20481024 512 256 128 64 32 16 8 4 2 1

"Negative value" when most significant bit is "1".

Fig.4.13 Numeric Expressions for High Performance model QCPU Registers

(b) Usable numeric data for High Performance model QCPU

As shown in Fig.4.13, the numeric expression range is -32768 to 32767.
Therefore, numeric data within this range can be stored in the High
Performance model QCPU registers.

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4.8.2 HEX (Hexadecimal)

(1) Hexadecimal notation

In hexadecimal notation, 4 binary bits are expressed in 1 digit.
If 4 binary bits are used in binary notation, 16 different values from 0 to 15 can be
represented.
Since hexadecimal notation represents 0 to 15 in 1 digit, letters A to F are used
to represent the numbers 10 to 15.
Then, a carry occurs after F.
Table 4.3 shows numeric expressions by binary, hexadecimal, and decimal
notations.

Table 4.3 Comparison of BIN, HEX, and DEC Numeric Expressions

DEC (Decimal) HEX (Hexadecimal) BIN (Binary)
0 0 0
1 1 1
2 2 10
3 3 11
• • •
• • •
• • •
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111 Carry
16 10 1 0000
17 11 1 0001
• • •
• • •
• • •
47 2F 10 1111

(2) Hexadecimal numeric expression

High Performance model QCPU registers (data registers, link registers, etc.)
consist of 16 bits.
Therefore, the numeric values expressed in hexadecimal notation can be stored
in each register within 0 to FFFFH range.

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4.8.3 BCD (Binary Coded Decimal)

(1) BCD notation

BCD notation is binary expression with a carry similar to that of the decimal
notation.
Though it uses 4-bit representation like hexadecimal notation, it dose not use
letters A to F.
Table 4.4 gives numeric expressions by binary, BCD, and decimal notations.

Table 4.4 Comparison of BIN, BCD, and DEC Numeric Expressions

BCD
DEC (Decimal) BIN (Binary)
(Binary Coded Decimal)
0 0 0
1 1 1
2 10 10
3 11 11
4 100 100
5 101 101
6 110 110
7 111 111
8 1000 1000
9 1001 1001 Carry
10 1010 1 0000
11 1011 1 0001
12 1100 1 0010

(2) BCD numeric expression

High Performance model QCPU registers (data registers, link registers, etc.)
consist of 16 bits.
Therefore, the numeric values expressed in BCD notation can be stored in each
register within 0 to 9999 range.

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4.8.4 Real numbers (floating decimal point data)

(1) Real numbers

Real numbers are single precision floating decimal point data.

(2) Internal expression of floating decimal point data

The High Performance model QCPU's internal expression of received real
number data is explained below.
Real number data is expressed as shown below, using 2 word devices.

1. [Mantissa] × 2 (characteristic)

The bit configuration used for internal expression of floating decimal point data is
shown and explained below.

b31 b30 b23 b22 b16 b15 b0

b23 to b30 b0 to b22

Characteristic Mantissa
b31
Mantissa code

• Mantissa code: The mantissa code is expressed at b31 as follows.

0: Positive
1: Negative

• Characteristic: The "n" of "2n" is expressed in various ways at b23 to b30,

depending on the b23 to b30 BIN value.

b23 to b30 FFH FEH FDH 81H 80H 7FH 7EH 02H 01H 00H
Non- Non-
n numeric 127 126 2 1 0 -1 -125 -126 numeric

• Mantissa: For a binary value of 1.XXXXXX..., the "XXXXXX" portion of

the value is expressed at b0 to b22 (23 bits).

(3) Calculation examples

Calculation examples are shown below (the nnnnn "X" indicates an X-system
data expression).
(a) Storing "10"
(10)10 (1010)2 (1.01000..... 23 ) 2

Mantissa code Positive to 0

Characteristic 3 to 82H to (10000010)2
Mantissa (010 00000 00000 00000 00000)2

Therefore, the data expression will be 41200000H, as shown below.

Code Characteristic Mantissa
0 10000010 01000000000000000000000

4 1 2 0 0 0 0 0

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(b) Storing "0.75"

(0.75) 10 (0.11) 2 (1.100.... 2 -1)2
Mantissa code Positive to 0
Characteristic -1 to 7EH to (01111110)2
Mantissa (100 00000 00000 00000 00000)2

Therefore, the data expression will be 3F400000H, as shown below.

Code Characteristic Mantissa
0 01111110 01000000000000000000000

3 F 4 0 0 0 0 0
POINT
(1) The monitor function for GX Developer permits monitoring the real number data
of the High Performance model QCPU.
However, if an attempt is made to monitor the data that cannot be represented
as a real number, e.g. "FFFFH", "_____" is displayed.
(2) For a "0" value, "0" will be indicated at all the b0 to b31 bits.
(3) It is possible to select either "Perform internal arithmetic operation in double
precision" or "Do not perform internal arithmetic operation in double precision"
with the floating point arithmetic processing on the PLC parameter's PLC
system settings. (The result of the operation will be short precision regardless
of the floating point arithmetic processing setting.)
It is recommended that "Do not perform internal arithmetic operation in double
precision" is selected if increased speed for the real arithmetic operations is
required, and "Perform internal arithmetic operation in double precision" is
selected if precision is required when applying compatibility with conventional
equipment.
• Only internal arithmetic operations will be performed at double precision (64-
bits) when "Perform internal arithmetic operation in double precision" is
selected (default setting.)
Precision will be increased for commands that use many real arithmetic
operations with internal arithmetic operations, such as the SIN command and
COS command, when double precision is set.
• Real arithmetic operations will be performed faster owing to the internal
arithmetic operations being performed with short precision (32-bit) when "Do
not perform internal arithmetic operation in double precision" is set, and there
are also cases where a certain amount of precision will be lost.

To turn off "Perform

internal arithmetic
operations in double
precision", uncheck
the check box.

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4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION
CONDITIONS
MELSEC-Q

REMARK
In binary notation, the portion of the value following the decimal point is calculated
as follows:
0.1 1 0 1

This bit expresses 2-1 This bit expresses 2-2 This bit expresses 2-3 This bit expresses 2-4

(0.1101)2 = 2-1 + 2-2 + 2-4 = 0.5 + 0.25 + 0.0625 = (0.8125)10

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CONDITIONS
MELSEC-Q

4.9 Character String Data

(1) Character String Data

The High Performance model QCPU uses ASCII code data.

(2) ASCII code character strings

ASCII code character strings are shown in the Table below.
"00H" (NUL code) is used at the end of a character string.

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Column
b8 b7 b6 b5 b4 b3 b2 b1 0 1 2 3 4 5 6 7 8 9 A B C D E F
Low
0 0 0 0 0 NUL (SP) 0 @ P ` p
0 0 0 1 1 ! 1 A Q a q
0 0 1 0 2 " 2 B R b r
0 0 1 1 3 # 3 C S c s
0 1 0 0 4 $ 4 D T d t
0 1 0 0 5 % 5 E U e u
0 1 1 0 6 & 6 F V f v
0 1 1 1 7 ' 7 G W g w
1 0 0 0 8 ( 8 H X h x
1 0 0 1 9 ) 9 I Y i y
1 0 1 0 A * : J Z j z
1 0 1 1 B + ; K [ k {
(Comma)
1 1 0 0 C , < L l |
(Minus)
1 1 0 1 D - = M ] m }
(Period)
1 1 1 0 E . > N ^ n
Under
line
1 1 1 1 F / ? O _ o

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5 ASSIGNMENT OF I/O NUMBERS

This section describes the necessary information on the I/O number assignment for the
data exchange between High Performance model QCPU and I/O modules or intelligent
function modules.

5.1 Relationship Between the Number of Stages and Slots of the Extension Base Unit

High Performance model QCPU allows the system configuration using eight base
units: one main base unit and seven extension base units.
However, the number of available slots (modules) is limited to 64 slots including empty
slots.
An error (SP. UNIT LAY ERR.) occurs when a module (input, output, or intelligent
function module) is installed to the 65th or subsequent slots.
Be sure to install modules within the range of 64 slots. (An error does not occur as
long as all modules are installed within the range of 64 slots, even if the total number of
slots of the main and extension base units results in 65 slots or more [e.g. When 6 12-
slot base units are installed].)
0 1 2 3 4 5 6 7 8 9 10 11 Slot No.
Power supply
QCPU

Setting of extension
stage
Q312B 5
(See Section 5.2.)

12 13 14 15 16 17 18 19 20 21 22 23
Power supply

Q612B

24 25 26 27 28 29 30 31 32 33 34 35
Power supply

2
Q612B

36 37 38 39 40 41 42 43 44 45 46 47
Power supply

3
Q612B

48 49 50 51 52 53 54 55 56 57 58 59
Power supply

4 Q612B

60 61 62 63
Power supply

Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid

5 Q612B

Mountable module . Unmountable module .

(Mounting module will result in error.)

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 5 ASSIGNMENT OF I/O NUMBERS
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5.2 Installing Extension Base Units and Setting the Number of Stages

There are two types of extension base units: Q5 B/Q6 B for mounting of Q-Series
modules and QA1S6 B and for mounting AnS Series modules.

(1) Connecting order of extension base units

When using both Q5 B/Q6 B and QA1S6 B, connect all Q5 B/Q6 B
modules closer to the main base unit, then connect QA1S6 B modules.

(2) Setting order of the stage numbers for extension base units
Extension base units require the setting of the extension stage numbers (1 to 7)
using the stage No. setting connector.
Assign the extension stage numbers starting from 1 to 7 to the extension base
units in the connected order starting from the one connected to the main base
unit.

(3) Cautions for assigning extension stage numbers to extension base

units
(a) Assign consecutive numbers to extension stages.
If you assign stage numbers to base units in "Auto" mode and assign some
stage numbers to no modules, "0" is assigned to the skipped stage as the
5 number of slots. Consequently, the number of empty slots does not
increase. The skipped stage is also assigned with "0" of I/O point.
(b) It is impossible to set and use the same extension stage number with two or
more extension base units.
(c) You cannot use the system if two or more connector pins are inserted to the
stage setting connector.
On the contrary, you cannot use the system if no connector pin is inserted
to the stage setting connector.
0 1 2 3 4 5 6 7
Power supply
QCPU

Setting of extension
Q38B Main base unit
stage

Stage setting
connector 8 9 10 11 12 13 14 15
Power supply

1
Extension base unit for mounting module
Q68B corresponding to the Q Series
(Q5 B/Q6 B is connected to
the main base unit or Q5 B/Q6 B.)

16 17 18 19 20 21 22 23
Power supply

2
QA1S68B

Extension base unit for mounting module

corresponding to the AnS Series
24 25 26 27 28 29 30 31 (QA1S6 B is connected to the end of
Power supply

Q5 B/Q6 B or QA1S6 B.)

3
QA1S68B

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5 ASSIGNMENT OF I/O NUMBERS
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5.3 Base Unit Assignment (Base Mode)

There are "Auto" and "Detail" modes to assign the number of modules can be mounted
in the main and extension base units of High Performance model QCPU.
(1) Auto mode
In Auto mode, the slot numbers are assigned to the main and extension base
units according to the number of slots than can be occupied.
The I/O numbers are assigned according to the modules which can be mounted
to the current base unit.
(a) For 3-slot base unit: 3 slots are occupied
Q33B type main base unit
0 1 2
Power supply
CPU module

Five slots are not occupied.

Q63B type extension base unit
3 4 5
Power supply

Five slots are not occupied.

Q63B type extension base unit
6 7 8
Power supply

Five slots are not occupied.

(b) For 5-slot base unit: 5 slots are occupied

Q35B type main base unit
0 1 2 3 4
Power supply
CPU module

Three slots are not occupied

Q65B type extension base unit
5 6 7 8 9
Power supply

Three slots are not occupied

Q65B type extension base unit
10 11 12 13 14
Power supply

Three slots are not occupied

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5 ASSIGNMENT OF I/O NUMBERS
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(c) For 8-slot base unit: 8 slots are occupied

Q38B type main base unit
0 1 2 3 4 5 6 7

Power supply
CPU module
Q68B type extension base unit
8 9 10 11 12 13 14 15
Power supply

(d) For 12-slot base unit: 12 slots are occupied

Q312B type main base unit
0 1 2 3 4 5 6 7 8 9 10 11
Power supply
CPU module

Q612B type extension base unit

12 13 14 15 16 17 18 19 20 21 22 23
Power supply

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MELSEC-Q

(2) Detail mode

(a) In Detail mode, the number of mountable modules is assigned to the
individual base units (main and extension base units) at the "I/O
assignment" tab screen in the “(PLC) Parameter" dialog box.
Use this mode to match the number of slots to the one for the AnS Series
base units (8 fixation).

(b) Cautions on setting the number of slots

The number of slots can be set regardless of the number of the module
being used.
However, the number of slots must be set for all the base units in use.
If the number of slot is not set for all the base units, I/O assignment may not
work correctly.
The followings result if the preset number of slots differs from that of the
installed base units.
1) When the designated number of slots is larger than that of the installed
base unit:
Among the designated slots, those after the slots occupied by the
installed base unit will be empty slots.
For example, when 8 slots are designated for a 5-slot base unit, 3 slots
will be empty slots.
Q35B type main base unit
0 1 2 3 4 5 6 7
Power supply
CPU module

Empty
Empty
Empty

Three slots are occupied.

The number of points for the empty slots is the one designated at the
"I/O assignment" tab screen in the “(PLC) Parameter" dialog box.
(Default value is 16 points.)
2) When the designated number of slots is smaller than that of the base
unit being used:
The slots other than those designated are disabled.
For example, when 8 slots are designated for a 12-slot base unit, the 4
slots on the right of the base unit are disabled.
(If a module is mounted to the prohibited slot, an error [SP. UNIT LAY
ERR.] occurs.)
Q312B type main base unit
0 1 2 3 4 5 6 7 8 9 10 11
Power supply
CPU module

Prohibit
Prohibit
Prohibit
Prohibit

Module can be mounted. Modules must not be mounted.

(When eight slots are set)

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MELSEC-Q

(3) Setting screen and setting items for Base mode of GX Developer

(e)

(a) (b) (c) (d)

(a) Base model name

Designate the model name of the installed base unit with 16 or less
characters. High Performance model QCPU does not use the designated
model name. (It is used as a user's memo or for parameter printing)

(b) Power model name

Designate the model name of the installed power supply module with 16 or
less characters. High Performance model QCPU does not use the
designated model name. (It is used as a user's memo or for parameter
printing)

(c) Increase cable name

Designate the model name of the extension cable being used with 16 or less
characters. High Performance model QCPU does not use the designated
model name. (It is used as a user's memo or for parameter printing)

(d) Points (Used with High Performance model QCPU)

Select the number of points for the slot of the base unit being used from the
followings:
• 2 (2 slots)
• 3 (3 slots)
• 5 (5 slots)
• 8 (8 slots)
• 10 (10 slots)
• 12 (12 slots)

(e) 8 fixation/12 fixation (Used with High Performance model QCPU)

Select either option to designate the number of slots for all base units to the
same number.

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5.4 What are I/O Numbers?

I/O numbers are used in sequence programs for importing ON/OFF data to High
Performance model QCPU from outsides and outputting ON/OFF data from High
Performance model QCPU to outsides.
Input (X) is used for the importing of ON/OFF data to High Performance model QCPU.
Output (Y) is used for outputting ON/OFF data from High Performance model QCPU.
I/O numbers are expressed as hexadecimal.
When using 16-point I/O modules, I/O numbers are consecutively assigned to the slots
having 0 to F, 16 points, as follows.
The module mounted in the base unit assigns the following:
• For the input module, "X" is assigned at the beginning of the I/O number.
• For the output module, "Y" is assigned at the beginning of the I/O number.
For the case of input module For the case of output module

X 0 0 0 X 0 1 0 X 0 2 0 Y 0 3 0 Y 0 4 0
Power CPU
supply module
module
X2C

X 0 0 F X 0 1 F X 0 2 F Y 0 3 F Y 0 4 F
16 input 16 input 16 input 16 output 16 output
points points points points points

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5 ASSIGNMENT OF I/O NUMBERS
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5.5 Concept of I/O Number Assignment

5.5.1 I/O numbers of main base unit and extension base unit

High Performance model QCPU assigns I/O numbers at power-on or reset according
to the following items.
As a result, High Performance model QCPU can be controlled without performing I/O
assignment using GX Developer.
To assign I/O numbers, follow the items below:

(1) Number of slots of base units

The numbers of slots of the main and extension base units are set according to
the Base mode setting. (For Base mode, see Section 5.3.)
(a) In Auto mode, the number of slots is determined as the available number of
modules mounted to each base unit.
For example, 5 slots are assigned to a 5-slot base unit, and 12 slots are
assigned to a 12-slot base unit.
(b) In Detail mode, the number of slots is determined as the one designated at
the "I/O assignment" tab screen in the “(PLC) Parameter" dialog box.

(2) Order of I/O number assignment

The I/O numbers are assigned to the modules from left to right consecutively,
starting from 0H assigned to the module on the right of the High Performance
model QCPU in the main base unit.

(3) Order of I/O number assignment for extension base units

The I/O numbers for extension base units continue from the last number of the
I/O number of the main base unit.
The I/O numbers are assigned to the extension base units from left (I/O 0) to right
consecutively, in the order in which the setting connectors of the extension base
unit are set.

(4) I/O numbers of each slot

Each slot of base units occupies the points of I/O numbers of the mounted I/O
modules or intelligent function modules (special function modules).
When 32-point input module is mounted on the right of High Performance model
QCPU, X0 to X1F are assigned as I/O numbers.

(5) I/O numbers of empty slots

If the base unit has empty slots mounted with no I/O modules or no intelligent
function modules (special function modules) are mounted, the points designated
at the "I/O assigment" tab screen in the “(PLC) Parameter" dialog box are
assigned to the empty slots. (Default value is 16 points.)
POINT
When the assignment of base units is conducted in Auto mode, the number of
empty extension stages is not assured even if the extension stage is skipped at the
stage number setting connector of the base unit. (Lower I/O numbers are assigned
first.)
To reserve empty extension stages for future expansion, use the PLC parameter to
set the base unit.

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5 ASSIGNMENT OF I/O NUMBERS
MELSEC-Q

The following shows the example of the I/O number assignment when the base unit is
set in Auto mode without I/O assignment:

Q35B (5 slots occupied)

0 1 2 3 4 ............. Slot No.

Output module

Output module
Input module

Input module

Input module
Power supply module

CPU module
Allocate the I/O number with
the I/O points of each slot
16 16 32 16 64
points points points points points
......... I/O numbering direction
X00 X10 X20 Y40 Y50
The slot numbers of the 1st stage's extension
X0F X1F X3F Y4F Y8F base unit continue from the last slot number
Q65B (5 slots occupied) of the main base unit.
Extension
cable
5 6 7 8 9
Output module
function module

function module

function module
Power supply module

Empty
Intelligent

Intelligent

Intelligent

1 Empty slot points designated at the "PLC system"

tab screen in the "(PLC) Parameter" dialog box are
IN OUT
allocated. (Default: 16 points)
32 32 32 16 16
points points points points points
90 B0 D0 YF0 100
The slot numbers of the 2nd stage's extension
AF CF EF YFF 10F
base unit continue from the last slot number of
Q68B (8 slots occupied)
the 1st stage's extension base unit.
10 11 12 13 14 15 16 17
Output module

Output module

Output module
function module

function module

function module
Power supply module

Input module

Input module

Intelligent

Intelligent

Intelligent

2
IN OUT

16 16 32 32 32 16 16 16
points points points points points points points points
X110 X120 130 150 170 Y190 Y1A0 Y1B0

X11F X12F 14F 16F 18F Y19F Y1AF Y1BF

POINT
The above example shows the case where the intelligent function module has 32
I/O points.
The number of occupied I/O points may vary depending on the intelligent function
module.
Refer to the manual of the intelligent function module being used and check the
number of the I/O points before assigning the I/O numbers.

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MELSEC-Q

5.5.2 Remote station I/O number

It is possible to allocate High Performance model QCPU device input (X) and output
(Y) to remote station I/O modules and intelligent function modules and control the
modules in the MELSECNET/H remote network, the CC-Link and other remote I/O
systems.

QJ61BT11
QJ71LP21
QX41

QX41

QY41
QY41

QX41

QY41
QJ72LP25
Q64AD

Q64AD
CPU module
Power supply

Power supply
Allocation of
QCPU input (X) and
MELSECNET/H output (Y) possible
Remote Remote
station station
CC-Link

When using High Performance model QCPU device input (X) and output (Y) in remote
stations, I/O numbers that succeed the numbers used by the main base unit and
extension base units' I/O modules and intelligent function modules will be allocated.
For example, if X/Y0 to X/Y3FF are being used by the main base unit and extension
base units' I/O modules and intelligent function modules, then numbers above X/Y400
can be used by the remote station.
However, the I/O numbers for remote stations should be set in consideration of
additions to the main base unit and extension base units' I/O modules and intelligent
function modules.

For example, if 1024 points from X/Y0 to X/Y3FF are being used by the main base unit
and extension base units, and 256 points from X/Y400 to X/Y4FF are to be held back
for use with future additions, then the situation shown in the diagram below is to be
observed.
I/O (X/Y)
X/Y0
I/O numbers being used by the main base unit and
to
extension base units
X/Y3FF
X/Y400
to Held back for future additions
X/Y4FF
X/Y500 For MELSECNET/H
remote I/O station

For CC-Link remote

station

to I/O numbers that can be used by remote stations

X/Y1FFF

POINT
If network parameter setting is not made in the CC-Link system, 2048 points in the
range from X/Y1000 to X/Y17FF are assigned to the master local module of the
CC-Link having the lowest number.

REMARK
There is restriction on the order of allocating I/O numbers for MELSECNET/H
remote I/O networks, CC-Link or other networks.
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5 ASSIGNMENT OF I/O NUMBERS
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5.6 I/O Assignment by GX Developer

This section describes the I/O assignment using GX Developer.

5.6.1 Purpose of I/O assignment by GX Developer

I/O assignment by GX Developer is used under the following circumstances.

(1) Reserving points when converting to module other than 16-point

modules
You can reserve the number of points in advance so that you do not have to
change the I/O numbers when the current module will be changed to one with a
different number of occupied I/O points in the future.
For example, you can assign a 32-point I/O module to the slot where a 16-point
I/O module is mounted at present.

(2) Preventing I/O numbers from changing when converting modules

You can avoid the change in the I/O numbers when an I/O module other than 16-
point module or intelligent function module (special function module) is removed
due to a malfunction.

(3) Changing the I/O numbers to those used in the program

When the designed program's I/O numbers are different from the actual system
I/O numbers, each module's I/O number of base units can be set to program-I/O
number.

(4) Setting the input response time of input modules and interrupt
modules (I/O response time)
To match the input response time of the input modules and interrupt modules to
the system, select "Type" at the "I/O assignment" tab screen in advance. (For
details, see Section 7.7.)

(5) Error-time output mode setting

The output mode at error can be set to the output module, I/O module or
intelligent function module. Make this setting after selecting "Type" in I/O
assignment. (For details, see Section 7.8.)

(6) Setting the switch of intelligent function modules

To set the switch of the intelligent function module, select "Type" at the "I/O
assignment" tab screen in advance. (For details, see Section 7.10.)

(7) Setting outputs during High Performance model QCPU error

To set the output status (retain/clear) of the output modules and intelligent
function modules when the High Performance model QCPU stops the operation
due to a stop error, select "Type" at the "I/O assignment" tab screen in advance.
(For details, see Section 7.8.)

(8) Setting High Performance model QCPU operation during a

hardware error of intelligent function modules
To set the High Performance model QCPU operation (continue/stop) during a
hardware error of an intelligent function module, select "Type" at the "I/O
assignment" tab screen in advance. (For details, see Section 7.9.)

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5 ASSIGNMENT OF I/O NUMBERS
MELSEC-Q

POINT
(1) The I/O assignment is necessary for changing the response time of the input
modules and the switch of intelligent function modules.
For the I/O assignment, input module response time setting, intelligent function
module switch setting, and error-time output mode setting, the PLC must be
powered off then on again (ON to OFF to ON) or the High Performance model
QCPU must be reset.
(2) If any of the I/O modules other than the 16-point modules fails without I/O
assignment being made using GX Developer, the I/O numbers after that module
may change, leading to a malfunction. Therefore, it is recommended to make
I/O assignment using GX Developer.

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5.6.2 Concept of I/O assignment using GX Developer

(1) I/O assignment for each slot

"Type" (module type), "Points" (number of occupied I/O points), and "Start" (head
I/O number) can be designated individually for each slot of the base unit.
For example, to change the number of occupied I/O points of the designated slot,
only the number of occupied I/O points can be designated.
The items other than designated are set to the status where the base unit is installed.
The I/O assignment is conducted at the "I/O assignment" tab screen in the “(PLC)
Parameter" dialog box.
(a) (b) (c) (d) (e)

(a) Slot
Displays the slot No. and the ordinal position of the slot in the base unit.
If the base unit is not designated in Detail mode, the stage number of the
base unit is shown as " ", and the ordinal number of a slot is counted
from slot 0 of the main base unit.
(b) Type (For High Performance model QCPU)
Select the type of module being mounted from the followings:
• Empty (Empty slot)
• Input (Input module)
• Hi Input (Q Series high speed module) 1
• Output (Output module)
• I/O Mix (I/O mixed module)
• Intelligent (Intelligent function module or AnS corresponding special
function module)
• Interrupt (Q Series interruption module) 2
If the type is not designated, the type of the actually mounted module is used.

REMARK
1: "Hi input" can be set using GX Developer Version 5 (products after SW5D5C-
GPPW-E)
2: "Interrupt" can be set using GX Developer Version 6 (products after SW6D5C-
GPPW-E)
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5 ASSIGNMENT OF I/O NUMBERS
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(c) Model name

Designate the model name of the mounted module with 16 or less
characters. High Performance model QCPU does not use the designated
model name. (It is used as a user's memo)

(d) Points (Used with High Performance model QCPU)

To change the number of occupied I/O points of each slot, select it from the
followings:
• 0 (0 point)
• 16 (16 points)
• 32 (32 points)
• 48 (48 points)
• 64 (64 points)
• 128 (128 points)
• 256 (256 points)
• 512 (512 points)
• 1024 (1024 points)
If the number of occupied I/O points is not designated for a slot, the one of
the actually mounted module is used.

(e) Start XY (Used with High Performance model QCPU)

1) When the I/O number of each slot is changed, you should designate
the head I/O number according to the change.
If Start XY is not designated for a slot, the I/O number continuing from
the last number of the currently designated slot is assigned.
2) Avoid the I/O number designation of each slot from overlapping the I/O
numbers assigned by High Performance model QCPU.
An error (SP. UNIT LAY ERR.) occurs when the I/O numbers overlap.

(2) Slot status after I/O assignment

When the I/O number is assigned to a slot, the assigned I/O number takes
priority regardless of the actual installation of a module.
(a) If the designated number of occupied I/O points is lower than that of the
actually mounted I/O module, some I/O points of the mounted module are
not used.
For example, if a slot where a 32-point input module is mounted is
designated for a 16-point input module, the latter 16 points of the 32-point
input module are disabled.

(b) If the designated number of occupied points is less than that of the actually
mounted intelligent function module, "SP. UNIT LAY ERR." will occur.

(c) If the designated number of occupied I/O points is higher than that of the
actually mounted I/O module, the points exceeding the points of the actually
mounted module are set as dummies.

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5 ASSIGNMENT OF I/O NUMBERS
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(d) Be sure to set the same module type for the mounted module and the I/O
assignment.
If the module type of the I/O assignment is different from that of the actually
mounted module, the module may not work normally.
For the intelligent function module, make sure that the numbers of I/O
points are the same.
Actually installed module I/O assignment Result
Input module Output/Empty Empty
Output module Input/Empty Empty
Input module/output module Intelligent Error (SP. UNIT LAY ERR.)
Empty Empty
Intelligent function module
Input/output Error (SP. UNIT LAY ERR.)
Empty slot Intelligent No error occurs.

(e) Be sure to assign the I/O numbers so that the last I/O number is within the
range of FFFH or less. An error (SP. UNIT LAY ERR.) occurs when the last
I/O number exceeds FFFH. (System monitor of GX Developer shows
" " as an I/O address.)

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5.7 Examples of I/O Number Assignment

This section shows the examples of the I/O number assignment using GX Developer.

(1) When changing the number of points of an empty slot from 16 to 32

points:
Reserve 32 points to the empty slot (slot No. 3) so that the I/O numbers do not
change when a 32-point input module is mounted in the future. (The empty slot
for slot No. 12 is not changed from 16 points.) 1

(a) System configuration and I/O number assignment before the I/O
assignment with GX Developer
Q38B
0 1 2 3 4 5 6 7

Input module

Input module

Input module

Output module

Output module

Output module

Output module
Power supply module

Empty
CPU module

32 32 32 16 32 32 32 32
points points points points points points points points
X00 X20 X40 60 Y70 Y90 YB0 YD0

X1F X3F X5F 6F Y8F YAF YCF YEF

Q68B

8 9 10 11 12 13 14 15
function module

function module

function module

function module

Output module

Output module

Output module
Power supply module

Empty
Intelligent

Intelligent

Intelligent

Intelligent

1 IN OUT

32 32 32 32 16 32 32 32
points points points points points points points points
F0 110 130 150 170 Y180 Y1A0 Y1C0

10F 12F 14F 16F 17F Y19F Y1BF Y1DF

REMARK
1: This is the case where the number of points for an empty slot is set to 16 at the
"PLC system" tab screen in the “(PLC) Parameter" dialog box.

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5 ASSIGNMENT OF I/O NUMBERS
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(b) I/O assignment with GX Developer

Designate slot No. 3 to "32 points" at the "I/O assignment" tab screen of GX
Developer.

Select 32 points.
(When the type is not selected,
the type of the installed module
will be selected.)

(c) I/O number assignment after the I/O assignment with GX Developer
Q38B
0 1 2 3 4
Output module 5 6 7

Output module

Output module

Output module
Input module

Input module

Input module

Empty
Power supply module

CPU module

32 32 32 32 32 32 32 32
points points points points points points points points
X00 X20 X40 60 Y80 YA0 YC0 YE0

X1F X3F X5F 7F Y9F YBF YDF YFF

Q68B

8 9 10 11 12 13 14 15
Empty

Output module

Output module

Output module
function module

function module

function module

function module
Power supply module

Intelligent

Intelligent

Intelligent

Intelligent

1
IN OUT

32 32 32 32 16 32 32 32
points points points points points points points points
100 120 140 160 180 Y190 Y1B0 Y1D0

11F 13F 15F 17F 18F Y1AF Y1CF Y1EF

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5 ASSIGNMENT OF I/O NUMBERS
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(2) Changing the I/O number of slots

Change the I/O number of an empty slot (slot No. 3) to X200 through X21F so
that the I/O numbers of slot No. 4 and later slots do not change when a 32-point
input module is mounted to the empty slot (slot No. 3).

(a) System configuration and I/O number assignment before the I/O
assignment with GX Developer
Q38B
0 1 2 3 4 5 6 7

Output module

Output module

Output module

Output module
Input module

Input module

Input module

Empty
Power supply module

CPU module
32 32 32 16 32 32 32 32
points points points points points points points points
X00 X20 X40 60 Y70 Y90 YB0 YD0

X1F X3F X5F 6F Y8F YAF YCF YEF

Q68B

8 9 10 11 12 13 14 15

Output module

Output module

Output module
Empty
function module

function module

function module

function module
Power supply module

Intelligent

Intelligent

Intelligent

Intelligent

1
IN OUT

32 32 32 32 16 32 32 32
points points points points points points points points
F0 110 130 150 170 Y180 Y1A0 Y1C0

10F 12F 14F 16F 17F Y19F Y1BF Y1DF

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5 ASSIGNMENT OF I/O NUMBERS
MELSEC-Q

(b) I/O assignment with GX Developer

Designate the head I/O number of slot No. 3 to "200" and that of slot No. 4
to "70" at the "I/O assignment" tab screen of GX Developer.

"200" is designated as the

head I/O number.

"70" is designated as the head

I/O number.
(When the head I/O number
is not designated, the I/O
number following the 3rd slot
will be assigned.)

(c) I/O number assignment after the I/O assignment with GX Developer
Q38B
0 1 2 3 4 5 6 7
Output module

Output module

Output module

Output module
Input module

Input module

Input module

Input module
Power supply module

CPU module

32 32 32 32 32 32 32 32
points points points points points points points points
X00 X20 X40 X200 Y70 Y90 YB0 YD0

X1F X3F X5F X21F Y8F YAF YCF YEF

Q68B

8 9 10 11 12 13 14 15
Output module

Output module

Output module
function module

function module

function module

function module
Power supply module

Empty
Intelligent

Intelligent

Intelligent

Intelligent

1 IN OUT

32 32 32 32 16 32 32 32
points points points points points points points points
F0 110 130 150 170 Y180 Y1A0 Y1C0

10F 12F 14F 16F 17F Y19F Y1BF Y1DF

5.8 Checking the I/O Numbers

System monitor of GX Developer allows the check of the mounted modules of High
Performance model QCPU and their I/O numbers. (For system monitor, refer to
Section 7.20.)

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6 MEMORIES AND FILES HANDLED BY HIGH PERFORMANCE MODEL

QCPU

(1) Files handled by High Performance model QCPU

(a) The High Performance model QCPU parameters, programs, comment data,
etc. are assigned "file names" and "extension", and are then stored in the
following memories:
• Program memory
• Standard ROM
• Memory card
When reading and writing this data from GX Developer to the High
Performance model QCPU, files can be specified by type (parameter,
program, comment, etc.) without regard to their extension. (GX Developer
automatically assigns the appropriate extension for the file type which has
been specified.)

(b) It is impossible to set and use the same extension stage number with two or
more extension base units.

(2) High Performance model QCPU file management

The use of different file and extension names permits multiple files to be stored in
the High Performance model QCPU.
Because the High Performance model QCPU can also process a given program
6 as one file, programs created can be managed individually according to their
"designer", "process", or "function" by using different program file names.
Moreover, program execution is allowed for multiple programs stored in the High
Performance model QCPU.
(See Chapter 4 for details on High Performance model QCPU program execution
details.)

(3) File written from GX Developer

The High Performance model QCPU stores files written from GX Developer in
the memory (program memory/standard ROM/memory card).

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(4) File details

File name, file size and writing date, which are set when created with GX
Developer, are added to every file written into High Performance model QCPU.
When monitoring the files by GX Developer, the files are displayed as shown
below.

(a) File name

1) The file name consists of the file name (max. 8 characters) and the
extension (3 characters).
A file name of any file written from the GX Developer into the High
Performance model QCPU will be displaced in uppercase characters
on screen. When naming a file by using a sequence program, type a 6
file name in uppercase characters.
An extension which corresponds to the file type designated when the
file was written in the High Performance model QCPU by GX
Developer is automatically appended to the file name.
2) The following Windows-reserved words cannot be used for a file name.
• COM1 to COM9
• LPT1 to LPT9
• AUX
• CON
• PRN
• NUL
• CLOCK$
(b) Date & time
The date & time when the file was written from GX Developer to the High
Performance model QCPU is indicated.
The set date and time indicate the GX Developer-side date and time.
(c) Size
The file size when written from GX Developer to the High Performance model
QCPU is indicated in byte units. (To view the latest High Performance model
QCPU data, click on the Update button.)
Files are stored in the High Performance model QCPU program file and
standard ROM in 4-byte units (1 step), and in the memory card in 1-byte units.
When calculating a file's size, at least 64 bytes (136 bytes for programs) will
be added to all user created files other than file registers.

6-2 6-2
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6.1 About the High Performance model QCPU's Memory

(1) User Memory

A user memory can be created within the memory of the High Performance
model QCPU by using the GX Developer/sequence program.
The High Performance model QCPU has the following built-in memories:
• Program memory
• Standard RAM
• Standard ROM
A memory card can be mounted on the High Performance model QCPU to
increase the size of a user memory.

(a) Programs used for arithmetic operations of the High Performance model
QCPU are stored in the program memory. Programs stored in the standard
ROM or on a memory card are booted (read) into the program memory for
arithmetic operation.

(b) Parameters and programs are stored in the standard ROM. These data are
used for ROM operation of the High Performance model QCPU.

(c) File register and local device data is stored in the standard RAM. The use
of file registers in the standard RAM will enable high speed access as is the
case with data registers.

(d) Memory card

A memory card can be connected to a memory card interface of the High
Performance model QCPU. This allows the read/write of data. The High
Performance model QCPU supports three types of memory cards: SRAM
card, Flash card, and ATA card.
1) The SRAM card allows the write/read of programs through a sequence
program in the following cases where:
• File registers are used in excess of the standard RAM capacity.
• Sampling trace data is stored.
• Failure history data is stored.
The use of file registers allows the write/read of data at 1017k points in
a sequence program.
2) The Flash card allows only the read through a sequence program. The
Flash card is useful when data written by the High Performance model
QCPU is read through a sequence program but no change is made to
the data.
The use of file registers allows a sequence program to read a
maximum of 1018 k points of data written by the High Performance
model QCPU.
3) The ATA card is used for PLC user data (general-purpose data).
Access to PLC user data stored on the ATA card can be made in CSV
format/binary format by using a file access instruction (e.g. FWRITE) in
a sequence program.

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(2) Types of Data Stored in the High Performance model QCPU

Memory or on the Memory Card
The table below shows the type of data stored in a standard RAM/standard ROM
or on a memory card.

High Performance model Memory

Memory Card (ROM)
QCPU Built-In Card (RAM)
Data Name Remarks
Program Standard Standard
SRAM Card Flash Card ATA Card
Memory RAM ROM
Parameter 1 data/drive
Intelligent function
1 data/drive
module parameter
1 1 1 1
Program
2 3
Device comment
Device initial value
5 4
File register
1 data/CPU
Local device
module
Debug data
Failure history data
6
PLC user data

: Needed, : Stored, : Not stored

REMARK
1: Boot the program memory to execute a program.
2: Data can be written by operating from the GX Developer. Device comments
cannot be used in an instruction of a sequence program.
3: The read from a sequence program requires several scans.
4: A sequence program allows the read only. No data can be written through
access from a sequence program.
5: A standard RAM hold a single file.
6: Data can be written or read with the following instructions:
• S.FREAD (allows the batch read from a specified file on a memory card)
• S.FWRITE (allows the batch write to a specified file on a memory card)
The table below shows file names and extensions of data files stored in the High
Performance model QCPU or on a memory card.
Data name File name
Parameter PARAM.QPA
Intelligent function module
IPARAM.QPA
parameter
Program .QPG
Device comment .QCD
Device initial value .QDI
File register .QDR
Local device .QDL
Debug data .QTD
Failure history data .QFD
PLC user data .
The portions can be named by the user.

6-4 6-4
6 MEMORIES AND FILES HANDLED BY HIGH PERFORMANCE MODEL QCPU
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(3) Drive Number

(a) The High Performance model QCPU uses drive numbers to control
standard RAMs, standard ROMs, and memory cards. GX Developer
specifies a selected memory (standard RAM, standard ROM or memory
card) to read/write parameters and program files from to the High
Performance model QCPU. There is no need to specify the drive number
when using the GX Developer.

(b) The table below shows the drive numbers used to specify a selected
memory (program memory, standard RAM, standard ROM or memory card)
when using a sequence program. The drive number must be used to
specify a selected memory when the read/write is made through access
from a serial communication module.

Memory Drive Number

Program memory 0
High Performance model
Standard RAM 3
QCPU built-in
Standard ROM 4
Memory card (RAM) SRAM card 1
Flash card 2
Memory card (ROM)
ATA card 2

(4) Memory Capacity and Formatting

The following table shows the size of a memory of the High Performance model
QCPU and whether to format a memory.

Q02CPU Q02HCPU Q06HCPU Q12HCPU Q25HCPU Whether to Format

Standard RAM 64 kbyte 128 kbyte 256 kbyte 1
28 k steps 28 k steps 60 k steps 124 k steps 252 k steps
Program memory 1
(112 kbyte) (112 kbyte) (240 kbyte) (496 kbyte) (1008 kbyte)
Standard ROM 112 kbyte 112 kbyte 240 kbyte 496 kbyte 1008 kbyte 2
Required.
SRAM Q2MEM-1MBS: 1 Mbyte
card (Use the GX Developer or
Q2MEM-2MBS: 2 Mbyte
a personal computer)
Memory Q2MEM-2MBF: 2 Mbyte
Flash card Not required.
card Q2MEM-4MBF: 4 Mbyte
Q2MEM-8MBA: 8 Mbyte
Required.
ATA card Q2MEM-16MBA: 16 Mbyte
(Use the GX Developer)
Q2MEM-32MBA: 32 Mbyte
1: If the memory is in the initial status or it is unstable due to low voltage of the battery (Q6BAT, Q7BAT),
formatting automatically starts upon power-on or resetting of the PLC. However, format with GX Developer
before starting operation.
2: The standard ROM is used in ROM formation of the program memory and therefore formatting is
unnecessary for it.

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6 MEMORIES AND FILES HANDLED BY HIGH PERFORMANCE MODEL QCPU
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6.2 Program Memory

(1) What is the Program Memory?

(a) The High Performance model QCPU's program memory is an internal RAM
that stores programs executed by the High Performance model QCPU.

(b) The data storage in the program memory is backed up by High

Performance model QCPU's built-in batteries (Q6BAT, Q7BAT).

(c) Before using the High Performance model QCPU for the first time, the
program memory must be formatted by GX Developer.
For details on the formatting procedure by GX Developer, refer to GX
Developer manuals.

(2) Data Storage

Data on parameters and programs can be stored in the program memory. For the
types of data stored in the program memory, see Section 6.1.

(3) Format
(a) Formatting
Choose "Online" "Format PLC memory" to open the Format PLC
memory dialog box. Select "Program memory/Device memory" from the
Target Memory list box.

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6 MEMORIES AND FILES HANDLED BY HIGH PERFORMANCE MODEL QCPU
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(b) Memory capacity after formatting

The memory capacity of the program memory after formatting (when the
user setting area of the system area is not set) is indicated in Table 6.1.
When the user setting area of the system area is set, the value in Table 6.1
decreases by the set capacity.

Table 6.1 Memory capacity after formatting 1

2
CPU model Name Memory Max. Number of Files Stored
Q02CPU 28 k steps (114688 bytes) to 13 k steps (53248 bytes) 28 files
Q02HCPU 28 k steps (114688 bytes) to 13 k steps (53248 bytes) 28 files
Q06HCPU 60 k steps (245760 bytes) to 45 k steps (184320 bytes) 60 files
Q12HCPU 124 k steps (507904 bytes) to 109 k steps (446464 bytes) 124 files
3
Q25HCPU 252 k steps (1032192 bytes) to 237 k steps (970752 bytes) 252 files

(c) Precautions for formatting

1) Formatting of program memory
The High Performance model QCPU program memory can only be
used after being formatted by GX Developer.
When formatting the program memory, designate whether or not a
system area is to be allocated for user settings and multiple-block
online change. (0 to 15 k steps (in 1 k-step units) can be allocated for
the user setting system area.)
0 to 15k steps
System area
(Unit of 1k step)

User files

Parameters, Memory capacity after formatting

programs etc.

2) System area setting

If RS-232 and USB interfaces are connected to GX Developer, the
system area user setting data is used for registering monitor data from
the GX Developer connected to serial communication module.
The allocation of space for system and user-defined areas will make it
much easier to perform monitoring operation by operating from the GX
Developer connected to the serial communications module.
Although the designation of a user setting area speeds up monitoring
from the GX Developer connected to serial communication module, it
also reduces the amount of space available for user files.

REMARK
1) 1: This table shows an example in which 0 k step is allocated for a system area.
2) 2: In computing the memory capacity, 1 step is equal to 4 bytes.
3) 3: Maximum number of executable program is 124. More than 124 programs
can not be executed.

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6.3 About the Standard ROM

(1) What is the standard ROM?

(a) The standard ROM is used for the ROM operation of the High Performance
model QCPU.

(b) Programs stored in the standard ROM can be used after being read
(boosted) to the program memory in accordance with the setting made at
the "Boot file" tab screen in the “(PLC) Parameter" dialog box.

(c) The standard ROM does not need formatting.

(d) Writing into standard ROMs is performed with the GX Developer's on-line
"PLC Writing" (flash ROM) of "Create Program Memory ROM" (see Section
6.6.1.) It is also possible to write in a standard ROM from the memory card
with "Automatic writing in the standard ROM" without using GX Developer.

POINTS
(1) Before writing data to a standard ROM, all previous data stored in the standard
ROM are erased. Therefore, all data stored in a standard ROM must be read
out and copied into the program memory at first. There, read through and
modify it as necessary. Then, write the modified data back into a standard
ROM at a time. Please note that an error may occur if data stored in the
standard ROM is used in a sequence program, with data being written in the
standard ROM.
(2) For details on the formatting procedure by GX Developer, refer to GX
Developer manuals.

(2) Data Storage

A standard ROM stores data such as parameters and programs.
See Section 6.1 for the data to store in the standard ROM.

(3) Memory Capacity

Table 6.2 shows the memory capacity of standard ROMs.

Table 6.2 Memory Capacity

2
Model Name Memory Capacity Max. Number of Files Stored
Q02CPU 28 k steps (114688 bytes) 28 files
Q02HCPU 28 k steps (114688 bytes) 28 files
Q06HCPU 60 k steps (245760 bytes) 60 files
Q12HCPU 124 k steps (507904 bytes) 124 files
Q25HCPU 252 k steps (1032192 bytes) 252 files

REMARK
In computing a memory capacity, 1 step is equal to 4 bytes.

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6.4 About the Standard RAM

(1) What is the standard RAM?

(a) The standard RAM is used when using file registers or local devices without
a memory card being mounted on the High Performance model QCPU.

(b) The standard ROM must be formatted by using GX Developer when using
the High Performance module QCPU for the first time. Refer to the GX
Developer manual for details on the formatting method.

(c) Data can be written into the standard RAM by using the online function:
"Write to PLC."

(2) Stored Data

A standard RAM holds two files: file register file and local device file. Any other
files cannot be written into a standard RAM.
(The standard RAM cannot store other files than the file register and local device
files.)

(3) Formatting
(a) Formatting
To format a standard RAM, choose "Online" "Format PLC memory" and
then select "Standard RAM" in the "Target memory" list box. See Section
6.2 for the PLC Memory Format dialog box.
(b) Memory capacity after formatted
Table 6.3 shows the memory capacity of standard RAM.

Table 6.3 Memory Capacity

Number of Files Stored
CPU Type Serial No. Number of Files Stored
File Register Local Device
Q02CPU — 32 k words (64 kbytes) 1 1
"04011"
32 k words (64 kbytes)
or earlier
Q02HCPU 1 1
"04012"
64 k words (128 kbytes)
or later
"04011"
32 k words (64 kbytes)
or earlier
Q06HCPU 1 1
"04012"
64 k words (128 kbytes)
or later
"02091"
32 k words (64 kbytes)
or earlier
Q12HCPU 1 1
"02092" 128 k words
or later (256 kbytes)
"02091"
32 k words (64 kbytes)
or earlier
Q25HCPU 1 1
"02092" 128 k words
or later (256 kbytes)

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(4) Precautions
When setting file registers and local devices in the standard RAM, memory
capacity is secured in 1024 byte units for the Q12HCPU/Q25HCPU that have the
serial number whose upper five digits are “02092” or later.
Memory capacity is secured in 512 byte units for the Q12HCPU/Q25HCPU,
Q02CPU, Q02HCPU and Q06HCPU that have the serial number whose upper
five digits are "02091" or earlier.

POINT
When specifying file registers using the serial access method (ZR ) with
commands that access the standard RAM on "02092" and subsequent High
Performance model QCPUs, the amount of time required for processing each
command from "02091" and previous High Performance model QCPUs will be
prolonged. (QnCPU: Average 0.65µs, QnHCPU: Average 1.1µs)
The processing time when the MOV command is used is shown below.

Q12HCPU Q02CPU
Command “02092” “02091” “02092” “02091”
or later or earlier or later or earlier
MOV K0 R0 0.11 0.11 0.26 0.26
MOV K0 ZR0 3.55 2.88 7.71 6.64

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6.5 Memory Card

(1) Memory card

(a) A memory card is used to expand the size of an internal memory of the High
Performance model QCPU.

(b) There are three types of memory cards for use in the High Performance
model QCPU: SRAM card, Flash card, and ATA card.

POINTS
(1) Before the memory card can be used for the first time, the memory card must
be formatted by GX Developer.
For details on the formatting procedure by GX Developer, refer to the GX
Developer manuals.
(2) Before writing data into a Flash card, all previous data stored on the Flash card
are erased. For this reason, to write data into the Flash card, you must first
read and copy all previous data stored in the Flash card before writing
necessary data. Please note that an error may occur if data stored in the Flash
card is used in a sequence program, with data being written on the Flash card.

(2) Stored Data

A memory card holds parameter and program data. See Section 6.1 for the
types of data stored in a memory card.

(3) Format
The SRAM card and ATA card must have all been formatted.
Since the SRAM card and ATA card purchased are not yet formatted, use them
after formatting with GX Developer.
(The Flash card need not be formatted.)

(a) Execution of formatting

To format the card, choose "Online" _ "Format PLC memory" and then
select "Memory card (RAM)" or "Memory card (ROM)" on GX Developer.
(Refer to Section 6.2 for the Format PLC memory screen.)

POINT
Do not format ATA card using other than GX Developer.
(If it is formatted using format function of Windows , the ATA card may not be
R

usable with set in a CPU module.)

(b) Precautions
When the SRAM card or ATA card is formatted, the "memory card
information area" is automatically secured, reducing the space by the size
of the "memory card information area".

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(4) Memory capacity

Table 6.4 indicates the the memory capacities of the memory cards.

Table 6.4 Memory Capacity

Memory Card Model
Type Memory Capacity Number of Files Stored
Name
Q2MEM-1MBS 1011.5 kbyte 1 256 files
SRAM card
Q2MEM-2MBS 2034 kbyte 1 288 files
Q2MEM-2MBF 2035 kbyte 288 files
Flash card
Q2MEM-4MBF 4079 kbyte 288 files
Q2MEM-8MBA 7940 kbyte 1 512 files
ATA card Q2MEM-16MBA 15932 kbyte 1 512 files
Q2MEM-32MBA 31854 kbyte 1 512 files

1: The indicated memory capacities of the SRAM card and ATA card are those
after formatting.

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6.6 Writing Data to the Standard ROM or the Flash Card

6.6.1 Writing Data to the standard ROM or to the Flash card using GX Developer

The "write to PLC" function in the GX Developer Online menu does not allow the user
to write files into a standard ROM or on a Flash card. For writing files to a standard
ROM or to a Flash card by operating from GX Developer, GX Developer Online menu
provides two functions: "Write the program memory to ROM" and "Write to PLC (Flash
ROM)."

(1) Write the program memory to ROM

(a) The "Write the program memory to ROM" function allows a batch of files
stored in a program memory to be written to a standard ROM or a Flash
card. This function is used to debug the programs stored in the program
memory.

(b) When the "Write a memory to ROM" function is executed, all files stored in
the standard ROM or Flash card are erased before a batch of files stored in
a program memory are written. No files can be added to the standard ROM
or Flash card.

(c) The memory capacity of a standard ROM or Flash card is the same as that
of a program memory. A memory of a larger size than the memory capacity
of a program memory cannot be used.

(d) To execute the "Write the program memory to ROM" function, set the length
of GX developer's time-check to 60 seconds or longer. Shorter time-check
may cause a time-out on the GX Developer side. To execute the "Write the
program memory to ROM" function via the CC-Link network by operating
from a GX Developer at a local station, set the length of CC-Link's CPU
monitoring time (SW0A) to 60 seconds or longer. The default is 90
seconds. Use the default value when making the setting.

(2) Write to PLC (Flash ROM)

(a) The "Write to PLC (Flash ROM)" function is used to write a batch of files
specified by GX Developer to a standard ROM or Flash card.

(b) The "Write to PLC (Flash ROM)" function can fill all available space in a
standard ROM or Flash card. If a program that contains a small number of
steps is written to a Flash card, it will take long to fill the Flash card with
programs. When a RS-232 interface is mounted at Q2MEM-4MBF, a baud
rate of 115.2k bps takes about 14 minutes. To write data to a Flash card,
increase a baud rate or use a USB interface. If the "Write to PLC (Flash
ROM)" function is executed from a local station, communication time will be
longer.
(c) To execute the "Write to PLC (Flash ROM)" function, set the length of
GX Developer's time-check to 60 seconds or longer. Shorter time-check
may cause a time-out on the GX Developer side. To execute the "Write to
PLC (Flash ROM)" function via the CC-Link network by operating from GX
Developer at a local station, set the length of CC-Link's CPU monitoring
time (SW0A) to 60 seconds or longer. The default is 90 seconds. Use the
default value when making the setting.

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(d) When the "Write to PLC (Flash ROM)" function is executed, all files stored
in the standard ROM or on the Flash card are erased before a batch of files
specified by GX Developer are written. No files can be added to the
standard ROM or Flash card. To add new files to old files, read all the old
files from High Performance model QCPU and write them again into the
High Performance model QCPU.

(e) The "Write to PLC (Flash ROM)" function can be executed when the High
Performance model QCPU is in RUN status. However, for the following
cases, execute the "Write to PLC (Flash ROM)" function after the High
Performance model QCPU enters into STOP status.
1) The file registers of the Flash card is used in a sequence program.
2) The file registers are used in a sequence program by setting the file
register to "set not to use" in the PLC parameter.
If the "Write to PLC (Flash ROM)" function is executed when the High
Performance model QCPU is in RUN status, an error may occur and the
High Performance model QCPU may stop running.

(f) While the "Write to PLC (Flash ROM)" function is executed, the read/write
cannot be made from other modules. This may cause a time out on the side
of other modules.

POINT
When the High Performance model QCPU is expanded to STOP status and Write
to PLC (Flash ROM) is being performed, do not set it in RUN status.
RUN cannot be performed normally during Write to PLC (Flash ROM).
Perform RUN after Write to PLC (Flash ROM) is completed.

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6.6.2 Automatic write to standard ROM (Auto Download all Data from Memory card to
Standard ROM)

"Automatic write to standard ROM" function writes the parameters and sequence
programs stored on the memory card into the High Performance model QCPU's
standard ROM without using GX Developer. (The writing of parameters and sequence
programs into the memory card is performed by GX Developer (Version 6 or later.)
With this function, the parameters and sequence programs are booted from the
memory card to the program memory, and the booted parameters and sequence
programs are then written from the program memory into the standard ROM, as shown
below.
High Performance model QCPU
Memory card Program memory

• Parameters • Parameters
Boot
• Sequence • Sequence
programs programs

Writing
Standard ROM

• Parameters
• Sequence
programs

"Automatic write to standard ROM" is used to change the High Performance model
QCPU programs that perform ROM operations with the standard ROM.
Overwriting in the standard ROM is performed by GX Developer, but using "Automatic
write to standard ROM" moves the memory card in which the parameters and the
changed programs are written to the High Performance model QCPU, so that they are
written into the standard ROM from the memory card.
"Automatic write to standard ROM" is available with a combination of the High
Performance model QCPU with the upper five digits of its serial No. as "02092" or later
and GX Developer Version 6 or later.
If the memory card, in which "Automatic write to standard ROM" is set, is mounted in the
High Performance model QCPU whose the upper five digits of its serial No. is the
"02092," or later the boot operations are performed from the standard ROM.
The followings are necessary for "Automatic write to standard ROM".
• Set "Automatic write to standard ROM settings" in the “(PLC) Parameters dialog box".
• Memory card on which the parameters and programs are stored.
• Memory card mounted onto the High Performance model QCPU and the High
Performance model QCPU switch settings.

POINT
Perform "Automatic write to standard ROM" after the High Performance model
QCPU control is suspended.
A suspension error (BOOT OK (Error Code: 9020)) occurs when automatic write to
standard ROM is completed.
It is necessary to reset the High Performance model QCPU or restart, the power
supply to the PLC after "Automatic write to standard ROM" is completed.

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(1) Execution procedure for "Automatic write to standard ROM"

Observe the following procedure for "Automatic write to standard ROM".

(a) Operations with the GX Developer (Settings for "Automatic write to

Standard ROM")
1) Check "Auto Download all Data from Memory card to Standard
ROM"at the "Boot file" tab screen in the “(PLC) Parameter" dialog box.
Set the parameters and programs to be booted.
(Set the "Transfer from" to "Standard ROM".)
Check "Auto Download all Data from
Memory card to Standard ROM"

Set the "Transfer from"

to the "Standard ROM"

2) Store the setup parameters and the programs to be booted in the

memory card.

(b) Operations with High Performance model QCPU (Automatic write to

standard ROM)
1) Switch off the power supply to the PLC.
2) Mount the memory card that contains the parameters and programs to
be booted onto the High Performance model QCPU.
3) Set the parameter valid drive to the mounted memory card with the
CPU's dip switches as follows:
• When a SRAM card is mounted: SW2 : ON, SW3 : OFF
• When a Flash/ATA card is mounted: SW2 : OFF, SW3 : ON
4) Switch on the power supply to the PLC.
Boot the file specified with the parameter to the program memory from
the memory card. Write the contenst of the program memory to the
standard ROM when the boot is completed.
5) "BOOT" LED will flicker when automatic write to standard ROM is
completed, and the High Performance model QCPU will assume a
suspension error status.
6) Switch off the power supply to the PLC.
7) Remove the memory card, and then set the parameter valid drive to
the standard ROM with the CPU's dip switches as follows:.
• Standard ROM: SW2 : ON, SW3 : ON

(c) The parameters and programs will be booted from the standard ROM to the
program memory to enable actual operations when the PLC is switched on.

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(2) Precautions
This section indicates the precautions for performing "Automatic write to standard
ROM"

(a) If the file to be booted from the memory card shares the same name as a
file in the program memory, the memory card data will be overwritten. Also,
if the file to be booted from the memory card does not share the same
name as a file in the program memory, it will be added to the program
memory. The "FILE SET ERROR (Error code: 2401)" will occur at this time
if the capacity of the program memory is exceeded.

(b) It is possible to select whether to perform the boot after the program
memory has been cleared, or perform the boot without clearing the program
memory when booting from the memory card to the program memory.
Performing the boot after the program memory has been cleared when
"Automatic write to standard ROM" prevents the program memory from
overflowing during the boot.

(c) The "Auto Download all Data from Memory card to Standard ROM" setting at
the "Boot file" tab screen is valid only when the High Performance model
QCPU parameter valid drive is to "Memory Card".
The "Auto Download all Data from Memory card to Standard ROM" setting
at the "Boot file” tab screen is disabled if the parameter valid drive is set to
"Program Memory" or "Standard ROM".

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6.7 Executing Standard ROM/Memory Card Programs (Boot Run)

(1) Executing High Performance model QCPU programs

(a) The High Performance model QCPU executes programs stored in the
program memory.
The High Performance model QCPU does not perform operation of
programs stored in the standard ROM or memory cards.
(b) To execute programs stored in the standard ROM and memory card,
designate file names to be booted (read) to program memory at the "Boot
file" tab screen in the “(PLC) Parameter" dialog box.
Programs with file names designated on the "Boot file" tab screen are
booted from the standard ROM/memory card to the program memory and
executed in the order set on the "Boot file" tab screen when the PLC is
powered ON or the High Performance model QCPU is reset.

(2) Preparation for Boot Run

Perform the following steps in preparation for boot run:
(a) Create a program using GX Developer.
Create a program used for the boot run.
(b) Select a boot file using GX Developer.
Select a boot file at the "Boot file" tab screen in the “(PLC) Parameter"
dialog box.

(c) Make the High Performance model QCPU hardware setting.

Set High Performance model QCPU Dip switches to specify a parameter-
driven drive.
(d) Insert a memory card.
Insert a memory card in a slot if you want to store parameters or programs
on the memory card during the boot run.
(e) Write parameters and programs using GX Developer.
Write parameters on the parameter-driven drive. Write a program to the
memory specified at the "Boot file" tab screen in the “(PLC) Parameter"
dialog box.
(f) Execute a program.
Reset the High Performance model QCPU with the RESET/L.CLR switch.
After the boot run is completed in the specified memory, the "BOOT" LED
lights up.

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(3) Changing Program Files While the High Performance model QCPU
is in the Run Status.
(a) While the High Performance model QCPU is in RUN status,
addition/change/deletion of program files from the standard ROM or
memory card to the program memory can be made by using any of the
following instructions in a sequence program.
• PLOAD (Loading program from memory card)
• PUNLAOD (Unloading program from program memory)
• PSWAP (Load + Unload)
For details on the PLOAD, PUNLAOD and PSWAP instructions, refer to the
QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions).

(b) Even if a program file is changed while the High Performance model QCPU
is in RUN status, the settings specified at the "Program" tab screen the
“(PLC) Parameter" dialog box will remain unchanged. When the High
Performance model QCPU is in STOP status, the settings made at the
"Program" tab screen in the “(PLC) Parameter" dialog box must be adjusted
to any changes (addition, change or deletion of program names) made
when the High Performance model QCPU was in RUN status.
If no adjustment is made at the "Program" tab screen in the “(PLC)
Parameter" dialog box, an error may occur when the High Performance
model QCPU enters into RUN status from STOP status.

(4) Precautions for Executing Programs in the Standard ROM/Memory

Card
(a) For boot run, store parameters (PLC parameters) of the boot file setting in a
standard RAM or memory card. If parameters are stored in a program
memory and a parameter valid drive is set to "Program Memory", the boot file
setting made in the “(PLC) Parameter" dialog box is ignored. As a result, a
boot run is not performed when power is turned on or when the PLC is reset.

(b) If programs are written in the program memory during RUN status while a
boot run is performed from a memory card (RAM), any change made will be
reflected in the programs stored on the memory card (RAM). For details on
the writing of programs during RUN status, see Section 7.10.

(c) If programs are written in the program memory during RUN status while a
boot run is performed from a standard ROM/memory card (ROM), any
change made will not be reflected in the programs stored in the standard
ROM or the memory card (ROM).
(d) At the "Boot file" tab screen in the “(PLC) Parameter" dialog box, set the
maximum number of boot files to the number of files stored in the program
memory. The number of boot files will be decreased by one in the following
cases where:
• A header is specified.
• A PLC parameter in which a boot file setting is maded is booted.
(e) If boot operation is made under the following conditions, it may take
maximum 200 ms for each 1k steps (4kbyte) during boot sequence.
• To boot from an ATA card.
• To boot from standard ROM with an ATA card mounted.

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(f) If the program memory is changed when a sequence program is written in

the program memory and PLC is turned on or reset, boot operation mode
may be selected.
If the "BOOT" LED is lit on the front panel of the High Performance model
QCPU, the boot operation mode is selected.

Cancel the boot operation mode with the following procedure.

1) Write parameters, in which no boot file settings are made, into the
program memory.
2) Using the DIP switch of the CPU module, set "program memory" for the
valid drive setting. (DIP switch setting: SW2: OFF. SW3: OFF)
3) Turn off and on the PLC or reset the CPU module.
(After the procedure, the settings given in steps 1) and 2) become valid.)

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6.8 Program File Configuration

(1) Program File Configuration

(a) Program files consist of a file header, an execution program, and allocate
memory allocated for "Write during RUN".
Program file configuration
34 steps
File header
(default)

Execution program
The area is allocated in file size unit.

Memory allocated for

500 steps
"Write during RUN"

(b) As shown below, the size of a program stored in the High Performance
model QCPU includes all the above components.
1) File header: The file name, file size, and file creation data, etc., are
stored in this area.
The file header size changes between 25 and 35 steps (100 and 140
bytes) depending on the device setting in the PLC parameter dialog
box.
2) Execution program: The created program is stored in this area.
1 step is 4 bytes.
3) Memory allocated for "Write during RUN": This area is used when write
during RUN that write during RUN increases the number of steps is
executed from GX Developer.
Default value is set to 500 steps (2000 bytes).
The number of memory allocated for "Write during RUN" can be
changed using the online write to PLC program.
The number of memory allocated for "Write during RUN" can be
redefined if the number of memory allocated is not sufficient for write
during RUN. (See Section 7.12.1.)

(2) The size of the program displayed by GX Developer

During programming by GX Developer, the program size (the total of the file
header size and the number of created program steps) is displayed as the
number of steps as shown below.
During programming, the size of the program created is displayed.
"Number of steps used" display

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PRECAUTIONS

1) The program capacity displayed during programming with GX Developer is the

sum of file header and executed program capacities and does not include the
capacity of steps secured for write during RUN.

(Example) The capacity of the program whose executed program part has 491
steps is displayed on GX Developer as shown below. (The file header
is fixed to 34 steps.)
File header 34 steps

Executed program 491 steps

Display on GX Developer:
34 steps + 491 steps = 525 steps

Status of File on GX Developer

2) Since a file is stored on the program memory in file size unit, the program
capacity displayed during programming with GX Developer may differ from the
capacity of the program file on the High Performance model QCPU.
Refer to Section 6.9.3 for details.

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6.9 GX Developer File Operation and File Handling Precautions

6.9.1 File operation

GX Developer online operation allows the files which are stored in the program
memory, standard ROM and memory card, to perform the file operations in the table
below.
However the available file operations vary according to the presence or absence of a
password (registered by GX Developer), the High Performance model QCPU "write
protect" switch setting status, and the High Performance model QCPU RUN/STOP
status.

Table 6.5 File Operations from GX Developer

Operation
File Operation Enabled/Disabled Operation Description
A B C D
Read from PLC Files are read from concerned memory.
Files are written to the program memory or
Write to PLC
SRAM card.
Verify the target memory and the GX Developer's
Verify with PLC
file.
Write the program Write a batch of files from the program memory
memory to ROM to the standard ROM or Flash card.
Write to PLC (Flash Write a batch of files from GX Developer to the
ROM) standard ROM or Flash card.
Delete PLC data A file stored in memory is deleted.
Format PLC memory Memory formatting is executed.
Memory files which are no longer contiguous
Arrange PLC memory
are re-organized to make them contiguous.
Write during RUN in Write changes made in the ladder mode into the
the ladder mode program memory.

: Execution enabled, : Execution enabled with some restrictions, : Execution disabled

REMARK
1) The codes (A, B, C, D) used at the "operation enabled/disabled" item in the above
table are explained below.
Table 6.6 Operation enabled/disabled
Code Description
A When "write prohibit" password is registered in a file
B When "read/write prohibit" password is registered in a file
C When the High Performance model QCPU's "system protect" switch is ON
D When High Performance model QCPU RUN status is in effect

2) : Execution is allowed only when the passwords match.

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6.9.2 File handling precautions

(1) Power OFF (or reset) during program operation

(a) If power is switched OFF during a file operation which will not cause a file
shift, the memory data will not be lost.

(b) If files and data in the memory of the High Performance model QCPU is
backed up using the battery (Q6BAT), the program memory data will not be
lost when the power is switched OFF during the following file operations
which cause a file shift.
• File size change
• PLC memory arrangement
• New file creation
• Writing a program file during the RUN status
• Writing a program in excess of memory allocated for 'Write during RUN'
• Reading a file with the PLOAD instruction
Files stored in the memory card will not be lost unless the memory card is
removed from the High Performance model QCPU while the power is OFF.

POINT
If the above operations are done, the half-processed data will be stored in the High
Performance model QCPU internal memory, and will be restored when power is
switched ON again. A battery backup is required in order to save internal memory
data for this reason.

(2) Simultaneous write to the same file from multiple GX Developers

The High Performance model QCPU does not allow access from other GX
Developers to the file being written.
It does not allow write from other GX Developers to the file being accessed,
either.
Therefore, to perform write from multiple GX Developers to the same file, start
the processing of next GX Developer after the processing of current GX
Developer is completed.

(3) Simultaneous access to different files from multiple GX Developers

The High Performance model QCPU allows simultaneous access from other GX
Developers to up to 10 different files of the same CPU module.

REMARK
For details on the PLOAD instruction, refer to the QCPU (Q Mode)/QnACPU
Programming Manual (Common Instructions).

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6.9.3 File capacity

The file size differs with the types of files used. When a program memory, standard
RAM, standard ROM, and memory card are used, calculate the size of a file by
referring to the table 6.7 shown below.

Table 6.7 List of File Capacity

Function Estimated File Size (in bytes)
Drive header 64
Default: 564 (increased by the parameter setting)
For Reference:
Boot setting to 70 + (18 (Number of files) )
With the MELSECNET/H setting to maximum 4096 / units increased
Parameter
With Ethernet setting to maximum 922 / units increased
With CC-LINK setting to maximum 251 / units increased
With remote password setting to 64 + 20 + (number of target modules 10), increased to up
to 164
Sequence program 136 1+ (4 ((number of steps) + (number of steps secured for write during RUN))
74 + (Total of comment data size of each device)
• Comment data size of a device = 10 + 10250 a + 40 b
Device comment
• a: quotient of (Number of device points) / 256
• b: remainder of (Number of device points) / 256
66 + 44 n+2 (Total number of device points specified in the device initial value setting)
Device init
• n : specified number of device initial values
User setting area When set at the time of formatting (0 to 15k)
Multiple-block online
When set at the time of formatting (0/1.25k/2.5k)
change setting
File register 2 (Number of file register points)
362 + (20 + 2 (Number of word device points) + (Number of bit device pints) / 8 ) (Number
Sampling trace data
of traces) + 12 (Device range) 2
Failure history data 72 + 54 (Number of failures stored)
70 + 6 (Type of specified device) + 2 ( (total number of M and V points) / 16 + (D points) + 18
(Total points of T, ST and C) / 16) (number of programs) 1
• Symbols "M, V, D, T, ST, and C" stand for the following devices:
M: internal relay
Local device V: edge relay
D: data register
T: timer
ST: relative timer
C: counter
1: 136 is the default (increases depending on the parameter setting).
2: Round down the fractional portions of (bit devices)/8, (total number of M and V points)/16, and (total number of T, ST
and C points)/16.

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6.9.4 Memory capacity for files

The memory capacity for files indicates a capacity after the files have been written to
the memory area.
For the files transferred from the memory card to the program memory in boot
operation, note that the secured memory capacity changes after transfer.

(1) File size unit

When files are written to the memory area, the storage capacity unit changes
depending on the CPU module and memory area to which the files will be
written. This unit is called the file size unit.
(a) File size units classified by memory areas
The following table indicates the file size units classified by the CPU
module and memory area to which files will be written.

Memory Area
File Size Unit of Program Memory/Standard
ROM/Flash Card 1
CPU Module Type
Q02CPU
Q02HCPU 128 steps/512 bytes 2
Q06HCPU
Q12HCPU 256 steps/1024 bytes 2
Q25HCPU 512 steps/2048 bytes 2
1: The file size unit of the Flash card applies to the case where the
program memory contents are written to the Flash card via the CPU
module using GX Developer.
2: 1024 steps/4096 bytes for the CPU module whose first five digits of
serial No. are "04121" or earlier.
(b) File size units classified by memory cards

Type Memory Card Model Name Memory Capacity

Q2MEM-1MBS 512 bytes
SRAM card
Q2MEM-2MBS 1024 bytes
Q2MEM-2MBF 1024 bytes
Flash card
Q2MEM-4MBF 1024 bytes
Q2MEM-8MBA 4096 bytes
ATA card Q2MEM-16MBA 4096 bytes
Q2MEM-32MBA 2048 bytes

1: The file size unit of the Flash card applies to either of the following
cases.
1) Where files are written to the Flash card via the CPU module using
GX Developer.
2) Where files bypass the CPU module and are written to the Flash
card using GX Developer.

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(2) Memory capacity calculation example

When files are written to the memory area, the storage capacity unit changes
depending on the CPU module and memory area to which the files will be
written. This unit is called the file size unit.
(a) Conditions
1) Write target CPU module: Q25HCPU
2) Written files
File Name File Capacity
PARAM. QPA (parameter file) 564 bytes
MAIN. QPG (sequence program) 525 steps/2100 bytes 1
1: Indicates the program capacity (file header + executed program)
displayed on GX Developer. (Refer to Section 6.8.)
3) Steps secured for write during RUN: 500 steps/2000 bytes

(b) Memory capacity calculation

Memory capacity calculation is based on the file size unit of the write target
CPU module. In the example, the file size unit of the Q25HCPU is 512
steps/2048 bytes according to Section (1).
1) Parameter file capacity calculation
The parameter file capacity is 564 bytes. However, since the parameter
file is stored in the file size unit in the program memory, it occupies 512
steps/2048 bytes.
<In program memory>

Parameter Parameter
564 bytes
file file

Occupies 2048 bytes

(512 steps).

2) Program capacity calculation

The program capacity is the sequence program capacity + steps
secured for write during RUN.
In the example, the program capacity is 525 steps + 500 steps = 1025
steps. However, since the program file is stored in the file size unit in the
program memory, it occupies 1536 steps/6144 bytes.
<In program memory>

Sequence Sequence
525 steps
program program

Steps secured Steps secured Occupies 1536 bytes

for write during 500 steps for write during (6144 steps).
RUN RUN

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3) Calculation result
File name File capacity Memory capacity
512 steps
PARAM.QPA 564 bytes
(2048 bytes)
Sequence program
525 steps
capacity
1536 steps
MAIN.QPG Steps secured for write
500 steps (6144 bytes)
during RUN
Total 1025 steps
2048 steps
Memory capacity total
(8192 bytes)

POINT
(1) The file, which was executed in the CPU whose serial No. is "04122" or later,
may not be executed in the CPU whose serial No. is "04121" or earlier.
(2) About combination of write to PLC and GX Developer
The following table indicates the combinations of the CPU module and GX
Developer versions used when files are read from the CPU module to GX
Developer and written to the other CPU module.
Legend : Write to PLC enabled : Restrictions on write to PLC

Write Source CPU GX Developer version8 GX Developer version7

Files executed in CPU Files executed in CPU Files executed in CPU Files executed in CPU
Write whose serial No. is whose serial No. is whose serial No. is whose serial No. is
Destination CPU "04122" or later "04121" or earlier "04122" or later "04121" or earlier
Serial No. "04122" or
2 2
later
Serial No. "04121" or
1 1 2 2
earlier
1: Since the file size units differ, the files may not be stored into the CPU depending on the file capacity.
2: Unless the steps secured for write during RUN is decreased, the files may not be stored into the CPU
depending on the file capacity.

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 7 FUNCTION
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7 FUNCTION
Function of High Performance model QCPU module is as follows:
7.1 Function List
Functions of High Performance model QCPU are listed below:
Item Description Reference section
Constant scan This function executes the program in a set time interval regardless of the program scan time. Section 7.2
Latch function This function maintains the device data when performing the reset operation during power off. Section 7.3
Output status selection function for
This function selects the output Y status (output before STOP/output after the calculation execution)
transition from STOP status to RUN Section 7.4
when the CPU module is set from STOP status to RUN status.
status
Clock function This function executes the CPU module internal clock. Section 7.5
Remote operation This function operates the CPU module from a remote place. Section 7.6
Remote RUN/STOP This function stops and starts operating the CPU module. Section 7.6.1
Remote PAUSE This function stops the CPU module operation while retaining the output (Y) of the CPU module. Section 7.6.2
Remote RESET This function resets the CPU module when the CPU module is in a STOP status. Section 7.6.3
Remote latch clear This function clears the latch data of the CPU module when the CPU module is in a STOP status. Section 7.6.4
Input response time selection for input The response time of the input module/ Composite I/O module compatible with Q Series can be
Section 7.7.1
module compatible with Q Series selected from 1 ms, 5 ms, 10 ms, 20 ms and 70 ms with this function. (Default: 10 ms)
Input response time selection for high
The response time of the high speed input module compatible with Q Series can be selected from
speed input module compatible with Section 7.7.2
0.1 ms, 0.2 ms, 0.4 ms, 0.6 ms and 1 ms with this function. (Default: 0.2 ms)
Q Series
Input response time selection for
The response time of the interrupt module compatible with Q Series can be selected from 0.1 ms,
interrupt module compatible with Q Section 7.7.3
0.2 ms, 0.4 ms, 0.6 ms and 1 ms with this function. (Default: 0.2 ms)
Series
This function sets whether the output to the Q series compatible output module, hybrid I/O module
Error-time output mode setting Section 7.8
or intelligent function module will be cleared or held when the CPU module results in a stop error.
Hardware error-time CPU operation This function sets whether the operation of the CPU module will be stopped or continued when the
Section 7.8
mode setting hardware error of the intelligent function module occurs.
Switch setting of intelligent function Use this function for various settings of the intelligent function module. (Refer to each intelligent
Section 7.10
module compatible with Q Series function module for the details of the setting.)
This function monitors the status of programs and devices on the CPU module by operating from
Monitoring function Section 7.11
the GX Developer.
Set monitor conditions This function monitors using a fine timing of the CPU module. Section 7.11.1
This function monitors and/or tests the local devices of the designated program using the GX
Monitor/test local Devices Section 7.11.2
Developer.
7 Turn ON/OFF external I/O This function forcibly turns the external I/O of the CPU module on or off from the GX Developer. Section 7.11.3
Write during RUN This function writes programs when the CPU module is in the RUN status. Section 7.12
This function displays the processing time of a program being executed, the number of times to
Measure execution time Section 7.13
execute an interrupt program, and the execution time of a program.
Program list monitor This function displays the processing time of a program being executed. Section 7.13.1
Interrupt program monitor This function displays the number of times to execute an interrupt program. Section 7.13.2
Scan time measurement This function measures the execution time of a program between selected steps. Section 7.13.3
Sampling trace function This function samples specified device data from the CPU module at a specified timing. Section 7.14
Multiple-user debugging function This function enables multiple users to debug programs by using several GX Developers. Section 7.15
Watch dog timer This function monitors operational delays caused by CPU module's hardware and program errors. Section 7.16
Self-Diagnosis function This function enables the CPU module to check for failures. Section 7.17
Failure history This function stores a failure history of diagnosis results in the memory. Section 7.18
This function prevents the programs from being modified from GX Developer, serial communication
System protect Section 7.19
module or like.
This function provides read/write protection for files stored in the CPU module against access from
Password registration Section 7.19.1
the GX Developer.
A function to prevent illegal access from external sources with serial communication modules and
Remote password Section 7.19.2
Ethernet modules.
System display This function connects to the GX Developer and monitors system configuration. Section 7.20
LED display This function enables the front-mounted LEDs to indicate the operating conditions of the CPU module. Section 7.21
LED display This function indicates the normal or abnormal operating conditions of the CPU module. Section 7.21.1
Preference setting This function sets failure preferences to turn off LED displays. Section 7.21.2
This function executes an interrupt program by fixed scan interrupt at 0.2ms to 1.0ms intervals
High speed interrupt function Section 7.22
using the interrupt pointer I49.
This function monitors the access interval time (time between the access acceptance of the CPU
Module service interval time read module and the next access acceptance) of the intelligent function module, network module or Section 7.23
peripheral device.

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7.2 Constant Scan

(1) What is Constant Scan?

The scan time differs because the processing time differs depending on whether
the instruction, which is used in the sequence program, is executed or not.
Constant scan is a function to execute the sequence program repeatedly while
maintaining the scan time at a constant time.
Because I/O refresh is made prior to execution of the sequence program, use of
the constant scan function helps maintain the I/O refresh interval at a constant
rate even if the sequence program execution time varies.

Scan time when constant scan is not used

Sequence program
END processing
END 0 END 0 END 0 END 0

5ms 6ms 5ms

Scan time when constant scan setting is set to 7 ms

Sequence program
END processing
END 0 END 0 END 0 END 0

Wait time
5ms 2ms 6ms 1ms 5ms 2ms

7ms 7ms 7ms

Scan time when constant scan is set to 10 ms during multiple program execution
Sequence program A
Sequence program B
Sequence program C 7
END processing

Wait time
8ms 2ms 9ms 1ms

10ms 10ms

Fig. 7.1 Constant scan operation

REMARK
When using a low speed execution type program, the constant scan function setting
or low speed execution type program execution time must be set.

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(2) Setting the constant scan time

(a) The constant scan time is set at the "PLC RAS" tab screen in the “(PLC)
Parameter" dialog box.
The constant scan can be set in the range of 0.5 ms to 2000 ms.
A setting can be made in 0.5 ms units.
• When executing constant scan, set the constant scan time.
• When not executing a constant scan, leave the constant scan time blank.

[Example] When the constant scan is set to 10 ms.

(b) Set the set time of the constant scan longer than the maximum scan time of
the sequence program. Also, set the constant scan set time shorter than
the WDT set time.

(WDT Set Time) > (Constant Scan Set Time) > (Sequence Program maximum Scan Time)

If the sequence program scan time is longer than the constant scan set time,
the High Performance model QCPU detects PRG.TIME OVER (an error
code: 5010), the sequence program is executed with the scan time by
ignoring the constant scan.
Constant scan setting

0 1 2 3 4 1 2 3 4 5 1 2 3 4 1 2 3 4 ms
Constant
scan
0 END 0 END 0 END 0 END 0
Sequence
program
3.5ms 0.5ms 3.5ms 3.4ms 0.6ms
4ms 5.3ms 4ms 0.5ms 4ms

Scan where the constant scan is not normal

Fig. 7.2 Operation when the Scan Time is longer than the Constant Scan

If the time is longer than the WDT set time, the High Performance model
QCPU detects a WDT error and stops the program execution.

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(c) The sequence program processing stops during the wait time from the last
END processing execution until the next scan starts.
1) If a low speed execution type program is executed, it will be interrupted
for - 0.5 ms (a constant scan time setting).
2) If an interrupt factor occurs after the END processing is performed, the
interrupt program or fixed scan execution type program is executed.

(d) Constant Scan Time Accuracy

This section describes the accuracy of a constant scan time setting.
1) The remaining portion (wait time) of a constant scan time setting is
0.02 ms on Q02CPU and 0.01 ms on Q02HCPU, Q06HCPU,
Q12HCPU, Q25HCPU when the following programs are not executed.
• low speed execution type program
• interrupt program
• fixed scan execution type program
2) Wait time is 0.5 ms when a low speed execution type program is used.
If the maximum processing time for one instruction in a low speed
execution type program is 0.5 ms, the remaining portion of constant
scan time is the same as described in 1). If the maximum processing
time exceeds 0.5 ms, constant scan delays for an excessive duration.
3) Interrupt is enabled while an interrupt program/fixed scan execution
type program is executed. If constant scan time runs out when an
interrupt program/fixed scan execution type program is executed,
constant scan cannot be finished. When an interrupt program/fixed
scan execution type program is used, constant scan time could be
shifted by the execution time of an interrupt program/fixed scan
execution type program.

REMARK
Refer to "QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)"
for the command processing time.

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7.3 Latch Functions

(1) What is Latch Functions?

(a) The values of each High Performance model QCPU device are set back to
the default (bit device: OFF and word device: 0) when;
• The PLC power is turned on.
• The reset operation is performed.
• There is a momentary power failure for more than the permissible amount
of time.
Latch function maintains the device information when the above conditions
occur.
The availability of latches does not affect the operation performed by a
program.

(b) The latch can be used to continue control by maintaining the production
quantity, defect count, and address even when there is a momentary power
failure for more than the permissible amount of time.

(c) The following devices can use the latch function:

(The default latch range is only the latch relay.)
1) Latch relay(L)
2) Link relay(B)
3) Annunciator(F)
4) Edge relay(V)
5) Timer(T)
6) Retentive timer(ST)
7) Counter(C)
8) Data register(D)
9) Link register(W)

(2) Latch Range Setting

The latch range setting is performed at the "Device" tab screen in the “(PLC)
Parameter" dialog box.
There are two types of range in which the latch clear key (RESET/L.CLR switch)
and remote latch clear operation become valid or invalid in the latch range
setting.

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(3) Clearing the Latch Range Device Data

The status of devices to which "latch clear" is made is shown in the table below.
Latch setting Clear/retention after "latch clear"
Devices not designated in latch range Clear
Latch (1) setting (Devices with "latch clear" option) Clear
Latch (2) setting (Devices without "latch clear" option) Retain
: Refer to Section 4.6 for the clearing method.

POINT
File registers (R) cannot be cleared with latch clear.
(See Section 10.7 for clearing file registers.)

(4) Precautions
(a) Even if the device has been latch-specified, it will not be latched the when
the local device or the device initialization is specified.

(b) The device details of the latch range are maintained with the battery
(Q6BAT) attached to the High Performance model QCPU.
1) The battery is necessary to latch the device if ROM operation is
performed using the sequence program that has been stored on the
standard ROM or memory card.
2) Take care that, if the battery connector is disconnected from the
connector of the High Performance model QCPU when PLC is turned
off, the latch range device memory is not retained but becomes
undefined.

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7.4 Setting the Output (Y) Status when Changing from/to STOP Status to/from RUN Status

(1) Output (Y) Status when changing from STOP Status to RUN Status
When changing from RUN status to STOP status, the RUN status output (Y) is
stored in the sequence and all the outputs (Y) are turned OFF.
The status after transition from STOP to RUN can be selected from the following
two options with the High Performance model QCPU.
• The output status prior to STOP is output.
• The output is cleared.
(Default: After transition from STOP to RUN, the output (Y) status prior to
STOP is output then the program is executed.)
(a) Output (Y) status prior to STOP is output
After the output (Y) status before the STOP status is output, the sequence
program calculations are performed.

(b) Output is cleared

Clears all output (Y) and outputs the output (Y) after executing the
sequence program calculations.

STOP status to RUN status

Is output (Y) NO (Output (Y) status prior to STOP is output)

status prior to
STOP output?

YES (Output is cleared)

Output the output (Y) status

Clear the output (Y) status.
right before changing to
STOP status.

Execute the sequence

program calculations

Fig. 7.3 Processing when Change from STOP Status to RUN Status

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(2) Setting the Output (Y) Status when Changing from STOP Status to
RUN Status
The output (Y) status before the STOP status when switching from STOP status
to Run status can be set at the "PLC System" tab screen in the “(PLC)
Parameter" dialog box.

Output mode setting

at STOP to RUN

(3) Precaution
If an output (Y) is forcefully turned ON with the High Performance model QCPU
in the STOP status, it will not remain in the ON status even if the STOP status is
switched to the RUN status.
The output status is effected as set for "Output mode at STOP to RUN" at the
"PLC System" tab screen.

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7.5 Clock Function

(1) What is Clock Function?

(a) Clock function reads the clock data inside the High Performance model
QCPU with a sequence program and uses the data for clock management.
Also, the time data is used for time maintenance for the High Performance
model QCPU system functions such as those for failure history.
The clock operations are maintained using the battery (Q6BAT) even when
the PLC power is off or when a momentary power failure for longer than the
permitted time occurs.
(b) Clock Data
The following table lists the time data, that are used for the High
Performance model QCPU clock element.
Data Name Contents
Year Four digits in AD (Countable from 1980 to 2079)
Month 1 to 12
Day 1 to 31(Automatic leap year calculation)
Hour 0 to 23 (24 hours)
Minute 0 to 59
Second 0 to 59
0 Sunday
1 Monday
2 Tuesday
Day of the week 3 Wednesday
4 Thursday
5 Friday
6 Saturday

(2) Writing/Reading Time Data To/From Clock Element

(a) The following two methods can be used to write to the time data clock
element.
1) Method to write from GX Developer
The time data is written to the clock element by displaying "Online"
"Set time" window.

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2) Method to Write from the Program

The time data is written to the clock element by using the clock
instruction (DATEWR).
A program example to write the time data using the time data write
instruction (DATEWR).
Write request
X0
0 MOVP K1999 D0 Year 1999

MOVP K8 D1 Month 8

MOVP K10 D2 Day 10

MOVP K11 D3 Hour 11

MOVP K35 D4 Minute 35

MOVP K24 D5 Second 24

MOVP K2 D6 Day Tuesday: 2

DATEWR D0

Refer to "QCPU (Q mode)/QnACPU Programming Manual (Common

Instructions)" for details on the DATEWR instruction.

(b) Reading Time Data

When reading the time data to the data register, use the time data read
instruction (DATERD) from the program.
The figure below shows an example of a program used to read the clock
data with the DATERD instruction and then store it in D10 to D16.
Read request
X1
The time data is read and
DATERD D10
then stored in D10 to D16.

Refer to the "QCPU (Q mode)/QnACPU Programming Manual (Common

instructions) for the details on the DATERD instruction.

REMARK
1) Time Data can be written to and read from by special relays (SM210 to SM213)
and special registers (SD210 to SD213).
See Appendix 1 for details on special relay. See Appendix 2 for details on
special registers.
2) : The figure below shows the clock data stored in D10 to D16.
D10 1999 4 digits in AD
D11 8 Month
D12 10 Date
D13 11 Hour See Section 7.5(1).
D14 35 Minute
D15 24 Second
D16 2 Day of the week

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(3) Precautions
(a) The clock data is not set prior to shipment.
The clock data is used in High Performance model QCPU system and
intelligent function module for failure history and other functions. Be sure to
set the accurate time when operating the High Performance model QCPU
for the first time.

(b) Even when a part of the time data correcting, all data must be written to the
clock element again.

(c) The data to be written to the clock element is checked in the range
described in (1) (b) of Section 7.5.
For this reason, if improbable clock data in the range described in (1) (b) of
Section 7.5 is written to the clock element, correct clock operation is
unavailable.

Example
Writing to clock element CPU module operation status
February 30 Executed Error is not detected
When DATEWR instruction is executed:
32 of month 13 Not executed OPERATION ERROR (Error code 4100)
When SM210 is on: SM211 is on

(4) Accuracy of Clock Data

The accuracy of the clock function differs with the ambient temperature, as
shown below:
Ambient Temperature ( C ) Accuracy (Day difference, S)
0 -3.18 to +5.25 (TYP.+2.12)
+25 -3.93 to +5.25 (TYP.+1.9)
+55 -14.69 to +3.53 (TYP.-3.67)

(5) Comparison of Clock Data

To compare High Performance model QCPU's clock data with a sequence
program, use the DATERD instruction to read the clock data. The year data is
read out in 4 digits. It can be compared as it is by using a compare instruction.

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7.6 Remote Operation

The High Performance model QCPU provides the RUN/STOP switches for switching
between the STOP status and the RUN status. The RESET/L.CLR switch also
provides the Reset and Latch Clear functions.
The High Performance model QCPU can allow control of the High Performance model
QCPU operation status by external operations
(GX Developer function, intelligent function module, and remote contact).
The following four options are available for remote operations:
• Remote RUN/STOP
• Remote PAUSE
• Remote RESET
• Remote LATCH CLEAR

REMARK
The serial communication module is used as the example to describe the intelligent
function module.

7.6.1 Remote RUN/STOP

(1) What is Remote RUN/STOP?

(a) The remote RUN/STOP performs RUN/STOP of the High Performance
model QCPU externally with the CPU module RUN/STOP switch at RUN.

(b) Using remote RUN/STOP for the following remote operations are useful:
1) When the High Performance model QCPU is at a position out of reach
2) When performing RUN/STOP of the control board High Performance
model QCPU externally

(c) Calculations during Remote RUN/STOP

The program calculation that performs remote RUN/STOP is as follows:
1) Remote STOP
Executes the program to the END instruction and enters the STOP
status.
2) Remote RUN
When remote RUN is performed while in the STOP status using remote
STOP, the status changes to RUN and executes the program from
step 0.

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(2) Method with Remote RUN/STOP

There are two ways to perform remote RUN/STOP:
(a) Method with remote RUN contact
The remote RUN contact is set at the "PLC system" tab screen in the
“(PLC) Parameter" dialog box of GX Developer.
The device can be set in the range of input X0 to 1FFF.
By turning the set remote RUN contact ON/OFF, the remote RUN/STOP
can be performed.
1) When the remote RUN contact is OFF, the QCPU enters the RUN
status.
2) When the remote RUN contact is ON, the QCPU enters the STOP
status.

Step 0 END Step 0 END

ON 0

OFF
Remote RUN contact
STOP

RUN
CPU module: RUN/STOP status

STOP status

Fig. 7.4 Time Chart for RUN/STOP with Remote RUN Contact

(b) Method with GX Developer, serial communication module, etc.

High Performance model QCPU RUN/STOP can be performed by the
remote RUN/STOP operation from the GX Developer, serial communication
module, etc.
The GX Developer operation is performed with on-line remote operations.
The serial communication module and Ethernet interface module are
controlled by commands complying with the MC protocol.
For details of the MC protocol, refer to the following manual.
• Q Corresponding MELSEC Communication Protocol Reference Manual

Step 0 END Step 0 END

ON 0
Remote STOP command
GX Developer OFF
ON
Serial OFF
Remote RUN command
communication
module STOP
RUN
CPU module: RUN/STOP status

STOP status

Fig. 7.5 Remote RUN/STOP Time Chart using GX Developer,

serial communication module, etc.

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(3) Precautions
(a) Take note of the following, because STOP has priority in High Performance
model QCPU:
1) The High Performance model QCPU enters the STOP status when
remote STOP is performed from remote RUN contact, GX Developer,
or by using serial communication module.
2) To set the High Performance model QCPU to RUN status from STOP
status again, perform the remote RUN from the external factor (remote
RUN contact, GX Developer, serial communication module, etc.) from
which the remote STOP was performed.

REMARK
The RUN/STOP status is described below:
• RUN Status ...............Status in which the calculations are repeatedly executed
from step 0 to the END/FEND instruction in the sequence
program.
• STOP Status .............Status in which the sequence program calculations are
stopped and the output (Y) is all OFF.

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7.6.2 Remote PAUSE

(1) What is Remote PAUSE?

(a) The remote PAUSE performs PAUSE of the High Performance model
QCPU externally with the CPU module RUN/STOP switch at RUN position.
The PAUSE function stops the High Performance model QCPU calculations
while maintaining the ON/OFF status of all output (Y).

(b) This can be used to maintain the output (Y) on even if the High
Performance model QCPU is changed to STOP status, in such areas as
process control.
POINT
The output (Y) is turned off upon a stopping error.
To retain the output even upon a stopping error, use I/O allocation of PC
parameters to set output retention.

(2) Method with Remote PAUSE

There are two ways to use remote PAUSE:
(a) Method with remote PAUSE Contact
The remote PUASE contact is set at the "PLC system" tab screen in the
“(PLC) Parameter" dialog box of GX Developer.
The device can be set in the range of input X0 to 1FFF.
1) The PAUSE status contact (SM204) is turned on when the END
processing is executed for the scan with both remote PAUSE contact
and PAUSE permission flag (SM206) on.
2) When the remote PAUSE contact is off or SM206 is turned off, the
PAUSE status is canceled, and the sequence program calculation is
performed again from step 0.

0 END END END

ON 0 END 0 0

Remote PAUSE OFF

contact ON

OFF
SM206
ON

OFF ON when
SM204 PAUSE
PAUSE
condition
RUN met
RUN/PAUSE
status
PAUSE status

Fig. 7.6 PAUSE Time Chart with Remote PAUSE Contact

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(b) Method with GX Developer, Serial Communication Module etc.

The remote PAUSE operation can be performed from the GX Developer or
by using serial communication module.
The GX Developer operation is performed by on-line remote operation.
The serial communication module and Ethernet interface module are
controlled by commands complying with the MC protocol.
For details of the MC protocol, refer to the following manual.
• Q Corresponding MELSEC Communication Protocol Reference Manual
1) When the END processing is performed for the scan where the remote
PAUSE command was accepted, the PAUSE status contact (SM204)
is turned on.
When the scan after the PAUSE status contact is turned on is executed
to the END process, it enters the PAUSE status and stops the
calculations.
2) When the remote RUN command is received, the sequence program
calculations are performed again from step 0.

0 END
0 END 0
0 END
ON

OFF
Remote PAUSE
command ON

OFF
Remote RUN
command ON

OFF ON when
SM204
PAUSE PAUSE
condition
RUN met
RUN/PAUSE
status
PAUSE status

Fig. 7.7 PAUSE Time Chart with GX Developer

(3) Precaution
To set the output (Y) ON/OFF status when change to the PAUSE status, perform
an interlock with the PAUSE status contact (SM204).
M20 Y70 ON/OFF is determined with the
Y070 ON/OFF of the M20 in the PAUSE status.
X000 SM204
Y071 Turns off at PAUSE status.

M0
Y072 Turns on at PAUSE status.

SM204

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7.6.3 Remote RESET

(1) What is Remote RESET?

(a) The remote RESET resets the High Performance model QCPU externally
when the High Performance model QCPU is at STOP status.
Even if the High Performance model QCPU RUN/STOP switch is at RUN,
the reset can be performed when the High Performance model QCPU is
stopped and an error that can be detected by the self-diagnosis function
occurs.
(b) Remote RESET can reset the High Performance model QCPU remotely
when an error occurs for which the High Performance model QCPU cannot
be operated directly.
Remote RESET can be executed only in STOP status. When the High
Performance model QCPU is in RUN status, use Remote STOP to arrange
the STOP status.
(2) Remote RESET Method
The remote RESET can only be performed from GX Developer or by operating
serial communication module.
To perform the remote RESET, follow the following steps:
(a) At the "PLC system" tab screen in the “(PLC) Parameter" dialog box, check
the "Allow" check box at the "Remote reset" section, and then write
parameters to the High Performance model QCPU.

Allow the
"Remote reset"

(b) When the High Performance model QCPU is in RUN status, use remote
STOP to arrange the STOP status.
(c) Reset High Performance model QCPU by the remote RESET operation.
1) For the GX Developer, this is performed by on-line remote operation.
2) The serial communication module and Ethernet interface module are
controlled by commands complying with the MC protocol.
For details of the MC protocol, refer to the following manual.
• Q Corresponding MELSEC Communication Protocol Reference Manual

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(3) Precautions
(a) To perform the remote RESET, check the "Allow" check box of the "Remote
reset" section at the "PLC system" tab screen in the “(PLC) Parameter"
dialog box, and then write parameters into High Performance model QCPU.
If the "Allow" check box is not checked, a remote RESET operation is not
performed.

(b) Remote RESET cannot be performed when the High Performance model
QCPU is in RUN status.

(c) After the reset operation is complete, the High Performance model QCPU
will enter operation status set at the RUN/STOP switch.
1) With the RUN/STOP switch in the "STOP" position, the High
Performance model QCPU enters into the "STOP" status.
2) With the RUN/STOP switch in the "RUN" position, the High
Performance model QCPU enters into the "RUN" status.

(d) Take care that Remote RESET does not reset High Performance model
QCPU if an error occurs in the High Performance model QCPU due to
noise.
If Remote RESET does not reset, use the RESET/L.CLR switch to reset or
turn the PLC off.

POINT
(1) If Remote RESET is executed when the High Performance model QCPU is
stopped due to an error, the High Performance model QCPU enters the
operation status set at the RUN/STOP switch after it is reset.
(2) Even if "Remote reset" is set as "Allow" at the "PLC system" tab screen in the
“(PLC) Parameter" dialog box, the remote process of the GX Developer is
completed.
However, the High Performance model QCPU is not reset since the reset
process is not performed in it.
If the status of the High Performance model QCPU does not change though a
reset process is performed from GX Developer, check if the "Remote reset" is
set as "Allow" at the "PLC System" tab screen in the “(PLC) Parameter" dialog
box.

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7.6.4 Remote latch clear

(1) What is Remote Latch Clear?

(a) The remote latch clear resets the device data latched to the High
Performance model QCPU using the GX Developer etc., when the High
Performance model QCPU is in STOP status.

(b) Remote latch clear is useful when the High Performance model QCPU is in
the following areas. In these cases, the operations are performed in
combination with the remote RUN/STOP.
• When the High Performance model QCPU is at a position out of reach
• When externally performing latch clear of the High Performance model
QCPU inside a control panel.

(2) Remote Latch Clear Method

The remote latch clear can only be performed from GX Developer or by using
serial communication module.
To perform the remote latch clear, follow the following steps:
(a) Use the remote STOP to bring the High Performance model QCPU to
STOP status.

(b) Use the Latch Clear to bring the High Performance model QCPU to the
Latch Clear status.
1) The GX Developer operations are performed by on-line remote
operation.
2) The serial communication module and Ethernet interface module are
controlled by commands complying with the MC protocol.
For details of the MC protocol, refer to the following manual.
• Q Corresponding MELSEC Communication Protocol Reference Manual

(c) To return the High Performance model QCPU to RUN status after the
remote latch clear, perform a remote RUN operation.

(3) Precautions
(a) Either remote latch clear or latch clear by RESET/L.CLR switch cannot be
performed when the High Performance model QCPU is in RUN status.

(b) The latch range for the device set at the "Device" tab screen in the “(PLC)
Parameter" dialog box includes a range that makes latch clear
(RESET/L.CLR switch) valid or invalid.
Remote latch clear operation is reset in the range of latch clear valid
setting.

(c) Devices that are not latched are cleared when the remote latch clear is
performed.
The data in the failure history storage memory of the High Performance
model QCPU will also be cleared by a remote latch clear operation.

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7.6.5 Relationship of the remote operation and High Performance model QCPU RUN/STOP
switch

(1) Relationship of the Remote Operation and High Performance

model QCPU Switch
The High Performance model QCPU operation status is as follows with the
combination of remote operations to RUN/STOP switch.
Remote operation
1 2 3
RUN/STOP RUN STOP PAUSE RESET Latch clear
switch
Cannot Cannot
RUN RUN STOP PAUSE 4 4
operate operate
5
STOP STOP STOP STOP RESET Latch clear

1 When performing the operation with remote RUN contact, "RUN-PAUSE contact" must be
set at the "PLC system" tab screen in the “(PLC) Parameter" dialog box.
2 When performing the operation with remote PAUSE contact, "RUN-PAUSE contact" must
be set at the "PLC system" tab screen in the “(PLC) Parameter" dialog box. In addition, the
remote PAUSE enable coil (SM206) must be set ON.
3 "Remote reset enable" must be set at the "PLC system" tab screen in the “(PLC)
Parameter" dialog box.
4 RESET or LATCH CLEAR can be performed if the High Performance model QCPU
changed to the STOP status by a remote operation.
5 This includes a situation where the High Performance model QCPU is stopped due to error.

(2) Remote Operations from the Same GX Developers

When remote operations are performed from the same GX Developer, the status
of the remote operation that is executed last will be effective.

(3) Remote Operations from Multiple GX Developers

While a remote operation is being performed by one GX Developer, another
remote operation cannot be performed by another GX Developer.
After a remote operation that is being performed by one GX Developer is
cancelled, a new remote operation can be performed by another GX Developer.
For example, a remote PAUSE operation is being performed by one
GX Developer, the PAUSE status will remain active even if a remote
STOP/remote RUN operation is attempted by another GX Developer.
When a remote RUN operation is performed by the GX Developer that is
performing a remote PAUSE operation, and then that remote operation is
cancelled, a new remote operation can be performed by another GX Developer.

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7.7 Selecting the Input Response Time of the Q Series Module (I/O Response Time)

7.7.1 Selecting the response time of the input module

(1) Selecting the response time of the input module

The input response time of a Q Series input module can be set to a desired
response time: 1 ms, 5 ms, 10 ms, 20 ms or 70 ms. The input module reads
external inputs at the specified response time. The default value of an input
response time is 10 ms.
ON

OFF
External input
ON

OFF
Input module

Input response time

(2) Setting the Input Response Time

At the "I/O Assignment" tab screen in the “(PLC) Parameter" dialog box, specify
the desired input response time. Select "Input" in the "Type" column of a slot for
which to specify the desired input response time.
For the Composite I/O module, choose "I/O mix".
Input module : Select "Input".
Composite I/O module: Select "I/O mix". Select "Detailed setting". Select "I/O response time".

(3) Reactions
(a) Higher input response time may result in response to inputs being
influenced by noise. Set the desired input response time by taking into
consideration the operating environment of an input module in use.
(b) No change can be made to the input response time of an AnS Series
corresponding input module. An input response time setting is not made for
a slot of an AnS Series corresponding input module.
(c) The input response speed setting is valid in the following cases.
• After the PLC is turned on
• When the High Performance model QCPU is reset

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7.7.2 Selecting the response time of the high speed input module

(1) Selecting the response time of the high speed input module
Changing the response time of the high speed input module means to amend the
input response speed for high speed input modules (QX40-S1) that support the
Q Series to 0.1 ms, 0.2 ms, 0.4 ms, 0.6 ms and 1 ms.
Input from external devices is accepted at the input response speed set for the
high speed input module. The default setting for the input response time is
0.2 ms.
ON

OFF
External input
ON

High-speed OFF
input module

Input response time

(2) Setting the Input Response Time

Input response time is set at the "I/O assigment" tab screen in the “(PLC)
Parameter" dialog box.
Select "Hi. input" among the slot types for which the input response time is to be
set.
Select "Hi. input" Select "Detailed setting" Select "I/O response time"

(3) Precautions
(a) The system will be adversely affected by noise, etc., when the input
response time is set to high speed. Set the input response time in
consideration of the operating environment.
(b) The GX Developer Version 5 (SW5D5C-GPPW-E) or later is required when
changing the response time of the high speed input module.
The input response time of the high speed input module cannot be
amended with the GX Developer Version 4(SW4D5C-GPPW-E.) (Fixed at
0.2 ms (default setting.)
(c) The input response speed setting is valid in the following cases.
• After the PLC is turned on
• When the High Performance model QCPU is reset

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7.7.3 Selecting the response time of the interrupt module

(1) Selecting the response time of the interrupt module

Changing the response time of the interrupt module means to amend the input
response speed for interrupt modules (QI60) that support the Q Series to 0.1 ms,
0.2 ms, 0.4 ms, 0.6 ms and 1 ms.
Input from external devices is accepted at the input response speed set for the
interrupt module. The default setting for the input response time is 0.2 ms.
ON

OFF
External input
ON

OFF
Interrupt module

Input response time

(2) Setting the Input Response Time

Input response time is set up at the "I/O assignment" tab screen in the “(PLC)
Parameter" dialog box.
Select "Interrupt" among the slot types for which the input response time is to be
set.
Select "Interrupt" Select "Detailed settings" Select "Input response time"

(3) Precautions
(a) The system will be adversely affected by noise, etc., when the input
response time is set to high speed. Set the input response time in
consideration of the operating environment.
(b) The input response time cannot be amended for the A1SI61 (interruption
module that supports the AnS Series.) No processing will be performed
with interruption modules that support the AnS Series, even if the input
response time is set in the slot.
(c) The GX Developer Version 6 (SW6D5C-GPPW-E) or later is required when
changing the response time of the interrupt module.
The input response time of the interrupt module cannot be amended with
the SW5D5C-GPPW-E or earlier GX Developers. (Fixed at 0.2 ms (default
setting.))
(d) The input response speed setting is valid in the following cases.
• After the PLC is turned on
• When the High Performance model QCPU is reset

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7.8 Error-time Output Mode Setting

(1) Error-time Output Mode Setting

The error-time output mode setting is to set whether the output to the Q series
compatible output module, hybrid I/O module or intelligent function module will be
cleared or held when the CPU module results in a stop error.

(2) Error-time Output Mode Setting

Make the error-time output mode setting in the I/O assignment of the PLC
parameter dialog box.
Choose "Output", "Hybrid I/O" or "Intelligent" as the type of the slot to which the
error-time output mode is set.
Then select Detailed setting.
Choose "Clear" or "Hold" for the slot to which the error-time output mode is set.
(The default is "Clear".)
Select Type.

Select Detailed setting.

Error-time output mode

Select "Clear" or "Hold".

(3) Precautions
The error-time output mode setting is made valid when:
The PLC CPU is powered ON; or
The CPU module is reset.
Failure to perform either operation after changing the error-time output mode
setting will result in "PARAMETER ERROR (error code: 3000)".

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7.9 Hardware Error-time CPU Operation Mode Setting

(1) Hardware Error-time CPU Operation Mode Setting

The hardware error-time CPU operation mode setting is to set whether the
operation of the CPU module will be stopped or continued when a hardware error
occurs in the intelligent function module.

(2) Hardware Error-time CPU Operation Mode Setting

Make the hardware error-time CPU operation mode setting in the I/O assignment
of the PLC parameter dialog box.
Choose "Intelligent" as the type of the slot to which the hardware error-time CPU
operation mode is set.
Then select Detailed setting.
Choose the hardware error-time CPU operation mode of the slot to which the
hardware error-time CPU operation mode is set.
(The default is "Stop".)
Select Intelligent.

Select Detailed setting.

Hardware error-time CPU operation mode

Select "Stop" or "Continue".

(3) Precautions
(a) The hardware error-time CPU operation mode setting is made valid when:
• The PLC CPU is powered ON; or
• The CPU module is reset.
Failure to perform either operation after changing the hardware error-time
CPU operation mode setting will result in "PARAMETER ERROR (error
code: 3000)".

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7.10 Setting the Switches of the Intelligent Function Module

(1) Setting the Switches of the Intelligent Function Module

The switches of the intelligent function module is to set the switches of an Q
Series intelligent function module using GX Developer.
The settings of the switches set by GX Developer is written from High
Performance model QCPU to each intelligent function module at the leading
edge or reset of High Performance model QCPU.
High Performance Intelligent function
GX Developer model QCPU module
Power supply
Parameter
ON/CPU
Switch setting of the Write Parameter module Reset Switch setting
intelligent function module
at the I/O assignment

(2) Setting the Switches of the Intelligent Function Module

At the "I/O assignment" tab screen in the “(PLC) Parameter" dialog box, specify
the desired switch setting. Select "Intelli." in the "Type" column of a slot for which
to set the switches of the intelligent function module.
Select "Intelli". Select "Switch Setting".

Designate the contents of the

intelligent function module switch.

(3) Precautions
(a) Do not apply the switch setting for an intelligent function module to an AnS
Series corresponding special function module.
If the switch setting for an intelligent function module is specified for an AnS
Series corresponding special function module, an error (SP.PARA.ERROR)
will occur.
(b) For details on the switch setting for an intelligent function module, refer to
the manual of the intelligent function module in use.
(c) The switch settings for interruption modules with the GX Developer Version 6
(SW6D5C-GPPW-E) or later are made by setting the type to "Interruption".
The switch settings for interruption modules with the SW5D5C-GPPW-E or
earlier GX Developers are made by setting the type to "Intelligent".
Refer to the following manual for further details on the interruption module's
switch settings.
• Building Block I/O Module User's Manual
(d) The switch setting of the intelligent function module is valid in the following
cases.
• After the PLC is turned on
• When the High Performance model QCPU is reset

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7.11 Monitoring Function

(1) What is Monitoring Function?

(a) This is a function to read the program, device and intellignet function
module status of the High Performance model QCPU by using GX
Developer.
The High Performance model QCPU performs the END processing to
handle monitor requests from GX Developer.
The results of High Performance model QCPU's END processing are
displayed on the GX Developer side.
(b) By setting the monitoring conditions with GX Developer, it is possible to
monitor the High Performance model QCPU operation status under the
specified conditions.
It is also possible to maintain the monitoring status under the specified
conditions by setting the monitoring stop conditions.
(c) The use of local devices for execution of multiple programs makes it
possible to monitor local device data.

7.11.1 Monitor condition setting

(1) Setting monitor execution conditions when monitoring circuits

Choose "Online" "Monitor" "Monitor condition" to open the Monitor
Condition dialog box. The following shows an example in which to start a
monitoring operation at the leading edge of Y70.

Select when monitoring

by setting the contents
of the device

Select when monitoring

by setting Step No.

(a) When only "Step No." is specified:

1) The monitor data sampled when the status previous to execution of the
specified step becomes "the specified".

2) The specification method for the execution status is indicated below:

a) When changing from non-execution status to executing status : <-P->
b) When changing from executing status to non-execution status : <-F->
c) Always when executing only : <ON>
d) Always when not executing only : <OFF>
e) Always regardless of status : <Always>

REMARK
When "Step No. [ 0]" is specified, set the condition to "Always".

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POINT
If a step between the AND/OR blocks is specified as a monitor condition, monitor
data is sampled when the status previous to execution of the specified step is
specified by the LD instruction. The monitor timing depends on the step specified
as a monitor condition. The following shows examples of monitoring when the 2nd
step is ON (Step No. [ 2] = <ON>).
(1) When the 2nd step is connected by the AND instruction:
As shown below, the monitor execution condition is established when both "X0"
and "X1" are ON.
Circuit mode List mode
2nd step
0 LD X0
X0 X1 X2 1 AND X1
0 Y20
2 AND X2
3 OUT Y20

(2) When the 2nd step is connected between the AND/ON blocks:
As shown below, the monitor execution condition is established when "X1" is
ON. Whether "X0" is ON or OFF, it does not affect the monitor execution
condition.
0 LD X0
2nd step
1 LD X1
X0 X1 X2 2 AND X2
0 Y20
3 OR X3
X3 4 ANB
5 OUT Y20

(3) If the beginning of a ladder block not at Step 0 is specified in Step No. as a
detailed condition, monitor data is collected when the execution status of the
instruction immediately before execution becomes the specified status. If (Step
No. [ 2] = <ON>) is specified in the following ladder, monitor data is collected
when OUT Y10 turns ON.
X0 0 LD X0
0 Y10
1 OUT Y10
X1 2 LD X1
2 Y11
3 OUT Y11

(b) When only "Device" is specified:

"Word Device" or "Bit Device" can be specified.
1) When "Word Device " is selected:
The monitor data is sampled is when the current value of the specified
word device becomes the specified value.
Type a current value in decimal digits or hexadecimal digits.
2) When "Bit Device" is specified:
The monitor data is sampled is when the execution status of the
specified bit device becomes the specified value.
Either the leading edge or the fall can be specified for execution
condition.
(c) When "Step No." and "Device" is selected:
The monitor data is sampled when the status previous to execution of the
specified status or the status (current value) of the specified bit device
(word device) is specified.
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7 FUNCTION
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POINT
When "Step No.[100]=<-P->, Word Device [D1]=[K5]" is specified as the detailed
condition in the following circuit, a monitor execution condition is established at the
leading edge of the 100th step where D1=5.
X0 M0 100th step
Y20

INC D1

The monitor interval of GX Developer depends on the processing speed of GX

Developer. When a monitor condition is established during the monitor interval of
GX Developer, the monitor will be performed, even if a monitor condition is
established at a shorter interval than the monitor interval .
Step No. 100 100 100 100

M0

X0

D1 = 5

Monitor timing
(QCPU)

(2) Monitor Stop Condition Set Up

Choose "Online" "Monitor" "Monitor stop condition" to open the "Monitor
Stop Condition" dialog box. The following shows an example of stopping a
monitoring operation at the leading edge of Y71.

(a) When "Step No." is specified:

1) Monitoring is stopped when the status at execution of the specified
step becomes as specified.
2) The specification method for the execution status is shown below:
a) When changing from non-execution status to executing status : <-P->
b) When changing from executing status to non-execution status : <-F->
c) Always when executing only : <ON>
d) Always when not executing only : <OFF>
e) Always regardless of status : <Always>
3) When "Step No." is not specified, the monitoring operation is stopped
after the High Performance model QCPU END processing.

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(b) When "Device" is specified:

"Word Device" or "Bit Device" can be specified.
1) When "Word Device " is selected:
The monitoring operation is stopped when the current value of the
specified word device becomes the specified value.
A current value can be expressed in decimal digits, hexadecimal digits,
16-bit integral numbers, 32-bit integral numbers, or real numbers.
2) When "Bit Device" is specified:
The monitoring operation is stopped when the execution status of the
specified bit device becomes the specified value.
Either the leading edge or the fall can be specified for execution
condition.

(3) Precautions
(a) When monitoring after setting the monitor condition, the file displayed on GX
Developer is monitored. Match the file to be monitored by executing the
"New PLC Read" and file name on GX Developer.

(b) When monitoring the file register which is not specified, 0 is displayed.

(c) Perform the monitoring by matching the device allocation of the High
Performance model QCPU and GX Developer.

(d) When monitoring the buffer memory of the intelligent function module, the
scan time takes longer, as well as when executing the FROM/TO
instruction.

(e) Multiple users can perform monitoring at the same time.

When multiple users are performing monitoring at the same time, take note
of the following:
• High speed monitoring can be performed by increasing 1k step in the
system area for other station's monitor file when formatting of program
memory.
Up to 15 stations can be set as the station monitor file, but the program
space will be reduced.
• The detailed condition setting for the monitoring can only be set for one
user.

(f) The monitoring detailed condition setting can only be set in circuit monitor.
(g) When the same device is specified as the monitor condition and monitor
stop condition, specify "ON" or "OFF".
(h) The monitoring conditions will not be established unless the following
specified steps commands are executed when "Step No." has been
specified for the monitoring conditions.
1) When skipping steps specified with the CJ command, the SCJ
command and the JMP command.
2) When the specified step is the END command, the FEND command
exists while the program is running, and the END command is not
executed.
(i) Do not reset the High Performance model QCPU while monitoring
conditions are being registered.

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7.11.2 Monitoring test for local device

(1) Monitoring and Testing Local Devices

(a) Local devices specified at the "Device" tab screen in the “(PLC) Parameter"
dialog box can be monitored or tested by operating from GX Developer.
This function is useful when debugging a program and monitoring local
devices in a program monitored by GX Developer. See Section 10.13.1 for
local devices.

(b) Monitoring the Local Devices

The table below shows the status of three programs "A", "B", and "C" being
executed on the High Performance model QCPU, with local devices D0 to
D99 specified. It assumes that these three programs are executed in the
order of A B C (END processing) A B ....
Monitor Device
D0 D100
When local devices are D0 in Program "C" is monitored. D100 is monitored after Program
specified "C" is executed.
When local devices are D0 in the displayed program is D100 is monitored after the
not specified monitored. displayed program is executed.

If the local device monitor setting is made and Program "B" is displayed, for
example, this makes it possible to monitor the local devices in Program "B".
High Performance model QCPU

Program execution ( "A" "B" "C" )

Program: A Program: B Program: C

X0 X10 X20
MOVP K2 D0 MOVP K4 D0 MOVP K3 D0

X1 X11 X21
MOVP K3 D9 MOVP K8 D9 MOVP K6 D9

The local device data of the program "B"

The local device monitor is
is displayed.
set and the program "B" is
monitored.
[EX]
In case that the local device is from
D0 to D10, D0=4 is displayed
Install the GX Developer when X10 is on and D9=8 is displayed
Personal computer when X11 is on.

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(2) Monitoring the Local Devices

Monitor local devices in the following steps:
Connect the personral
computer to the CPU module.

Display the circuit in the

circuit mode.

Change the mode to the

monitor mode.

Select "Tool".

Select "Option". Display option window

Select "Program type". Change to the option selection

window by program

Select "Monitor" to monitor

Setting of the local device monitor
the local device.

The local device of the

displayed program is
monitored.

(3) Precautions
(a) It is only a single program that local devices can be monitored or tested by
operating from a single GX Developer. Local devices in multiple programs
cannot be monitored or tested by operating from a single GX Developer.

(b) It is a maximum of 16 programs that local devices can be monitored or

tested by operating from multiple GX Developers connected to a RS-232
serial communication module of the High Performance model QCPU.

(c) If local devices in a stand-by type program are monitored, scan time is
extended for some time because local device data is read and saved. See
Section 10.13.1 for details.

(d) Local devices in a fix scan execution type program cannot be monitored or
tested.

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7.11.3 Enforced ON/OFF for external I/O

Enforced ON/OFF operations from GX Developer will forcibly switch the external I/O
on and off.
The information registered for ON/OFF will be cancelled with GX Developer
operations.
A GX Developer Version 6 or higher is required to use this function.
It is possible to perform enforced ON (enforced ON registration,) enforced OFF
(enforced OFF registration) and cancel enforced ON/OFF (cancel registration) with the
enforced ON/OFF function.
The operations for performing enforced ON, enforced OFF and canceling enforced
ON/OFF are shown in the table below.
Operation Input (X) operation Output (Y) operation
During canceling Performs sequence program Outputs the results of sequence
(no operations) operations with external input. program operations externally.
Performs sequence program Outputs "ON" externally regardless
During enforced ON operations in the enforced ON of the results of sequence program
status. operations.
Performs sequence program Outputs "OFF" externally
During enforced OFF operations in the enforced OFF regardless of the results of
status. sequence program operations.

The operations when enforced ON/OFF is performed are shown in the diagram below.

Output enforced ON/OFF operations Y10 device enforced OFF

Output refreshed Y10 output External

(OFF) output
(Y10 OFF)
Input refreshed X0 input
External
(ON) input
Input enforced ON/OFF operations X0 device enforced OFF (X0 ON)

Sequence execution
M0
Y10
X0 External input Y11
forcibly set at OFF

Y10
M1
Set at ON on the rudder
even during enforced OFF
(external output set at OFF)
END

(1) Explanation of specifications

(a) Enforced ON/OFF can be performed regardless of the High Performance
model QCPU's RUN/STOP status. However, enforced ON/OFF is only
allowed for input during stop errors. The output is only performed to device Y.
(b) Devices can be registered within the ranges: input (X0 to X1FFF), output
(Y0 to Y1FFF).

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(c) The input and output eligible for enforced ON/OFF are shown below.
1) Input (X) and output (Y) for modules mounted on the base unit.
2) I/O (X/Y) of High Performance model QCPU or I/O (LX/LY) of
MELSECNET/H modules to be refreshed High Performance model
QCPU.
3) I/O (X/Y) of High Performance model QCPU or I/O (RX/RY) of CC-Link
to be refreshed High Performance model QCPU.
When enforced ON/OFF registration is performed for devices outside the
above refresh ranges (ex: empty slots) only the High Performance model
QCPU device memory is set at ON/OFF, and this is not output externally.

(d) Canceling ON/OFF registration information

1) ON/OFF registration information can be canceled from GX Developer.
Devices for which enforced ON/OFF has been performed will assume
the following statuses when ON/OFF registered information has been
cancelled.
ON/OFF performed with ON/OFF not performed
Enforced ON/OFF device
sequence programs with sequence programs
Input from modules mounted on Assumes the ON/OFF status received from the
the base unit module.
Input of High Performance model
Assumes the refreshed ON/OFF status from
QCPUs to be refreshed from LX
MELSECNET/H.
of MELSECNET/H module
Input
Input of High Performance model
Assumes the refreshed ON/OFF status from
QCPUs to be refreshed from RX
CC-Link.
of CC-Link
Input other than above
Maintains the enforced ON/OFF status.
(outside of the refresh range)
Outputs the results of the
Output from modules mounted
sequence program OFF is output.
on the base unit
operations.
Output of High Performance
Outputs the results of the
model QCPUs to be refreshed
sequence program OFF is output.
from LX of MELSECNET/H
operations.
Output module
Output of High Performance Outputs the results of the
model QCPUs to be refreshed sequence program OFF is output.
from RX of CC-Link operations.
Assumes the result of the
Output other than above (outside
sequence program Assumes the OFF status.
of the refresh range)
operations.

2) The enforced ON/OFF settings are cleared with the following

operations.
• Power supply OFF ON
• Reset with the High Performance model QCPU RESET/L. CLR
switch
• Reset with remote reset operations

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(e) The timing for external I/O enforced ON/OFF is shown in the table below.
Refresh area Input Output
• During END processing (input • During END processing (output
refresh) refresh)
• During the execution of • During the execution of
I/O modules on the
commands that used direct commands that used direct
base unit (X, Y)
access input (DX) (LD, LDI, AND, access output (DY) (OUT, SET,
ANI, OR, ORI, LDP, LDF, ANDP, DELTA, RST, PLS, PLF, FF, LDF,
ANDF, ORP, ORF) MC)
I/O of High
Performance model • During END processing (MELSECNET/H refresh)
QCPU to be refreshed • During execution of the COM command
from LX, LY of • During execution of the ZCOM command
MELSECNET/H
I/O of High
Performance model • During END processing (CC-Link refresh)
QCPU to be refreshed • During execution of the COM command
from RX, RY of CC- • During execution of the ZCOM command
Link

(f) A total of thirty-two devices can be registered for enforced ON and OFF.

(g) Sequence program operations take precedence when used with an output
Y contact.

(h) The enforced ON, OFF and cancelled status (including those that are not
set up) can be confirmed with GX Developer. Confirmation is also allowed
with the MODE judgment LED when at least one device is registered. (the
MODE LED will flicker.)

(i) It is possible to register enforced ON/OFF for external I/O in the same CPU
module from multiple GX Developers connected to the network.
However, when enforced ON/OFF is registered in the same device from
multiple GX Developers, it will assume the most recent registered ON/OFF
status.
Owing to this, there are cases when the GX Developer executed first will
display different ON/OFF information to the CPU module ON/OFF information.
When performing enforced ON/OFF from multiple GX Developers, ensure
that the most up-to-date information is set with the "Load Registration
Status" switch before executing the enforced ON/OFF procedure.

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(2) Operation procedure

The operation procedure is explained below.

(a) Register enforced ON/OFF for the specified device.

[Online] [Debug] [Enforced I/O Registration/Cancellation]

It is possible to perform enforced ON or enforced OFF for a specified

device by selecting [Enforced ON Registration] or [Enforced OFF
Registration] after the device has been specified on the [Enforced I/O
Registration/Cancellation] setup screen.

4)
1)
5)

2)

3)

6)

(b) Descriptions of the fields to set up are provided below.

No. Name of setup field Function description

Enter the I/O number for which enforced
1) Device ON/OFF is to be set, or for which
enforced ON/OFF is to be cancelled.
Displays the registration status of
2) Registration status displayed area
registered enforced input and output.
Displays the registration status loaded
3) Load registration status
from CPU module.
Performed enforced ON/OFF registration
4) Enforced ON/OFF registration
for specified devices.
Cancels the enforced ON/OFF for
5) Registration cancellation
registered devices.
Cancels all registered enforced I/O
6) Bulk registration cancellation
registrations.

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7.12 Writing in Program during High Performance model QCPU RUN

When the High Performance model QCPU is in the RUN status, you can write
programs or files in any of the following steps:
• Writing data in the circuit mode during RUN (see Section 7.12.1).
• Writing data by using pointers during RUN (see Section 7.12.2).
• Writing a batch of files during RUN (see Section 7.15.2).

7.12.1 Writing data in the circuit mode during RUN

(1) Writing data in the circuit mode during RUN Status

(a) Writing data in the circuit mode during RUN is a function to write a program
during the High Performance model QCPU RUN status.

(b) The program can be changed without stopping the process in High
Performance model QCPU program by performing writing data in the circuit
mode during RUN status.

X0 X2
Y30
X1

X3 X4
SET M10
X5

END

GX Developer

(c) Writing program during RUN can be performed from a GX Developer

connected to another station in the network.

MELSECNET/H

Change by GX Developer and write in

High Performance model QCPU at the conversion.
Personal computer
(GX Developer)

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(2) Precautions
Take a note of the following when writing during RUN:
(a) The memory that can be written during RUN is only program memory.
1) If the write during RUN is performed while booting a program from a
memory card (RAM), the program to be booted will be changed. While
booting, it takes some time until the write during RUN is completely
executed.
2) If the write during RUN is performed while booting a program from the
standard ROM or memory card (ROM), the program to be booted will
not be changed.
Before turning off the PLC or resetting the High Performance model
QCPU, write the program memory into the standard ROM or memory
card (ROM).

(b) A maximum of 512 steps can be written at once during RUN.

(c) When a low speed execution type program is being executed, the RUN
write is started once the low speed execution type program is complete.
Also, the low speed execution is stopped temporarily during a RUN write.
1) 2) 3) 4)

Scan execution type Scan execution type Scan execution type Scan execution type
program step 0 to END program step 0 to END program step 0 to END program step 0 to END

Low speed execution Low speed execution Low speed execution Low speed execution
type program step type program step type program step type program step
0 to 200 201 to 320 321 to END 0 to 120

1 Scan 1 Scan 1 Scan 1 Scan

1): RUN write command of the scan execution type program

2): RUN write execution of the scan execution type program
3): RUN write command of the low speed execution type program
4): RUN write execution of the low speed execution type program

(d) If the write during RUN is executed while the PLOAD, PUNLOAD or
PSWAP instruction is executed, the processing will enter into a stand-by
status for the write during RUN. If the write during RUN is executed while
the PLOAD, PUNLOAD or PSWAP instruction is executed, the execution of
the instruction is delayed until the write during RUN is executed.

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(e) The capacity of a High Performance model QCPU's program file is a sum of
the capacity of the program created and steps used for the write during
RUN. The write during RUN is executed when the capacity of a program file
is increased. If the capacity of a program file becomes larger than what it
was before, steps can be assigned for the write during RUN. This means
that the write during RUN can be executed only when enough space is
available in a user memory area. If steps are assigned again while the write
during RUN is executed, scan time could be extended for a value shown
below in the table. Controls are interrupted for a value shown below in the
table.
Step for Write During RUN
CPU Type
If Not Changed If Assigned Again
QnCPU max. 2 ms max. 30 ms.
QnHCPU max. 1 ms max. 90 ms
(f) High Performance model QCPU does not work correctly, if the following
instructions are written during RUN write.
1) Trailing edge instruction
If the execution conditions of the following trailing edge instructions are
not arranged upon completion of writing, the trailing edge instruction is
executed.
• LDF
• ANDF
• ORF
• MEF
• PLF
2) Leading edge instruction
If the execution conditions for leading edge instructions (PLS instruction
and P instruction) are arranged upon completion of writing, leading
edge instruction is not executed.
The leading edge instruction is executed when the execution conditions
are OFF then ON.
3) SCJ instruction
If the execution conditions of the SCJ instruction are arranged upon
completion of writing, a jump to the designated pointer occurs even in a
scan cycle.

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7.12.2 Writing a batch of files during RUN

(1) File-Write During RUN function

(a) The file-write during RUN function is used to write a batch of files to the
High Performance model QCPU as shown below in the table.

High Performance model QCPU Built-in Memory Card (RAM) Memory Card (ROM)
Memory Name
Program Memory Standard RAM Standard ROM SRAM Card Flash Card ATA Card
Parameter
Intelligent function
module parameter
Program
Device comment
Device initial value
File register
Local device
Debug data
Failure history data
PLC user data

: Writable data , : Unwritable data

: Writable data if access is not being made in sequence
program

Writing of
program file A

Program file A

Personal computer
(GX Developer)

POINT
The file-write during RUN allows writing three types of files:
• Program: program memory, SRAM card, ATA card
• Device comment: program memory, SRAM card, ATA card
• File register: standard RAM, SRAM card
Any other files cannot be written while the High Performance model QCPU is in the
RUN status.

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(2) Precautions
The precautions for file-write during RUN are as follows.

(a) The file-write during RUN can be executed when any of the following
conditions is met.
1) Program memory
• When continuous space is available.
• When space is available.
2) Memory card
• When space is available.
(b) Please note that scan time could be extended as shown below in the table if
the file-write during RUN is executed. Controls are stopped for some time
as specified by a value in the table.
Event QnCPU QnHCPU
When continuous space is available in a program memory max. 80 ms max. 300 ms
When space is available in a program memory max. 80 ms max. 300 ms
When space is available in a memory card (except ATA card) max. 120 ms max. 570 ms

Please note that scan tame is extended for 1.25 seconds at 30 k step when
an ATA card is in use.
(c) Please note that no access can be made from an instruction in a sequence
program while a batch of files is written, with the High Performance model
QCPU in the RUN status. While the file-write during RUN is being
executed, an instruction to make access to a file is not executed.
(d) Do not execute file write during RUN simultaneously from multiple locations.
Doing so may erase program file contents.
(e) If a sequence program file being executed is written when the High
Performance model QCPU is in the RUN status, the following will not work
properly. After the write is complete, a fall instruction is executed only when
its execution condition is OFF.
• LDF
• ANDF
• ORF
• MEF
• PLF
(f) If batch write of SFC program files during RUN is executed, an initial start is
made after execution.

POINT
The following CPU module and GX Developer versions are required to execute
batch write of SFC program files during RUN.
• CPU module whose serial No. is "04122" or later
• GX Developer Version 8 or later

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7.13 Execution Time Measurement

This is a function to display the processing time of the program being executed.

This is used to find out the effect of each program's processing time on the total scan
time.

There are three functions to the execution time measurement. The details of each
function are indicated in sections 7.13.1 to 7.13.3.
• Program monitor list
• Interrupt program monitor list
• Scan time measurement

7.13.1 Program monitor list

(1) What is Program Monitor List?

(a) This is a function to display the processing time of the program being
executed.

(b) The scan time, number of times executed, and processing time by item can
be displayed for each program.

(2) Using the Program Monitor List

(a) Choose "Online" "Monitor" "Program monitor list". "Program Monitor
List" dialog box appears on screen.

(b) The following shows an example of executing program monitor list.

b)

a)

c)

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a) "Total Scan Time"

The monitor time set in WDT(the watch dog timer) of "PLC RAS" tab
screen in the (PLC) "Parameter" dialog box and total scan time for
each program type are displayed.
• "Monitor Time"
The monitoring time for the scan execution type program,
initialization program, and low speed execution type program are
displayed.
If the scan time exceeds this time, the High Performance model
QCPU displays the watch dog timer error.
• "Sum of Scan Time"
The total time in each item stated in "Scan Time Details for Scan
Execution" are displayed.
"Constant" indicates the constant scan waiting time when the setting
is made for constant scan.

b) "Scan Time Details for Scan Execution"

The details of the scan time are displayed.
• "Program"
The total execution time of the scan execution type program is
displayed.
• "END operation time"
The END operation time is displayed.
• "Low speed program"
This indicates the total execution time of a low speed execution type
program when making the setting for the execution time of a low
speed execution type program or constant scan time.
• "Constant waiting"
The constant scan waiting time is displayed when setting the
constant scan time. However, when the low speed execution type
program execution time is set as well, this value is 0.000 ms.
c) "Each Program Execution Status"
The execution status of program specified at the "Program" tab screen
in the (PLC) "Parameter" dialog box is displayed.
• "Program"
The program name is displayed in the order set in the parameter.
• "Execute"
The program type set in the parameter is displayed.
• "Scan Time"
The actual scan time (current value) is displayed. At the program
stop (wait) status, the scan time is displayed as 0.000 ms.
• "Execute count"
The number of times the program was executed is displayed, setting
the starting point of when the measurement is started as "0". The
number of execution times is displayed up to 65535 times and
returns to 0 when the 65536th time measurement is made. The ex
times remains even when the program is stopped.

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(3) Program can be started and stopped on the program list monitor
screen.
(a) Startup program button
Clicking the startup program button displays the following dialog box.

1)

2)

1) Program name
Only the program, that is set at the "Program" tab screen in “(PLC)
Parameter" dialog box, can be selected. It is not allowed to enter a
program name freely.

2) Startup mode
A stand-by type program for "Scan execution", "Low speed execution"
or "Fixed scan execution" can be set.
Startup mode defaults to the value that was set by choosing [PLC
Parameter] - <Program>. ms or s can be selected as the unit.

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(b) Stop program button

Clicking the stop program button displays the following dialog box.

1)

2)

1) Program name
Only the program, that is set at the <Program> tab in the “(PLC)
Parameter" dialog box, can be selected.
It is not allowed to enter a program name freely.

2) Stop mode
• Executing "After stop, output stop" for the scan execution type turns
off the output (non-execution processing) at the next scan. The
program is put in the standby status at and after the next scan. (This
operation is the same as performed when the POFF instruction is
executed.)
• Executing "After stop, output stop" for the low speed execution type
suspends the execution of the low speed execution type and turns
off the output at the next scan. The program is put in the standby
status at and after the next scan. (This operation is the same as
performed when the POFF instruction is executed.)
• Executing "After stop, output stop" for the standby program stops the
program after one-scan OFF is executed as scan execution.
For this reason, "Execute count" is also increased by 1.
• "Execute count" is also increased by 1 if an error occurs in the
RET/IRET instruction during execution of one-scan OFF in the
standby program.
At this time, the execution type is "scan execution".

POINT
Depending on the instruction, the output may not turn OFF if "After stop, output
stop" is executed.
For details, refer to the section of the POFF instruction in the following manual.
• QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)

(4) Precaution
The scan time of a constant scan execution type program being executed is not
displayed on screen, but a dash (-) is displayed in the Scan Time column.

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7.13.2 Interrupt program monitor list

(1) What is Interrupt Program Monitor List?

(a) This function displays execution count of the interrupt program (I0 to I255).

(b) This is used to confirm the execution status of the interrupt program.

(2) Using the Interrupt Program Monitor List

Choose "Online" "Monitor" "Interrupt program monitor list". The "Interrupt
Program Monitor List" dialog box appears on screen.

The following shows an execution example of the interrupt program monitor list:

a) b)

a) "Execute count"
The number of times the interrupt program was executed is displayed.
This function starts counting the number when High Performance
model QCPU is in RUN status (When the number reaches 65536
times, it is reset to 0).
b) "Common Comment"
This indicates device comments created on interrupt points (I0 to
I255).

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7.13.3 Scan time measurement

(1) What is Scan Time Measurement?

(a) This function displays the set program interval processing time.

(b) To specify a scan time measurement range, follow either of the following
two steps:
• Make the setting on the "Ladder monitor" window.
• Make the setting on the "Scan Time Measurement" dialog box.

(c) The time for the subroutines and interrupt program can be measured as
well.

(d) The time includes the time required for processing sub-routines, when the
sub-routine CALL command is within the range of scan time measurement.
The amount of time required for executing interruption programs and fixed
scan execution type programs is all added to this.
Measurement range

Main
program

Sub-routine
program

Measurement range

(2) Measuring Scan Time

To measure scan time, follow the following steps.
(a) Display the leading edge of the circuit of which scan time to be measured,
and set the monitor mode.

Y20
50 M0

Y21
52 M1

Y22
104 M2

106 END

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(b) The scan time measurement range is specified.

(The specified area is highlighted.)
Y20
50 M0

Y21
52 M1

Y22
104 M2

106 END

(c) Choose "Online" "Monitor" "Scantime measurement" to open "Scan

time Measurement" dialog box.

(d) Click on the "Start" button.

(3) Precautions
(a) Set the "Measurement limit" so that the value of "Start step" is larger than
that of "End step".

(b) The scan time to skip to another program file cannot be measured.

(c) If the measurement time is less than 0.100 ms, 0.000 ms is displayed.

(d) If a measurement range is specified between the FOR instruction and the
NEXT instruction, scan time will show the execution time of making a
measurement in the measurement range between specified steps.

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7.14 Sampling Trace Function

POINT
(1) The SRAM card (Q2MEM-1MBS, Q2MEM-2MBS) is required to store the trace
data and trace results.
After mounting the SRAM card to the High Performance model QCPU, execute
sampling trace.
(2) Sampling trace is not executed if the Flash card (Q2MEM-2MBF, Q2MEM-
4MBF) or ATA card (Q2MEM-8MBA, Q2MEM-16MBA, Q2MEM-32MBA) is
installed, because the cards cannot store the trace data and trace results.

(1) What is Sampling Trace Function?

(a) This function samples the device continuously on the High Performance
model QCPU at specified timings.
(b) The changed contents of the device that program uses during debugging
can be checked at the specified timing.
The sampling trace function reads device contents if trigger conditions are
satisfied.
(c) The sampling trace samples the contents of the specified device at a set
interval (sampling cycle), and stores the trace results at the sampling trace
file in the memory card.
(d) The sampling trace file stores the trace condition data and trace execution
data necessary to perform the sampling trace. When trace is started by
using GX Developer, the trace is performed as many times as specified.
The sampling trace area is 60 kbyte.
The number of traces can be obtained by dividing 60 kbyte by the number
of bytes specified as a device. The experssion is: (Number of Bit Devices) /
1
8 + 2 (Number of Word Devices)
1: Round up result of "(number of Bit Devices)/8" in the expression to the
right of the decimal point.

High Performance model QCPU

Memory card GX Developer

Specified Sampling trace area
device data Sampling trace area
1 Data for 1st time Read to the 1 Displays the
Device data for the
2 Data for 2nd time peripheral 2
area specified
3 Data for 3rd time device 3
4 Data for 4th time 4 amount Sampling trace
File
register 5 Data for 5th time 5 data monitoring
area 6 Data for 6th time 6

n-1 Data for (n-1)th time n-1

n Data for n th time n

When stored for n th time, the next

data overwrites the 1st time data.

If the trigger point is executed, the sampling trace area data is latched after sampling as many times as specified.

Fig. 7.8 Sampling Trace Operation

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(e) The trace result displays the ON/OFF status of the bit device for the
sampling cycle, and the current value of the word device.

POINT
Device details are read under trigger conditions specified in the trigger point setting.
Sampling is performed for each scan. Before the sampling is finished by a trigger
operation of a peripheral device, data is sampled twice because the sampling
timing is the same as that of trigger conditions.

Sampling trace data

Data when trigger condition is met

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(f) The execution status of the sampling trace function is stored in the special
relay (SM800, SM802, SM804 and SM805).
If an error occurs while the sampling trace function is used, SM826 turns
on. By using special relays in a sequence program, the execution status of
the sampling trace function can be checked.
1) After the "trace data" and "trace conditions" set using GX Developer
are written to the High Performance model QCPU, SM800 (sampling
trace ready) turns on. SM800 indicates whether the sampling trace can
be executed or not.
2) When a sampling trace start request is accepted, the sampling trace
starts and SM802 (sampling trace executing) turns on. SM802
indicates whether the sampling trace is executed or not.
• A trace from GX Developer starts.
• SM801 is turned on.
3) When a next trigger condition is satisfied, SM804 (after sampling trace
trigger) turns on. SM804 indicates whether the trigger conditions are
satisfied or not.
• A trigger from GX Developer executed.
• The TRACE instruction is executed.
• SM803 is turned on.
4) After the sampling trace is completed, SM805 (sampling trace
complete) is turned on.
Trigger SM801 SM801 Trigger Trace
execution OFF ON execution complete

Number of Number of
trace after trace after
trigger Clear the trace count trigger

SM800
(Sampling trace ready)

SM801
(Sampling trace start)

SM802
(Sampling trace executing)

SM803
(Sampling trace trigger)

SM804
(After sampling trace trigger)

SM805
(Sampling trace complete)

When trace is interrupted from GX Developer, the SM800 is also turned off.

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(g) Trace interrupt

1) When SM801 (sampling trace start) is turned off during sampling trace,
the sampling trace is interrupted.
In the meantime, the number of traces is cleared.
2) When turning on SM801 again, trace is restarted.
Trigger SM801 SM801 Trigger Trace
execution OFF ON execution complete

Number of Number of
trace after trace after
trigger Clear the trace count trigger

SM800
(Sampling trace ready)

SM801
(Sampling trace start)

SM802
(Sampling trace executing)

SM803
(Sampling trace trigger)

SM804
(After sampling trace trigger)

SM805
(Sampling trace complete)

When trace is interrupted from GX Developer, the SM800 is also turned off.

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(2) Operation Procedure

The sampling trace operation is performed in the following procedures:
Each operation is performed on the "Sampling trace" dialog box within the online
mode trace menu.
(a) Trace Device Setting
Set the device to perform sampling trace at the "Trace data" tab screen in
the "Sampling trace" dialog box.

1) Bit Device
Maximum of 50 bit devices can be set as follows.
• X, DX, Y ,DY, M, L, F, SM, V, B, SB
• T(contact), T(coil), ST(contact), ST(coil)
• C(contact), C(coil)
• J \X, J \Y, J \B, J \SB, BL \S
2) Word Device
Maximum of 50 word devices can be set as follows.
• T(current value), ST(current value), C(current value), D, SD, W, SW,
R, Z, ZR,
• U \G, J \W, J \SW

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(b) Setting the Trace Condition

Set the trace condition at the "Conditions" tab screen in the "Sampling
trace" dialog box.
The trace condition setting can set to "No. of traces", "Trace point setup",
"Trigger point setup", and "Additional trace information".

1) No. of traces
a) The "No. of times" sets the number of times to execute the
sampling trace from trace execution to trace complete.
b) The "After trigger number of times" sets the number of times to
executes the sampling trace from trigger execution to trace
complete.
Trace start Trigger point Trace complete

After trigger number

of traces

No. of times (Number of total times)

c) The setting range for each number of times is shown below:

(After trigger number of times) (No. of times) (8192)

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2) Trace Point Setup

This sets the timing to collect trace data. Select one from the
following:
a) Each Scan
Collects trace data for every scan (END processing).
b) Interval
Collects trace data at specified times.
c) Detailed
Sets the device and step no. The setting method and trace data
sampling timing is the same as mentioned in section 7.11.1.,
(when setting the monitor condition.)
The devices that can be set in the detailed condition are as
follows:
• Bit Device : X, Y, M, L, F, SM, V, B, SB, T(contact),
ST(contact), C(contact), J \X, J \Y, J \B, J
\SB, BL \S
• Word Device : T(current value), ST(current value),C(current
value), D, SD, W, SW, R, Z, ZR, U \G, J \W, J
\SW
The following attributes can be set for the above devices:
• Bit device number of digits specification
• Word device bit number specification
3) Trigger Point setup
This sets the point to execute the trigger. Select one from the
following:
a) At the time of TRACE order:
The time of execution of TRACE instruction is set as the trigger.
b) At the time of trigger operation:
The trigger operation from GX Developer device is set as the
trigger.
c) Detailed setting
The device and step number is set. The setting method and
trigger execution timing is the same as mentioned in Section
7.11.1., (the monitor condition setting.)
4) Additional trace information
The information to be added for every trace is set. Multiple items can
be selected from the following (of none of the items have to be
selected):
a) Time
Stores the time when the trace was executed.
b) Step No.
Stores the step number when the trace was executed.
c) Program Name
Stores the program name that executed the trace.

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(c) The created trace data and trace condition is written to the memory card.
The trace file is written to the memory card (SRAM card).
The trace file is written to the memory card (SRAM card) from the "Write to
PLC" dialog box in the "Sampling Trace" dialog box.
The files are written in the memory card (SRAM card) with file names, so
multiple trace files can be stored.
(d) Sampling trace is executed.
The sampling trace is executed at the " Execute and status" tab screen in
the "Sampling Trace" dialog box.

Displays only when

"Display Status" is selected

"Operation", "Trace data (Condition + Results) storing dest", and "Trace

condition" can be set when "Execute and Status" is displayed.
1) At the "Operation" section, select one of the following:
• Start trace
The trace is started. Starts to count the trace count.
• Stop trace
The trace is interrupted. The total trace count and trace count after
trigger are cleared. (When restarting trace, select "Start trace" again.)
• Execute trigger
Starts to count the trace count after trigger. The trace is complete
when the trace count reaches the specified trace count after trigger.
• Regist trace
Registers trace data when a program is executed.
2) In the "Trace data (Conditions+Results) storing dest." section, specify a
file name of a file in which to store trace data and trace conditions.
Trace results are also stored in a selected file with a specified file
name.

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3) At the "Trace Condition" section, select one of the following:

• Execute by overwriting the conditions on PLC side.
Overwrites trace condition to the existing trace file.
• Execute by following conditions written on PLC side
Executes the program with the conditions in the trace file specified in
"Trace Data (Condition + Results) storing dest".
(e) Read the trace results form the High Performance model QCPU and display
the data.
1) "Read from PLC" reads the trace result from the High Performance
model QCPU.
2) The read trace results appears in "Trace results" display.

POINT
Sampling trace is executed only once.
When re-executing, execute the TRACE instruction, and reset the sampling trace.

(3) Precautions
(a) SRAM card is required for sampling trace.
Set the sampling trace file in the memory card (SRAM).
(b) The sampling trace can be executed from other station on the network or
serial communication module. However, the trace cannot be executed from
multiple areas at once. The trace can only be executed from one area with
High Performance model QCPU.
(c) The trace information (trace file) registered in the High Performance model
QCPU is registered in the SRAM card and latched. As the condition data is
stored in the trace file, even if the power is off or the High Performance
model QCPU is reset, the sampling trace can be executed under registered
trace conditions.
At power on/reset of High Performance model QCPU, latched trace
information is cleared in the cases where:
• The SRAM card registered in a trace file is not inserted
• The trace file is corrupted
This requires registering trace information once again by operating from
GX Developer.
To clear data, perform the latch-clear operation with the RESET/L.CLR
switch.
To perform sampling trace again after latch clear, execute sampling trace
after selecting "Regist trace".
(d) This is performed by connecting the High Performance model QCPU and
GX Developer.
(e) While in STOP status, the High Performance model QCPU cannot read
sampling trace results. To enable the High Performance model QCPU to
read the sampling trace results, enter the High Performance model QCPU
into RUN status.
(f) When executing the sampling trace, ensure that trigger conditions cannot
be satisfied at trigger points. If the trigger conditions are met when
executing the sampling trace, they will not be recognized as trigger
conditions.

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7.15 Debug Function with Multiple Users

(1) What is Debug Function with Multiple Users?

(a) This function performs debugging from multiple GX Developer connected to
High Performance model QCPU or Serial communication module at the
same time.
(b) If debugging tasks are classified by process or by function, this function is
used to perform debugging of different files from multiple GX Developer at
once.

(2) Function Description

The debug function combination for multiple users are as follows:
Functions to be executed
Write Execution time Sampling
later Monitor
during RUN measurement trace
Functions being executed
Monitor
Write during RUN
Execution time measurement
Sampling trace
: Can be performed at the same time. (However, the detailed condition can only be set from
one GX Developer. In this case, the detailed condition setting cannot be performed from
another GX Developer.)
: Can only be performed from one GX Developer. (This function cannot be performed by the
GX Developer while it is being executed by another
GX Developer.)

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7.15.1 Multiple-user monitoring function

(1) What is Multiple-User Monitoring Function?

(a) The multiple-user monitoring operation can be performed by operating from
multiple GX Developers connected to the High Performance model QCPU
or the Serial communications module.
(b) Multiple users can monitor at the same time. By setting a station monitor
file, high speed monitoring can be performed. (It is not necessary to set
host station monitor file.)

(2) Operation Procedure

(a) For multi-user monitoring operation, create a user-defined system file in the
following steps.
1) Choose "Online" "Format PLC Memory" to open the "Format PLC
Memory" dialog box.
2) Select "program memory" from the "Target Memory list box".
3) At the "Format Type" section, select "Create a user setting system
area..." so that its radio button is checked.
4) Specify the desired k steps in the "System Area" text box.
(b) The follwing figure illustrates an example in which "1k step" is specified in
the "System Area" text box.

1) A maximum of 15 k steps can be set in 1 k step modules as a system

area. Only 1 k step can correspond to one station monitor file.
Therefore, a maximum of 15 station monitor files can be set.

(3) Precautions
(a) The detailed condition setting of the monitor can only be set from one area.
(b) Monitoring can be performed even if a station monitor file is not set, but high
speed monitoring cannot be performed.
The system area is in the same area as the program memory, so the area
of the stored program decreases when the system area is set.
(c) When a user-defined system area of 15k steps is created, simultaneous
monitoring of a single CPU from 16 areas can be speeded up.

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7.15.2 Multiple-user RUN write function

(1) What is Multiple-User RUN Write Function?

(a) Multiple users can write to one file or different files during RUN.
(b) To enable multiple users to write to a single file at the same time during
RUN operation, specify the desired pointer for the "write during RUN" in
advance, and then select "Relative step No. by pointer" so that its radio
button is checked.

(2) Operation Procedure

The multiple-user RUN write operation is performed in the following procedures:
(a) Select Tool from Option menu and set "After conversion writing behavior"
and "Step No. specification used in writing".

1)

2)

1) Set "Write during RUN (while PLC is runnning)" in "After conversion

writing behavior".
2) Select "Absolute step No. (default)" or "Relative step No. by pointer" in
"Step No. specification used in writing".

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(b) The specified circuit of the pointer is displayed to write the circuit after
conversion during RUN.
The following is an example of GX Developer A writing during RUN from P0
and GX Developer B writing during RUN from P1. The program area
surrounded with is the area to be written during RUN.

Area after P0 in the processing Area after P1 in the processing

program is written during RUN. program is written during RUN.
X0 X2 X0 X2
P0 Y30 P0 Y30
X1 X1
Serial
communication
module
X3 X4 X3 X4
P1 SET M10 P1 SET M10
X5 X5

END END

Personal computer A Personal computer B

(GX Developer) (GX Developer)

(3) Precautions
Precautions on "write during RUN" is the same as precautions on "write during
RUN in the circuit mode" in Section 7.12.1. For further information, see Section
7.12.1.

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7.16 Watch dog Timer (WDT)

(1) What is Watch dog Timer (WDT)?

(a) The watch dog timer is an internal sequence timer to detect High
Performance model QCPU hardware and sequence program error.
(b) When the watch dog timer expires, a watch dog timer error occurs.
The High Performance model QCPU responds to the watch dog timer error
as follows:
1) The High Performance model QCPU turns off all outputs.
2) The front-mounted RUN LED turned off, and the ERR. LED starts
flicking.
3) SM1 turns ON and the error code 5001 (WDT ERROR) is stored in
SD0.
(c) The default value of the watch dog timer is 200 ms.
The setting range is 10 to 2000 ms (in 10ms units).

(2) Watch dog Timer Setting and Reset

(a) The watch dog timer setting can be changed at the "PLC RAS" tab screen
in the “(PLC) Parameter" dialog box.
(b) High Performance model QCPU resets the watch dog timer during the END
processing.
1) When the END/FEND instruction is executed within the set value of the
watch dog timer in the sequence program and the High Performance
model QCPU is operating correctly, the watch dog timer does not time
out.
2) When the scan time of a sequence program is extended due to the
High Performance model QCPU hardware error or execution of
interrupt program/fixed scan execution type program, and END/FEND
instruction cannot be executed within the set watch dog timer value,
the watch dog timer times out.

(3) Precautions
(a) An error of 0 to 10 ms occurs in the measurement time of the watch dog
timer. Set the watch dog timer for a desired value by taking such an error
into account.
(b) The watch dog timer is reset with the WDT instruction in the sequence
program. If the watch dog timer expires while the FOR and NEXT
instructions are repetitiously executed, reset the watch dog time with the
WDT instruction.

FOR K1000

Program for repetition processing

Repetition
M0 (1000 times)
WDT WDT reset

NEXT

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(c) The scan time value is not reset even if the watch dog timer is reset in the
sequence program.
The scan time value is measured to the END instruction.

Internal processing time Sequence program Internal processing time

Low speed execution type Low speed execution type
program C program C
Scan execution Scan execution Scan execution type
END 0 type program A type program B END 0 program A

Next scan time

WDT reset Scan time WDT reset (QCPU internal processing)
(QCPU internal processing)
Watchdog timer measured time

Fig. 7.9 Watch dog Timer Reset

REMARK
1) Scan time is the time from when the High Performance model QCPU starts
processing a sequence program at Step 0 until it restarts processing another
sequence program with the same filename at Step 0.
The scan time is not the same at every scan, and differs, depending on
• Whether the commands used are executed or not executed.
• Whether to execute or not an interrupt program and a fixed scan execution
type program.
2) To execute at the same scan time at every scan, use the constant scan function.
For details of the constant scan function, see section 7.2.

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7.17 Self-Diagnosis Function

(1) What is Self-Diagnosis Function
(a) The self-diagnosis is a function performed by the High Performance model
QCPU itself to diagnose whether there is an error in the High Performance
model QCPU.
(b) The self-diagnosis function is used to prevent the High Performance model
QCPU erroneous operation as well as preventive maintenance.
The self-diagnosis processing detects and displays the error when an error
occurs at the High Performance model QCPU power on or during High
Performance model QCPU RUN mode. It also stops High Performance
model QCPU calculations.

(2) Processing for Error Detection

(a) When the High Performance model QCPU detects an error, it turns on
ERR. LEDs. When an error is detected, special relays (SM0, SM1) are
turned ON and an error code of the error is stored in the special register
SD0. When multiple errors are detected, error codes of the latest errors are
stored in the special register SD0. For error detection, use special relays
and special registers in programs so that these devices can interlock with
sequencers and mechanical systems.
(b) The High Performance model QCPU stores 16 latest error codes. (See
Section 7.18.)
The failure history can be checked in the GX Developer function PLC
diagnostics mode.
The failure history can be stored even when the power is shut off using the
battery backup.

(3) High Performance model QCPU operation at the time of error

detection
(a) When an error is detected from the self-diagnosis, there are two types of
modes that the High Performance model QCPU operation can change to.
1) High Performance model QCPU calculation stop mode
The calculation is stopped on detecting an error, and all outputs of
modules are set to OFF if the outputs for the modules have been set to
"Clear (Default)" at the "Error time output mode" section in the "I/O
assignment" tab screen within the “(PLC) Parameter" dialog box. And
output (Y) is held.
(The outputs (Y) on the device memory are retained.)
However, the outputs of the modules are held if they have been set to
"Hold" there. The output (Y) is also held.
2) High Performance model QCPU calculation continue mode
When an error is detected, the program (Instruction) area where the
error occurred is skipped and the rest of the program is executed.
(The outputs (Y) on the device memory are retained.)
(b) The calculation "continue/stop" can be set at the "PLC RAS" tab screen in
the (PLC) "Parameter" dialog box if the following error occur.
(All parameter defaults are set at "Stop".)
1) Computation error
2) Expanded Command error
3) Fuse blown
4) I/O module comparison error
5) Intelligent module program execution error
6) Memory card access error
7) Memory card operation error
8) External power supply OFF
For example, when the I/O module verification error is set to "continues",
the calculations are continued in the I/O address before the error occurred.
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(4) Error check selection

The following error checking can be set to "yes/no" at the "PLC RAS" tab screen
in the “(PLC) Parameter" dialog box.
(All parameter defaults are set at "Yes".)
(a) Battery check
(b) Fuse blown check
(c) I/O unit comparison

Self-Diagnosis List
Diagnosis description Error message Diagnostic timing

CPU error MAIN CPU DOWN • Always

END instruction not executed END NOT EXECUTE • When the END instruction is executed
RAM check RAM ERROR • When the power is turned on/when reset
Calculation circuit check OPE.CIRCUIT ERR. • When the power is turned on/when reset
1 • When the END instruction is executed
Fuse blown (default... stop) FUSE BRAKE OFF
(Default... Yes) 2
Hardware failure I/O interrupt error I/O INT ERROR • When an interrupt occurs
• When the power is turned on/when reset
Intelligent function module error SP.UNIT DOWN
• When the FROM/TO instruction is executed
• When the power is turned on/when reset
Control bus error CONTROL-BUS ERROR. • When the END instruction is executed
• When the FROM/TO instruction is executed
Momentary stop occurred AC/DC DOWN • Always
3
Battery low BATTERY ERROR • Always (Default...Yes)
I/O module verification (Default... • When the END instruction is executed
UNIT VERIFY ERROR
Stop) 1 (Default... Yes) 2
Intelligent function module • When the power is turned on/when reset
SP.UNIT LAY ERR.
allocation error • When switched from STOP to RUN
Intelligent program execution error
SP.UNIT ERROR • When the FROM/TO instruction is executed
(Default... Stop) 1
Intelligent function module version
SP.UNIT VER.ERR. • When the power is turned on/when reset
error
Handling error No parameter MISSING PARA. • When the power is turned on/when reset
Boot error BOOT ERROR • When the power is turned on/when reset
Memory card operation error
ICM.OPE.ERROR • When the memory card is installed/removed
(Default... Stop) 1
File setting error FILE SET ERROR • When the power is turned on/when reset
File access error
FILE OPE.ERROR • When an instruction is executed
(Default.. Stop) 1
Instruction execution not possible CAN´T EXE.PRG. • When the power is turned on/when reset
• When the power is turned on/when reset
Parameter setting check PARAMETER ERROR
• When switched from STOP to RUN
• When the power is turned on/when reset
Link parameter error LINK PARA.ERROR
Parameter error • When switched from STOP to RUN
SFC parameter error SFC PARA.ERROR • When switched from STOP to RUN
Intelligent function module
SP.PARA.ERROR • When the power is turned on/when reset
parameter error

1:Can be changed to "Continue" in the GX Developer function parameter setting.

2:Can be set to "No" in the GX Developer function parameter setting. Also, checking is not performed when SM251 is on.
3:Can be set to "No" in the GX Developer function parameter setting.

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Self-Diagnosis List (Continued from the preceding page)

Diagnosis description Error message Diagnostic timing
• When the power is turned on/when reset
Password error REMOTE PASS.ERR.
• When switched from STOP to RUN
• When the power is turned on/when reset
Instruction code check INSTRUCT CODE ERR. • When switched from STOP to RUN
• When an instruction is executed
• When the power is turned on/when reset
No END instruction MISSING END INS.
• When switched from STOP to RUN
• When the power is turned on/when reset
Pointer setting error CAN´T SET(P)
• When switched from STOP to RUN
• When the power is turned on/when reset
Pointer setting error CAN´T SET(I)
• When switched from STOP to RUN
Operation check error (Default...
OPERATION ERROR When an instruction is executed
Stop) 1
FOR to NEXT instruction structure
FOR NEXT ERROR When an instruction is executed
error
CALL to RET instruction structure
CAN´T EXECUTE(P) When an instruction is executed
Program error error
Interrupt program error CAN´T EXECUTE(I) When an instruction is executed
Instruction execution not possible INST.FORMAT ERR. When an instruction is executed
SFC program structure error SFCP.CODE ERROR When switched from STOP to RUN

SFC block structure error CAN´T SET(BL) When switched from STOP to RUN
SFC step structure error CAN´T SET(S) When switched from STOP to RUN
SFC syntax error SFCP.FORMAT ERR. When switched from STOP to RUN
SFC operation check error
SFCP.OPE.ERROR When an instruction is executed
(Default... Stop) 1
SFC program execution error SFCP.EXE.ERROR When switched from STOP to RUN
SFC block execution error BLOCK EXE.ERROR When an instruction is executed
SFC step execution error STEP EXE.ERROR When an instruction is executed
Watch dog error supervision WDT ERROR Always
PLC error
Program time exceeded PRG.TIME OVER Always
• Always
Other CPU major error MULTI CPU DOWN
• When the power is turned on/when reset
Multiple CPU
Multiple CPU consistency error CPU VER.ERR. • When the power is turned on/when reset
Other CPU minor error MULTI CPU ERR. • Always
BOOT OK BOOT OK • When the power is turned on/when reset

Annunciator check F When an instruction is executed

CHK Instruction check <CHK>ERR - When an instruction is executed

1:Can be changed to "continues" in the GX Developer function parameter setting.

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7.17.1 Interrupt due to error occurrence

The High Performance model QCPU can execute the interrupt program of the interrupt
pointer that is set as the interrupt object when an error occurs.

Only when the error set to "continue" at the "PLC RAS" tab screen in the “(PLC)
Parameter" dialog box occurs, the High Performance model QCPU executes the
interrupt program corresponding to the error. When the error set to "stop" there occurs,
the interrupt program (I32) for "Stop all errors" is executed.

Interrupt pointer Corresponding error message

I32 Stop all errors
I33 Empty
I34 UNIT VERIFY ERR.
FUSE BREAK OFF
SP.UNIT ERROR
I35 OPERATION ERROR
SFCP OPE.ERROR Errors that occur when the system can continue
SFCP EXE.ERROR the drive mode, where or "continue" is selected from
I36 ICM.OPE.ERROR "continues/stops".
FILE OPE.ERROR
I37 EXTEND INS.ERR.
I38 PRG.TIME OVER
CHK instruction
I39
Annunciator detect
I40 to I47 Empty

POINT
(1) The interrupt pointers I32 to I39 is at an execution disable mode when the
power is started or High Performance model QCPU is reset. When using I32 to
I39, use the IMASK instruction and EI instruction to enable execution.
(2) : The I32 interrupt program is not executed upon the following serious errors.
• MAIN CPU DOWN
• END NOT EXECUTE
• RAM ERROR
• OPE CIRCUIT ERR.

7.17.2 LED display when error occurs

When an error occurs, the LED located on the front of the High Performance model
QCPU turns on / flickers.
See Section 7.21 for the details on the LED operation.

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7.17.3 Error cancellation

High Performance model QCPU error cancel operation can be performed only for error
that can continue the High Performance model QCPU operation.

(1) Error cancellation

(a) Procedures for error cancellation
The error cancel is performed as follows:
1) Resolve the cause of error.
2) Store the error code of the error to be canceled in the special register
SD50.
3) Switch special relay SM50 from OFF to ON.
4) The error is canceled.

(b) Status after error cancellation

When the CPU module is recovered by canceling the error, the special
relay, special register, and LED affected by the error are set to the status
before the error occurred.
When the same error occurs after canceling the error, it is logged again in
the failure history.

(c) Cancellation of annunciator

For the cancellation of the annunciator detected multiple times, only the first
detected "F" is canceled.

POINT
(1) When error cancellation is performed by storing the code of the error to cancel
is stored in SD50, the lower 2 digits of the code number is ignored.
[Example]
When the error codes 2100 and 2101 occur, canceling the error code 2100 will
also cancel the error code 2101.
When 2100 and 2111 occur in the error code and error code 2100 is canceled,
error code 2111 is canceled as well.
(2) If the cause of the error is not in the CPU module, the error cause cannot be
resolved if error cancellation is performed using the special relay (SM50) and
special register (SD50).
[Example]
Since "SP. UNIT DOWN" is an error that occurred on the Q bus, the error
cause cannot be resolved if error cancellation is performed using the special
relay (SM50) and special register (SD50).
Refer to the error code list in the High Performance model QCPU (Q mode)
User's Manual (Hardware Design, Maintenance and Inspection), and resolve
the error cause.

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7.18 Failure History

The High Performance model QCPU can store the failure history (results detected from
the self-diagnosis function and the time) in the memory.

POINT
The detection time uses the High Performance model QCPU internal clock, so
make sure to set the correct time when using the High Performance model QCPU
for the first time.

(1) Storage Area

(a) The latest 16 failures are stored in the latched High Performance model
QCPU failure history storage memory.

(b) When storing more than 16, the history can be stored in the memory card
file using PLC RAS setting in the “(PLC) Parameter” box.

(c) When the history count set in the parameter and that stored in the memory
card are different after the following operation is performed, the contents of
the memory card history file is cleared, then the 16 failure data in the High
Performance model QCPU failure history storage memory is trandferred to
the history file.
1) When the history count in the parameter history file is changed in the
middle of operation.
2) When a memory card, which has a different history count from that set
in the parameter, is mounted.

(d) The storage area in the failure history file is as follows:

Storage area File in the set memory card
1
Amount that can be stored Max. 100 (can be changed)
1: When the number of storage exceed the amount that can be stored, the oldest
history is overwritten with the latest history.

POINT
Even if the failure history file set in the parameter does not exist in the memory
card, the error will not occur in the High Performance model QCPU.
The High Performance model QCPU stores the failure to the failure history storage
file.

(2) Failure History Clearing Method

The failure history storage memory/failure history file are cleared using the failure
history clear in the GX Developer PLC diagnosis mode.
Data stored in both the High Performance model QCPU failure history storage
memory and failure history file within the memory card can be cleared with a
failure history clear.

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7.19 System Protect

The High Performance model QCPU has a few protection functions (system protect) to
prevent the program changes by a third party other than the designer (from GX
Developer function or serial communication module).
There are the following methods for system protects.
Valid
Item to protect Protect valid file Protection description Method Remarks
Timing
Set the High
Prohibits all write/control
Performance model Valid for
All of CPU All files instructions to the High Always
QCPU system setting devices too
Performance model QCPU
switch SW1 on.
Memory card Performs drive protect for the Set write-protect switch
All files Always —
module memory card, and write protect. on the memory card on.
Changes the attribute for each
Programs Change the attribute for
file as follows:
File module Device comments the file in the Password Always —
1) Read/Write display prohibit
Device initial values Registration.
2) Write prohibit

The control instruction, read/write display, and write mentioned above are as follows:

Item Description
High Performance model QCPU operation instruction by
Control instruction
remote operation. (Remote RUN, remote STOP, etc.)
Read/Write display Program read/write operations.
Operation related with write processing such as program
Write
writes the program and tests.

POINT
The following functions set the “(PLC) Parameter" and High Performance model
QCPU dip switches are performed even when the High Performance model QCPU
system's SW1 setup switch is set to ON and the system protect function is
activated.
• Booting from the standard ROM and the memory card
• Automatic write to standard ROM

7.19.1 Password registration

Password is used to prohibit reading and writing data of the program and comments in
High Performance model QCPU from GX Developer.
The Password Registration is set for the specified memory (program memory/standard
memory/memory card) program file, device comment file, and device initial file.
Either of the following two descriptions is to be registered.
• The file name is not displayed and read/write cannot be performed as well.
• Write cannot be performed to the file. (Read only)
If the password is registered, file operations from GX Developer cannot be performed
unless the same password is input.

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(1) Password Registration

To register the password, select GX Developer Online Password
setup/keyword set up for writing to PLC Register password.

(a)

(b) (c) (d) (e) (f)

Each item is described below:

(a) Target memory ....................Specifies the memory storing the file whose
password is to be registered or changed.

(b) Data type..............................Displays the type of a file stored in the target

memory.

(c) Data name ...........................Displays a filename of a file stored in the target

memory.

(d) Registration..........................Displays an asterisks " " that indicates a

password-protected file.

(e) Password .............................Defines or changes a password.

(f) Registration Condition

1) Write Protect ................Write operation is restricted by a password.
(Reading is not allowed.)
2) Read/Write protect.......Read/Write operation is restricted by a
password.
3) Clear.............................Password is cleared.
(Sets password currently registered in
"Password".)

POINT
(1) Password-protected files are limited to program files, device comment files, and
device initial value files. Other files cannot be password-protected.
(2) The password registered to a file can not read out from the file.
If the password can not be remembered, file operation other than following can
not be performed.
• Program memory/Memory card: Format PLC memory
• Standard ROM: Write to PLC (Flash ROM)
Take notes of the password registered and keep it on hand.

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7.19.2 Remote passwords

The remote password function prevents illegal access to the High Performance model
QCPU by users in remote locations.
The remote password function is enabled for use by setting it up in the High
Performance model QCPU.
When the remote password function has been set, a check will be run on remote
passwords when users in remote locations attempt to access the High Performance
model QCPU with serial communication modules or Ethernet modules with modem
functions.

(1) Setting up, amending and canceling remote passwords

(a) Remote password setup
Remote passwords are set up on the GX Developer's remote password
setup screen. The GX Developer is then connected to the High
Performance model QCPU into which the remote password is to be set,
and the password uploaded.
The High Performance model QCPU will transmit the remote password to
specified serial communication modules and Ethernet modules when the
power supply to the sequence is switched on or the High Performance
model QCPU is reset.

(b) Amending and canceling remote passwords

It is possible to amend and cancel remote passwords by connecting the GX
Developer to the relevant High Performance model QCPU.
Remote passwords set in the High Performance model QCPU can be
amended or cancelled by setting up an amended password or canceling a
remote password with the GX Developer.
Remote passwords cannot be amended or cancelled from a remote
location.

For example, an outline of what will happen when a remote passwords is

set up, amended or cancelled from an Ethernet module is shown below.

GX Developer

Ethernet
QJ71E71
Power supply

CPU module

The remote password is

transmitted to QJ71E71 A check is run on the remote password
when the power is switched
on or the system reset
. . . . The remote password is
GX Developer set up,
amended
or cancelled,
and the result written in the
High Performance model QCPU

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(2) Remote password lock/unlock processing

Unlocks the Ethernet module remote passwords for the access source via
modems, serial communication modules and the Ethernet.
Access to the High Performance model QCPU is enabled if the remote password
matches up.

For example, an outline of what will happen during remote password lock/unlock
processing with an Ethernet module is shown below.

GX Developer . . . . The remote password is unlocked (relesed) and access

to the QCPU is allows.
The remote password locking process is performed when
Ethernet the line is closed.

QJ71E71
Power supply

CPU module

The remote password is

transmitted to QJ71E71 A check is run on the remote password
when the power is switched
on or the system reset
GX Developer

(3) Number of remote password-set modules

The number of remote password-set modules changes depending on the version
of used GX Developer.
The following table indicates the number of remote password-set modules
depending on the GX Developer version.

Maximum Number of Maximum Number of Set

GX Developer Version Module Name
Set Modules Modules in System
Ethernet module 4 modules
Version6
Serial communication module 8 modules
Version7 4 modules
Modem interface module
Ethernet module 4 modules
Version8 or later Serial communication module 8 modules
8 modules
Modem interface module

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(4) Procedure for setting up the remote password

[GX Developer] [Remote Password] [Remote Password Setup] screen
[Advanced Remote Password Setup] screen.

(a) Setup screen

Remote password setup
Detail is required with
the QJ71E71

(b) Setup fields

Field Description Setup range/Selection range
Password settings Remote password entry 4 bytes, alphanumerics, special characters
Password active Model name Model selection QJ71E71/QJ71C24
module settings Start XY Module's head address setup 0000H to 0FE0H
Detail — Setup/Not setup
User's connection No. User's connection No. setup Connection No. 1 to Connection No. 16
Automatic open UDP port
FTP communication port
(TCP/IP)
System GX Developer communication Adds a check to the valid
—
connection port (TCP/IP) remote password port
GX Developer communication
port (UDP/IP)
HTTP port

POINT
Refer to the following manuals for further details on the remote password function.
• Using Serial Communication Modules
Q Corresponding Serial Communication Module Users' Manual (Application)
• Using Ethernet Modules
Q Corresponding Ethernet Interface Module Users' Manual (Basic)

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7.20 Monitoring High Performance model QCPU System Status from GX Developer
(System Monitor)

(1) In Case of GX Developer Version 4 (SW4D5C-GPPW-E) or GX

Developer Version 5 (SW5D5C-GPPW-E)
The System Monitor window provides the following information about the High
Performance model QCPU connected to the personal computer:
• Base information
• Installed status
• Parameter status
• Overall information
• Product information

(a) (d)

(b) (e)

(c)

(f) (g)

(a) Base Information

The Base Information section shows information about a selected base
unit: the name of a base unit (main base or extension base 1 to 7), the
number of slots, base type, the number of modules mounted on the base.
1) The "Base name" field indicates the main base or extension base (with
power source). It indicates the extension base even if a power source
module is not installed on the extension base.
2) The "Base type" field indicates the following abbreviations:
• Q for Q33B, Q35B, Q38B, Q312B
• Q for Q63B, Q65B, Q68B, Q612B
• QA for QA1S65B, QA1S68B
3) The "Number of Installed Module" field indicates the number of
modules installed on the base unit.

(b) Installed status

The "Installed status" section shows the model name of the selected base
unit and the number of points. The "slot" column indicates "Unmounting" if a
base unit is not installed in a particular slot.

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(c) Parameter status

The "Parameter status" section shows the I/O number of each slot of a
base unit, module type, and the number of points. If the number of available
points and the installed status are displayed in any column of the
Parameter status section, make the setting so that I/O assignments of PLC
parameter can match the installed status.

(d) Overall Information

The Overall Information section shows the number of base units used and
the number of modules installed on the base.

(e) Base
The Base section indicates the status of base units used and modules
installed. The Module column indicates the status of a module when the
module is in an abnormal condition.

(f) PLC diagnostics

This button is used to monitor the status of the High Performance model
QCPU and an error.

(g) Module's Detailed Information

This button is used to view detailed information about a selected module.
For details on intelligent function modules, see the manual of an intelligent
function module.

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(2) In case of GX Developer Version 6 (SW6D5C-GPPW-E) or later

It is possible to confirm the following information for High Performance model
QCPUs connected to personal computers with the GX Developer system monitor
(see illustration below.)
• Installed status
• Operation status
• Module’s detailed information
• Product information

(a) (c)

(b)

(d)
(e)

(f)
(g)

(a) Installed status

Enables the controlling CPU, the model an07 d the number of modules
mounted onto the selected base unit to be confirmed.
"Not installed" will be displayed for slots in which modules have not been
mounted.
When slots have been set as "Empty" at the "I/O assignment" tab screen in
the “(PLC) Parameter" dialog box, the module's model will not be displayed
when if a module has been mounted.
(b) Parameter status
Enables the I/O number, the module type and the number of modules
mounted for each of the slots on the selected base unit to be confirmed.
If the operation status shows 0 empty points and an allocation error is
displayed, it means that the PLC parameter's I/O allocation and the actual
status are different.
In this event, align the PLC parameter's I/O allocation with the actual status
by allocating an I/O.
(c) Base
Enables the status of the modules mounted onto the base unit in use to be
confirmed.
The status will be displayed in the unit column when an error has occurred
for even one of the modules.
(d) Diagnostics
This function is used to confirm the status of the High Performance model
QCPU and errors.

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(e) Module’s detailed information

This function is used to confirm the detailed information for selected
modules.
Refer to the instruction manual for details on the relevant intelligent function
module and intelligent function modules.

(f) Base information

Enables the "Overall Information" and "Base Information" to be confirmed.
1) Overall information
Enables the number of base units in use and the number of modules
mounted on the base units to be confirmed.
2) Base information
Enables the base name, the number of slots, the base type and the
number of modules mounted onto the base for the selected base unit
(main base unit, additional base units 1 to 7) to be confirmed.

(g) Product Information List

Enables the individual information for mounted CPU modules, I/O modules
and intelligent function modules to be confirmed (type, series, model,
number, head I/O, control PLC, serial No., function version.)

Serial No. Function version

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7.21 LED Display

The High Performance model QCPU has an LED to indicate the High Performance
model QCPU operation status on the front of the High Performance model QCPU.
The display details of each LED are described below.

7.21.1 LED display

(1) The details of the LED display are shown below:

LED name Display Description
Indicates the High Performance model QCPU mode (Q mode/ A mode)
ON (green): Q mode (No registration of enforced ON/OFF for external I/O)
Mode
ON (orange): A mode
Flicker (green) : with registration of enforced ON/OFF for external I/O
Indicates the CPU module operation status.
On : When operating with the RUN/STOP switch at "RUN".
Off : When stopped with the RUN/STOP switch at "STOP".
Or when an error that stops operation is detected.
Flicker : When writing parameters ad programs during STOP, and when setting the RUN/STOP switch
from [STOP] [RUN]. Perform the following operations in order to illuminate the RUN LED after
program writing.
• Set the RUN/STOP switch to [RUN] [STOP] [RUN].
RUN
• Reset the system with the RESET/L. CLR switch.
• Switch on the power to the PLC again.
Perform the following operations in order to illuminate the RUN LED after parameter writing.
• Reset the system with the RESET/L. CLR switch.
• Switch on the power to the PLC again.
(When the RUN/STOP switch has been set to [RUN] [STOP] [RUN] after the parameters
have been amended, the parameters related to intelligent function modules and other network
parameters will not be reflected back.)
Indicates the CPU module error detection status.
On : When a self-diagnosis error that does not stop the operation (except for battery error) is
detected. (Set the operation error set mode to "continue" in the parameter mode PLC RAS
ERR. setting.)
Off : Normal
Flicker : When an error that stops the operation is detected.
When automatic write to standard ROM is complete normally (BOOT LED also flickers)
The detection status for the CHK instruction or annunciator F status is indicated.
On : When an error is detected with the CHK instruction, or when the annunciator is turned on.
USER
Off : Normal
Flicker : When the latch clear is executed.
Indicates the CPU module and Memory card battery status.
BAT. On : When a battery error is detected due to low battery voltage.
Off : Normal
Indicates the execution status of the boot operation.
On : When the execution is complete.
BOOT
Off : When not executed.
Fricker : When automatic write to standard ROM is complete normally. (ERR. LED also flickers)

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(2) Method to turn off the LED

The LED that is on can be turned off by the following operation. (Except for the
reset operation.)
Applicable LED
Method to Turn LED Off
ERR. USER BAT. BOOT
Executing the LEDR instruction after resolving the cause of
error.
After the cause of error is resolved, cancel the error by
operating the special relay SM50 and special register SD50.
(Only for the operation continue errors.)
Turn off the LED by operating the special relay SM202 and
special register SD202.
: Valid : Invalid

1: Special relay and special register contents

SM50 ................. When switch from OFF to ON, the error is canceled for the error
code stored in the SD50.
SD50.................. The error code for the error to be canceled is stored.
(For further information on error codes, see the High Performance
model QCPU (Q Mode) Users Manual (Hardware Design,
Maintenance and Inspection)
SM202 ............... When turned from OFF to ON, the LED corresponding to each bit in
the SD202 is turned off.
SD202................ This specifies the LED to turn off. (Only USER LED and BOOT LED
can be turned off.)
15 bit 8 4 0 bit
SD202 1/0 1/0

BOOT LED USER LED

1 means "turn off" and 0 means "leave on" in the setting.

The setting to turn off each LED is as follows. (All in hexadecimal.)
• When turning off both LEDs: SD202=110H
• When turning off only the BOOT LED: SD202=100H
• When turning off only the USER LED: SD202=10H

(3) Method to not display the ERR. LED, USER LED, and BAT. LED
The ERR. LED, USER LED, and BAT. LED have the same priorities explained in
Section 7.21.2.
When an error number for an LED is deleted from this priority, the LED will not
turn on even if an error with that error number occurs.
(See POINT in Section 7.21.2 for the setting method.)

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7.21.2 Priority setting

When multiple factors that can be displayed occur, the display is performed with the
following conditions:
1) A stop error is displayed without condition.
2) An operation continue error is displayed according to the priority factor number set
as the default.
The priority can be changed. (Set with special registers SD207 to SD209)
3) When errors with the same priority level occur, the error detected first is displayed.

The priority is set with the special registers SD207 to SD 209 in the following manner:
(Factor number default value: Hexadecimal)
15 to 12 11 to 8 7 to 4 3 to 0 bit 15 to 0 bit
SD207 Priority order 4 Priority order 3 Priority order 2 Priority order 1 SD207 4 3 2 1

Factor number setting area

SD208 Priority order 8 Priority order 7 Priority order 6 Priority order 5 SD208 8 7 6 5

Factor number setting area

SD209 Priority order 10 Priority order 9 SD209 0 0 A 9

Neglected Factor number setting area

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The description and default priority for the factor number to be set in the special
registers SD207 to SD209 are as follows:
Factor number
Priority Description Remarks
(Hexadecimal)
1 1 AC/DC DOWN Power shutoff
UNIT VERIFY ERR. I/O module verification error
2 2 FUSE BREAK OFF Fuse shutoff
SP.UNIT ERROR Intelligent function module verify error
OPERATIN ERROR Calculation error
LINK PARA. ERROR Link parameter error
3 3
SFCP OPE.ERROR SFC instruction calculation error
SFCP EXE.ERROR SFC program execution error
ICM.OPE.ERROR Memory card operation error
4 4
FILE OPE.ERROR File access error
Constant scan setting time time up over
5 5 PRG.TIME OVER
Low speed execution monitoring time time up
6 6 CHK instruction
7 7 Annunciator
8 8 ——
9 9 BATTERY ERR.
10 A Clock data

POINT
(1) When leaving the LED turned off at the error described above, set the factor
number setting area (each 4 bits), which stores the factor number
corresponding to SD207 to SD209 to "0".
[Example]
To leave the ERR. LED off when a fuse shutoff error is detected, set the
factor number setting area to "0" where the error number is "2".
SD209 SD208 SD207

0 0 A 9 8 7 6 5 4 3 0 1

Because the factor number "2" is not set, the ERR. LED remains off even if the
fuse shutoff is detected. In this case, even if another error with the factor
number "2" (I/O module verify error or intelligent function module verify error) is
detected, the ERR. LED remains off.
(2) Even if the LED is set to be turned off, error code storage is performed for SM0
(Diagnostic error flag) on, SM1 (self-diagnosis flag) on, and SD0 (CPU
diagnostic error register).

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7.22 High Speed Interrupt Function

When an interrupt program is created using the interrupt pointer I49, the QnHCPU can
run a program by making high speed, fixed-cycle interrupts at intervals of 0.2ms to
1.0ms.
And, the QnHCPU improves the I/O response by refreshing the I/O signals and
intelligent function module buffer memories in the parameter-set ranges before and
after the execution of the high speed interrupt program.
High accuracy control, e.g. accurate positioning detection, is available with the PLC
CPU alone.
Interrupt cycle interval: 0.2ms (parameter setting)

Step 0 END
Main routine program
(Scan time 1ms)

I49 interrupt program

Main routine program

Waiting time

High speed interrupt start

X input

Buffer memory read

I49 overhead

High speed interrupt program execution

Buffer memory write

Y output

High speed interrupt end

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POINT
Since the high speed interrupt function need to pick up interrupts at very short
intervals of 0.2ms to 1.0ms with the interrupt pointer I49, please do not run the
interrupt programs, which use the other interrupt pointers I0 to I48, I50 to I255, and
fixed scan execution type programs.
If any of the interrupt and fixed scan execution type programs is executed, interrupt
cannot be made at the cycle intervals set for the high speed interrupt function.
Refer to Section 7.22.3 for other restrictions.

(1) Compatible CPUs

CPU Type Compatibility Remarks
Q02HCPU, Q06HCPU Upper 5 digits of serial No. is
Compatible
Q12HCPU, Q25HCPU "04012" or later
Q02CPU Incompatible —

(2) Specifications of high speed interrupt function

Item Description Remarks
Interrupt cycle interval 0.2 to 1.0ms 0.1ms units
Number of interrupt
1 Interrupt pointer I49
programs
To set the high speed interrupt function, choose "PLC system" - "System
interrupt settings" - "High speed interrupt setting" on the PLC parameter screen.

(3) Detailed items of high speed interrupt function

Item Description
Interrupt program execution Runs the interrupt program created with I49.
Updates I/O signals between the I/O, intelligent function
High speed I/O refresh
modules and CPU module at interrupt cycle intervals.
Updates data between the intelligent function module
High speed buffer transfer buffer memories and CPU module devices at interrupt
cycle intervals.

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7.22.1 High speed interrupt program execution

The high speed interrupt program execution function is designed to run an interrupt
program according to the setting of high speed interrupt pointer I49.
Set the high speed interrupt pointer I49 at "High speed interrupt I49 fixed scan interval"
after choosing "PLC system" - "System interrupt settings" - "High speed interrupt
setting" on the PLC parameter screen.

Set within the range 0.2 to 1.0ms.

Note the following when executing a high speed interrupt program.

(1) The high speed interrupt program is only executed as interrupt enable.
(Refer to Section 7.22.4 (3) for the items that delay high speed interrupt's start
from interrupt disable.)

(2) If the interrupt disable period continues longer than the set interrupt cycle interval,
high speed interrupt may be ignored.
(High speed interrupt is ignored once when it occurs twice during interrupt
disable.)

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7.22.2 High speed I/O refresh, high speed buffer transfer

High speed I/O refresh is a function that updates I/O signals between the I/O and
intelligent function modules and CPU module at interrupt cycle intervals.
High speed buffer transfer is a function that updates data between the intelligent
function module buffer memories and CPU module devices at interrupt cycle intervals.

(1) To execute this function, set "High speed interrupt I49 fixed scan interval" that was
set in Section 7.22.1 and "High speed I/O regresh setting" and "High speed buffer
transfer setting".

• High speed I/O refresh setting

Set the X/Y refresh ranges.

Choose here when setting

the high speed buffer
transfer ranges.

• High speed buffer transfer setting

Set the buffer memory

transfer ranges.

POINT
It is recommended to mount the target modules of this function on the main base.
(Access time to modules mounting on the main base is shorter than that on the
extension base.)

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The settings for high speed I/O refresh and high speed buffer transfer are as follows.

Number of
Item Sub Item Contents Restrictions
Settings
Head device No. I/O and intelligent function Up to 6 points for
Start (X/Y)
High speed I/O (X0 to XFF0/Y0 to YFF0) modules X input and Y
refresh setting Number of transferred bits Specify multiples of 16 output,
Points
(16 to 4096) only. 1 respectively.
Head I/O address / 10H Intelligent function
Starting I/O No.
(0 to FFH) modules only 2
Buffer memory Intelligent function
High speed Head address (0 to FFFFH) Up to 6 points for
start modules only
buffer transfer read and write,
Number of transferred bits Specify even addresses
setting Points respectively.
(1, 2 to FFFEH) and even words only 3
PLC side
Head device No. D, W, R, ZR only
device start
1: Only multiples of 16 can be set for both the head device No. and the number of transferred bits.
2: Since the QA base cannot be connected, the A/QnA series intelligent function modules are not the target.
(When the QA base is connected, "PARAMETER ERROR (3006)" is detected.)
"PARAMETER ERROR (3006)" is also detected if an error occurs in intelligent function module mounting check or
buffer memory capacity check.
3: Only when the specified number of transferred words is 1, an odd address can be specified.

(2) This function's execution requires both the EI instruction is in execution, and I49 is
not masked by the IMASK instruction. By default, I49 is not masked by the
IMASK instruction.

Executability of high speed interrupt ( : Executable, : Inexecutable)

High speed I/O refresh
Conditions High speed interrupt program
High speed buffer transfer

EI instruction IMASK instruction (I49 unmasked)

in execution IMASK instruction (I49 masked)
DI instruction
—
in execution

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7.22.3 Processing time

The following chart shows the processing times of the high speed interrupt function
between a start and an end.
Main routine program

Waiting time

High speed interrupt start

X input

Buffer memory read

I49 overhead

High speed interrupt program execution

Buffer memory write

Y output

High speed interrupt end

High speed I/O refresh and high speed buffer transfer take the following processing
times in their processings.

Processing Item Processing Time

• Max. 37.5 s or more than 37.5 s instruction processing time
Waiting time • Max. 40 s when MELSECNET/H, CC-Link or intelligent function modules are
mounted on extension base.
High speed interrupt start high
22 s
speed interrupt end
(1) Main base
Time = 0.14 (total number of X points) 0.65 (number of settings) 0.85
(2) Extension base
X input
Time = 0.21 (total number of X points) 0.65 (number of settings) 0.85
(Calculation example) 3.74 s when the module is mounted on the main base, the
number of settings is 1, and the number of X points is 16
(1) Main base
(a) 16 words or less:
Time = 0.47 (total number of transferred words) 2.85 (number of
settings) 0.95
(b) More than 16 words:
Time = 0.5 (total number of transferred words) 0.95
(2) Extension base
Buffer memory read
(a) 16 words or less:
Time = 1.07 (total number of transferred words) 2.85 (number of
settings) 0.95
(b) More than 16 words:
Time = 1.1 (total number of transferred words) 0.95
(Calculation example) 4.74 s when the module is mounted on the main base, the
number of settings is 1, and the number of words is 2
I49 overhead 41 s
High speed interrupt program
Depends on the user-created interrupt program.
execution

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Processing Item Processing Time

(1) Main base
(a) 16 words or less:
Time = 0.47 (total number of transferred words) 2.65 (number of
settings) 0.95
(b) More than 16 words:
Time = 0.55 (total number of transferred words) 0.95
(2) Extension base
Buffer memory write
(a) 16 words or less:
Time = 1.07 (total number of transferred words) 2.65 (number of
settings) + 0.95
(b) More than 16 words:
Time = 1.15 (total number of transferred words) 0.95
(Calculation example) 4.54 s when the module is mounted on the main base,
the number of settings is 1, and the number of words is 2
(1) Main base
Time = 0.13 (total number of Y points) 1.55
(2) Extension base
Y output
Time = 0.2 (total number of Y points) 1.55
(Calculation example) 3.63 s when the module is mounted on the main base,
the number of settings is 1, and the number of Y points is 16

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7.22.4 Restrictions

This section explains the items to be noted when the high speed interrupt function is
executed.
Depending on the items, a WDT error may occur or high speed interrupt may not be
executed at preset cycle intervals if the corresponding restrictions are not satisfied.
The restrictions are roughly classified into the following four different items.
(1) Items that are all disabled when high speed interrupt setting is made
(2) Items that are disabled only within high speed interrupt
(3) Items that hold high speed interrupt by interrupt disable
(4) Items to be noted in addition to (1) to (3)
The time taken to run an interrupt program once should not exceed the preset time of
the interrupt cycle interval. (If that time exceeds the preset time of the interrupt cycle
interval, high speed interrupt operation cannot be guaranteed.)

(1) Items that are all disabled when high speed interrupt setting is
made
No. Item Restriction When Used
1 Q02CPU No function for Q02CPU. Parameter error is detected.
QA1S6 B or QA6 B base is not
2 Base unit Parameter error is detected.
available.
3 Multiple PLC system Multiple PLC system is not available. Checked at parameter setting of GX Developer.
PR/PRC, UDCNT1/2, PLSY, PWM, SPD,
Any of the instructions indicated on left is not available
4 Instruction PLOADP/PUNLOADP/PSWAPP
and error is detected.
instructions are not available.
Instruction that will take longer
Since interrupt is disabled during instruction execution,
5 Instruction processing time than high speed interrupt
high speed interrupt is not available at preset cycle.
cycle is not available.
Response to instruction search will be slow, or
6 Programming unit Programming unit is not available. communication error may occur on programming unit
side.
The following two SFC functions are not
available.
1) SFC transition monitor check function Functions given on the left are not available and are
7 SFC
using SM90 to 99, SD90 to 99 ignored.
2) Fixed-time executed block execution
function
Time-based sampling trace is not
available.
Sampling trace is not available and is ignored.
8 Sampling trace (Sampling trace can be used every scan
(When trace read is performed, data may not be set.)
or when detailed conditions are
executed.)
Interrupt program (I0
Interrupt program (I0 to I48, I50 to I255) Since multiple interrupts are disabled, high speed
to I48, I50 to I255),
9 and fixed scan execution type program is interrupt is not available at preset cycle while any
fixed scan execution
not available. interrupt or fixed scan execution type program is run.
type program
Since interrupt is disabled during online program
correction, a high speed interrupt start is delayed during
Online program Online program correction is not that period and therefore high speed interrupt is not
10 correction, online file available. available at preset cycle.
batch-write Online file batch-write is not available. (The following time is taken.
• Max. 102 s for online program correction
• Max. 300ms for online file batch-write)
Since interrupt is disabled when file registers having the
same file name as the program name are changed,
File registers having
high speed interrupt is not available at preset cycle.
the same file name File registers having the same file name
11 (The following time is taken.
as the program as the program name is not available. • Max. 410 s for standard RAM
name
• 400 s + 100 s number of program files for
SRAM card)

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No. Item Restriction When Used

Since interrupt is disabled when local devices are
changed, high speed interrupt is not available at preset
cycle.
12 Local devices Local devices are not available. (The following time is taken.
• 390 s 170 s n for standard RAM
• 390 s 950 s n for SRAM card
n: number of program files)
Since interrupt is disabled at the time of CPU access
Command of
Issue of CPU access command from command issue, a high speed interrupt start is delayed
intelligent function
intelligent function module that accesses during that period and high speed interrupt is not
13 module that
CPU module, e.g. QJ71C24 or QJ71E71, available at preset cycle.
accesses CPU
is not available. N points read/write: (0.07 N 34) s
module
N points random read/write: (0.07 N 101) s
If host monitor request and intelligent function module-
Monitor via MELSECNET/H, QJ71C24 or relayed monitor request overlap, interrupt disable
Monitor via other
14 other intelligent function module is not processing time increases. Therefore, a high speed
station
available during host monitoring. interrupt start is delayed (102 s) during that period and
high speed interrupt is not available at preset cycle.
If there is interrupt counter setting, setting for I49 is
ignored and high speed interrupt I49 is executed
Interrupt counter corresponding to interrupt
15 Interrupt counter properly.
pointer I49 is not available.
(For other interrupt pointers, interrupt programs are not
available and interrupt counters are executed.)

(2) Items that are disabled only within high speed interrupt
No. Item Restriction When Used
In high speed interrupt program, device
Device comment in high speed interrupt program is
1 Device comment comment that is the same as program
overwritten.
name is not saved/restored.
In high speed interrupt sequence, index Index register in high speed interrupt program is
2 Index register
register is not saved/restored. overwritten.
Bus access flag In high speed interrupt program, bus SM390 value in high speed interrupt program is
3
SM390 access flag SM390 is not saved/restored. overwritten.
In high speed interrupt, forced ON/OFF is not executed
High speed X/Y refresh area cannot be
4 Forced ON/OFF and is ignored.
turned ON/OFF forcibly.
(Does not result in time-out error.)
Detailed condition Cannot be specified within high speed Is not executed properly.
5
monitor interrupt program. (Does not result in time-out error.)
Execution time Cannot be specified within high speed Is not executed and is ignored.
6
measurement interrupt program. (Does not result in time-out error.)

(3) Items that hold high speed interrupt by interrupt disable

No. Item Restriction
1 Instruction Interrupt is disabled during instruction execution.
Interrupt is disabled during refresh (bus access).
2 Link refresh For MELSECNET/H, CC-Link or intelligent function module refresh, waiting time is max. 37.5 s
when modules are mounted on main base or max. 40 s when they are mounted on extension base.
When multiple programs are run, interrupt is disabled during program switching. Waiting time is
Multiple program
3 30 s.
execution
When high speed interrupt function has been set, the recommended number of programs is 1.
For ladder monitor, device batch-monitor or device entry monitor, waiting time is as follows.
4 Monitor
(0.096 number of device points 20) s
5 AC DOWN Waiting time is max. 20ms for high speed interrupt start.

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(4) Items to be noted in addition to (1) to (3)

(a) If "High speed execution" is selected at the "Interrupt program/fixed scan
execution program setting" section on the "PLC system" tab screen in thd
"(PLC) parameter" dialog box of GX Developer, this setting is invalid for the
high speed interrupt function.

(b) Using the file registers outside the setting range (range in excess of the
maximum number of points) for high speed buffer transfer does not result in
an error and does not transfer data to outside the range. (The contents of
the other devices are not corrupted.)

(c) As in the other interrupt programs, there are the following items as
precautions for program creation.
1) The device turned on by the PLS instruction in the high speed interrupt
program remains on until the same interrupt program is executed again.
2) While the high speed interrupt program is executed, DI (interrupt disable)
is established. Do not execute the EI/DI instruction in the high speed
interrupt program.
3) Timers cannot be used in the high speed interrupt program.
4) If the high speed interrupt program is executed during time measurement
such as scan time or execution time measurement, the high speed
interrupt program running time is added to the measurement time.
Hence, if the high speed interrupt program is executed, the values to be
stored into the following special registers and the monitor values of GX
Developer become longer than the values when the high speed interrupt
program is not executed.
(Special registers)
• SD520, SD521: Current scan time
• SD522, SD523: Initial scan time
• SD524, SD525: Minimum scan time
• SD526, SD527: Maximum scan time
• SD528, SD529: Current scan time for low speed
• SD532, SD533: Minimum scan time for low speed
• SD534, SD535: Maximum scan time for low speed
• SD540, SD541: END processing time
• SD542, SD543: Constant scan waiting time
• SD544, SD545: Low speed program cumulative execution time
• SD546, SD547: Low speed program execution time
• SD548, SD549: Scan program execution time
• SD551, SD552: Service interval time
(GX Developer monitor values)
• Execution time measurement
• Scan time measurement
• Constant scan

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7.23 Module Service Interval Time Reading

The High Performance QCPU can monitor the service interval time (time from service
acceptance to next service acceptance) of the intelligent function module, network
module or GX Developer. This indicates the frequency at which access to the CPU
occurs from outside.

1
To read the module service interval time , operate the following special relay and
special registers.

(1) Special relay

Number Name Description
Turning this relay from OFF to ON reads to SD551
and SD552 the module service interval time of the
Module service interval intelligent function module specified in the special
SM551
time read register SD550.
ON: Read
OFF: No processing

(2) Special registers

Number Name Description
Set the I/O number of the module whose module
service interval time will be measured.
Module service interval time
SD550 Set the I/O number of the peripheral device
measured module
connected to the RS-232 or USB interface of the
CPU module to FFFFH.
Stores the service interval time from the module
specified in SD550 when SM551 is turned on.
SD551: 1ms units (range 0 to 65535)
SD551, SD552: 100 s units (range 0 to 900, stored at
Module service interval time
SD552 intervals of 100 s)
(Example) When module service interval time is
123.4ms
SD551 = 123, SD552 = 400

REMARK
1: The module service interval indicates the time between a transient request such
as monitor, test, program read/write.
The access interval in cyclic communication from the network module is not
stored.

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(Program example)
When reading the module service interval time of the intelligent function module of
X/Y160

Read start signal

Sets I/O number 160 (hexadecimal) to SD550.

Starts module service interval time read.

Stores module service interval time into D551, D552.

POINT
To read the service interval time when access is made from GX Developer of the
other station on the network, set the I/O number of the network module.

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FUNCTION MODULE
MELSEC-Q

8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL

FUNCTION MODULE

(1) Description of intelligent function modules/special function modules

High Performance model QCPU allows the use of the Q Series compatible
intelligent function modules and the AnS series compatible special function
modules.
The intelligent function module/special function module is a module that allows
High Performance model QCPU to process analog values or high speed pulses
which cannot be processed with I/O modules.
For example, an analog value is converted into a digital value with the
analog/digital conversion module, one of the intelligent function modules, before
being used.

(2) Communication with intelligent function modules/special function

modules
The intelligent function module/special function module is equipped with memory
(buffer memory) to store the data received from or output to external devices.
High Performance model QCPU reads/writes the data from/to the buffer memory.

8.1 Communication Between High Performance model QCPU and Intelligent Function
Modules

The following methods enable the communication between High Performance model
QCPU and intelligent function modules:
• Initial setting or automatic refresh setting using GX Configurator
• Device initial value
• FROM/TO instruction
• Intelligent function module device
• Instructions dedicated for intelligent function modules
The following table shows the communication timing for the communication methods
with intelligent function modules described above:
Communication timing Storage location 1
High 2
Communication method with intelligent function 3
Power Performance STOP Instruction END High
modules
ON model QCPU RUN execution processing Performance Intelligent
reset model QCPU
Initial setting — — —
GX Configurator
Automatic refresh setting — — — — —
8 Device initial value — — —
FROM/TO instruction 4 — — — — —
Intelligent function module device 4 — — — — —
Instructions dedicated for intelligent function modules
— — — — —
4

: Can be stored. —: Cannot be stored.

REMARK
1: Indicates whether the data (designated by the GX Configurator, of the device
initial value, etc.) is stored in High Performance model QCPU or in an intelligent
function module.
2: Represents the internal memory of High Performance model QCPU or a
memory card.
3: "Intelligent" represents an intelligent function module.
4: Represents the program using the intelligent function module device, the
FROM/TO instruction, or the instructions dedicated for intelligent function
modules.

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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
FUNCTION MODULE
MELSEC-Q

8.1.1 Initial setting and automatic refresh setting using GX Configurator

(1) Initial and automatic refresh settings of intelligent function modules

Installing the GX Configurator compatible with the intelligent function module
enables the initial setting and automatic refresh setting with GX Developer.
When the initial setting and automatic refresh setting of the intelligent function
module is designated with GX Developer, you can write/read data without
creating the program for the communication with the intelligent function module.
Moreover, you can conduct the initial setting or automatic refresh setting without
designating the buffer memory address of the intelligent function module.

(2) Setting using the GX Configurator

This section describes the example to set the initial setting and automatic refresh
setting of A/D conversion module Q64AD.
(a) Initial setting
The initial setting of Q64AD offers the following four settings:
• A/D conversion enable/disable setting
• Sampling process/averaging process setting
• Time/number of times specifying
• Average time/average number of times setting
The initial setting of Q64AD is designated on the following initial setting
screen of GX Configurator.

[Initial setting screen]

The designated initial setting data is stored in the intelligent function

module.

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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
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MELSEC-Q

(b) Auto refresh setting

For the auto refresh setting, designate the device at High Performance
model QCPU to store the following data.
• Digital output of Q64AD
• Maximum/minimum values of Q64AD
• Error code
The auto refresh setting of Q64AD is designated on the following auto
refresh setting screen of GX Configurator.

[Auto refresh setting screen]

The designated auto refresh setting data is stored in the intelligent function
parameters of High Performance model QCPU.

REMARK
For the details of GX Configurator, refer to the manual of the intelligent function
module being used.

8.1.2 Communication using device initial value

(1) Device initial value

The device initial value is used to designate the initial setting of the intelligent
function module without using a program.
The designated device initial value is written from High Performance model
QCPU to the intelligent function module when High Performance model QCPU is
turned ON, is reset, or is switched from STOP to RUN.

(2) Designation of the device initial value

Using the device memory of GX Developer, designate the data of the intelligent
function module to be used as the device initial value.
In the device initial value setting of GX Developer, designate the range to be
used with the intelligent function module device as the device of the device initial
value.

REMARK
1) For the device initial value, see Section 10.13.2.
2) For the intelligent function module device, see Section 10.5.
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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
FUNCTION MODULE
MELSEC-Q

8.1.3 Communication using FROM/TO instruction

(1) FROM/TO instruction

At the execution of the FROM/TO instruction, the data stored in the buffer
memory of the intelligent function module can be read, or data can be written to
the buffer memory of the intelligent function module.
The FROM instruction stores the data read from the buffer memory of the
intelligent function module to the designated device.
The TO instruction writes the data of the designated device to the buffer memory
of the intelligent function module.

REMARK
1) For the details of the FROM/TO instruction, refer to the following manuals.
• QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)
2) For the details of the buffer memory of the intelligent function module, refer to the
manual of the intelligent function module being used.

8.1.4 Communication using the intelligent function module device

(1) Intelligent function module device

The intelligent function module device is the buffer memory of the intelligent
function module represented as a device of High Performance model QCPU in
High Performance model QCPU programs.
It enables reading data stored in the buffer memory of the intelligent function
module, or enables writing data to the buffer memory of the intelligent function
module.

(2) Difference from the FROM/TO instruction

The intelligent function module device can be handled as a device of High
Performance model QCPU, enabling the processing of data read from the
intelligent function module with one instruction.
This saves the number of steps in the entire program.
The processing speed is the total of the instruction execution time and the access
time to/from the intelligent function modules.

POINT
When reading and processing the data of the intelligent function module frequently
in the program, use the FROM instruction to read the data at one point in the
program and store and process it in a data register, instead of using the intelligent
function module device every time.
Otherwise, the intelligent function module device accesses the intelligent function
module every time the instruction is executed, resulting in longer scan time for the
program.

REMARK
For the intelligent function module device, see Section 10.5.

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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
FUNCTION MODULE
MELSEC-Q

8.1.5 Communication using the instructions dedicated for intelligent function modules

(1) Description of the instructions dedicated for intelligent function

modules
(a) The instructions dedicated for intelligent function modules are the
instructions that facilitate programming using the functions of the intelligent
function modules.
For example, the OUTPUT instruction, which is the instruction dedicated for
serial communication modules, allows data transmission in user-specified
message format with no handshaking protocol.
In this case, the communication is possible without considering the buffer
memory address of the objective serial communication module.
QCPU Serial communication module set the channel
to use by control
b15 b0 trans- data
Channel mission
S2 +0
1
+1
+2 trans-
Channel mission
2

(b) A completion device should be designated for the instruction dedicated for
intelligent function modules.
The designated completion device turns ON for one scan when the
execution of the instruction dedicated for intelligent function modules is
completed.
When the completion device turns ON, another instruction dedicated for
intelligent function modules can be executed to the same intelligent function
module.
To use two or more instructions dedicated for intelligent function modules to
one intelligent function module, be sure to execute the next instruction
dedicated for intelligent function modules after the completion device turns
ON.

(2) Note
(a) If the instruction dedicated for intelligent function modules are executed and
High Performance model QCPU is switched from RUN to STOP before the
completion device turns ON, the completion device turns ON one scan later
when High Performance model QCPU is switched to RUN next time.

(b) The instruction dedicated for intelligent function modules can be executed to
the intelligent function modules of the main base unit and extension base
unit.
The instruction dedicated for intelligent function modules cannot be
executed to the intelligent function module installed to the remote I/O
station of MELSECNET/H.

REMARK
For the instruction dedicated for intelligent function modules and the completion
device, refer to the manual of the intelligent function module being used.

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MELSEC-Q

8.2 Request from Intelligent Function Module to High Performance model QCPU

8.2.1 Interrupt from the intelligent function module

(1) Interrupt from the intelligent function module

High Performance model QCPU executes an interrupt program (I50 to I255) by
the interrupt request from the intelligent function module.
For example, the serial communication module processes the data reception by
an interrupt program when the following data communication functions are
executed.
• Data reception during the communication with no handshaking protocol
• Data reception during the communication with bi-directional protocol
Processing data reception with an interrupt program improves the data reception
speed of High Performance model QCPU.
The objective serial
communication module

data transmission

Serial communication
Occurrence of
module reception
interrupt

Main program Main program

Interrupt program
PLC CPU
execution
FEND

SM400
I BUFRCVS

(2) Setting an interrupt from the intelligent function module

To execute an interrupt program by the interrupt of the intelligent function
module, it is necessary to designate the "Intelligent function module setting
(Interrupt pointer setting)" at the "PLC system" tab screen in the “(PLC)
Parameter" dialog box.
You should also designate "System setting" at the intelligent function module.
To execute an interrupt program by the interrupt from the intelligent function
module, refer to the manual of the intelligent function module being used.

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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
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MELSEC-Q

8.3 Communication Between High Performance model QCPU and AnS Series Special
Function Modules

The following methods enable the communication between High Performance

model QCPU and the special function modules compatible with AnS Series:
• Device initial value
• Intelligent function module device
• FROM/TO instruction
The following table shows the communication timing for the communication
methods with special function modules described above:
Communication timing Storage location 1

High 2
Communication method with special function
Performance STOP Instruction END High 3
modules Power ON
model QCPU RUN execution processing Performance Special
reset model QCPU
Device initial value — — —
FROM/TO instruction 4 — — — — —
Intelligent function module device 4 — — — — —

: Executable. —: Not executable

REMARK
1: Indicates whether the data of the device initial value is stored in High
Performance model QCPU or in a special function module.
2: Represents the internal memory of High Performance model QCPU or a
memory card.
3: "Special" represents a special function module.
4: Represents the program using the intelligent function module device or the
FROM/TO instruction.

8.3.1 Communication using device initial value

(1) Device initial value

The device initial value is used to designate the initial setting of the special
function module without using a program.
The designated device initial value is written from High Performance model
QCPU to the special function module when High Performance model QCPU is
turned ON, is reset, or is switched from STOP to RUN.

(2) Designation of the device initial value

In the device initial value setting of GX Developer, designate the special function
module device as the device of the device initial value.

REMARK
1) For the device initial value, see Section 10.13.2.
2) For the intelligent function module device, see Section 10.5.

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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
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MELSEC-Q

8.3.2 Communication using FROM/TO instruction

(1) FROM/TO instruction

At the execution of the FROM/TO instruction, the data stored in the buffer
memory of the special function module can be read, or data can be written to the
buffer memory of the special function module.
The FROM instruction stores the data read from the buffer memory of the special
function module to the designated device.
The TO instruction writes the data of the designated device to the buffer memory
of the special function module.

REMARK
1) For the details of the FROM/TO instruction, refer to the following manuals.
• QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)
2) For the details of the buffer memory of the special function module, refer to the
manual of the special function module being used.

8.3.3 Communication using the intelligent function module device

(1) Intelligent function module device

The intelligent function module device is the buffer memory of the special
function module represented as a device of High Performance model QCPU in
High Performance model QCPU programs.
It enables reading data stored in the buffer memory of the special function
module to be read, or writing data to the buffer memory of the special function
module.

(2) Difference from the FROM/TO instruction

The intelligent function module device can be handled as a device of High
Performance model QCPU, enabling the processing of data read from the special
function module with one instruction.
This saves the number of steps in the entire program.
The processing speed is the total of the instruction execution time and the access
time to/from the special function modules.

POINT
When reading and processing the data of the special function module frequently in
the program, use the FROM instruction to read the data at one point in the program
and store and process it in a data register, instead of using the intelligent function
module device every time.
Otherwise, the intelligent function module device accesses to the special function
module every time the instruction is executed, resulting in longer scan time for the
program.

REMARK
For the intelligent function module device, see Section 10.5.

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8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE/SPECIAL
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MELSEC-Q

8.3.4 Effects of quicker access to the special function module and countermeasures against
them

(1) Effects of quicker access to the special function module

As the scan time of High Performance model QCPU increases, there are some
limitations for the execution of the FROM/TO instruction to the AnS-compatible
special function module.
The following effects may be produced in the program which reads/writes data
from/to a special function module with the FROM/TO instruction at every scan:

(a) Special function modules which assign priority to the FROM/TO instruction
1) When the FROM/TO instruction is executed, the special function module
stops its processing and processes the FRO/TO instruction first.
As a result, the processing time of the special function module becomes
longer, resulting in watch dog timer error of the special function module.
2) The followings are the special function modules which assign priority to
the FROM/TO instruction.
• A1S64AD, A1S68AD
• A1S62RD3, A1S62RD4
• A1S68DAV, A1S68DAI
• A1S68TD
• A1SD75P1(-S3), A1SD75P2(-S3), A1SD75P3(-S3)
• A1SD75M1, A1SD75M2, A1SD75M3

(b) Special function modules which suspend processing of the FROM/TO

instruction
1) Even when the FROM/TO instruction is executed, the special function
module continues its processing and suspends processing of the
FROM/TO instruction until the processing is completed.
As a result, the scan time becomes longer by the period to wait the
completion of the processing of the special function module.
2) The following are the special function modules which suspend the
FROM/TO instruction.
• A1S63ADA, A1S66ADA
• A1SD61, A1SD62, A1SD62D, A1SD62E
• A1SD70, A1SD71-S2, A1SD71-S7
• A1SJ71PT32-S3, A1SJ71T32-S3
• A1SD51S
• A1SJ71ID1-R4, A1SJ71ID2-R4

(2) Countermeasures against the effects of quicker access to the

special function module
To use a special function module with High Performance model QCPU, adjust
the execution time with SM415 (2n-ms clock) and SD415 (2n-ms clock setting).
The initial value of SD415 is "30." When SD415 is used for interlock of the
FROM/TO instruction, the FROM/TO instruction is executed at every 120 ms.
SM400
MOVP K30 SD415

SM415
FROMP H0 K1 D0 K1

REMARK
1) To change the clock value of SM415, store the new value in SD415.
2) For details of SM415, see appendix 1. For details of SD415, see appendix 2.

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9 PARAMETER
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9 PARAMETER

(1) Parameter types and setting

(a) The High Performance model QCPU has two different parameter types: the
"PLC parameters" set for a system that uses the PLC independently; and
the "network parameters" set for use of MELSECNET/H, Ethernet or CC-
Link.
(b) In the High Performance model QCPU of function version B, the following
items necessary to configure a multiple CPU system have been added to
the PLC parameters. (Refer to Section 14.2.6)
• Multiple CPU setting
• Control CPU setting (I/O assignment)
(c) In this chapter, the PLC parameters and network parameters to be set
using GX Developer are listed in a table.
For details of each setting item, refer to the reference section or reference
manual given in the table.
For the setting operation on GX Developer, refer to the GX Developer
Operating Manual.

(2) When any PLC parameter setting has been changed, power off and then on the
PLC (ON OFF ON) or reset the QCPU.
If the High Performance model QCPU is switched from STOP RUN without
any operation after the PLC parameter setting change, the new parameter setting
may not become valid or PARAMETER ERROR (error code: 3000) may occur.

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 9 PARAMETER
MELSEC-Q

Table 9.1 Parameter List

Item Parameter No. Description
Designate the label and comment for the CPU module to be used.
PLC name —
These settings do not affect CPU operation
Label 0000H Designates the label setting (name and use).
Comment 0001H Designates the comment setting.
These are the settings required for using the CPU module.
PLC system —
Default values are available for PLC control.
Timer limit Low Speed
1000H Designates the low speed/high speed timer settings
setting High Speed
Designates the contact which controls the CPU module's
RUN-PAUSE contacts 1001H
RUN/PAUSE operation.
Enables/disables the remote reset operation from the GX
Remote reset 1002H
Developer.

Output mode at STOP to RUN 1003H Designates the output(Y) mode at STOP-RUN switching.

Floating point arithmetic Specifies whether to perform floating-point arithmetic processing

1004H
processing with double precision.
Intelligent functional module Specifies the assignment of interrupt pointers (I50 to I255), leading
100AH
setting (interrupt pointer setting) I/O Nos. and leading SI Nos. of an intelligent function module.
Common pointer 1005H Designates the common pointer "first No.".
Designates the number of empty slot points in the main/extension
Number of empty slots 1007H
base units.
Interrupt counter
Designates the interrupt counter "first No."
start No.
1008H
Fixed scan interval Specifies time intervals at which to execute interrupt pointers (I28
System
(n: 28 to31) to I31).
interrupt
settings High X input 100FH
Sets the fixed-cycle interval, high speed I/O refresh setting, and
speed Y output 1010H
high speed buffer transfer setting of the high speed interrupt
interrupt Buffer read 1011H
pointer I49.
setting Buffer write 1012H
Interrupt program/fixed scan Specifies whether to perform the high speed execution of an
1008H
program setting interrupt program.
Specifies whether to bring the start of a CPU module into
Module synchronization 100CH
synchronization with the start of an intelligent function module.
Specifies whether to use MELSEC-A Series special relays/special
A series CPU compatibility setting 100DH
registers (SM1000/SD1000 to SM1299/SD1299).
9
PLC file setting — Designates the various files used in the CPU module.

File register 1100H Designates the file for file registers to be used in the program.

Comment file used in a command 1101H Designates the file for comments to be used in the program.

Designates the file for the device initial values to be used in the
Initial Device value 1102H
CPU module.

File for local device 1103H Designates the file for local devices to be used in the program.

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9 PARAMETER
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Default Value Setting Range Reference Section

— — —

No setting Max. of 10 characters —

No setting Max. of 64 characters —

— — —

100 ms 1 to 1000 ms(1 ms units) Section 10.2.10

10.0 ms 0.1 to 100.0 ms Section 10.2.10

No setting X0 to X1FFF Section 7.6.1

Disabled Enabled/Disabled Section 7.6.3

Previous status (produce the status of Produce the status of an output (X) before STOP/Clear the
Section 7.4
an output (X) before STOP output (output is 1 scan later)
Perform internal arithmetic operation Check/Not Checked to perform internal arithmetic operation
Section 4.8.4
with double precision with double

No setting I50 to I255, leading I/O No, leading SI No. Section 10.10

No setting P0 to P4095 Section 10.9.2

16 points 0/16/32/64/128/256/512/1024 points Section 5.6.1

No setting C0 to C22722 (Counter setting points can be set up to 256.) Section 10.2.11
I28: 100.0 ms
I29: 40.0 ms
0.5 to 1000 ms (0.5 ms units) Section 10.10
I30: 20.0 ms
I31: 10.0 ms

No setting I49 : 0.2 to 1.0 ms (0.1ms units) Section 7.21

Section 4.1.3
The high speed execution is disabled. Enable/Disable the high speed execution.
Section 4.2.5
The start of an intelligent function Yes/No to synchronize the start of an intelligent function
—
module is synchronized. module.
Special relays/special registers after Yes/NO to use the special relays/special registers after Section 10.3.2
SM1000/SD1000 are used. SM1000/SD1000. Section 10.3.3
— — —
• Not used
Not used • Use the same file name as the program Section 10.7
• Use the designated file
• Not used
Not used • Use the same file name as the program —
• Use the following file
• Not used
Not used • Use the same file name as the program Section 10.13.2
• Use the following file
• Not used
Not used Section 10.13.1
• Use the following file

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9 PARAMETER
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Table 9.1 Parameter List (continued)

Item Parameter No. Description
PLC RAS setting — These settings are used for the RAS function.
WDT WDT setting Set the watch dog timer of the CPU module.
setting Initial execution watching Set the watch dog timer for the use of an initial execution type
(Watch time 3000H program.
dog Low speed execution Set the watch dog timer for the use of a low speed execution type
timer) watching time program.
Operating mode when there is an Designates the CPU module operation mode to be established when
3002H
error an error is detected.
Error check 3001H Designates whether or not to detect a specified error .
Constant scanning 3003H Designates the constant scanning time.
Low speed program execution Designates the time setting for low speed execution program
3006H
time execution at each scanning.
Designates the storage designation for the CPU module fault
Fault history 3005H
history.
These settings designate the number of points for each device, the
Device setting —
latch range, and the local device range.

Device point 2000H Designates the number of device points used.

Latch(1) head/end
2001H Designates the latch range where the latch clear key is enabled.
(Latch clear key enabled)
Latch(2) head/end
2002H Designates the latch range where the latch clear key is disabled.
(Latch clear key disabled)

Local device head/end 2003H Designates the device range used for local devices.

Specifies a program name and execution conditions to write

Program setting
several programs onto the CPU module.
Designates whether the program memory is cleared or not during
Boot option
boot.
7000H
Designates the boot operation program file type, data name and
Boot file setting Boot file setting
destination drive.

Automatic refresh Designates whether automatic refresh to the standard ROM is

to standard ROM made or not.
SFC program start
8002H
mode
Starting conditions 8003H Designates the SFC program start mode, starting conditions, and
SFC setting
the output mode in a block stop for SFC program use.
Output mode when
the block is 8005H
stopped

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Default Value Setting Range Reference Section

— — —
200 ms 10 to 2000 ms (10 ms units) Section 4.2.2
No setting 10 to 2000 ms (10 ms units) Section 4.2.1

No setting 10 to 2000 ms (10 ms units) Section 4.2.3

Stop Stop/Continue Section 7.16

Checked Checked/Not checked Section 7.16
No setting 0.5 to 2000 ms(0.5 ms units) Section 7.2
No setting 1 to 2000 ms Section 4.2.3

Record in PLC RAM Record in PLC RAM/Record in the following history file Section 7.17

— — —

X: 8 k points
Y: 8 k points
M: 8 k points
L: 8 k points
B: 8 k points
X(8 k points), Y(8 k points), S(8 k points), SB(2k points) and
F: 2 k points
SW(2 k points) are fixed.
SB: 2 k points
Including the above points(3.7 k words), a total range of 29 k Section 10.1
V: 2 k points
words is available. Section 10.2
S: 8 k points
• For one device: Max. 32 k points
T: 2 k points
• Total number for the bit devices: Max. 64 k points
ST: 0 k point
C: 1 k point
D: 12 k points
W: 8 k points
SW: 2 k points
Only 1 range is designated for each device of B, F, V, T, ST,
No setting Section 7.3
C, D, W.
Only 1 range is designated for each device of L, B, F, V, T,
No setting Section 7.3
ST, C, D, W.
Only 1 range is designated for each device of M, V, T, ST, C,
No setting Section 10.13.1
D.
Program name, execution type (fixed scan for fixed scan
No setting Section 4.2
execution), file use setting, I/O refresh setting
Do not clear the program memory Do not clear the program memory during boot. /
Section 6.6.2
during boot. Clear the program memory during boot.
Type, data name and source drive
No setting (The destination drive is automatically set in the program Section 6.6
memory.)
Do not execute automatic refresh to Do not execute automatic refresh to the standard ROM. /
Section 6.6.2
the standard ROM. Do not execute automatic refresh to the standard ROM.

See the QCPU (Q mode) / QnACPU Programming Manual

— —
(SFC).

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Table 9.1 Parameter List (continued)

Item Parameter No. Description
I/O assignment setting — Designates the status of installation of each module of the system.

Type Designates the type of the installed module.

I/O
Assign- 400H Designates the model of the installed module. (Memorandum for
ment Model name
users who do not use the CPU module.)
Points Designates the number of points of each slot.
Head XY
Designates the first input and output numbers of each slot.
(Head I/O number)
Designates the model of the used main base unit and extension
Base model name base unit. (Memorandum for users who do not use the CPU
module.)
Designates the model of the power supply module installed to the
Power module model
Standard main and extension base units. (Memorandum for users who do
name 401H
setting not use the CPU module)
Extension cable model Designates the model of the extension cable. (Memorandum for
name users who do not use the CPU module)
Designates the number of slots of the main and extension base
Number of slots
units. The number of slots is designated for each base unit.
Switch setting 407H Designates various switches of the intelligent function module.
Error time output Designates whether the output is cleared or retained upon a
403H
module stopping error of the control PLC.
H/W error time CPU Designates whether the control PLC continues operation or it is
4004H
Detailed operation mode stopped upon a hardware error of the intelligent function module.
setting Designates the response time of the input module, high speed
I/O response time 405H
input module and I/O mixture module.
Designates the control PLC of the I/O module and intelligent
Control CPU 406H
function module.
Contents of I/O allocation, MELSECNET/Ethernet setting and CC-
Acknowledge XY assignment —
Link setting can be checked.
Multiple CPU setting — Defines settings for establishment of a multiple CPU system.
No. of CPU E00H Designates the number of CPUs used in the multiple CPU system.
Designates the operation of the multiple CPU system upon a
stopping error of the PLC No.2 to No.4 CPU modules.
Operating mode E01H
The multiple CPU system is stopped if a stopping error occurs to
the PLC No.1 (Fixed)
Designates whether online module change will be enabled or
Online module change setting E006H disabled for other CPU modules. (When it is enabled, the out of
group I/O status cannot be imported.)
Designates whether the input status of the input module and
Out of group input setting intelligent function module controlled by other PLCs are acquired
E04H or not.
Designates whether the output status of the output module
Out of group output setting
controlled by other PLCs are acquired or not.

Designates the devices and the number of points for which data
E002H
Refresh settings write/read will be performed by automatic refresh between CPU
E003H
modules in the multiple CPU system.

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MELSEC-Q

Default Value Setting Range Reference Section

— — —
• PLC CPU No.2 to No.4: PLC No.n/Empty (Designate "CPU
(empty)" for slots where no CPU module is installed.)
No setting • Input/output module and intelligent function module
• Input, high speed input, output, intelligent, input/output
mixture, interrupt
Section 5.6
No setting • 16 single-byte characters
• 0 point, 16 points, 32 points, 48 points, 64 points, 128
No setting
points, 256 points, 512 points, 1024 points
No setting • 0H to FF0H

No setting • 16 single-byte characters

No setting • 16 single-byte characters

Section 5.3

No setting • 16 single-byte characters

No setting • 2,3,5,8,10,12
• See the manual of the intelligent function module to be
No setting Section 7.6
used.
Clear • Cleared/retained Section 7.8

Stop • Stopped/continue —
Input, I/O mixture: 10 ms • Input, I/O mixture: 1 ms, 5 ms, 10 ms, 20 ms, 70 ms
Section 7.7
High speed input: 0.2 ms • High speed input: 0.1 ms, 0.2 ms, 0.4 ms, 0.6 ms, 1.0 ms
PLC No.1 • PLC No.1, PLC No.2, PLC No.3, No.4 Section 14.2.1

— — —
— — —
1 module • 1 to 4 modules Section 14.2.1

Stop all CPUs upon error of PLC No.n • Stop or do not stop all PLCs upon an error of PLC No.n. Section 14.2.8

Online module change is disabled for • Online module change is enabled/disabled for other CPU
—
other CPU modules modules.

Do not permit inputs from outside

• Permit or do not permit inputs from outside the group. Section 17.2
group

Do not permit outputs to outside group • Permit or do not permit outputs to outside the group. Section 17.2
• Setting range of each CPU: 0 to 2048 points (in 2-point
intervals) / module
Max. 4k points (4096 points) /
system
• Device on CPU side: B, M, Y, D, R, ZR
No setting Devices equivalent to the number of points Section 16.1
set for the transmission range from the
designated device number are occupied.
• 16 points are occupied with B, M and Y for
each point of transmission range.
• 1 point is occupied with D, W, R and ZR for
each point of transmission range.

9-7 9-7
9 PARAMETER
MELSEC-Q

Table 9.1 Parameter List (continued)

Item Parameter No. Description
Designates parameters for MELSECNET/H, Ethernet and CC-
Network parameter
Link.
MELSECNET/H setting 1
No. of module setting 5000H
Valid module during other
5001H
station access
Interlink transmission parameter 5002H
Routing parameters 5003H
Network setting 5NM0H
Designates network parameters for MELSECNET/H.
Network refresh parameters 5NM1H
Common parameter 5NM2H
Station inherent parameter 5NM3H
Common parameter No.2 5NMAH
Station inherent parameter
No.2 5NMBH
Interrupt setting
Ethernet setting 1
No. of module setting 9000H
Starting I/O No.
Network No.
Operational settings
Initial settings
Designates network parameters for Ethernet.
Open settings 9N00H
Routing information
MNET/10 routing information
FTP Parameters
E-mail setting
Interrupt setting 9N09H

9-8 9-8
9 PARAMETER
MELSEC-Q

Default Value Setting Range Reference Section

— — —

No setting • Refer to the Q Corresponding MELSECNET/H manual. —

No setting • Refer to the Q Corresponding Ethernet manual. —

9-9 9-9
9 PARAMETER
MELSEC-Q

Table 9.1 Parameter List (continued)

Item Parameter No. Description
Designates parameters for MELSECNET/H, Ethernet and CC-
Network parameter
Link.
CC-Link setting 2
No. of module setting C000H
Remote input (RX)
Refresh device
Remote output (RY)
Refresh device
Remote register (RWr)
Refresh device
Remote register (RWw)
Refresh device
Ver.2 Remote input (RX)
Refresh device
CNM1H
Ver.2 Remote output (RY)
Refresh device
Ver.2 Remote register (RWr)
Refresh device
Ver.2 Remote register (RWw)
Refresh device Designates network parameters for CC-Link.
Special relay (SB)
Refresh device
Special register (SW)
Refresh device
Start I/O No.
All connect count
Retry count
Automatic reconnection
station count
Stand by master station No.
CPU down specification CNM2H
Scan mode specification
Delay time setting
Station information setting
Remote device station initial
setting
Interrupt setting
Set the remote password for the Ethernet, serial communication or
Remote password
modem interface module.
Password setting — Enter the remote password.
Select the module model name to be checked for the remote
Model name —
Password valid password set to the QCPU.
module setting Set the head address of the module to be checked for the remote
Head X/Y —
password.
Detailed setting — —
User connection No. valid
— Set the user connection No.
setting

System connection valid

— Set the remote password valid port of the system connection.
setting

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9 PARAMETER
MELSEC-Q

Default Value Setting Range Reference Section

— — —

No setting • Refer to the CC-Link manual. —

No 4 bytes, alphanumeric characters, special symbols

No QJ71E71/QJ71C24

No 0000H to 0FE0H

— —

No Connection No. 1 to connection No. 16

Specify the remote password valid port.

• Automatic open UDP port
• FTP communication port (TCP/IP)
No
• GX Developer communication port (TCP/IP)
• GX Developer communication port (UDP/IP)
• HTTP port

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9 PARAMETER
MELSEC-Q

1: N and M indicate the following.

N: Indicates the module number.
M: Indicates the network type.
M Network Type
1H MELSECNET/10 mode (Control station), MELSECNET/H mode (Control station)
2H MELSECNET/10 mode (Normal station), MELSECNET/H mode (Normal station)
5H MELSECNET/H (Remote master)
AH MELSECNET/H Stand by station

2: N and M indicate the following.

N: Indicates the module number.
M: Indicates the network type.
M Network Type
0H Master station
1H Local station
2H Standby master station

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10 EXPLANTION OF DEVICES

This chapter describes all devices that can be used in the High Performance model
QCPU.

10.1 Device List

The names and data ranges of devices which can be used in the High Performance
model QCPU are shown in Table 10.1 below.

Table 10.1 Device List

Default Values Parameter
Reference
Class Type Device Name Designated
Number of Points Range Used Section
Setting Range
Input 3 8192 points X0 to X1FFF Section 10.2.1
Output 3 8192 points Y0 to Y1FFF Section 10.2.2
Internal relay 8192 points M0 to M8191 Section 10.2.3
Latch relay 8192 points L0 to L8191 Section 10.2.4
Bit devices Anunciator 2048 points F0 to F2047 Section 10.2.5
Edge relay 2048 points V0 to V2047 Section 10.2.6
Step relay 3 8192 points S0 to S511 / block Section 10.2.9
Internal user Changeable within
Link special relay 3 2048 points SB0 to SB7FF Section 10.2.8
devices 29k words. 3
Link relay 8192 points B0 to B1FFF Section 10.2.7
Timer 1 2048 points T0 to T2047
Section 10.2.10
Retentive timer 1 0 points (ST0 to ST2047)
Counter 1 1024 points C0 to C1023 Section 10.2.11
Word devices
Data register 12288 points D0 to D12287 Section 10.2.12
Link register 8192 points W0 to W1FFF Section 10.2.13
Link special register 1 2048 points SW0 to SW7FF Section 10.2.14
FX0 to FXF 4
Function input 5 points Section 10.3.1
Internal Bit devices FY0 to FYF 4
Function output 5 points Section 10.3.1
system Special relay 2048 points SM0 to SM2047 Unchangeable Section 10.3.2
devices
Function register 5 points FD0 to FD4 Section 10.3.1
Word devices
Special register 2048 points SD0 to SD2047 Section 10.3.3
Link input 8192 points Jn\X0 to Jn\X1FFF
Link output 8192 points Jn\Y0 to Jn\Y1FFF
Bit device
Link direct Link relay 16384 points Jn\B0 to Jn\B3FFF
Unchangeable Section 10.4
devices Link special relay 512 points Jn\SB0 to Jn\SB1FF
Link register 16384 points Jn\W0 to Jn\W3FFF
Word device
Link special register 512 points Jn\SW0 to Jn\SW1FF

10

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 10 EXPLANTION OF DEVICES
MELSEC-Q

Default Values Parameter

Reference
Class Type Device Name Designated
Number of Points Range Used Section
Setting Range
Intelligent
function Un\G0 to
Word device Buffer register 65536 points Unchangeable Section 10.5
module Un\G65535 2
device
Index
Word device Index register 16 points Z0 to Z15 Unchangeable Section 10.6
register
0 to 1018 k points
File register Word device File register 0 points —— Section 10.7
(1 k units)
Nesting —— Nesting 15 points N0 to N14 Unchangeable Section 10.8
Pointer 4096 points P0 to P4095 Section 10.9
Pointers —— Unchangeable
Interrupt pointer 256 points I0 to I255 Section 10.10
SFC block device 320 points BL0 to BL319 Section 10.11.1
Bit devices
SFC transition device 512 points TR0 to TR511 Section 10.11.2
Network No 256 points J1 to J255 Section 10.11.3
Other Unchangeable
I/O No —— U0 to UFF Section 10.11.4
——
Macro instruction
—— VD0 to VD Section 10.11.5
argument device
Decimal constants K-2147483648 to K2147483647 Section 10.12.1
Hexadecimal constants H0 to HFFFFFFFF Section 10.12.2
Constants —— Real number constants E 1.17550-38 to E 3.40282+38 Section 10.12.3
Character string
"ABC" and "123" Section 10.12.4
constants

REMARK
1: For the timer, retentive timer, and counter, bit devices are used for the "contact"
and the "coil", and the word device is used for the "present value".
2: The actual number of usable points varies according to the intelligent/special
function module.
For details regarding the buffer memory's "number of points", refer to the
Intelligent/Special Function Module Manual.
3: Inputs, outputs, step relays, link special relays, link special registers remain at
their default values, which cannot be changed.
4: In a program, only FX0 to FX4 and FY0 to FY4 can be used.

10

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10 EXPLANTION OF DEVICES
MELSEC-Q

10.2 Internal User Devices

Internal user devices can be used for various user applications.

The "number of usable points" setting is designated in advance (default value) for
internal user devices.
However, this setting can be changed at the "Device" tab screen in the “(PLC)
Parameter" dialog box.

[Device setting screen]

Default value
"Dev. point" can be changed
for the device where a "Dev. point"
value is shown in brackets.

(1) Setting range in the internal user device

The number of points for internal user devices other than the input(X), output(Y),
step relay(S), link special relay(SB), and link special registers(SW) can be
changed within a 29 k words (including 3.7 k words for an internal user device)
range, at the "Device" tab screen in the “(PLC) Parameter" dialog box.
The following gives more information.
(a) Setting range
1) The number of device points is designated in 16-point units.
2) A maximum of 32 k points can be designated for one device.
The maximum total number of points for the internal relay, latch relay,
anunciator, edge relay, link relay, link special relay, step relay, timer,
retentive timer, and counter, is 64 k points.
1 point is calculated as 2 points (1 for coil, 1 for contact) for the timer,
retentive timer, and counter.

(2) Memory capacity

Use the following expression to obtain the memory capacity of an internal user
device.
3.7 + (Bit devices capacity) + (Word devices capacity) + (Timer, retentive timer and counter capacity) 29k

(a) For bit devices:

For bit devices, 16 points are calculated as 1 word.
(M+L+F+V+B total number of points)
(Bit device capacity) = (Word)
16

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10 EXPLANTION OF DEVICES
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(b) For timer (T) retentive timer (ST), and Counter (C):
For the timer, retentive timer, and counter, 16 points are calculated as 18
words.
(T, ST, C total number of points)
(Timer, retentive, counter capacity) = 18 (Word)
16

(c) For word devices:

For data registers (D) and link registers (W), 16 points are calculated as 16
words.
(D, W total number of points)
(Word device capacity) = 16 (Word)
16

POINT
(1) When an internal user device's "number of usable points" setting is changed,
the following files which were created under the previous setting cannot be
used as they are.
• The sequence program
• The SFC program
After changing the setting, the sequence program and SFC program must be
read from the High Performance model QCPU to GX Developer, and then they
must be written back to the High Performance model QCPU again.

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10 EXPLANTION OF DEVICES
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10.2.1 Inputs (X)

(1) Definition
(a) Inputs transmit commands or data to the High Performance model QCPU
from an external device such as push-button switches, selector switches,
limit switches, digital switches.
Push-button switch

Selector switch Input (X)

Sequence
operation

Digital switch

1 2 3

(b) If the input point is the Xn virtual relay inside the High Performance model
QCPU, the program uses the Xn's N/O contact or N/C contact.
Virtual relay
PB1 X0
Programmable
X0 controller
LS2 X1
X1

PB16
XF
XF

Input ladder (external device) Program

Figure 10.1 Inputs(X)

(c) There are no restrictions on the number of Xn N/O contacts and N/C
contacts used in a program, provided the program capacity is not
exceeded.

X0 X2
Y20
No restrictions on X0 X1 X2
the quantity used. Y21
Y21
X0
Y23

Figure 10.2 Input(X) Used in Program

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10 EXPLANTION OF DEVICES
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(2) Reading the inputs

(a) There are 2 types of input: "refresh inputs" and "direct access inputs".
1) The refresh input executes an operation with ON/OFF data. The data is
read by performing an input refresh before the sequence programs is
executed. 1
CPU module Input module
Acquisition of ON/OFF data
Input refresh area

0
X10

ON/OFF
data

The refresh input is indicated as "X " in the sequence program.For

example, a "10" input becomes "X10".
2) The direct access input executes an operation with ON/OFF data. The
data is read from an input module when the instruction is executed. 2
CPU module Input module

Input refresh area

0 Acquisition of ON/OFF data

DX10

The direct access is indicated as "DX " in the sequence program.

For example, a "10" input becomes "DX10".
The direct access input can be made in a LD/AND/OR instruction that
uses an input in units of 1 point.
(b) Differences between refresh input and direct access input
The direct access input accesses an input module directly when an
instruction is executed, which results in slower processing speed compared
with the refresh input.
The direct access input is used only for inputting to the input module or the
intelligent function module/special function module mounted on the main
base unit or extension base unit.
The refresh input and direct access input differences are shown in Table
10.2 below.
Table 10.2 Differences Between Refresh
Item Refresh Input Direct Access Inputs
Main base unit : 8.0 s
Q02CPU 0.079 s
Extension base unit : 8.0 s
Processing speed Q02HCPU,
(LD X/DX) Q06HCPU, Main base unit : 4.0 s
0.034 s
Q12HCPU, Extension base unit : 4.8 s
Q25HCPU
Input module mounted on base/extension
base unit
Input of intelligent function module
Usable Usable
mounted on base/extension base unit
Input of I/O link module mounted on
extension base unit
Input used at MELSECNET/H network
Usable Unusable
system or CC-Link system

REMARK
1: See Section 4.7.1 for details on the refresh mode.
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10 EXPLANTION OF DEVICES
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(c) The same input number can be designated for a refresh input and a direct
access input.
If the number is used as a refresh input after being used as a direct access
input, the operation is executed with the ON/OFF data read by performing a
direct access input.

Operation is based on the ON/OFF data read at

the input refresh before sequence program
X0
operation starts
Y10
Direct access input
DX0 Operation is based on the ON/OFF
Y11 data read from the input module.
Operation is based on the ON/OFF data read at
X0 the direct access input.
Y12

Figure 10.3 Refresh Input & Direct Access Input

POINT
(1) When debugging a program, an input (X) can be set to ON/OFF as described
below.
• OUT Xn instruction
OUT X1
ON/OFF command
X1

• GX Developer test operation

(2) An input (X) can be used in the following cases.
• Destination device for RX refresh of CC-link
• Destination device for refresh of link input of MELSECNET/H

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10 EXPLANTION OF DEVICES
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10.2.2 Outputs (Y)

(1) Definition
(a) Outputs give out the program control results to the external devices such as
solenoid, electromagnetic switch, signal lamp and digital display.
Signal lamp

Output (Y) Digital display

Sequence
operation

Contact

(b) Outputs give out the result equivalent to one N/O contact.
(c) There are no restrictions on the number of output Yn N/O contacts and N/C
contacts used in a program, provided the program capacity is not
exceeded.
Programmable No restrictions on the quantity used.
controller
Load
X0
Y20 M51
Y20

X1 Y20 X2
Y21
Y20 X3
Y22

Program Out ladder (external device)

Figure 10.4 Output(Y)

(2) Using outputs as internal relays (M)

"Y" corresponding to the slots installed with input modules and empty slots can
serve as internal relays (M).
Power supply module

Output module
Output module
Output module
Input module
Input module
CPU module

OUT Yn
Equivalent to internal relay

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10 EXPLANTION OF DEVICES
MELSEC-Q

(3) Output method

(a) There are 2 types of output: "refresh outputs" and "direct access outputs".
1) The refresh output gives out the ON/OFF data to an output module by
performing an output refresh before the sequence program is
executed. 1
High Performance model QCPU Output module
ON/OFF data output
Output refresh area

0
Y10

The refresh output is indicated as "Y " in the sequence program.

For example, a "10" output becomes "Y10".
2) The direct access output gives out the ON/OFF data to an output
module when the instruction is executed.
High Performance model QCPU Output module

Output refresh area

DY10
ON/OFF data output

The direct access output is indicated as "DY " in the sequence

program.
For example, a "10" output becomes "DY10".
(b) Differences between refresh output and direct access output
The direct access output accesses an output module directly when an
instruction is executed, which realizes shorter external output time.
However, it processes an instruction slower compared with the refresh
output.
The direct access output is used only for outputting to the output
module or the intelligent function module/special function module
mounted on the base unit or extension base unit.
The refresh and direct output differences are shown in Table 10.3 below.
Table 10.3 Differences Between Refresh Outputs & Direct Access Outputs
Item Refresh Input Direct Access Outputs
Main base unit : 8.0 s
Q02CPU 0.158 s
Extension base unit : 8.8 s
Processing speed Q02HCPU,
(OUT Y/DY) Q06HCPU, Main base unit : 4.0 s
0.068 s
Q12HCPU, Extension base unit : 4.8 s
Q25HCPU
Output module installed at base/extension
base unit
Outputs of intelligent function module
Usable Usable
installed at base/extension base unit
Outputs of I/O link module installed at
extension base unit
Outputs used at MELSECNET/H network
Usable Unusable
system or CC-Link system

REMARK
1: See Section 4.7.1 for details on the refresh mode.
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10 EXPLANTION OF DEVICES
MELSEC-Q

10.2.3 Internal relays (M)

(1) Definition
(a) Internal relays are auxiliary relays which cannot be latched by the
programmable controller's internal latch (memory backup).
All internal relays are switched OFF at the following times:
• When power is switched from OFF to ON.
• When reset occurs.
• When latch clear operation is executed.

(b) There are no restrictions on the number of contacts (N/O contacts, N/C
contacts) used in the program, provided the program capacity is not
exceded.
No restrictions on the quantity used.

M0 switches ON at X0 OFF to ON
X0
SET M0 The internal relay (M0) ON can only be used for internal
High Performance model QCPU processing, and cannot
M0 K20 be output externally.
T0

Y20 M0 ON/OFF information is output from the output module

to an external destination.
X1 M0
M100

X2 M0
M2047

Figure 10.5 Internal Relay

(2) Procedure for external outputs

Outputs (Y) are used to output sequence program operation results to an
external destination.

REMARK
Latch relays (L) should be used when a latch (memory backup) is required.
See Section 10.2.4 for details on latch relays.

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10.2.4 Latch relays (L)

(1) Definition
(a) Latch relays are auxiliary relays which can be latched by the programmable
controller's internal latch (memory backup).
Latch relay operation results (ON/OFF information) are saved even in the
following cases:
• When power is switched from OFF to ON.
• When reset occurs.
The latch is backed up by the High Performance model QCPU battery.

(b) Latch relays can be switched OFF by pertorming latch clear for the High
Performance model QCPU. However, the latch relay set as "Latch (2):
Cannot clear with Latch Clear key" at the "Device" tab screen in the “(PLC)
Parameter" dialog box cannot be turned off, even when the RESET/L.CLR
switch/remote latch clear is made for latch clear of it.

(c) There are no restrictions on the number of contacts (N/O contacts, N/C
contacts) used in the program, provided the program capacity is not
exceeded.

No restrictions on the quantity used.

L0 switches ON at X0 OFF to ON.

X0
SET L0 The latch relay (L0) ON can only be used for internal
QCPU processing, and cannot be output externally.
L0 K20
T0

Y20 L0 ON/OFF information is output from the output

module to an external destination.
X1 L0
L100

X2 L0
L2047

Figure 10.6 Latch Relay

(2) Procedure for external outputs

Outputs (Y) are used to output sequence program operation results to an
external destination.

REMARK
Internal relays (M) should be used when a latch (memory backup) is not required.
See Section 10.2.3 for details on internal relays.

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10.2.5 Anunciators (F)

(1) Definition
(a) Anunciators are internal relays used for fault detection programs created by
the user.

(b) When anunciators switch ON, a special relay (SM62) switches ON, and the
Nos. and quantity of the anunciators which switched ON are stored at the
special registers (SD62 to SD79).
• Special relay :SM62.................... :Switches ON if even one anunciator
switches ON.
• Special register :SD62 .................... No. of first anunciator which switched
ON is stored here.
SD63 .................... The number (quantity) of anunciators
which are ON is stored here.
SD64 to SD79...... Anunciator Nos. are stored in the order
in which they switched ON.
(The same anunciator No. is stored at
SD62 and SD64.)
The anunciator No. stored at SD62 is also registered in the "fault history
area".

(c) Using annunciators for a fault detection program, an equipment fault or fault
presence/absence (annunciator number) can be checked by monitoring the
special register (SD62 to SD79) when the special relay (SM62) switches
ON.
Example
The program which outputs the No. of the ON annunciator (F5) is shown below.

[Fault detection program]

X0 X10
SET F5
SM62 OFF to ON
SD62 0 to 5
SM62 SD63 0 to 1
BCDP SD62 K4Y20 SD64 0 to 5
SD65 0
Output of annunciator
No. which switched ON SD79 0
Annunciator ON detection

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(2) Anunciator ON procedure

(a) Anunciator ON procedure
Anunciator operation can be controlled by the SET F and OUT
F instructions.
1) The SET F instruction switches the anunciator ON only at the leading
edge (OFF to ON) of the input condition, and keeps the anunciator ON
when the input condition switches OFF.
In cases where many anunciators are used, the OUT F instruction
can be used to speed up the scan time.
2) The OUT F instruction can switch the anunciator ON or OFF. It takes
longer to do so than the SET F instruction. If the anunciator is
switched OFF by using an OUT F instruction, this will require the
execution of an RST F or LEDR instruction. Use a SET F
instruction to switch the anunciator ON.
POINT
If switched ON by any method other than the SET F and OUT F instructions,
the anunciator functions in the same way as the internal relay.
(Does not switch ON at SM62, and anunciator Nos. are not stored at SD62, SD64
to SD79.)
(b) Processing at anunciator ON
1) Data stored at special registers (SD62 to SD79)
a) Nos. of anunciators which switched ON are stored in order at
SD64 to SD79.
b) The anunciator No. which was stored at SD64 is stored at SD62.
c) "1" is added to the SD63 value.
SET F50 SET F25 SET F2047

SD62 0 50 50 50
SD63 0 1 2 3
SD64 0 50 50 50
SD65 0 0 25 25
SD66 0 0 0 2047 Up to 16 annunciator
SD67 0 0 0 0 No. can be stored.

SD79 0 0 0 0

2) Processing at CPU
"USER" LED at High Peformance model QCPU front is ON.
3) Setting the display priority at error occurrence to SD207 - SD209
allows you to select whether the ERR. LED is to be ON or OFF when
the annunciator turns ON.

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(3) Anunciator OFF procedure and processing content

(a) Anunciator OFF procedure
An anunciator can be switched OFF by the RST F , LEDR, BKRST, and
OUT F instructions.
1) An anunciator No. which has been switched ON by the SET F
instruction can be switched OFF by the RST F instruction.
2) The LEDR instruction is used to switch OFF the anunciator Nos. stored
at SD62 and SD64.
3) The BKRST instruction is used to switch all the anunciator Nos. within
a specified range.
4) The OUT F instruction can execute ON/OFF of the anunciator No. by
the same instruction.
However, if an anunciator is switched OFF by the OUT F instruction,
the "processing at anunciator OFF" (item (b) below) is not performed.
Execute the RST F , LEDR or BKRST instructions after the
anunciator has been switched OFF by the OUT F instruction.

1) To switch OFF only the anunciators stored at SD62 and SD64:

Fault detection program

(Annunciator ON program)
Display reset input
LEDR SD62 and SD64 annuciators OFF
program

2) To switch OFF all anunciators which are ON:

Fault detection program
(Annunciator ON program)
Display reset input
BKRSTP F0 K10 F0 to F9 OFF program

REMARK
For details on the LEDR and BKRST instruction, refer to the QCPU(Q
mode)/QnACPU Programming Manual(Common Instructions).

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(b) Processing at anunciator OFF

1) Special register (SD62 to SD79) data operation at execution of LEDR
instruction
a) Anunciator No. stored at SD64 is deleted, and anunciator Nos.
stored at subsequent registers (SD65 to SD79) are moved up to
fill the empty space.
b) The anunciator No. stored at SD64 is stored at SD62.
c) "-1" is subtracted from the SD63 value.
d) If the SD63 value is "0", SM62 is switched OFF.
SET F50 SET F25 SET F2047 LEDR

SD62 0 50 50 50 25
SD63 0 1 2 3 2
SD64 0 50 50 50 25
SD65 0 0 25 25 2047
SD66 0 0 0 2047 0
SD67 0 0 0 0 0

SD79 0 0 0 0 0

2) Special register (SD62 to SD79) data operation when an anunciator is

switched OFF by the RST F instruction
a) The anunciator No. which was switched OFF is deleted, and all
subsequent anunciator Nos. are moved up to fill the empty space.
b) If the anunciator No. stored at SD64 was switched OFF, the new
anunciator No. which is stored at SD64 is stored at SD62.
c) "-1" is subtracted from the SD63 value.
d) If the SD63 value is "0", SM62 is switched OFF.
SET F50 SET F25 SET F2047 RST F25

SD62 0 50 50 50 50
SD63 0 1 2 3 2
SD64 0 50 50 50 50
SD65 0 0 25 25 2047
SD66 0 0 0 2047 0
SD67 0 0 0 0 0

SD79 0 0 0 0 0

3) Processing by High Performance model QCPU

If all SD64 to SD79 anunciator Nos. are switched OFF, the "USER"
LED on the High Performance model QCPU front display is switched
OFF.

POINT
If an error occurs to continue operation with the higher-priority over an anunciator
when the anunciator is switched ON, eliminate the error by executing an LEDR
instruction. See Section 7.20.2 for priority. In this case, executing an LEDR
instruction will not switch the anunciator OFF. To switch the anunciator OFF, you
must first eliminate the error before executing the LEDR instruction because the
error takes priority over the anunciator.

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10.2.6 Edge relay (V)

(1) Definition
(a) An edge relay is a device which stores the operation results (ON/OFF
information) from the beginning of the ladder block.
Edge relays can only be used at contacts, and cannot be used as coils.
X0 X1 X10 V1

Edge relay
Stores the X0, X1 and X10 operation results

(b) The same edge relay number cannot be used twice in programs executed
by the High Performance model QCPU.

(2) Edge relay applications

Edge relays are used for detecting the leading edge (OFF to ON) in programs
configured using index modification.
[Ladder example]
SM400
MOV K0 Z1 Index register (Z1) clear

FOR K10 Repetition (10 times) designation

*1 *1
X0Z1 V0Z1
M0Z1 M0Z1 is turned ON 1 scan at leading edge of X0Z1
SM400
INC Z1 Increment Index Register (Z1) (+1)

NEXT Return to FOR instruction

[Timing chart]
ON
X0 OFF
ON
When Z1=0 V0 OFF
ON
M0 OFF

1 Scan
ON
X1 OFF
ON 1 scan ON at X1 leading edge
When Z1=1 V1 OFF
ON
M1 OFF

1 Scan

REMARK
1: The ON/OFF information for X0Z1 is stored at the V0Z1 edge relay.
For example, the X0 ON/OFF information is stored at V0, and the X1 ON/OFF
information is stored at V1.

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10.2.7 Link relays (B)

(1) Definition
(a) A link relay is the High Performance model QCPU relay used to refresh the
High Performance model QCPU from the MELSECNET/H network
module's link relay (LB) and to refresh the MELSECNET/H network
module's link relay (LB) from the High Performance model QCPU data.
High Performance model QCPU MELSECNET/H network module
Link relay Link relay
B0 LB0
Link refresh Link refresh setting range

Internal relays or latch relays can be used for data ranges not used by the
MELSECNET/H network system.
• Range where no link relay latch is performed...Internal relay
• Range where link relay latch is performed........Latch relay

(b) There are no restrictions on the number of contacts (N/O contacts, N/C
contacts) used in the program.

No restrictions on the quantity used.

B0 switches ON at X0 OFF to ON.

X0
SET B0 The link relay (B0) ON can only be used for internal QCPU
processing, and cannot be output externally.
B0 K20
T0

Y20 B0 ON/OFF information is output from the output module

to an external destination.
X1 B0
B100

X2 B0
B1FFF

Figure 10.7 Link Relay

(2) Using link relays in the network system

In order to use link relays in the network system, a network parameter setting is
required. Link relays for which no network parameter setting has been
designated can be used as internal relays or latch relays.

REMARK
1) For details on the network parameters, refer to the For Q Corresponding
MELSECNET/H Network System Reference Manual.
2) The MELSECNET/H Network Module has 16384 link relay points assigned.
High Performance model QCPU has 8192 link relay points assigned. When using
subsequent points after Point 8192, change the number of link relay points at the
"Device" tab screen in the “(PLC) Parameter" dialog box.
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10.2.8 Link special relays (SB)

(1) Definition
(a) A link special relay indicates the communication status and error detection
of an intelligent function module, such as the MELSECNET/H Network
Module.

(b) Because link special relays are switched ON and OFF in accordance with
various problems which may occur during a data link, they serve as a tool
for identifying data link problems.

(2) Number of link special relay points

There are a total of 2048 link special relay points between SB0 and SB7FF. Link
special relays are assigned at a rate of 512 points per each intelligent function
module, such as the MELSECNET/H Network Module. Link special relays are
assigned as shown below.
SB0
For 1st network module 512 points
SB1FF
SB200
For 2nd network module 512 points
SB3FF 2048 points
SB400
For 3rd network module 512 points
SB5FF
SB600
For 4th network module 512 points
SB7FF

REMARK
For details on link special relays used at the QCPU, refer to the QCPU (Q
mode)/QnACPU Programming Manual (Common Instructions).

10.2.9 Step relays (S)

A step relay is an SFC program device.

For details regarding procedures for using step relays, refer to the QCPU (Q
mode)/QnACPU Programming Manual (SFC).

POINT
Because the step relay is a device exclusively for the SFC program, it cannot be
used as an internal relay in the sequence program.
If used in this manner a SFC error will occur, and system operation will be stopped
(system down).

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10.2.10 Timers (T)

Timers are of up-timing, with the time measurement beginning when the coil switches
ON, and ending (time out) when the current value exceeds the set value.
The current value matches the set value when a "time-out" occurs.
There are two types of timers: a low/high speed that allows the current value to return
to "0" when a timer coil switches OFF, and a retentive timer that retains the current
value even when a timer coil switches OFF.
Timers Timers Low speed timers
High speed timers
Retentive timers Low speed retentive timers
High speed retentive timers

With a timer setting (instruction format), a device is assigned for a low speed timer or
high speed timer. The OUT T0 instruction is used to assign a device for a low -speed
timer. The OUTH T0 instruction is used to assign a device for a high speed timer.
With a timer setting (instruction format), a device is assigned for a low speed retentive
timer or high speed retentive timer. The OUT T0 instruction is used to assign a device
for a low speed retentive timer. The OUTH T0 instruction is used to assign a device for
a high speed retentive timer.

Low-speed timers
(1) Definition
(a) Low speed timers are valid only while the coil is ON.

(b) The time measurement begins when the timer's coil switches ON, and the
contact switches ON when a "time-out" occurs. When the timer's coil
switches OFF, the current value becomes "0", and the contact switches
OFF.
[Ladder example]
K10 When X0 switches ON, the T0 coil switches ON, and the
X0
contact switches ON 1 second later. (The low-speed timer
T0
measures time in 100 ms units.)

[Time chart]
ON
X0 OFF
ON
T0 coil OFF
1s
ON
T0 contact OFF

(2) Measurement units

(a) The default time measurement units setting for low speed timers is 100 ms.

(b) The time measurement units setting can be designated in 1 ms units within a
1 ms to 1000 ms range.
This setting is designated at the "PLC system" tab screen in the “(PLC)
Parameter" dialog box.

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High-speed timers
(1) Definition
(a) High speed timers are valid only while the coil is ON. A high speed timer is
marked with a symbol "H".

(b) The time measurement begins when the timer's coil switches ON, and the
contact switches ON when the time elapses. When the timer's coil switches
OFF, the current value becomes "0", and the contact switches OFF.
[Ladder example]
High-speed timer display
X0 H K200 When X0 switches ON, the T200 coil switches ON, and
T200 the contact switches ON 2 second later. (The high-speed
timer measures time in 10 ms units.)

[Time chart]
ON
X0 OFF
ON
T200 coil OFF
2s
ON
T200 contact OFF

(2) Measurement units

(a) The default time measurement units setting for high speed timers is
10 ms.

(b) The time measurement units setting can be designated in 0.1ms units within
a 0.1 ms to 100 ms range.
This setting is designated at the "PLC system" tab screen in the “(PLC)
Parameter"dialog box.

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Retentive timers
(1) Definition
(a) Retentive timers measure the "coil ON" time.

(b) The measurement begins when the timer coil switches ON, and the contact
switches ON when a time-out (coil OFF) occurs.
Even when the timer coil is OFF, the current value and the contact ON/OFF
status are saved. When the coil is switched ON again, the time
measurement resumes from the current value which was saved.

(c) There are 2 retentive timer types: low speed retentive timer, and high speed
retentive timer.

(d) The RST T instruction is used to clear (reset) the current value and switch
the contact OFF.
[Ladder example]
X0 K200
X0 ON time is measured as 20 seconds when the timer
ST0
measures time in 100 ms units.

X1 Retentive timer display

RST ST0 When X1 switches ON, the ST0 contact is reset, and
the current value is cleared.
[Time chart]

ON
X0 OFF
ON
T0 coil OFF
15s 5s

T0 present value 0 1 to 150 151 to 200 0

Present value is saved when coil switches. ON

T0 contact OFF

Contact remains ON when coil switches. Instruction execution

RST ST0 instruction

ON
X1 OFF

(2) Measurement units

(a) The measurement units settings for retentive timers are the same as those
for low speed timers and high speed timers.
• Low speed retentive timer: Same as low speed timer
• High speed retentive timer: Same as high speed timer

REMARK
In order to use retentive timers, a retentive timer "number of points used" setting
must be designated at the "Device" tab screen in the “(PLC) Parameter" dialog box.

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Timer Processing and accuracy

(a) When an OUT T instruction is executed, the following is processed: timer
coil ON/OFF, current value update and contact ON/OFF processing. Timer
current value update and contact ON/OFF processing are not performed at
END processing.
[Ladder example]
X0 K10
T0

[Processing at execution of OUT T0 instruction]

END OUT T0 END

Sequence
program
Processing content
Coil ON/OFF
Current value update
Contact ON/OFF

(b) When the OUT T instruction is executed, the current value is added to the
scan time measured at the END instruction.
If the timer coil is OFF when the OUT T instruction is executed, the
current value is not updated.
[Ladder example]
X0 H K8
T0

[Current value update timing]

OUT T0 OUT T0 OUT T0 OUT T0 OUT T0 OUT T0
END END END END END END
processing processing processing processing processing processing
Program
ON
X0 external input OFF

ON
QCPU's X0 OFF

ON
T0 coil OFF

ON
T0 contact OFF

10 ms 1 2 1 2 3 1 2 1 2 3 1 2 1 2 3
measurement

Measured value
at END instruction 2 3 2 3 2 3

T0 current value 0+2=2 2+3=5 5+2=7 7+3=10

Input reading timing Timer accuracy

(+1 scan) - (1 scan time + timer time
limit setting) to 1 scan time

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(c) The timer response accuracy from when reading input (X), until when
outputing it is + (2-scan time + timer time limit setting).

Precautions for using timers

The following are a few precautions regarding timer use:
(a) A given timer cannot be designated (by OUT T ) more than once in a
single scan.
This designation results in measurement, since the timer current value is
updated at execution of each OUT T instruction.
OUT OUT OUT OUT OUT
END T T T END T T
Sequence
program
Current value is updated.
1 Scan

(b) When a timer (for example. T1) coil is ON, the OUT T1 instruction cannot be
skipped using a CJ instruction, and so forth.
If the OUT T instruction is skipped, the timer current value will not be
updated.

(c) Timers cannot be used in interrupt programs and fixed scan execution
programs.

(d) If the timer set value is "0", the contact turnes ON when the OUT T
instruction is executed.

(e) If the set value changes to a value which is higher than the current value
following a timer "time-out", the "time-out" status will remain in effect, and
timer operation will not be performed.

(f) If a timer is used at a low speed execution type program, the current value
will be added to the low speed scan time when the OUT T instruction is
executed.
See Section 4.3.2 for details on the low speed scan time.

(g) If two timers are used, the ON/OFF ladders should be created as shown
below.
T0 K10
T1 1 second measurement
following T0 ON
T1 K10
T0 1 second measurement
when T1 ON
T0
M0 ON/OFF repeated every
1 second

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10.2.11 Counters (C)

Counters are "up-timing" types, with the contact being switched ON when the count
value equals the set value (count-out condition).
There are two counter types: counters which count the number of input condition start-
ups (leading edges) in sequence programs, and counters which count the number of
interrupt factor occurrences.

Counters
(1) Definition
A counter is a device which counts the number of input condition leading edges
in sequence programs.

(2) Count processing

(a) When and OUT C instruction is executed, the following counter
processing occurs: coil ON/OFF, current value update (count value + 1),
and contact ON/OFF.
Counter current value update and contact ON/OFF processing are not
performed at END processing.
[Ladder example]
X0 K10
C0

[Processing at OUT C0 Instruction (X0: OFF to ON)]

END OUT C0 END

Sequence
program
Processing content
Coil ON/OFF
Current value update
Contact ON/OFF

(b) The current value update (count value + 1) is performed at the leading edge
(OFF to ON) of the OUT C instruction.
The current value is not updated in the following OUT C instruction
statuses: OFF, ON to ON, ON to OFF
[Ladder example]
X0 K10
C0

[Current value update timing]

END OUT C0 END OUT C0 END OUT C0

Sequence
program
ON
X0 OFF

ON
C0 coil OFF

Current value update Current value update

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(c) Multiple counters can be used within a single scan to achieve the maximum
counting speed.
In such cases, the direct access input (DX ) method should be used for
the counter input signals. 1
OUT OUT OUT OUT OUT
END C C C END C C
Sequence
program

OUT C execution intervals

(3) Resetting the counter

(a) Counter current values are not cleared even if the OUT C instruction
switches OFF. Use the RST C instruction to clear the counter's current
value and switch the contact OFF.
(b) The count value is cleared and the contact is switched OFF at execution of
when the RST C instruction.
[Ladder example]
X0
RST C0

[Counter reset timing]

END RST C0 END RST C0 END RST C0

Sequence
program
ON
X0 OFF

Execution
RST C0 OFF
instruction

Count value cleared & contact OFF Count value cleared & contact OFF

(4) Precautions for resetting the counter

When the RST C instruction is executed, the coil of C also turns OFF.
Hence, if the execution condition of the OUT C instruction is still ON after
execution of the RST C instruction, the coil of C is turned ON at the
execution of the OUT C instruction to update the current value (increment the
count value by 1).
[Ladder example]
M0 K10
C0

C0
RST C0

In the above ladder example, when M0 turns from OFF to ON, the coil of C0
turns ON, updating the current value. When C0 reaches the preset value finally,
the contact of C0 turns ON, and the execution of the RST C0 instruction clears
the current value of C0. At this time, the coil of C0 also turns OFF.
When M0 is still ON in the next scan, the current value is updated since the coil
of C0 turns from OFF to ON at the execution of the OUT C0 instruction. (The
current value turns to 1.)

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10 EXPLANTION OF DEVICES
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[Current value update timing]

Sequence END OUT C0 RST C0 END OUT C0 RST C0 END

program
ON
M0 OFF

ON
Coil of C0 OFF
Current value update & Current value is updated
contact ON Coil of C0 OFF since coil of C0 turns from
OFF to ON.
RST C0 OFF

Count value cleared & contact OFF

As a remedy for the above, it is recommended to insert the normally closed

contact of the OUT C0 instruction execution condition as the execution condition
of the RST C0 instruction as shown in the following modified ladder example so
that the coil of C0 will not turn OFF while the OUT C0 instruction execution
condition (M0) is ON.
[Modified ladder example]
M0 K10
C0

C0 M0
RST C0

(5) Maximum counting speed

The counter can count only when the input condition ON/OFF time is longer than
the execution interval of the corresponding OUT C instruction.
The maximum counting speed is calculated by the following expression:
Maximum counting n 1 n: Duty(%) 2
= [times/s]
speed (Cmax) 100 T T: Execution interval of the OUT C instruction

REMARK
1) 1: See Section 10.2.1 for details on direct access inputs.
2) 2: The "duty" is the count input signal's ON-OFF time ratio expressed as a
percentage value.
T1
When T1 T2 n = 100
T1+T2
T2
When T1 < T2 n = 100
T1+T2

T1 T2
ON
Count input signal OFF

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Interrupt counters
(1) Definition
Interrupt counters are devices which count the number of interrupt factor
occurrences.

(2) Count processing

(a) The interrupt counter's current value is updated when an interruption
occurs. It is not necessary to create a program which includes an interrupt
counter function.
(b) Interrupt counter operation requires more than the simple designation of a
set value.
To use the interrupt counter for control purposes, comparison instructions
(=, <=, etc.) must also be used to enable comparisons with the set value,
with an internal relay (M), etc., being switched ON or OFF according to the
comparison result.
The figure below shows a sample program in which M0 is switched ON
after 10 interrupt inputs are performed. (In this example, "C300" is the
interrupt counter No. corresponding to I0.)
= K10 C300 M0

(3) Setting the interrupt counter

(a) In order to use interrupt counters, at first interrupt counter No. setting must
be designated at the "PLC system" tab screen in the “(PLC) Parameter"
dialog box.
256 points are then allocated for interrupt counters, beginning from the "first
counter No." which is designated.
If C300 is designated as the first interrupt counter No., numbers C300 to
C555 will be allocated for interrupt counters.
C300 I0
C301 I1
C302 I2
Interrupt counter (256 points)

C555 I255

Values corresponding to the interrupt counter No.

(b) In order to use an interrupt counter, an "interruption permitted" status must

be established by E1 instruction at the main routine program.

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(4) Precautions
(a) One interrupt pointer is insufficient to execute interrupt counter and interrupt
program operation.
Moreover, an interrupt program cannot be executed by an interrupt counter
setting designated at the "PLC system" tab screen in the “(PLC) Parameter"
dialog box.

(b) If the processing items shown below are in progress when an interruption
occurs, the counting operation will be delayed until processing of these
items is completed.
The count processing starts after the execution of programs is completed.
Even if the same interruption occurs again while processing of these items
is in process, only one interruption will be counted.
• During execution of sequence program instructions
• During interrupt program execution
• During execution of a fixed scan execution type program

(c) The maximum counting speed of the interrupt timer is determined by the
longest processing time of the items shown below.
• Instruction with the longest processing time among the instructions used
in the program
• Interrupt program processing time
• The processing time of a fixed scan execution type program

(d) The use of too many interrupt counters will increase the sequence program
processing time, and may cause a "WDT ERROR".
If this occurs, reduce the number of interrupt counters or the counting
speed for the input pulse signal.

(e) The interrupt counter's count value can be reset by using the RST C
instruction in the sequence program prior to the FEND instruction.

(f) The interrupt counter's count value can be read out by using the sequence
program MOV instruction.

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10.2.12 Data registers (D)

(1) Definition
(a) Data registers are memory devices which store numeric data (-32768 to
32767, or 0000H to FFFFH).

(b) Data registers, which consist of 16 bits per point, read and write data in 16-
bit units.
b15 b0
Dn

(c) If the data registers are used for 32-bit instructions, the data will be stored in
registers Dn and Dn + 1. The lower 16 bits of data are stored at the data
register No. (Dn) designated in the sequence program, and the higher 16
bits of data are stored in the designated register No. + 1 (Dn + 1). For
example, if register D12 is designated in the DMOV instruction, the lower
16 bits are stored in D12, and the upper 16 bits are stored in D13.

DMOV K500000 D12

Processing object: D12, D13

D13 D12

Upper 16 bits Lower 16 bits

Two data registers can store a range of numeric data from -2147483648 to
2147483647 or from 0H to FFFFFFFFH.

(d) Data stored by the sequence program is maintained until another data save
operation occurs.

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10.2.13 Link registers (W)

(1) Definition
(a) A link register is the High Performance model QCPU memory used to
refresh the High Performance model QCPU with data from the link registers
(LW) of intelligent function modules including MELSECNET/H network
module.
Link registers are used to store numeric data (-32768 to 32767, or 0000H to
FFFFH).
High Performance model QCPU MELSECNET/H network module
Link register Link register
W0 LW0
Link refresh
Link refresh setting range

When used outside the MELSECNET/H network system's range, link

registers can serve as data registers.

(b) Link registers, which consist of 16 bits per point, read and write data in 16
bit units.
b15 b0
Wn

(c) If the link registers are used for 32-bit instructions, the data is stored in
registers Wn and Wn + 1. The lower 16 bits of data are stored in the link
register No. (Wn) designated in the sequence program, and the higher 16
bits of data are stored in the designated register No. + 1 (Wn + 1).
For example, if link register W12 is designated in the DMOV instruction, the
lower 16 bits are stored in W12, and the upper 16 bits are stored in W13.

DMOV K500000 W12

Processing object: W12, W13

W13 W12

Upper 16 bits Lower 16 bits

In two link register points, -2147483648 to 2147483647 or 0H to

FFFFFFFFH data can be stored.

(d) Data stored by the link register is maintained until another data is save.

REMARK
The MELSECNET/H network module has 16384 link register points. The High
Performance model QCPU has 8192 link register points. When subsequent points
after Point 8192 are used for link registers, change a "number of points" setting of
link registers at the "Device" tab screen in the “(PLC) Parameter" dialog box.

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(2) Using link registers in a network system

In order to use link registers in the network system, network parameter settings
must be made.
Link registers not set in the network parameter settings can be used as data
registers.

REMARK
For details on network parameters, refer to the Q Corresponding MELSECNET/H
Network System Reference Manual.

10.2.14 Link special registers (SW)

(1) Definition
(a) Link special registers are used to store data on the communication status
and errors of an intelligent function

(b) Because the data link information is stored as numeric data, the link special
registers serve as a tool for identifying the locations and causes of faults.

(2) Number of link special register points

There are 2048 link special register points from SW0 to SW7FF. The link special
register points are assigned at the rate of 512 points per intelligent function
module, such as a MELSECNET/H network module.
By default, the following points are assigned for link registers as shown below.
Link special register
SW0
For the 1st network module 512 points
SW1FF
SW200
For the 2nd network module 512 points
SW3FF 2048 points
SW400
For the 3rd network module 512 points
SW5FF
SW600
For the 4th network module 512 points
SW7FF

REMARK
For details on link special registers used in the QCPU, refer to the QCPU(Q
mode)/QnACPU Programming Manual (Common Instructions).

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10.3 Internal System Devices

Internal system devices are used for system operations.

The allocations and sizes of internal system devices are fixed, and cannot be changed
by the user.

10.3.1 Function devices (FX, FY, FD)

(1) Definition
(a) Function devices are used in a sub-routine program with arguments to
perform write/read of data between the sub-routine call source with
argument and the sub-routine program with argument.
Example
If FX0 and FD1 are used at the sub-routine program, and if M0 and D0 are designated by the sub-routine
CALL instruction, the M0 ON/OFF data is transferred to FX0, and the D0 data is transferred to FD1.
[Sub-routine program CALL source] [Sub-routine program]
X0 FX0
CALL P0 M0 D0 P0 MOV FD1 R0

RET

(b) Because the function devices used for each sub-routine program CALL
source can be set, the same sub-routine program can be used without
regard to other sub-routine CALL sources.

(2) Types of function devices

There are 3 function device types: function input devices (FX), function output
devices (FY), and function register devices (FD).
(a) Function input devices (FX)
• These devices are used to designate inputs of ON/OFF data to a sub-
routine program.
• In the sub-routine program, these devices are used for reading and
processing bit data designated by sub-routine with argument CALL
instruction.
• All the QCPU bit data designation devices can be used.

(b) Function output devices (FY)

• These devices are used to designate outputs of sub-routine program
operation results (ON/OFF data) to the sub-routine program CALL source.
• The operation results are stored at the device designated by using sub-
routine programs with arguments.
• All bit data designation devices except High Performance model QCPU
inputs (X, DX) can be used.

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(c) Function registers (FD)

• Function registers are used to perform write/read of data between the sub-
routine call source and the sub-routine program.
• The function register I/O condition is automatically determined by the High
Performance model QCPU. If the sub-routine program data is the source
data, the data is designated as sub-routine input data.
If the sub-routine program data is the destination data, the data is
designated as sub-routine output data.
• 1 point occupies 4 words.
The number of words used depends on an instruction in a sub-routine
program.
A one-word instruction requires 1 word.

CALLP P0 D0 P0 MOV R0 FD0

The data is stored in one point (D0).

A two-words instruction requires 2 words.

CALLP P0 D0 P0 DMOV R0 FD0

The data is stored in two points (D0 and D1).

The destination of 32-bit multiplication/division operation requires 4 words.

CALLP P0 D0 P0 D R0 R10 FD0

The data is stored in four points (D0 to D3).

• Valid devices cannot be used in a sub-routine program that contains

arguments. If devices assigned for function registers are used, values of the
function registers will not correctly be returned to a calling program.

CALLP P0 D0 P0 D R0 R10 FD0

MOV K0 D3

Since the points (D0 to D3) are used

for FD0, D3 can not be used for the
sub-routine program.
• High Performance model QCPU's word data devices can be used.

REMARK
For a procedure for using function devices, refer to the QCPU (Q mode)/QnACPU
Programming Manual (Common Instructions).

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10.3.2 Special relays (SM)

(1) Definition
A special relay is used to store High Performance model QCPU status data.

(2) Special relay classifications

Special relays are classified according to their applications, as shown below.
(a) For fault diagnosis : SM0 to SM199

(b) System information : SM200 to SM399

(c) System clock/system counter : SM400 to SM499

(d) Scan information : SM500 to SM599

(e) Memory card information : SM600 to SM699

(f) Instruction related : SM700 to SM799

(g) For debugging : SM800 to SM899

(h) Latch area : SM900 to SM999

(i) For A-PLC : SM1000 to SM1299

REMARK
1) For details on special relays which can be used by the High Performance model
QCPU, refer to Appendix 1.
2) : This takes effect only after you have turned on the "Use special relay/special
register form SM1000/SD1000" check box in the "Compatibility with A-PLC"
section at the "PLC system" tab screen in the “(PLC) Parameter" dialog box.

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10.3.3 Special registers (SD)

(1) Definition
A special register is used to store High Performance model QCPU status data
(diagnosis and system information).

(2) Special register classifications

Special registers are classified according to their applications, as shown below.
(a) For fault diagnosis : SD0 to SD199

(b) System information : SD200 to SD399

(c) System clock/system counter : SD400 to SD499

(d) Scan information : SD500 to SD599

(e) Memory card information : SD600 to SD699

(f) Instruction related : SD700 to SD799

(g) For debugging : SD800 to SD899

(h) Latch area : SD900 to SD999

(i) For A-PLC : SD1000 to SD1299

(j) Fuse-blown module : SD1300 to SD1399

(k) Check of I/O modules : SD1400 to SD1499

REMARK
1) For details on special relays which can be used by the High Performance model
QCPU, refer to Appendix 2.
2) : This takes effect only after you have turned on the "Use special relay/special
register form SM1000/SD1000" check box in the "Compatibility with A-PLC"
section at the "PLC system" tab screen in the “(PLC) Parameter" dialog box.

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10.4 Link Direct Devices (J \ )

(1) Definition
(a) At END processing of sequence program, a data refresh (data transfer) is
performed between the High Performance model QCPU and the
MELSECNET/H network modules. Link direct devices are used to directly
access the link devices in the MELSECNET/H network modules.
(b) Designation method
• Link direct devices are designated by network No. and device No.
Designation method: J \
Device No.
Input...........................X0
Output........................Y0
Link relay.................. B0
Link register...............W0
Link special relay.......SB0
Link special register ..SW0
Network No.(1 to 239)

• For link register 10 (W10) of network No.2, the designation would be

"J2\W10"

MOVP K100 J2\W10

Network modules at network No.2

W0

W10

• For a bit device (X, Y, B, SB), digit designation is necessary.

Designation example : J1\K1X0, J10\K4B0
(2) Designation range
Link direct device designations are allowed for all the link devices in network
modules.
Device outside the range specified by the network refresh
parameters can also be designated.
(a) Writing
1) Writing is executed within that part of the link device range set as the
send range in the common parameters of the network parameters that
is outside the range specified as the "refresh range" in the network
refresh parameters.
High Performance model QCPU Network module

B0 LB 0
Link range
Refresh
range
send range

Writing range

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2) Although writing is also allowed in the "refresh range" portion of the link
device range (specified by refresh parameters), the link module's link
device data will be rewritten when a refresh operation occurs.
Therefore, when writing by link direct device, the same data should
also be written to the High Performance model QCPU related devices
designated by refresh parameter.
[Refresh parameter settings]
Network No. : 1
High Performance model QCPU(W0 to W3F) Network module (LW0 to LW3F)
[Sequence program]

MOV K100 W1 "100" is written to network module LW1 when

a refresh occurs.

MOV W1 J1\W1 "100" is written to network module LW1 when

the MOV instruction is executed.
[Writing timing]
QCPU Network module

MOV K100 W1 Writing at

instruction
execution
MOV W1 J1\W1
W0
W1 LW1
Writing at instruction execution

Writing at refresh operation

3) When data is written to another station's writing range using a link

direct device, the data which is received from that station will replace
the written data.

(b) Reading
Reading by link direct device is allowed in the entire link device range of
network modules.
POINT
Only one network module capable of writing/reading link direct devices can be used
per network number.
If two or more network modules are installed at the same network number, the
network module with the lowest first I/O number will be the one that handles
writing/reading using link direct devices.
For example, if station No.1 and station No.2 network modules are installed in
network No.1 as shown in the figure below, the station No.2 network module will
handle link direct device operations.
Network No.1
Network module

Network module
Power supply module
CPU module

Station Station
No.2 No.1
Writing/reading using link direct devices not allowed
Writing/reading using link direct devices allowed

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(3) Differences between "link direct devices" and "link refresh"

The differences between "link direct devices" and "link refresh" are shown in
Table 10.4 below.

Table 10.4 Differences Between "Link Direct Devices" and "Link Refresh"

Item Link Direct Device Link Refresh

Link relay J \K4B0 or later B0 or later
Program
Link register J \W0 or later W0 or later
notation
Link special relay J \K4SB0 or later SB0 or later
method
Link special register J \SW0 or later SW0 or later
Number of steps 2 steps 1 step
All network module link Refresh parameter
Network module access range
devices designated range
Access data guarantee range Word units (16 bits)

REMARK
1) For details on the MELSECNET/H network system, refer to the Q Corresponding
MELSECNET/H Network System Reference Manual.
2) For details on network parameters, common parameters, and network refresh
parameters, refer to the following manuals:
• Detailed information : Q Corresponding MELSECNET/H Network System
Reference Manual
• Setting procedures : GX Developer Operating Manual, Windows Version

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10.5 Intelligent Function Module Devices (U \G )

(1) Definition
(a) The intelligent function module devices allow the High Performance model
QCPU to directly access the buffer memories of intelligent function
modules/special function modules which are mounted on at the main base
unit and extension base units.

(b) Intelligent function module devices are designated by the intelligent function
module/special function module I/O No., and the buffer memory address.
Designation method: U \G
Buffer memory address (setting range: 0 to16383 (decimal)) 1
Intelligent function module/special function module I/O No.
Setting: If the I/O No. is a 3-digit value, designate the first 2 digits.
For X/Y1F0.....X/Y1F0
Designate "1F"
Setting range: 00H to FEH
When digital output values of channels (CH.1 to CH.4) of the Q64AD Type
Analog-Digital Conversion Module (X/Y20 to 2F) mounted at Slot 2 of the main
base unit are stored in D0 to D3, the I/O number and the buffer memory address
are specified as shown below.
Q64AD
BMOV U2\G11 D0 K4

11 CH.1 Digital output value

12 CH.2 Digital output value
13 CH.3 Digital output value
14 CH.4 Digital output value

(2) Processing speed

The processing speed for intelligent function module devices is;

(a) Reading or writing the buffer memory of the intelligent function

module/special function module is rather faster than the "processing speed
of FROM/TO instructions." (For example, case of "MOV U2\G11 D0")

(b) To conduct reading the buffer memory of the intelligent function

module/special function module and another process in a single instruction,
add the "processing speed of FROM/TO instruction" and "processing speed
of instruction" to setup the reference value.
(For example, case of "+ U2\G11 D0 D10")
If the same buffer memory of the same intelligent function module/special
function module is used two or more times in a sequence program, the
processing speed can be increased by using the FROM instruction to read
that buffer memory data to a High Performance model QCPU device.

REMARK
1: For details on buffer memory addresses and applications, refer to the intelligent
function module/special function module manual.

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10.6 Index Registers (Z)

(1) Definition
(a) Index registers are used in the sequence program for indirect setting (index
qualification) designations.
An index register point is used for index modification.

X0
MOVP K5 Z0

SM400
BCD D0Z0 K4Y30

Index registers consist of 16 bits per point.

(b) There are 16 index registers (Z0-Z15).

(c) Index registers, which consist of 16 bits per point, read and write data in
16bit units.
b15 b0
Zn

(d) If the index registers are used for 32-bit instructions, the data is stored in
registers Zn and Zn +1.
The lower 16 bits of data are stored in the index register No. (Zn)
designated in the sequence program, and the upper 16 bits of data are
stored in the designated index register No. + 1.
For example, if register Z2 is designated in the DMOV instruction, the lower
16 bits are stored in Z2, and the upper 16 bits are stored at Z3.

DMOV D0 Z2

Processing object: Z2, Z3

Z3 Z2

Upper 16 bits Lower 16 bits

REMARK
For index modification using the index register, refer to the following manual.
QCPU (Q mode) / QnACPU Programming Manual (Common instructions)

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10.6.1 Switching between scan execution type programs and low speed execution type
programs

When switching from a scan execution type programs or low speed execution type
program to another program type, the index register (Z0 to Z15) data is saved
(protected) and reset.

(1) Index register processing at switching between scan execution type

programs and low speed execution type programs

(a) When switching from a scan execution type program to a low speed
execution type program occurs, the scan execution type program's index
register data is saved, and the low speed execution type program's index
register data is restored.

(b) When switching from a low speed execution program to a scan execution
type program occurs, the low speed execution type program's index
register data is saved, and the scan execution type program's index register
data is restored.
Switch- Switch- Switch-
ing Low speed ing ing Low speed
Scan execution Scan execution
Executed program execution execution
type program type program
type program type program

1 2
Z0=1 Z0=0 to Z0=3 Z0=1 to Z0=6 Z0=3
Index register value
Saved Reset Saved Reset Saved Reset

For scan execution

type programs Z0=0 Z0=1 Z0=1 Z0=1 Z0=1 Z0=6 Z0=6
Index register
storage area For low speed
execution type Z0=0 Z0=0 Z0=0 Z0=3 Z0=3 Z0=3 Z0=3
program

1: For low-speed execution type program, Z0 is changed to 3.

2: For scan execution type program, Z0 is changed to 6.

(2) Exchanges of index register data

Word devices should be used for exchanges of index register data between scan
execution type programs and low speed execution type programs.

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10.6.2 Switching between scan/low speed execution type programs and interrupt/fixed scan
execution type programs

The following processing is performed at the time of switching between scan/low-

speed execution type program and interrupt program/fixed-cycle execution type
program.
Index register (Z0 to Z15) value is saved (protected)/restored.
File register block No. is saved (protected)/restored.
For the index register (Z0 to Z15), when not writing date to index registers check by
using an interrupt program/fixed scan execution type program, the "High speed
execution" check box in the "Interrupt program/Fixed scan program setting" section at
the "PLC system" tab screen in the “(PLC) Parameter" dialog box. This will switch
between programs quickly.

(1) Index register processing

(a) When "High-speed execution" is not selected
1) When the scan/low speed execution type program is switched to the
interrupt/fixed scan execution type program, the scan/low speed
execution type program's index register value is first saved, and is then
transferred to the interrupt/fixed scan execution type program.

2) When the interrupt/fixed scan execution type program is switched to

the scan/low speed execution type program, the saved index register
value is reset.
Switch-
Scan/low speed ing Interrupt program/ Reset Scan/low speed
Executed program execution type Fixed scan execution execution type
program type program program
Transf-
erred
Index register value Z0=1 Z0=1 to Z0=3 Z0=1
Saved Reset
Index register storage area
For scan/low speed Z0=0 Z0=1 Z0=1 Z0=1 Z0=1
execution type program

: For interrupt program, Z0 is changed to 3.

Word devices should be used to transfer index register data from an

interrupt or fixed scan execution type program to a scan or low speed
execution type program.

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(b) When "High-speed execution" is selected

1) If a scan execution type program/low speed execution type program is
switched to an interrupt program/fixed scan execution type program,
index register data will not be saved/restored.
2) If data is written to index registers by using an interrupt program/fixed
scan execution type program, the values of index registers used for an
scan/low speed execution type program will be corrupted.
Switch-
Scan/low speed ing Interrupt program/ Reset Scan/low speed
Executed program execution type Fixed scan execution execution type
program type program program
Transf- Transf-
Index register value Z0=1 erred Z0=1 to Z0=3 erred Z0=3

Index register storage area

For scan/low speed Z0=0 Z0=0 Z0=0 Z0=0 Z0=0
execution type program

: For interrupt program, Z0 is changed to 3.

3) Before writing data to index registers by using an interrupt

program/fixed scan execution type program, use the ZPUSH/ZPOP
instruction to save/restore the data.
SM400
The points after D0 stores the
I0 ZPUSH D0
data (Z0 to Z15).

SM400 The data after D0 is stored

ZPOP D0
in points (Z0 to Z15).
IRET

(2) File register block No. processing

(a) At the time of switching from the scan/low-speed execution type program to
the interrupt program/fixed-cycle execution type program, the block No. of
the file register in the scan/low-speed execution type program is saved and
then transferred to the interrupt program/fixed-cycle execution type
program.
(b) At the time of switching from the interrupt program/fixed-cycle execution
type program to the scan/low-speed execution type program, the saved
block No. of the file register is restored.
Scan/low-speed Switching Interrupt program/ Restored Scan/low-speed
Executed program execution type fixed-cycle execution execution type
program type program program

Block No. Transferred [RSET K0]

Block 1 Block 1
of file register : Block 1 0
Saved Restored

Save area Block 0 Block 1 Block 1 Block 1 Block 1

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10.7 File Registers (R)

(1) Definition
(a) File registers are expansion devices for data registers.
(b) File register data is stored in files in the standard RAM, the memory card.
Refer to the table as follows:
CPU Module Type Number of File Registers
Q02CPU 32k points
Q02HCPU, Q06HCPU 64k points
Q12HCPU, Q25HCPU 128k points
Use a memory card to store much more points if necessary.

MOV K100 R2
Standard RAM/Memory card
File register
R0
R1
"100" is written to R2.
R2

(c) File registers, which consist of 16 bits per point, read and write data in 16bit
units.
b15 b0
Rn

(d) If the file registers are used for 32-bit instructions, the data will be stored in
registers Rn and Rn + 1.
The lower 16 bits of data are stored in the file register No. (Rn) designated
in the sequence program, and the upper 16 bits of data are stored in the
designated file register No.+ 1.
For example, if file register R2 is designated in the DMOV instruction, the
lower 16 bits are stored in R2, and the upper 16 bits are stored in R3.

DMOV D0 R2

Processing object: R2, R3

R3 R2

Upper 16 bits Lower 16 bits

Two file registers can be used to store numeric data from -2147483648 to
2147483647 or from 0H to FFFFFFFFH.
(e) The content of the file register is retained if power-off or reset operation is
performed. (It is not initialized if latch clear is conducted.)
To initialize the file register contents, perform data clear operation in a
sequence program or using GX Developer.
Example: To clear R0 to R999

FMOV K0 R0 K1000

• When using GX Developer, select file register all clear in the PLC memory
clear of the Online dialog box to clear the data.

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10.7.1 File register capacity

(1) Using the Standard RAM

The standard RAM can store the following points of file registers.
Q02CPU: 32k points, Q02HCPU/Q06HCPU: 64k points, Q12HCPU/Q25HCPU:
128k points
The standard RAM can store only the file registers and local devices.
Hence, when the local devices are not used, the above number of points can be
used for the file registers.

(2) Using the SRAM Card

The size of a file can be expanded at the rate of 32 k words per block, up to 32
blocks, 1017 k words. The number of expandable blocks depends on the size of
programs or device comments stored on a memory card.

(3) Using the Flash Card

The size of a file can be expanded at the rate of 32 k words per block up to 32
blocks, 1018 k words. The number of expandable blocks depends on the size of
programs or device comments stored on a memory card.

REMARK
For details regarding the High Performance model QCPU memory cards, see
Section 6.1.

10.7.2 Differences in memory card access method by memory card type

File registers are stored in three types of memories: standard RAM, SRAM card, and
Flash card.
Note that the file register access method differs depending on the memory type.

Standard SRAM Flash

How to Access
RAM Card Card
Read with a user's program
Write with a user's program
PLC read through the device setting
PLC write through the device setting
Online test operation from GX Developer
PLC write from GX Developer
How to Modify the PLC write from GX Developer (Flash ROM)
Stored Data Batch write from serial communication module
Device write from GOT900 Series
Random write command from GOT 900 Series

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10.7.3 Registering the file registers

To use file registers, register the file registers with the High Performance model QCPU
in the following steps.

Start

Setting of file register

to be used
............"PLC file" tab screen at (PLC) "parameter" dialog box

"Use the following files" is selected.

"Not used" or "Use the same file

name as the program" is selected.
File register setting
............Creating new device memory screen

Writing of file register

............Online write to PLC screen

Writing of the file register to the QCPU

Writing of the parameter to the QCPU

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(1) Designating file registers for use

The standard RAM or the memory card file registers which are to be used in the
sequence program are determined at the "PLC file" tab screen in the “(PLC)
Parameter" dialog box.

(a)
(b)
(c)

(a) When selecting "Not used"

This setting should be selected for the following cases:
• When not using the file registers
• When designating the file registers to be used in the sequence program.
The QDRSET instruction is used to designate which file registers are to
be used.

(b) When selecting "Use the same file name as the program"
1) This setting should be selected when the file registers having the same
file name as the sequence program are to be used.

2) If the program is changed, the file registers are automatically changed

to conform to the new program name.
There are also cases where it is convenient to use the file registers as
local devices which can only be used with the program currently being
executed.

3) The number of file register to use can be set by writing to PLC online.
Example
When file registers (A to C) having the same name as the programs (A to C) are to be used,
operation is as shown below.
At program A execution --- File register A is accessed.
At program B execution --- File register B is accessed.
At program C execution --- File register C is accessed.

Synchronized
Program A execution R0 File register A

Synchronized
Program B execution R0 File register B

Synchronized
Program C execution R0 File register C

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POINT
File registers dedicated to each program may not be designated with some
instructions. Refer to the allowable device in the programming manual of each
instruction for details.

(c) When selecting "Use the following file"

1) This setting should be selected when a given file register is to be
shared by all executed programs.
2) Specify the desired parameters in the "Corresponding memory", "File
name", and "Capacity" text boxes. The High Performance model
QCPU creates a file register file with the specified parameters. If a
parameter is not specified in the Capacity test box, this may result in
the following:
• If a file register file with the specified filename is stored on the
specified drive, that file register file is used.
• If a file register file with the specified filename is not found on the
specified drive, a “PARAMETER ERROR (3002)” will occur.
• When an ATA card is used, a memory card (ROM) cannot be
registered with the targeted memory. If a memory card is registered
with the targeted memory, a parameter error (3000) will occur when a
file register file is written to the High Performance model QCPU.

(2) File Register Setting

Use the device memory screen to specify a filename of a file register file.
(a)

(b)

(a) Setting the file registers

Type "Rn" in the list box to view a listing of file registers.

(b) Setting the parameters

Enter the desired data in columns to specify file registers. This step is not
needed when you specify only the capacity of file registers.

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(3) Registering the File Register File with the High Performance model
QCPU
If you click on the following check boxes at the "PLC file" tab screen in the “(PLC)
Parameter" dialog box, you must register a file register file with the High
Performance model QCPU:
• Not used
• Use the same file name as the program
For registration of a file register file, use the "Write to PLC" dialog box.

(a)

(d)

(b)

(c)

(a) Selecting a memory to store file registers

Choose the standard RAM, memory card (RAM), or memory card (ROM)
from this list box to specify a memory to store file registers. If you want to use
the same filename as that of a program, store a file register file in the memory
specified in the PLC File sheet of the PLC Parameter dialog box.
(b) Selecting a file register file
If a memory for file registers is selected, a filename of a file register file is
displayed. Select the desired filename of a file register file.
(c) Specifying the capacity and filename
This section is used to specify the capacity of file registers and a filename
of the file register file to be written onto the High Performance model QCPU
(QCPU-side filename).

1) The capacity of file registers can be specified from ZR0 in the units of 1
point. Note that the capacity is secured in 256 point units as a file. If file
registers cannot be assigned from ZR0, this will result in a file register
file that contains points from ZR0 to the last point. For example, if the
storing range of file registers are designated from ZR1000 to ZR1791,
a file register file will contain points from ZR0 to ZR1791. Specify file
registers from ZR0 because undefined data is from ZR0 to ZR999. A
check on the capacity of file registers is made in the units of 1k points.
The capacity of file registers should be specified from R0 in the units of
1k points.

(d) Storing a file register file in the High Performance model QCPU's memory
This button is used to store a file register file with the specified number of
points in the specified High Performance model QCPU's memory.

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10.7.4 File register designation method

(1) Block switching format

The block switching format designates the number of file register points in 32k
point (R0 to R32767) units.
If multiple blocks are used, switch to the block No. to be used in the RSET
instruction for further file register settings.
Settings are designated in the R0 to R32767 range for each block.

RSET K1 R0 designation Memory card

for block 1 R0

MOV D0 R0 Block 0

R32767
RSET K2 R0 designation R0
for block 2
Block 1

MOV D0 R0 R32767
R0
Block 2

(2) Serial number access format

This format is used for designating file register beyond 32k points by device
name.
Multiple blocks of file registers can be used as a continuous file register.

Memory card
MOV D0 ZR32768 ZR0

(Block 0)

ZR32767
MOV D0 ZR65536 ZR32768

(Block 1)

ZR65535
ZR65536
(Block 2)

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10.7.5 Precautions in using file registers

(1) Using file register Nos. not registered or outside the registered
range
(a) When file register files are not registered in the High Performance model
QCPU, no error occurs even if reading/writing to file registers
Reading data from a file register results in the following:
• Undefined data is stored in the standard RAM.
• "0H" is stored in a memory card.

(b) Writing/reading file register Nos. outside the registered range (points)
No error occurs even if reading/writing occurs to these file registers.
Reading data from a file register results in the following:
• Undefined data is stored in the standard RAM.
• "0H" is stored in a memory card.

(2) File register capacity check

(a) Perform a file register capacity check in the sequence program, so that
reading/writing from/to the file register is performed within the size (number
of points) set in the High Performance model QCPU.
• A file register capacity check should be executed at step 0 of programs in
which file registers are used.
• After switching to another file register file using the QDRSET instruction,
execute a file register capacity check.
• When using the RSET instruction to switch blocks, confirm that the
switching destination block has a capacity of 1k points or more before
executing the RSET instruction.
(File register capacity) > [32k points (switching block No.) + 1k points]

(b) The available file register capacity can be checked in the file register
capacity storage register (SD 647). 1
The file register capacity is stored in SD647 in 1k point units.

The "less than 1k points" surplus portion of a file register

capacity is not stored.
In order to ensure an accurate "range of use" check, be sure
to designate the file register setting in 1k point (1024 points)
units.

REMARK
1 : If a file register file is switched to another, the file register capacity of the
currently selected file register file is stored in SD647.

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(c) Checking the file register capacity

1) Check The file register capacity used for each sequence program.
2) Determine if the file register capacity exceeds the number of points
used, on the basis of the total file register capacity set in SD647 in the
sequence program.

[Program example 1]
The file register "range of use" is checked at the beginning of each program.
Designates 4k points
SM400
< SD647 K4 M0 Final file register range check

M0
Y0 Alarm processing

M0 Transfer command
MOVP K4X20 R0 Writing to file register

[Program example 2]
The file register "range of use" is checked after executing the QDRSET instruction.

QDRSET "1:ABCD" File register is changed

to drive 1 ABCD.
SM400
< SD647 K4 M0 Final file register range
check
M0
Y0 Alarm processing

M0 Transfer command
MOVP K4X20 R0 Writing to file register

[Program example 3]
For block switching.
SM400
< SD647 K33 M0 Final file register range
check
M0
Y0 Alarm processing

M0 Block switching command

RSET K1 Switching to block 1

(3) Deleting a File Register

To erase unwanted file register files, perform the PLC data deletion online.

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10.8 Nesting (N)

(1) Definition
Nesting devices are used to nest MC or MCR master control instructions when
programming operating conditions.

(2) Designation method with master control

The master control instructions are used to open and close the ladders' common
bus so that switching of ladders may be executed efficiently by the sequence
program.
Nesting devices must be numbered in descending order (from N0 to N7) of
nested relation.
For details on how to use master control, refer to the QCPU(Q mode)/QnACPU
Programming Manual (Common Instructions).
Designated in ascending
A No. order
MC N0 M15
N0 M15

B Executed when condition

MC N1 M16 "A" is satisfied.
N1 M16

C Executed when conditions

MC N2 M17 "A" and "B" are satisfied.
N0 N1 N2 N2 M17 Designated in descending
nesting nesting nesting No. order
control range control range control range Executed when condition "
MCR N2 A", "B" and "C" are satisfied.
N1 is reset.

Executed when conditions

MCR N1 "A" and "B" are satisfied.
N1 to 2 are reset.

Executed when condition

MCR N0 "A" is satisfied.
N0 to 2 are reset.

Executed regardless of
A, B, C condition statuses.

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10.9 Pointers (P)

(1) Definition
Pointer devices are used in jump instructions (CJ, SCJ, JUMP) or sub-routine call
instructions (CALL, ECALL).
A total of 4096 pointers can be used (total for all programs being executed).

(2) Pointer applications

(a) Pointers are used in jump instructions (CJ, SCJ, JMP) to designate jump
destinations and labels (jump destination beginning).

(b) Pointers are used in sub-routine CALL instructions (CALL, CALLP) to

designate the CALL destination and label (sub-routine beginning).

(3) Pointer types

There are 2 pointer types: "local pointers (Section 10.9.1)" which are used
independently in programs, and "common pointers (Section 10.9.1)" which are
used to call sub-routine programs from all programs executed in the CPU.

10.9.1 Local pointers

(1) Definition
(a) Local pointers are pointers which can be used independently in program
jump instructions and sub-routine call instructions.
Local pointers cannot be used from other program jump instructions and
sub-routine CALL instructions.
Use an ECALL instruction to call a sub-routine subprogram in a program file
that contains local pointers.

(b) The same pointer No. can be used in each of the programs.
Program A Program B
Same pointer is
used.
CALL P0 CALL P0

FEND FEND

P0 P0

RET RET

END END

REMARK
For further information on jump instructions and sub-routine call instructions, see the
QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions).

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(2) Number of local pointer points

Local pointers can be divided among all the programs stored in the program
memory.
The local pointer No. ranges from P0 to the highest No. of the local pointer in use.
(The High Performance model QCPU's OS computes the number of points used.)
Even if only P99 is used in a program, for example, the number of points used
will be counted as 100 between P0 and P99.
Therefore, when local pointers are used at several programs, the pointer settings
should begin from P0.
If the total number of pointers (total for all programs) exceeds 4096 points, a
pointer configuration error (error code:4020) occurs.
Example
If the local pointer points are used as follows, the total is 600 points.
Program A Program B Program C

P0 to P99 used in P100 to P199 used Only P299 is used

program in program in program

P0 to P99 occupy P0 to P199 occupy 200 points P0 to P299 occupy 300 points Total of 600
100 points points used.

If P0 to P99 are used, If P0 is used, the

the number of number of occupied
occupied points is 100. points is 1.

10.9.2 Common pointers

(1) Definition
(a) Common pointers are used to call sub-routine programs from all programs
being executed in the High Performance model QCPU.
Program A Program C

CALL P204 P204 CALL P0

FEND RET

P205
Program B

RET
CALL P205

END
FEND

Label

(b) The same pointer No. cannot be used again as a label.

Such use will result in a pointer configuration error (error code:4021).

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(2) Common pointer range of use

In order to use common pointers, the first common pointer No. must be
designated at the "PLC system" tab screen in the “(PLC) Parameter" dialog box.
A range of common pointers starts from a specified pointer number to P4095.
However, only pointer numbers subsequent to the local pointer range can be
designated by parameter setting as common pointers.
If a total of 400 points are used in three programs (100 points in Program A, 100
points in Program B, and 200 points in Program C), for example, all local pointers
after P400 can be used as common pointers.
If the last number of local pointers used in several programs overlaps the first
number of common pointers, a "pointer configuration error (Error Code: 4020) will
occur.
Program A Program B Program C
P0 to P99 used P0 to P99 used P0 to P199 used
in program in program in program

P0 to P99 occupy 100 points P0 to P99 occupy 100 points P0 to P199 occupy 200 points

Total of 400 points used All pointers after P400

can be used as common
pointers.

[Common pointer settings screen]

Set the head number
of the common
pointers here.

POINT
(1) In the jump instruction, jumping to common pointers in other programs is not
allowed.
Common pointers should be used only with sub-routine call instructions.

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10.10 Interrupt Pointers (I)

(1) Definition
(a) Interrupt pointers are used as labels at the beginning of interrupt programs.
Interrupt pointer (interrupt program label)

I
Interrupt program

IRET

(b) A total of 256 interrupt points (I0 to I255) can be used (total for all programs
being executed).

(2) Interrupt pointer No. & interrupt factor

(a) As shown below, there are four types of interrupt factor.
• QI60/A1SI61 factor..............Interrupt input from the QI60/A1SI61
interruption module.
• Sequence start generator....Interruption input from special function
module factor modules which can dictate an interrupt start to
the High Performance model QCPU (QI60,
A1SI61 excluded).
• Internal time factor...............Fixed scan interruption by High Performance
model QCPU's internal timer.
• Error interruption..................Interruption by an error that does not stop
sequence program operation.
• Intelligent function................Interruption by an intelligent function module.
module interrupt 1

REMARK
1: To use the intelligent function module interrupt, the intelligent function module
setting (interrupt points setting) is required at the "PLC system" tab screen in the
“(PLC) Parameter" dialog box.
(For the interrupts from the intelligent function module, see Section 8.2.1.)

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(b) A list of interrupt pointer Nos. and interrupt factors is given in Table 10.5
below.
Table 10.5 List of Interrupt Pointer Nos. and Interrupt Factors
I No. Interrupt Factors Priority I No. Interrupt factors Priority
Ranking Ranking
I0 1st point 237 I32 3 Errors that stop operation 1
I1 2nd point 238 I33 Empty ——
I2 3rd point 239 UNIT VERIFY ERR.
I3 4th point 240 I34 FUSE BREAK OFF 2
I4 5th point 241 SP. UNIT ERROR
I5 6th point 242 OPERATION ERROR
I6 QI60/A1SI61 7th point 243 I35 SFCP OPE. ERROR 3
I7 8th point 244 Error factor 4 SFCP ECE. ERROR
interrupt module EX. POWER OFF
I8 9th point 245
factor
I9 10th point 246 I36 ICM. OPE ERROR 4
I10 11th point 247 FILE OPE. ERROR
I11 12th point 248 I37 Empty ——
I12 13th point 249 I38 PRG. TIME OVER 5
I13 14th point 250 I39 CHK instruction execution 6
I14 15th point 251 Anunciator detection
I15 16th point 252
I40 to —— Empty ——
I16 1st point 224 I48
I17 2nd point 225
I18 3rd point 226 I49 Internal timer factor 0, 2 to 1.0mg 5 7
I19 4th point 227
I20 Sequence start 5th point 228
I21 6th point 229
generator module
I22 7th point 230
I23 factor 1 8th point 231
I24 9th point 232 Specifies which intelligent
I50 to Intelligent function
I25 10th point 234 function module is used 18 to 223
I255 module factor 6
I26 11th point 235 with parameters.
I27 12th point 236
I28 100ms 256
I29 Internal timer factor 40ms 255
I30 2 20ms 254
I31 10ms 253

REMARK
1 : 1st to 12th points are allocated in order, beginning from the sequence start
generator module installed closest to the High Performance model QCPU.
2 : The internal times shown are the default setting times.
These times can be designated in 0.5 ms units through a 0.5 to 1000 ms range
set at the "PLC system" tab screen in the "(PLC) Parameter" dialog box.
3 : When an error interruption with "I32 (error that stops operation)" occurs, the
High Performance model QCPU is not stopped until I32 processing is
completed.
4 : Execution of error interruptions is prohibited for the interrupt pointer Nos. I32 to
I39 when the power is turned on and during a High Performance model QCPU
reset. When using interrupt pointer Nos. I32 to I39, set the interruption
permitted status by using the IMASK instruction.
5 : Set the time-out period of the internal timer by choosing "PLC system" -
"System interrupt setting" - "High speed interrupt setting" on the PLC parameter
screen.
Set it in the setting range 0.2 to 1.0ms in 0.1ms increments.
6 : To use the intelligent function module interrupt, the intelligent function module
setting (interrupt points setting) is required at the "PLC system" tab screen in
the “(PLC) Parameter" dialog box.
(For the interrupts from the intelligent function module, see Section 8.2.1.)

POINT
7: When I49 is set in the PLC parameters, other interrupt programs (I0 to I48, I50
to I255) or fixed scan execution type programs must not be executed. If or
fixed scan execution type program or the like is executed, the interrupt
program using I49 cannot be executed at the set interrupt cycle intervals.

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10.11 Other Devices

10.11.1 SFC block device (BL)

This device is used for checking if the block designated by the SFC program is valid.
For details on the use of SFC block devices, refer to the QCPU(Q mode)/QnACPU
Programming Manual (SFC).

10.11.2 SFC transition device (TR)

This device is used for checking if a forced transition is designated for a specified
transition condition in a specified SFC program block.
For details regarding the use of SFC transition devices, refer to the QCPU(Q
mode)/QnACPU Programming Manual (SFC).

10.11.3 Network No. designation device (J)

(1) Definition
The network No. designation device is used to designate the network No. in data
link instructions.

(2) Designating network No. designation device

The network No. designation device is designated in the data link instruction as
shown below.

JP.READ Jn S1 S2 S3 D

Network No. designation device

(n: network No.)
Instruction name
Network No. designation instruction

REMARK
For details on data link instructions, refer to the Q Corresponding MELSECNET/H
Network System Reference Manual.

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10.11.4 I/O No. designation device (U)

(1) Definition
I/O No. designation devices are used with instructions dedicated to intelligent
function module to designate I/O numbers.

(2) Designating the I/O No. designation device

I/O No. designation devices are designated with the intelligent function module
instructions as shown below.

GP.READ Un S1 S2 S3 D

I/O No. designation device

(n: I/O No.)
Instruction name
I/O No. designation instruction

REMARK
For details on intelligent function module instructions, refer to the corresponding
manual for the intelligent function module to be used.

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10.11.5 Macro instruction argument device (VD)

(1) Definition
Macro instruction argument devices are used with ladders registered as macros.
When a VD setting is designated for a ladder registered as a macro,
conversion to the designated device is performed when the macro instruction is
executed.

(2) Designating macro instruction argument devices

Specify the devices transferred from sequence programs to macro registration
ladders as macro instruction argument devices among the devices used in the
ladders registered as macro with GX Developer. 1
Designate devices that correspond to the macro argument devices used in the
macro registration ladders in ascending order, when using macro instructions in a
sequence program.
Sequence program Ladder registered as a macro (registration name: MAX)

M.MAX D0 D1 R0 > VD0 VD1 MOV VD0 VD2

Transfer to VD2
Transfer to VD1
Transfer to VD0

<= VD0 VD1 MOV VD1 VD2

Name of ladder registered as a macro

Actual sequence program executed at CPU

> D0 D1 MOV D0 R0

<= D0 D1 MOV D1 R0

REMARK
1) 1 : With the macro instruction argument device, VD0 to VD9 can be used in one
ladder registered as a macro instruction.
2) The GX Developer read mode provides an option to view a program in macro
instruction format.(Choose "View" - "Macro Instruction format display" to view
macro instructions.)

Change of macro instruction display

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10.12 Constants

10.12.1 Decimal constants (K)

(1) Definition
Decimal constants are devices which designate decimal data in sequence
programs.
They are designated as "K "settings (e.g. K1234), and are stored in the High
Performance model QCPU in binary (BIN) code.
See Section 4.8.1 for details on binary code.

(2) Designation range

The designation ranges for decimal constants are as follows:
• For word data (16 bits)............K-32768 to K32767
• For 2-word data (32 bits) ........K-2147483648 to K2147483647

10.12.2 Hexadecimal constants (H)

(1) Definition
Hexadecimal constants are devices which designate hexadecimal or BCD data in
sequence programs.
(For BCD data designations, 0 to 9 digit designations are used.)
Hexadecimal constants are designated as "H " settings (e.g. H1234).
See Section 4.8.3 for details on hexadecimal code.

(2) Designation range

The setting ranges for hexadecimal constants are as follows:
• For word data (16 bits)........... H0 to HFFFF (H0 to H9999 for BCD)
• For 2-word data (32 bits) ....... H0 to HFFFFFFFF (H0 to H99999999 for BCD)

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10.12.3 Real numbers (E)

(1) Definition
Real numbers are devices which designate real numbers in the sequence
program.
Real numbers are designated as "E "settings (e.g. E1.234).
X1
EMOVP E1.234 D0

See Section 4.8.4 for details on real numbers.

(2) Designation range

128 -126 -126
The setting range for real numbers is -1.0 2 to -1.0x2 , 0 and 1.0 2 to
128
1.0 2 .

(3) Designation method

Real numbers can be designated in sequence programs by a "normal
expression" or an "exponential expression".
• Normal expression............ The specified value is designated as it is.
For example, 10.2345 becomes E10.2345.
• Exponential expression..... The specified value is multiplied by a
n
" 10 "exponent.
For example, 1234 becomes E1.234 + 3. 1

REMARK
n 3
1:The "+3" in the above example represents a 10 value (10 ).

10.12.4 Character string ( " " )

(1) Definition
Character string constants are devices used to designate character strings in
sequence programs.
They are designated by quotation marks (e.g. "ABCD1234").

(2) Usable characters

All ASCII code characters can be used in character strings.
The QCPU is sensitive to uppercase and lowercase characters.

(3) Number of designated characters

Character strings extend from the designated character to the NUL code (00H).
You can use up to 32 characters for a character string in an instruction such as
$MOV.

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10.13 Convenient Uses for Devices

When executing multiple programs in the High Performance model QCPU, local
devices among the internal user devices can be designated to execute each of the
programs in an independent manner.
Moreover, the device initial settings allow the data setting for devices and intelligent
function modules/special function modules without using a program.

10.13.1 Global devices and local devices

A number of programs can be stored and executed in the High Performance model
QCPU.
High Performance model QCPU devices are classified into "global devices" shared by
all the programs being executed and "local devices" used independently by each of the
programs.

(1) Global devices

(a) Global devices can be shared by all the programs being executed in the
High Performance model QCPU. Global device data are stored in the High
Performance model QCPU's device memory, and can be used by all
programs.
High Performance model QCPU

Global devices are shared by all programs being executed.

Program A Device memory

M0 Internal relay
Y12 M0 ON/OFF

M0 ON/OFF data

Program B

M0
Y11

M0 ON/OFF data

(b) When executing multiple programs, the "shared range" for all programs, and
the "independent range" for each program must be designated in advance.
Example: Internal relay
M0 Shared by all programs

Used in program A The "range of use" must be designated for each program.

Used in program B
Used in program C

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(2) Local devices

(a) Local devices are used independently by the programs.
The use of local devices permits programming of multiple "independent
execution" programs without regard to other programs.
Local devices data can be stored in the standard RAM and the memory
card.
High Performance model QCPU

If local devices are designated as M7000 or later, they can be used independently in each
program executing M7000 or later.
Program A Memory card

For program A
M7000
Internal relay
Y12
M7000 ON/OFF
M7000 ON/OFF data

Program B
For program B
M7000 Internal relay
Y11 M7000 ON/OFF

M7000 ON/OFF data

(b) Five device types can be used as local devices: internal relays (M), edge
relays (V), timers (T, ST), counters (C), and data registers (D).

(c) Programs used as local devices exchange the local device file data stored
in the memory card with the data in the device memory of High
Performance model QCPU.
Therefore the scan time is extended by this data exchange time.
Program A Program B Program C
Sequence program

Restored Saved Restored Saved Restored

Local device Local device Local device
For For For
program A program A program A
For For For
program B program B program B
For For For
program C program C program C

POINT
The local device may not be designated with some instructions.
Refer to the allowable device in the programming manual of each instruction for
details.

REMARK
Refer to Section 10.2 for the concept of the number of words of the devices used as
local devices.

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(d) Local device designation

1) In order to use the above devices as local devices, the usable local
device range must be designated at the "Device" tab screen in the
“(PLC) Parameter" dialog box.
Note that the range designated for local devices applies to all
programs, and cannot be changed for individual programs.
For example, if the local device range is designated as M0 to M100,
this range will be used for local devices in all programs.
Program A Program B Program C
M0
This range becomes
Local device Local device Local device the local device range
for all programs.
M100

2) When local device settings are designated, the drive and file name
where the local device data is to be stored must be designated at the
"PLC file" tab screen in the “(PLC) Parameter" dialog box.
3) To write data from the GX Developer onto the High Performance model
QCPU, specify whether to use a local device at the "PLC file" tab
screen in the “(PLC) Parameter" dialog box. If a local device is not
specified, the local devices used for previously-executed programs are
selected. This does not require replacing local devices in a memory
card with the device memory of the High Performance model QCPU. If
local devices are not used for Program B while executing Programs A,
B, and C, the local devices are used as shown below.
Used local device of program A
Program A Program B Program C Program A Program B
Sequence program

Restored Saved Restored Saved Restored

Local device Local device Local device
For For For
program A program A program A
For For For
program B program B program B
For For For
program C program C program C

POINT
Unless designated as "local devices", all devices are global devices.

(e) Using local devices used by the file where a sub-routine program is stored
It is possible to use local devices that are used by the file where a sub-
routine program is stored when executing a sub-routine program.
Whether or not such local devices are used is set by special relay "SM776"
ON/OFF setting.

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1) Switching over local devices by setting ON/OFF for a special relay

(SM776)
SM776
Executes calculation by the local devices that are used by the file
OFF
where the sub-routine program was called
Executes calculation by the local devices that are used by the file
ON
where the sub-routine program is stored.

[Operation at "SM776 : OFF"]

File name: DEF
File name: ABC (Standby program)

X0 Execution of the
CALL P100 P100
sub-routine program
X2
INCP D0 Sub-routine
program

RET
END

Read/write of the
Local devices used by local devices Local devices used by
the file name: ABC the file name: DEF

[Operation at "SM776 : ON"]

File name: DEF
File name: ABC (Standby program)

X0
CALL P100 Execution of the P100
sub-routine program
X2
INCP D0 Sub-routine
Read/write of the program
local devices
RET
END

Local devices used by Local devices used by

the file name: ABC the file name: DEF

2) Cautions
• If SM776 is ON, the local device data is read when the sub-routine
program is called and the local device data is saved after the execution of
the RET instruction. Accordingly, scan time is elongated by the time as
when a sub-routine program is executed once with the setting of "SM776:
ON". (See Section 10.13.1)
• ON/OFF setting of SM776 is enabled in CPU modules.
Setting in file units is not enabled.
• If the ON/OFF setting of SM776 is changed while a sequence program is
executed, the control is made according to the information after change.

REMARK
For details on SM776, see Appendix 1.

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(f) Using local devices when executing an interrupt/fixed scan execution type
program
It is possible to use local devices in the file where an interrupt/fixed scan
execution type program is stored when executing an interrupt/fixed scan
execution type program.
The local devices can be set available/unavailable by special relay "SM777"
ON/OFF setting.
1) Switching over local devices by setting ON/OFF for a special relay
(SM777)
SM777
Executes operation with the local devices in the file which was
OFF executed before the execution of the interrupt/fixed scan execution
type program.
Executes operation with the local devices in the file where the
ON
interrupt/fixed scan execution type program is stored.

[Operation at "SM777 : OFF"]

File name: DEF
File name: ABC (Standby program)

X0
DECP D1 I0
Occurrence
X2
of interrupt INCP D0 Execution of the
Interrupt
interrupt program
program

IRET
END

Read/write of the
local devices
Local devices used by Local devices used by
the file name: ABC the file name: DEF

[Operation at "SM777 : ON"]

File name: DEF
File name: ABC (Standby program)

X0
DECP D1 I0
Occurrence
X2
of interrupt INCP D0 Execution of the
Interrupt
interrupt program
program

IRET
END

Read/write of the
local devices
Local devices used by Local devices used by
the file name: ABC the file name: DEF

REMARK
For details on SM777, see Appendix 1.

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2) Cautions
• If SM777 is ON, the local device data is read before the
interrupt/fixed scan execution type program is executed and the local
device data is saved after the execution of the IRET instruction.
Accordingly, scan time increases when an interrupt/fixed scan
execution type program is executed once with the setting of "SM777:
ON". (See Section 10.13.1)
• ON/OFF setting of SM777 is enabled in CPU module units.
Setting in file unit is not enabled.
• If the ON/OFF setting of SM777 is changed while a sequence
program is executed, the control is made according to the information
after change.

(g) Clearing the Local Device Data

The local device data is cleared in the following cases where:
1) The PLC is powered on or the CPU module is reset.
2) The CPU module enters into the RUN status from the STOP status.

The local device data cannot be cleared by operating from the GX Developer.
To clear the local device data, follow the above-listed steps 1) and 2).

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10.13.2 Device initial values

(1) Definition
(a) Using device initial value registers, the data used for a program in device or
intelligent function module buffer memories without using a data setting
program.

The use of device initial values provides a shortcut to specify device data in a
program without using a device data setting program (initial program).

[Data setting by initial processing program]

SM402 Power supply ON/
MOV H100 D0 STOP/RESET
to RUN
Device memory
MOV H2020 D1

Device initial At power on, reset or STOP RUN

Device memory
value

(b) In order to use the device initial values, the device initial data must be
created with GX Developer in advance, and this data must be stored as a
device initial value file in the High Performance model QCPU's program
memory, standard RAM or memory card.
At power ON, or on switching from STOP to RUN, the High Performance
model QCPU writes the data from the device initial value file to the specified
device or intelligent function module buffer memory.
High Performance model QCPU

Program memory, Standard ROM,

GX Developer Memory card
"Device initial Device initial value writing Device initial value writing Designated
value range"
Device initial (At power on, reset device
setting
value file or STOP RUN)

"Device initial
Intelligent
value data"
function
setting
module

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(c) Device initial values can be used by the following devices:

1) Timer present value (T) 8) File register (R0 to R32767)
2) Retentive timer present value (ST) 9) File register (ZR0 to ZR1042431)
3) Counter present value (C) 10) Intelligent function module device
4) Data register (D) (U \G )
5) Special register (SD) 11) Link direct device (J \W ,
6) Link register (W) J \SW )
7) Link special register (SW)

(2) Procedure for using device initial values

(a) Designate the device initial value range settings in the device mode, in the
"Device initial value setting" screen.

(b) Designate the device initial value data settings in the "device mode" screen.
[Device initialization range setting screen] [Device mode screen]

(c) At the "PLC file" tab screen in the “(PLC) Parameter" dialog box, designate
the name of the file where the device initial value data is to be stored.
[PLC file screen]

(d) Write the device initial value data and parameter settings to the High
Performance model QCPU.

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MELSEC-Q

(3) Precautions for the use of device initial values

(a) In cases where both device initial value data and latch range data are
overlapped, the device initial value data takes priority.
Therefore, the latch range data is rewritten by device initial value data at
power ON.

(b) Device initial values cannot be used in areas where no setting is made for
switching from STOP to RUN (for data that is changed by a program at
power ON). Create a program to specify a device by using the MOV
instruction in the main routine program. Use the TO instruction to write data
to the buffer memory of the intelligent function module.

REMARK
For details on the setting procedures for the "device initial value range", "device
initial value data" items, and for writing the device initial values to the High
Performance model QCPU, refer to the GX Developer Operating Manual.

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11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME
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11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME

This chapter describes how to estimate the length of High Performance model QCPU
11
processing time.

11.1 Reading High Performance model QCPU's Scan Time

The length of scan time is the total of the following times:

• I/O refresh time
• Instruction execution time
• END processing time

(1) I/O refresh time

(a) I/O refresh time is the total time required for refreshing I/O data of the
following modules:
• Input module
• Output module
• Intelligent function module (special function module)
(b) I/O refresh time is given in the formula:
(I/O refresh time) = (Number of inputs point/16) N1 + (Number of outputs point
/16) N2

(c) The table below shows N1 and N2.

N1 N2
CPU type Q5 B Q5 B
Q3 B QA1S B Q3 B QA1S B
/Q6 B /Q6 B
Q02CPU 2.2 s 2.9 s 4.3 s 1.3 s 2.1 s 3.5 s
Q02HCPU
Q06HCPU
1.7 s 2.4 s 3.7 s 1.3 s 2.1 s 3.5 s
Q12HCPU
Q25HCPU

(2) Instruction execution time

(a) Instruction execution time is the total processing time required to execute an
instruction in a program on the High Performance model QCPU.
For details on the execution time of each instruction, see the QCPU (Q
Mode)/QnACPU Programming Manual (Common Instructions).
(b) Overhead time is required for an interrupt program/fixed scan execution
type program. Add overhead time to execution time.

(3) END processing time

(a) END processing time is the High Performance model QCPU processing
time common to the above-listed items (1) and (2).

(b) The table below shows the length of END processing time.
CPU Type END Processing Time
Q02CPU 0.38 ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.15 ms

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 11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME
MELSEC-Q

11.2 Factors Responsible for Extended Scan Time

11 The following functions increase the length of scan time. When using any of the
following functions, add a value of extended time to values obtained from Section 11.1.
• MELSECNET/H refresh • Local devices
• CC-Link automatic refresh • Execution of multiple programs
• Sampling trace • Installation/removal of a memory card
• GX Developer monitoring • File register with the same filename as a program.

(1) MELSECNET/H refresh

MELSECNET/H refresh requires additional processing time to refresh data
between the High Performance model QCPU and the MELSECNET/H network
module. For details on MELSECNET/H refresh time, see Q Corresponding
MELSECNET/H Network System Reference Manual.

(2) CC-Link automatic refresh

Refresh time between the High Performance model QCPU and CC-Link
master/local module.
(a) When module is QJ61BT11N
Refer to the following manual for CC-Link automatic refresh processing
time.
• QJ61BT11N CC-Link System Master/Local Module User's Manual
(Details)
(b) When module is QJ61BT11
Refer to the following manual for CC-Link automatic refresh processing
time.
• QJ61BT11 CC-Link System Master/Local Module User's Manual (Details)

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11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME
MELSEC-Q

(3) Sampling trace time

Sampling trace requires additional processing time. When sampling trace data is
specified to execute the sampling trace function, add the sampling trace time to
the total processing time.
The table below shows the length of processing time required when sampling
trace data is specified to assign 50 internal relay points for bit devices and 50
data register points for word deices.
CPU Type Processing Time
Q02CPU 0.24 ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.12 ms

(4) GX Developer Monitoring

GX Developer monitoring requires additional processing time. Add the GX
Developer monitoring time to the total processing time.

(a) The table below shows the processing time required when 64 data register
points are assigned by the registered monitor.
CPU Type Processing Time
Q02CPU 0.10 ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.06 ms

(b) The table below shows the processing time required when monitoring
conditions are specified.
Processing Time
CPU Type When steps are When devices
in match are in match
Q02CPU 0.05 ms 0.01 ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.03 ms 0.01 ms

(5) Local devices

Local devices require additional processing time. Add the processing time of local
devices to the total processing time.
CPU Type Processing Time
Q02CPU 0.94+0.40 n ms
Standard RAM
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.39+0.17 n ms
Q02CPU 0.94+1.38 n ms
SRAM Card
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.39+0.95 n ms
Conditions Local devices: 1k points, n: number of program files

(6) Execution of multiple programs

Execution of multiple programs requires overhead time of each program being
executed. Add overhead time to the total processing time.
CPU Type Processing Time
Q02CPU 0.08 n ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.03 n ms
Conditions n: Number of program files

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11 HIGH PERFORMANCE MODEL QCPU PROCESSING TIME
MELSEC-Q

(7) Installation/Removal of a memory card

Installation/removal of a memory card requires additional processing time. If a
memory card is installed or removed, add 1-scan time to the total processing
time.
Processing Time
CPU Type Memory Card Memory Card
Inserted Removed
Q02CPU 0.16 ms 0.10 ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.08 ms 0.04 ms

(8) File register

File register requires additional processing time. Add the processing time of file
registers to the total processing time.
CPU Type Processing Time
Q02CPU 1.03 ms
Standard RAM
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.41 ms
Q02CPU 0.94+0.2 n ms
SRAM Card
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.40+0.1 n ms
Conditions n: number of program files

11.3 Factors Responsible for Shortened Scan Time

The length of scan time can be shorted by making changes to the PLC Parameter
setting as follows:
• A series CPU compatibility
• Arithmetic operation of floating-point

(1) A series CPU compatibility

When "Use special relay/special register after SM1000/SD1000" is set in the PLC
system settings of the PLC parameter, the scan time can be reduced by the
value in the following table by setting to "Do not use special relay/special register
after SM1000/SD1000."
In this case, the A-series compatible special relays/special registers
SM1000/SD1000 to SM1299/SD1999 must be replaced with the Q-series
dedicated special relays/special registers SM0/SD0 to SM999/SD999.
CPU Type Processing Time
Q02CPU 0.07 ms
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU 0.03 ms

(2) Arithmetic operation of floating-points

By default, the "Perform internal arithmetic operations in double precision" check
box in the PLC System sheet of the PLC Parameter dialog box is on. Turning off
the check box will increase the processing speed of executing an instruction that
includes a floating-point.
For details on floating-point arithmetic operation, see the QCPU (Q
Mode)/QnACPU Programming Manual (Common Instructions).

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE

MODEL QCPU

This chapter describes the procedure for writing programs created at the GX
Developer to the High Performance model QCPU.

12.1 Writing Procedure for 1 Program 12

This section describes the procedure for writing one program to the High Performance
model QCPU and executing it.

12.1.1 Items to consider when creating one program

In order to create a program, the program size, number of device points used, and the
program file name, etc., must be set in advance.

(1) Program size considerations

Check that CPU module's program capacity is adequate for storing the program
and parameter data.
The program capacities of the CPUs are shown below:
• Q02CPU : 28 k steps
• Q02HCPU : 28 k steps
• Q06HCPU : 60 k steps
• Q12HCPU : 124 k steps
• Q25HCPU : 252 k steps
If the CPU module capacity is only adequate for the program, the parameter data
should be stored in the standard ROM/memory card.

(2) Designating a program file name

The file name of the program to be stored in the High Performance model QCPU
must be designated.
This file name is used when writing the program and parameters from GX
Developer to the High Performance model QCPU, and when designating the
program to be executed in the High Performance model QCPU.
See Chapter 6 for details regarding file names.

(3) Designating devices

The number of devices required for the program must be determined.
See Chapter 10 for details regarding devices which can be used in the High
Performance model QCPU.

(4) Device initial value setting

Designate whether or not the device initial value settings are to be used in the
High Performance model QCPU devices and intelligent function modules.
See Section 10.13.2 for details regarding device initial values.

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 12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

12.1.2 Procedure for writing programs to the High Performance model QCPU

The procedure for writing programs and parameters created with GX Developer to the
High Performance model QCPU standard ROM is shown below.
In order to write programs and parameters to the High Performance model QCPU
standard ROM, the valid parameters settings must be designated by the High
12 Performance model QCPU DIP switches (SW2, SW3), and the boot settings must be
designated in the PLC parameter mode.
For details regarding High Performance model QCPU DIP switches, refer to the High
Performance model QCPU(Q mode) User's Manual(Hardware Design, Maintenance
and Inspection).

When writing programs and parameters to the High Performance model QCPU
program memory, the steps indicated by asterisks ( ) below are not required.

Procedural steps shown in boxes are performed at the GX Developer, and those
shown in boxes are performed in the High Performance model QCPU.

Start

Start the GX Developer Refer to the GX Developer Operating Manual.

Mode selection screen

is displayed.

Change the
NO
number of device See Section 10.1.2.
points?

YES

Change the number of device

points at the device setting
item in the PLC parameter.

Create the program which is

to be executed in the CPU
module.

1)

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

1)

NO Use the device

See Section 10.13.2.
initial value?

YES

Right-click on the device

memory and select "Add" to
specify device initial value data.

Right-click on a device initial

value and select "Add" to spe-
cify a device initial value range.

Select the device memory to be

used in the device memory
registration setting of the device
initial value, and click on "Use
device memory".

In the PLC file setting in the

PLC parameter, designate the
name of file to be used for the
designated device initial values.

In the boot file setting item in

the PLC parameter, designate
the file name of parameter and
program to be read from the
standard ROM.

In the program settings in the PLC

parameter, designate the name
of the program to be executed,
and its execution condition.

Set the High Performance ERR. LED switches ON.

model QCPU RUN/STOP key
to the STOP position, then
switch the power ON.

Connect the GX Developer to

the High Performance model
QCPU.

2)

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

2)

In PLC memory format in the

GX Developer online mode,
select "Program memory/device
memory" and press "Execute"
(format the program memory).

In Write to PLC(Flash ROM) in the

GX Developer online mode, select
"Standard ROM" and write the
parameter data and crated program.

Use the High Performance

model QCPU RESET/L.CLR
switch to execute a reset.

High Performance model QCPU If a boot file setting is not made

"BOOT" LED switches ON. (or when writing parameters or
programs onto the program memory),
the "BOOT" LED does not light up.
End

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

12.2 Procedure for Multiple Programs

This section describes the procedure for writing multiple programs split up according to
function, process, designer to the High Performance model QCPU and executing
them.

12.2.1 Items to consider when creating multiple programs

To create multiple programs, it is necessary to set in advance the size of each

program, the device used, and the program file name, etc.

(1) Program size considerations

Set the program capacity within the range of the High Performance model QCPU
program capacity.
The program capacities of the High Performance model QCPU's are shown
below:
• Q02CPU : 28 k steps
• Q02HCPU : 28 k steps
• Q06HCPU : 60 k steps
• Q12HCPU : 124 k steps
• Q25HCPU : 252 k steps
Decide whether the parameters are to be stored in the program memory, the
standard ROM, or the memory card.
If they are to be stored in the program memory/the standard ROM, the area
available for the program will be the capacity shown above, minus the parameter
data size.

(2) Designating a program file name

Designate the file name of the program to be stored in the High Performance
model QCPU.
This file name is used when writing the program and parameters from GX
Developer to the High Performance model QCPU, and when designating the
program to be executed in the High Performance model QCPU.
See Chapter 6 for details regarding file names.

(3) Designating the program execution conditions

In order to execute multiple programs in the High Performance model QCPU,
execution conditions must be designated for each program.
Execution is impossible for programs without file name and execution condition
settings.
See Section 4.2 for details regarding execution conditions.

(4) Designating devices

(a) Designate the number of device points used in each program, and the
number of device points which are shared by all programs.
See Chapter 10 for details regarding devices which can be used in the High
Performance model QCPU.
(b) Designate whether or not the internal relays, edge relays, timers, counters,
and data registers of each program are to be designated as local devices.
See Section 10.13.1 for details regarding local devices.
(c) When creating sub-routine programs, designate whether or not common
pointers are to be used.
See Section 10.9.2 for details regarding common pointers.

(5) Device initial value setting

Designate whether or not the device initial value settings are to be used for the
High Performance model QCPU devices and intelligent function modules.
See Section 10.13.2 for details regarding device initial values.

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

12.2.2 Procedure for writing programs to the High Performance model QCPU

The procedure for writing programs and parameters created by GX Developer to the
memory card mounted in the High Performance model QCPU memory card interface
is shown below.
In order to write programs and parameters to the High Performance model QCPU
memory card, the memory card must be mounted, the valid parameters drive settings
must be designated by the High Performance model QCPU DIP switches (SW 2, SW
3), and the boot settings for the PLC parameters must be designated by GX
Developer.
For details regarding High Performance model QCPU DIP switches, refer to the High
Performance model QCPU (Q mode) User's Manual (Hardware Design, Maintenance
and Inspection).

When writing programs and parameters to the High Performance model QCPU
program memory, the steps indicated by asterisks ( ) below are not required.

Procedural steps shown in boxes are performed at GX Developer side, and those
shown in boxes are performed at the High Performance model QCPU side.

Start

Start the GX Developer Refer to the GX Developer Operating Manual.

Mode selection screen

is displayed.

Change the
NO
number of device See Section 10.1.2.
points?

YES

Change the number of device

points at the device setting
item in the PLC parameter.

Create the program which is

to be executed in the High
Performance model QCPU
module.

1)

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

1)

NO Use the device

See Section 10.13.2.
initial value?

YES

Right-click on the device

memory and select "Add" to
specify device initial value data.

Right-click on a device initial

value and select "Add" to specify
a device initial value range.

Select the device memory to

be used in the device memory
registration setting of the device
initial value, and click on "Use
device memory".

In the PLC file setting in the

PLC parameter, designate the
name of file to be used for the
designated device initial values.

NO Designate local
See Section 10.13.1.
devices?

YES

In the device setting item in the

PLC parameter, designate the
name of the local device range.

In the PLC file setting item in

the PLC parameter, designate
the name of the local device file.

NO Use the common

See Section 10.9.2.
pointers?

YES

In the PLC system setting item

in the PLC parameter, desig-
nate the first pointer No.

2)

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12 PROCEDURE FOR WRITING PROGRAMS TO HIGH PERFORMANCE
MODEL QCPU
MELSEC-Q

2)

In the boot file setting item in

the PLC parameter, designate
the file name of parameter and
program to be read from the
memory card.

In the program settings in the

PLC parameter, designate the
name of the program to be exe-
cuted, and its execution condition.

Set the CPU module's RUN/ ERR. LED switches ON.

STOP switch to the STOP
position, then switch the power
ON.

Connect the GX Developer to

the CPU module.

In the GX Developer online

mode, select the program
memory, and use the PLC
memory batch operation to
format the program memory.

In the GX Developer online

mode, select the memory card
(RAM), then use the PLC
memory batch operation to
format the memory card.

In the GX Developer online When the device initial value is

mode, select the memory card designated, write the device initial
(RAM), and write the parameter value in the designated memory during
data and created program. the PLC file setting in the PLC parameter.

Use the CPU module's RESET/

L.CLR switch toexecute a reset.

CPU module's "BOOT" If a boot file setting is not made (or when
LED switches ON. writing parameters or programs onto the
program memory), the "BOOT" LED does
not light up.
End

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13 OUTLINE OF MULTIPLE CPU SYSTEM
MELSEC-Q

13 OUTLINE OF MULTIPLE CPU SYSTEM

13.1 Features

(1) Multi control

(a) Since each system is not configured on one High Performance model
QCPU but on the High Performance QCPU, Motion CPU, and PC CPU
module according to the system, the development efficiency and ease of
maintenance of the system can be enhanced.
(b) Each CPU module in the multiple CPU system controls the I/O module and
intelligent function module of the base unit slot-by-slot.
GX Developer groups the I/O modules and intelligent function modules
13
controlled by each CPU module in the multiple CPU system.

(2) Enables system configuration through load dispersion

(a) By dispersing the high-load processing performed on a single High
Performance model QCPU between several High Performance model
QCPUs, it is possible to reduce the overall system scan time.
Data processing (low speed) (Control at 1 ms or higher) (Control at several to several tens of ms)
Mechanical control Mechanical control
Data processing CPU module
(high speed) CPU module

Everything controlled on a single CPU Mechanical control made even father by load dispersion in
accordance with control tact

(b) It is possible to increase the amount of memory used throughout the entire
system by spreading the memory used between several High Performance
model QCPUs.

Expansion possible in CPU modules

Vacant
memory
10%

Used memory
90% One CPU module added
• Program memory expanded
• Device memory expanded

(3) Enables system configuration through function dispersion

By dispersing the functions so that control for production line A and control for
production line B is performed on different High Performance model QCPUs, it is
possible to debug each function individually.

13 - 1 13 - 1
 13 OUTLINE OF MULTIPLE CPU SYSTEM
MELSEC-Q

(4) Communication can be made between CPU modules in the

multiple CPU system
The following data transfer can be made between CPU modules in the multiple
CPU system.

(a) Automatic refresh setting at GX Developer enables the data transfer

between CPU modules.

(b) The High Performance model QCPU can use the FROM/S.TO instruction to
read data from other CPU as necessary.

(c) Instructions dedicated to Motion can be used to issue control commands

13 from the High Performance model QCPU to the Motion CPU. 1

(d) The High Performance model QCPU can issue instructions dedicated to
communication between multiple CPUs, to read or write device data from/to
the Motion CPU.
The High Performance model QCPU can issue events to the PC CPU
module. 2

REMARK
1: Refer to the manual of the Motion CPU for instructions dedicated to Motion.
2: Refer to the manuals of Motion CPU and PC CPU module for instructions
dedicated to the communication between multiple CPUs.

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13 OUTLINE OF MULTIPLE CPU SYSTEM
MELSEC-Q

13.2 Outline of Multiple CPU System

(1) What is a multiple CPU system?

(a) A multiple CPU system is a system in which main base units are mounted
on several (maximum four) High Performance model QCPUs and motion
CPU in order to control the I/O modules and intelligent function modules.
PLC CPU Motion CPU
PC CPU module

PLC CPU

Motion CPU

PC CPU module

The allowable CPU modules are shown in the table below.

PLC CPU Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU,

Motion CPU Q172CPU, Q173CPU,Q172CPUN,Q173CPUN
PC CPU module CONTEC Co., Ltd.
Choose the CPU modules suitable to the system size and application to configure
the system.
It is necessary to set (control CPU setup) which High Performance model
QCPU and Motion CPUs are to control which I/O modules and intelligent
function modules with a multiple CPU system.
CPU 0 1 2 3 4 5 6 7
CPU module

CPU module

Output module

Output module
function module

function module
Input module

Input module

Input module
Power supply

Intelligent

Intelligent

1 2 1 1 1 1 2 2 2 Setup of the controlling

QCPU 1

Control performed with

the QCPU1 sequence program

Control performed with the QCPU2 sequence program

(b) The CPU module that controls the I/O modules and intelligent function
modules is known as the "Control CPU".
The I/O modules and intelligent function modules controlled by the control
PLC are known "controled modules".
Other modules not controlled by the control CPU are known as "non-
controlled modules".

REMARK
1: For further information on PC CPU module, consult CONTEC Co.,Ltd.
Tel:+81-6-6472-7130
2: Indicates the grouping configuration on the GX Developer.
CPU module1 indicates the "CPU No.1," and "1" on the I/O module and
intelligent function module indicates that their control CPU is the CPU No.1.

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13 OUTLINE OF MULTIPLE CPU SYSTEM
MELSEC-Q

(2) Multiple CPU system setup

It is necessary to set up the "Number of mounted CPU modules" and the "Control
CPU" with PLC parameters in all CPU modules onto which main base units are
mounted in order to control a multiple CPU system (see Chapter 9.)

(3) Multiple CPU system access range

(a) It is possible for a multiple CPU system's control CPU to perform the I/O
refresh procedure on control modules and write in the buffer memory of
intelligent function modules in the same way as a single CPU system.
(b) It is possible to access non-control modules in the following ways.
• Refresh the input for I/O modules and intelligent function modules (the
PLC parameter multiple CPU setup is necessary.)
• Read the intelligent function module's buffer memory.
• Download the output data for the output module, the I/O combination
module and the intelligent function modules. (the PLC parameter multiple
CPU setup is necessary.)
However, it is not possible to access non-control modules in the following
ways.
• Outputting data to the output module and intelligent function module.
• Writing data into the intelligent function module's buffer memory.
CPU 0 1 2 3 4 5 6 7
Input module

Input module

Output module

Input module

Output module
function module

function module
Power supply

CPU module

CPU module

Intelligent

Intelligent

1 2 1 1 1 1 2 2 2

Possible to read with the

CPU module2

Possible to read with the CPU module1

(4) GX Developer access range

(a) It is possible to write parameter programs and perform monitoring and tests
in High Performance model QCPUs connected to personal computers,
To access High Performance model QCPUs that are not connected to
personal computers, specify the High Performance model QCPU to be
accessed (connection destination specification) with the GX Developer.
(b) It is possible for the GX Developer to access the High Performance model
QCPU regardless of the control modules and non-control modules.
By connecting a single High Performance model QCPU to a personal
computer, it is possible to perform monitoring and tests on all modules
being controlled by the multiple PLC system's High Performance model
QCPU in the same way as with a single CPU system.
Other station High Performance model QCPUs on the same
MELSECNET/H, Ethernet or other network can also be accessed.
(c) It is possible for all High Performance model QCPUs on a multiple CPU
system to be accessed from a GX Developer that is connected to other
stations on the same network.

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13 OUTLINE OF MULTIPLE CPU SYSTEM
MELSEC-Q

13.3 Differences with Single CPU System

The differences between single CPU system and multiple CPU system are explained
below.

(1) Function versions (see Sections 14.2.1 to 14.2.5)

(a) Function version B High Performance model QCPUs are supported by
multiple CPU system. Function version A High Performance model QCPUs
cannot be used on a multiple CPU system.
(b) All I/O modules can be used on a multiple CPU system.
(c) Use function version B intelligent function modules on the multiple CPU
system.
Function version A intelligent function modules can be used if set up as
control CPU by the CPU No.1.

(2) Mounting position of CPU module (see Section 14.2.1)

High Performance model QCPUs can be mounted on the CPU slot from the
right-hand side of the power unit sequentially. The motion CPUs are mounted
together on the slot to the right of the High Performance model QCPUs.
The PC CPU module is installed on the extreme right side in the multiple CPU
system.
The total number of High Performance model QCPU, Motion CPU and PC CPU
module must be up to four.

(3) Multiple CPU system parameters (see Section 14.2.6)

In comparison with independent CPU systems, there are more PLC parameter
items on a multiple CPU system.
Of the PC parameters that have been added to the multiple CPU system, the
parameters that must be set are listed below.
• Number of CPUs: Sets the number of mounted High Performance model
QCPUs, motion CPUs and PC CPU module that are in use.
• Control CPU settings: Sets which High Performance model QCPU, Motion
CPU and PC CPU module controls while modules.

(4) Sameness check (see Section 14.2.6)

A setting exists to indicate that the QCPU / motion CPU / PC CPU module used
are the same in the number of CPUs, control CPU settings and other multiple
CPU system parameters.
The High Performance model QCPU / Motion CPU / PC CPU module run a
check (sameness check) to ascertain that the multiple CPU system parameters
are the same when the PLC power is set at ON, the High Performance model
QCPU is reset, and the STOP status is changed to the RUN status.
The multiple PLC system will not start up if an error is triggered during the
sameness check.

(5) Concept of the I/O number (see Section 15.1)

The right side of the installed CPU module is I/O number "00H" in the multiple
CPU system. For this reason, the position of I/O number "00H" varies according
to the number of installed CPUs. However, because each PC CPU module
occupies two slots (one slot for CPU and one empty slot), the I/O number
deviates by the number of points set to the empty slot. (Default: empty 16 points)

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13 OUTLINE OF MULTIPLE CPU SYSTEM
MELSEC-Q

(6) Interactive transmission with non-control CPUs (see Chapter 17)

(a) It is possible to control I/O modules and intelligent function modules
controlled by the host CPU in the same way as on an single CPU system.
(b) It is not possible to output ON.OFF data to modules that are not controlled
by the host CPU or write in the buffer memory of intelligent function
modules.
It is possible to read I/O data from non-control modules with PLC parameter
settings.
It is possible to confirm the status of modules controlled by other CPUs, the
control status of other CPUs, and control the host CPU.

(7) Interactive transmission between each CPU modules on a multiple

CPU system (see Chapter 16)
It is possible to perform the following interactive transmission between each CPU
modules with a multiple CPU system.
(a) Automatically refreshing the device data between each CPU modules with
multiple CPU system parameter settings.
(b) Data transfer between other High Performance model QCPU and PC CPU
module via CPU shared memory using multiple CPU instructions (FROM,
S.TO instructions)
(c) Reading CPU shared memory of Motion CPU from High Performance
model QCPU with multiple CPU instructions (FROM instruction).
(d) Control instruction from the High Performance model QCPU to the Motion
CPU with Motion dedicated CPU instructions.
(e) Writing and reading of the device data from the High Performance model
QCPU to the Motion CPU with communication dedicated instructions
between multiple CPUs.
(f) Event issuance from High Performance model QCPU to PC CPU module
using instructions dedicated to multiple CPU communication

(8) Processing during resets and errors (see Sections 14.2.7 and
14.2.8)
The processing performed when resets and errors occur are different for the
multiple CPU system's CPU No.1 and the CPU No.2 to CPU No.4.
(a) High Performance model QCPU for CPU No.1 can be reset with a multiple
CPU system.
CPU modules for CPU No.2 to No.4 and Motion CPU cannot be reset.
(b) Multiple CPU system operations will be suspended when a stop error
occurs with the CPU No.1.
It is possible to select whether to suspend or continue with multiple CPU
system operations when a stop error occurs with CPU Nos. 2 to 4 and
Motion CPU.

(9) Clock function

An intelligent function module with which the error code and time of occurrence is
stored in the buffer memory when an error is triggered is available (time data
read from the High Performance model QCPU.)
The CPU No.1 time data will be stored as the time that the error occurred
regardless of whether the module concerned is a control CPU or a non-control
CPU.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM

This chapter explains the system configuration of Multiple CPU System, and the
precautions for Multiple CPU System configuration.

14.1 System Configuration

This section explains the equipment configuration of Multiple CPU System, the
connections with peripheral device, and an output of the system's configuration.
(1) Equipment configuration of Multiple CPU System
(a) When main base unit (Q3 B) is used

MITSUBISHI

MITSUBISHI
LITHIUM BATTERY

Memory card 1 High Performance model QCPU

(Q2MEM-1MBS,Q2MEM-2MBS, Battery
(Q02CPU,Q02HCPU,Q06HCPU,
Q2MEM-2MBF,Q2MEM-4MBF, (Q6BAT)
Q12HCPU,Q25HCPU)
Q2MEM-8MBA,Q2MEM-16MBA,
Motion CPU 5
Q2MEM-32MBA)
PC CPU module 3, 5
14
MITSUBISHI
LITHIUM BATTERY

Battery
Battery holder
(Q7BAT)
Q7BAT-SET

Power supply module 6 ,

Main base unit
I/O module , Intelligent function
(Q33B, Q35B,Q38B,Q312B)
module of the Q Series
2
Extension of the AnS Series module Extension of the Q Series module

Q5 B extension base unit

Extension cable
QA1S6 extension base unit (Q52B, Q55B)
(QC05B,QC06B,QC12B,
(QA1S65B,QA1S68B) Q6 B extension base unit
QC30B, QC50B,QC100B)
(Q63B, Q65B,Q68B,Q612B)

Power supply module , Power supply module 4 6,

I/O module , Intelligent function I/O module , Intelligent function
module of the AnS Series module of the Q Series

POINT
1: Only one memory card can be mounted.
Select the memory card SRAM, Flash and ATA in accordance with application and capacity.
When commercial memory cards, the operation is not assured.
2: The additional QA1S65B and QA1S68B base units are used as the AnS Series power supply
module, the I/O module and the special function module.
3: For further information on PC CPU module, consult CONTEC Co., Ltd Tel: +81-6-6472-7130
4: The Q Series power supply module is not required for the Q5 B extension base unit.
5: The motion CPU and PC CPU module do not accept a battery..
6: As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P. The slim type power
supply module (Q61SP) cannot be used.

14 - 1 14 - 1
 14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

(b) When slim type main base unit (Q3 SB) is used

MITSUBISHI

MITSUBISHI
LITHIUM BATTERY

Memory card *1
High Performance model QCPU
(Q2MEM-1MBS,Q2MEM-2MBS, Battery
(Q02CPU,Q02HCPU,Q06HCPU,
Q2MEM-2MBF,Q2MEM-4MBF, (Q6BAT)
Q12HCPU,Q25HCPU)
Q2MEM-8MBA,Q2MEM-16MBA,
Q2MEM-32MBA) Motion CPU *4

MITSUBISHI
LITHIUM BATTERY

Battery
Battery holder
(Q7BAT)
Q7BAT-SET
14

Slim type power supply module, *3

Slim type main base unit
I/O module ,
(Q32SB,Q33SB,Q35SB) *2
Intelligent function module

POINT
1: One memory card is installed.
Select the memory card from the SRAM card, Flash card and ATA card
according to the application and capacity.
When the memory card available on the market is used, operation is not
guaranteed.
2: The slim type main base unit does not have an extension cable connector. The
extension base or GOT cannot be connected.
3: As a power supply module, use the slim type power supply module (Q61SP).
The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply
module.
4: The Motion CPU do not accept a battery.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

(2) Configuration of peripheral devices for High Performance model

QCPU

MITSUBISHI

Memory card 1 High performance model QCPU USB cable 1

(Q2MEM-1MBS,Q2MEM-2MBS, (To be procured yourself)
(Q02CPU,Q02HCPU,Q06HCPU,
Q2MEM-2MBF,Q2MEM-4MBF, Used only for Q02HCPU,Q06HCPU
Q2MEM-8MBA,Q2MEM-16MBA, Q12HCPU,Q25HCPU)
,Q12HCPU and Q25HCPU
Q2MEM-32MBA)

RS-232 cable
(QC30R2)

PC card adapter Personal computer

GX Developer Version 6 or later
(Q2MEM-ADP)
(SW6D5C-GPPW-E)

1: For writing into memory card on GX Developer, and USB cable, refer to the
operating manual of the GX Developer.

POINT
1) Refer to the Motion Controller User’s Manual for connection between the Motion
CPU and peripheral modules.
2) The GX Developer installed in a Personal computer connected to the Motion
CPU is not used to communicate with the High Performance model QCPU.
3) You cannot install GX Developer and Motion CPU software package in a single
PC.
4) Refer to the manual of the PC CPU module for the connection between the PC
CPU module and peripheral modules.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

Main base unit (Q312B)

0 1 2 3 4 5 6 7 8 9 10 11 Slot No.

Power supply module

CPU module 1
CPU module 2
CPU module 3
CPU module 4
00 20 40 60 80 A0 C0 E0 100

Extension cable

OUT
1F 3F 5F 7F 9F BF DF FF 11F

The figure shows the configuration

Extension base unit (Q612B)
1 extension 12 13 14 15 16 17 18 19 20 21 22 23 when 32-I/O modules are mounted
stages to each slot.
Power supply module 120 140 160 180 1A0 1C0 1E0 200 220 240 260 280
OUT
IN

13F 15F 17F 19F 1BF1DF 1FF 21F 23F 25F 27F 29F

Extension base unit (Q68B) Extension base unit (QA1S68B)

2 extension 24 25 26 27 28 29 30 31 5 extension 45 46 47 48 49 50 51 52
stages stages
Power supply module

Power supply module

2A0 2C02E0 300 320 340 360 380 540 560 580 5A0 5C0 5E0 600 620

System
OUT

OUT
configuration
IN

IN
2BF 2DF2FF 31F 33F 35F 37F 39F 55F 57F 59F 5BF 5DF5FF 61F 63F

Extension base unit (Q68B) Extension base unit (QA1S68B)

3 extension 32 33 34 35 36 37 38 39 6 extension 53 54 55 56 57 58 59 60
stages stages
Power supply module

Power supply module

3A0 3C0 3E0 400 420 440 460 480 640 660 680 6A0 6C0 6E0 700 720
OUT

OUT
IN

IN
3BF3DF 3FF 41F 43F 45F 47F 49F 65F 67F 69F 6BF 6DF6FF 71F 73F

Extension base unit (Q65B) Extension base unit (QA1S65B)

4 extension 40 41 42 43 44 7 extension 61 62 63
stages stages
Power supply module

Power supply module

4A0 4C0 4E0 500 520 740 760 780

Prohibit
Prohibit
OUT

OUT
IN

IN

4BF4DF4FF 51F 53F 75F 77F 79F

When module is installed,

an error occurs.
Number of CPU CPU module1: CPU No.1, CPU module 2: CPU No.2, CPU module 3: CPU No.3, CPU module 4: CPU No.4
Maximum number
7 extension stages
of extension stages
Module count setting for
Maximum number the multiple PLC setting 1 2 3 4
of mounted I/O
modules Number of module
64 modules 63 modules 62 modules 61 modules
mounted
Maximum
number of
4096
occupied I/O
points
Main base units Q33B, Q35B, Q38B, Q312B
Extension base
Q52B, Q55B, Q63B, Q65B, Q68B, Q612B, QA1S65B, QA1S68B
units
Extension cables QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
(1) A maximum of 7 extension base units can be used.
(2) Do not use extension cable longer than 13.2 m (43.28 feet).
(3) When using an extension cable, it should not be connected to or allowed to come close to the main circuit (high voltage and large current).
(4) When setting the number of extension stages, set the number in ascending order to avoid setting the same number repeatedly.
(5) If Q5 B / Q6 B and QA1S6 B are to be mounted on the same extension base unit, be sure to connect Q5 B / Q6 B at first and then
Notes QA1S6 B.
Make the setting of the number of levels of an extension base unit, starting with Q5 B / Q6 B in a descending order.
(6) Connect an extension cable between the OUT connector of an extension base unit and the IN connector of another extension base unit.
(7) An error may occur if more than 66 mounted. (number of mounted modules including CPU module 1 (CPU No. 1))
(8) Refer to section 14.2 (1) for mounting Motion CPUs.
(9) For the I/O number of multiple CPU system other than above, see Section 15.1.1.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

14.2 Precautions For Multiple CPU System Configuration

14.2.1 Function versions of High Performance model QCPU, Motion CPUs and PC CPU
module that can be used, and their mounting positions

(1) Function versions

(a) Allowable function versions and version confirmation method
1) To configure a multiple CPU system, use the High Performance model
QCPU and Motion CPU of function version B.
2) To use the PC CPU module, use the following High Performance
model QCPU and Motion CPU.
• High Performance model QCPU: First five digits of the serial No. is
"03051" or later and function
version is B
• Motion CPU: The first digits of the serial No. must be as follows.
Q172CPU ....... "H" or later
Q173CPU ....... "G" or later
3) The function version of the High Performance model QCPU and Motion
CPU can be checked at the following places.
• Ratings nameplate of High Performance model QCPU and Motion
CPU
• Product data list of system monitor of GX Developer
(See Section 2.3 for details.)

(b) Operations with different function versions

Function version A High Performance model QCPUs cannot be used on a
multiple CPU system.
Errors shown in table 14.1 will occur and the multiple CPU system will not
start up if function version A High Performance model QCPUs are used on
a multiple CPU system.
If any of the errors shown in table 14.1 are displayed after executing GX
Developer Version 6 or later PLC diagnosis function, replace the function
version A High Performance model QCPU with a function version B High
Performance model QCPU.
Table 14.1 List of operations with differing function versions
PLC No.1 PLC Nos. 2 to 4 Status of PLC No.1 Status of PLC Nos. 2 to 4
UNIT VERIFY ERROR SP. UNIT LAY ERROR
Function version A Function version A
(Error code: 2000) (Error code: 2125)
UNIT VERIFY ERROR MULTI EXE. ERROR 1
Function version A Function version B
(Error code: 2000) (Error code: 7010)
MULTI EXE. ERROR 1 SP. UNIT LAY ERROR
Function version B Function version A
(Error code: 7010) (Error code: 2125)
Function version B Function version B No error No error
1: The following errors may occur except "MULTI EXE. ERROR" when the PLC is
turned on or the High Performance model QCPU for CPU No.1 is reset.
• CONTROL-BUS ERR. (error code: 1413, 1414)
• MULTIPLE PLC DOWN (error code: 7000, 7002)

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

(2) High Performance model QCPU, Motion CPU and PC CPU module
mounting positions
(a) Up to four modules of High Performance model QCPU can be mounted in
the CPU slots (starting from the slot on the right side of power supply
module closely) and the neighboring slots up to slot 2.
There must be no empty slot between CPU modules.

Mount the Motion CPU or PC CPU module in the following way.

• Mount the Motion CPU on the right side of the High Performance model
QCPU.
• Mount only one PC CPU module at the right end of CPU modules.
(No CPU module can be mounted on the right side of the PC CPU
module.)

Table 14.2 Installation positions of CPU modules

Number of CPUs Mounting positions of CPU modules
CPU 0 1 2
CPU module
Power supply

1 —
module

CPU 0 1 2 CPU 0 1 2 CPU 0 1 2

PC CPU module
CPU module
CPU module

CPU module

Power supply

Motion CPU
Power supply

Power supply

CPU module

1
2
module
module

module

CPU 0 1 2 CPU 0 1 2 CPU 0 1 2

CPU module

CPU module

CPU module

CPU module

CPU module

CPU module
Power supply

Power supply

Power supply
Motion CPU

Motion CPU

Motion CPU
module

module

module

3
CPU 0 1 2 CPU 0 1 2
1
PC CPU module

PC CPU module
Motion CPU
1

Power supply

CPU module
CPU module

CPU module
Power supply

—
module
module

CPU 0 1 2 CPU 0 1 2 CPU 0 1 2

CPU module

CPU module

CPU module

CPU module
Power supply

Power supply

Motion CPU

Motion CPU
CPU module

CPU module

CPU module

CPU module

CPU module
Power supply
Motion CPU

4
module

module

module

1: The PC CPU module occupies two slots.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

Number of CPUs Mounting positions of CPU modules

CPU 0 1 2 CPU 0 1 2 3 CPU 0 1 2 3

Motion CPU

Motion CPU

Motion CPU
CPU module
Power supply

1
PC CPU module
1

CPU module

CPU module
Power supply
CPU module

CPU module

CPU module

PC CPU module
Power supply

Motion CPU
module
module
module
CPU 0 1 2 3

PC CPU module
1
Motion CPU

Motion CPU
CPU module
Power supply
module

1: The PC CPU module occupies two slots.

(b) Motion CPUs are mounted together on the slot to the right of the High
Performance model QCPU.
High Performance model QCPUs cannot be mounted to the right of Motion
CPUs.
Mounting is allowed Mounting is not allowed
CPU 0 1 2 CPU 0 1 2
CPU module

CPU module

CPU module

CPU module
Power supply

Power supply

Motion CPU

Motion CPU
Motion CPU

Motion CPU
module

module

(c) Mount the PC CPU module at the right end in the multiple PLC system.
No CPU module can be mounted on the right side of the PC CPU module.
CPU 0 1 2 3
PC CPU module

Motion CPU
CPU module
Power supply
module

(d) An empty slot is secured for future addition of a CPU module.

The number of CPU module including empty slots are set with the No. of
CPU setting, and the type is set in the "CPU (empty)" setting from the slot
immediately to the right of the number of CPU modules set at the "I/O
Assignment" tab screen in the (PLC) "Parameter" dialog box.
For example, when four CPU modules have been set with the multiple CPU
setting and two High Performance model QCPUs and one Motion CPU
have been mounted, the High Performance model QCPUs are mounted in
the CPU module slot and slot 0, the Motion CPU is mounted in slot 1, and
slot 2 is left empty.
However, the empty slot must be on the right side of CPU modules.
Mounting is allowed Mounting is not allowed
CPU 0 1 2 CPU 0 1 2
Motion CPU

Motion CPU
Power supply

Power supply
CPU module

CPU module

CPU module

CPU module
Empty

Empty
module

module

14 - 7 14 - 7
14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

POINT
To add a High Performance model QCPU or Motion CPU to a system where the
PC CPU module is used, shift the PC CPU module to the right because no CPU
module is allowed on the right side of the PC CPU module.

(2) High Performance model QCPU, Motion CPU and PC CPU module
CPU numbers
(a) CPU numbers are allocated for identifying the High Performance model
QCPUs, Motion CPUs and PC CPU module mounted on the main base unit
in the multiple CPU system. The CPU No.1 is allocated to the CPU slot,
and the CPU No.2, No.3 and No.4 are allocated to the right of the CPU
No.1.
CPU slot: CPU No.1
Slot: CPU No.2
Slot: CPU No.3
Slot: CPU No.4
CPU module
CPU module
CPU module
CPU module
Power supply
module

These PLC numbers are used for the following purposes of

• To access the High Performance model QCPU when the GX Developer
(personal computer) is not connected in the multiple CPU system.
• To set up control CPUs with the I/O Assignment in the multiple CPU
system.

(b) The High Performance model QCPU stores the host number in the special
register (SD395).
It is recommended to build a program for checking the host number using
the High Performance model QCPU.
This will enable easy verification when High Performance model QCPUs
are not mounted correctly and when programs are written into other CPUs
with the GX Developer.
In the program shown below, the annunciator (F1) is set to ON when the
High Performance model QCPU writing programs is a CPU other than the
CPU No.1 (SD395 = 1.)
The "USER" LED on the front of the High Performance model QCPU is
illuminated when the annunciator (F1) is set to ON. The number of the
annunciator that has been set at ON will also be stored in a special register
(SD62).

Set a CPU number used for comparison.

REMARK
For the own number confirmation method for the Motion CPU and PC CPU module,
refer to the manual of the Motion CPU and PC CPU module.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

14.2.2 Precautions when using Q Series I/O modules and intelligent function modules

(1) Compatible I/O modules

All I/O modules (QX , QY ) are compatible with to multiple CPU system.
They can be used by setting any of CPU No.1 to No.4 as a control CPU.

(2) Compatible intelligent function modules

(a) The intelligent function modules compatible with the multiple CPU system
are those of function version B or later. They can be used by setting any of
CPU No.1 to No.4 as a control CPU.
(b) Q Series high speed count modules (QD62, QD62D, QD62E) are
compatible with by multiple CPU system are those of function version A or
later. They can be used by setting any of CPU No.1 to No.4 as a control
CPU.
(c) Q Series interruption modules (QI60) do not have a function version, but are
supported by multiple CPU system. CPUs No.1 to No.4 can be set up as
control CPUs.
(d) Intelligent function modules of function version A can be used in multiple
CPU system by setting CPU No.1 as a control CPU.
However, only control CPU can be accessed from serial communication
modules and other external modules. (MELSECNET/H, serial
communication modules and other external modules cannot access non-
control CPUs.)
The "SP. UNIT VER. ERR (error code: 2150)" occurs if any of CPU No.2 to
No.4 has been set as a control CPU, and the multiple CPU system will not
be a started up.

(3) Ranges of access to control and non-control modules

In a multiple CPU system, non-control modules can be accessed by setting "I/O
setting outside of the group" at the "Multiple CPU settings" dialog box in "PLC
Parameter". The following table indicates accessibility to the control and non-
control modules in the multiple CPU system.
Accessibility
Access target Non-control module (I/O setting outside of the group)
Control module
Disabled Enabled
Input (X)
Read
Output (Y)
Write
Buffer Read
memory Write
: Accessible : Inaccessible

REMARK
• The function version of intelligent function modules can be confirmed at the rated
name plate of the intelligent function module and with the GX Developer's "System
monitor product information list window" (see Section 2.3.)
• See Section 14.2.4 for details on restrictions on the number that can be used with
intelligent function modules.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
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14.2.3 Limitations when mounting AnS Series corresponding I/O modules and special
function modules

(1) Compatible I/O modules and special function modules

AnS Series corresponding I/O modules and special function modules (compact
types) can be used with the High Performance model QCPU.

(2) Control CPU

The AnS Series corresponding I/O modules or special function module can be
controlled by only one CPU (control CPU) of the CPUs No.1 to No.4 when
configuring a multiple CPU system. For example.
If the control CPU is set up as the CPU No.2 as shown in the illustration below,
every slot's control CPU on which I/O modules and special function modules
compatible with the AnS Series are mounted are set as the CPU No.2.
The "PARAMETER ERROR (error code: 3009)" occurs even if only one AnS
Series corresponding I/O module or special function module is set up, the
multiple CPU system will not be started up.
Control CPU can be set for each slot

Power
supply CPU CPU CPU CPU Module Module Module Module Module Module Module Module Module
module module module module module
1 2 3 4 1 1 2 2 3 4 4 4 4 Module No.

Q312B

Power
AnS AnS AnS AnS AnS AnS AnS AnS
supply Module Module Module Module Module Module Module Module
module Same CPU set as the control CPU
2 2 2 2 2 2 2 2

QA1S68B

Power
AnS AnS AnS AnS AnS
supply Module Module Module Module Module
module
2 2 2 2 2

QA1S68B
The Module No. shown in the illustration represents the
following:
CPU 1 to 4 : CPU's CPU number
Modules 1 to 4 : Control CPU's CPU number

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

(3) Ranges of access to control and non-control modules

The following table indicates accessibility to the control and non-control modules
in the multiple CPU system.
Accessibility
Access target Non-control module (I/O setting outside of the group)
Control module
Disabled Enabled
Input (X)
Read
Output (Y)
Write
Buffer Read
memory Write
: Accessible : Inaccessible

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
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14.2.4 Modules that have mounting restrictions

The following table indicates restrictions on the number of modules that can be
mounted in multiple CPU system. Ensure that the number of modules mounted is
within these ranges.
Number of modules that can be Number of modules that can be
Product Model
mounted per system mounted per PLC
• QJ71LP21
• QJ71BR11 Maximum of four PLC to PLC Maximum of four PLC to PLC
Q series MELSECNET/H
• QJ71LP21-25 networks and remote I/O networks and remote I/O
network modules
• QJ71LP21G networks networks
• QJ71LP21GE
• QJ71E71
Q series Ethernet
• QJ71E71-B2 Maximum of four Maximum of four
interface modules
• QJ71E71-100
Q series CC-Link system • QJ61BT11
No limit No limit
master/local modules • QJ61BT11N
No restrictions No restrictions
MELSECNET/MINI-S3 • A1SJ71PT32-S3
(however, the automatic refresh (however, the automatic refresh
data link modules • A1SJ71T32-S3
function cannot be set up) function cannot be set up)
• A1SD51S
• A1SD21-S1
AnS series corresponding
• A1SJ71J92-S3 Maximum of six Maximum of six
Special function modules
(When the GET and PUT
services are used)
• A1SI61 Only one
Maximum of four
Interruption modules Only one
• QI60 (maximum of three when the
A1SI61 is in use)
: A maximum of 4 modules per PLC (16 modules per system) can be controlled if the
network parameters for CC-Link are set and controlled by GX Developer. There is
no restriction in the number of modules when the parameters are set by the
instructions dedicated to the CC-Link.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

14.2.5 Compatible GX Developers and GX Configurators

(1) Compatible GX Developers

GX Developer Version 6 (SW6D5C-GPPW-E) or later are compatible with on
multiple CPU system.
GX Developer Version 5 (SW5D5C-GPPW-E) or earlier are not compatible with
multiple CPU system.

(2) Compatible GX Configurators

The GX Configurators listed can be used on multiple CPU system without
modification.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
MELSEC-Q

14.2.6 Parameters that enable the use of multiple CPU system

(1) Parameters that enable the use of multiple CPU system

Compared with the single CPU system, the multiple CPU system includes the
"No. of CPU", "control CPU", "refresh setting (automatic refresh setting)" of PLC
parameters.
The PLC parameters must be set to the same for all the CPU modules used in
the multiple CPU system, except some modules.
Make similar settings to the PC CPU module, if one is included, using the PC
CPU module setting utility.
For the setting method, refer to the manual of the PC CPU module.
(2) The PLC parameter settings for use with multiple CPU system
The PLC parameters, necessity of setup, and descriptions that are required for
using multiple CPU system are listed in table 14.3.
Table 14.3 Setting list for the multiple CPU and I/O Assignment
Necessity of 2
PC parameter Description
setup 1
I/O Assignment
Type —
Model name — —
Points —
Start —
Standard setting
Base model name — —
Power model name — —
I/O Assignment
Extension cable — —
Points —
Switch settings — —
Detailed settings
Error time output made — —
H/W error time PLC operation made — —
I/O response time — —
Control PLC
PLC system —
Number of empty slots
settings
No. of CPU
Operation mode
Online module change
Multiple CPU The input condition outside of the group is taken
settings The output condition outside of the group is taken
Refresh setting
Send range for each CPU
CPU side devices —
1: Necessity of setup column
: Items that must be set up for multiple CPU system (operations not possible if not set up.)
: Items that may be set up when required for multiple CPU system (Operations carried out
with the default values when not set up.)
—: Items that are the same as single CPU system.
2: Descriptions
: Items that have the same settings for all CPU modules on the multiple CPU system.
: Items that have the same settings for all High Performance model QCPUs and PC CPU
module on the multiple CPU system (items that do not have settings for Motion CPUs).
—: Items that can be setup up individually for each CPU modules on the multiple CPU system.
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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
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After parameters such as multiple CPU settings are changed, reflect the changes
to keep uniformity among all CPUs in the multiple CPU system, then reset the
CPU No.1.
It is possible to transfer across and use the CPU settings and I/O Assignments
set up for other projects with GX Developer.
(See section 19.2.3 for details on transferring and using multiple CPU settings
and I/O Assignments.)
(a) Number of CPUs setting (setup necessary)
1) The number of CPU modules to be used on a multiple CPU system are
set at the PLC parameter's "Multiple CPU settings" screen in the (PLC)
Parameter dialog (indicated with the "A" arrow.)
A

2) Ensure that the No. of CPU set for the multiple CPU system is the
same as the number of CPUs actually mounted.
When an empty slot is secured for the purpose of mounting additional
CPU modules in the future, set "PLC (Empty)" at the "I/O assignment"
tab screen in the (PLC) "Parameter" dialog box.
For example, when setting "4" as "No. of CPU" in the "Multiple CPU
settings" screen and securing one of them for future use, set slot 3 to
"CPU (Empty)" (indicated with the "B" arrow.)

3) A "PARAMETER ERROR (error code: 3010)" occurs to all mounted

CPU modules in the following cases.
• The number of mounted CPU modules exceeds the number set with
the No. of CPU setting.
• No CPU module is installed in slots set for CPU No.1 to No.4.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
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(b) Operation mode setting (optional)

This is set to continue operation of other CPUs where a stopping error has
not occurred when an error occurs at any of CPUs No.2 to No.4.
The operation mode for the CPU No.1 cannot be changed (all CPUs will
suspend operations when a stop error is triggered for the CPU No.1.)
See Section 14.2.8 for further details.
(c) I/O settings outside of the group (optional)
This is set when the input and output (X, Y) for I/O modules and intelligent
function modules being controlled by other CPUs is to be downloaded to
the host CPU.
See Section 17.2 for further details.
(d) Refresh setting (optional)
This is set up to automatically refresh the device data on the multiple CPU
system.
See Section 16.1 for further details.
(e) Control CPU settings (optional)
Sets up the control CPUs for the I/O modules and intelligent function
modules mounted on the base units on the multiple CPU system (indicated
by the "C" arrow.)
All default settings are set for the CPU No.1.

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(3) Multiple CPU setting and I/O Assignment checks

Checks, as shown in table 14.4, will be run to ascertain that all CPU modules
have the same settings (sameness check) when the description column in table
14.3 has been set with the "O" symbol and the power to the sequence is
switched on, the High Performance model QCPU is reset, or the status is
changed from STOP to RUN.

(a) The multiple CPU system will be started up if all CPUs have the same
settings.

(b) The operations described in table 14.4 will be performed when all CPUs do
not have the same settings.
In this event, check the multiple CPU settings and I/O Assignment, and set
all CPUs with the same settings.
To start the multiple CPU system, reset the High Performance model
QCPU for CPU No.1 or turn off and on the CPU (power ON OFF ON).
(For the action after the High Performance model QCPU for CPU No.1 is
reset, see Section 14.2.7.)

Table 14.4. List of sameness check contents

Item CPU No.1 CPU No.1 to 4
When the power to the CPU is switched on • A comparison check will be run on the
When CPU No.1 is reset multiple CPU settings and I/O
Assignments for CPU No.1.
No sameness check will be run
• A "PARAMETER ERROR (error code:
3012)" will occur in the host CPU if they
do not match.
• A comparison check will be run on the multiple CPU settings and I/O Assignments for
When CPUs in the the CPU in the RUN mode with the lowest number.
RUN mode exist • A "PARAMETER ERROR (error code: 3012)" will occur in the host CPU if they do not
match.
• When the RUN/STOP
• A comparison check will be run on the • A comparison check will be run on the
switch has been changed
multiple CPU settings and I/O multiple CPU settings and I/O
from STOP to RUN. When CPUs in the
Assignments for CPU No.2. Assignments for CPU No.1.
• When parameters are RUN mode do not
• A "PARAMETER ERROR (error code: • A "PARAMETER ERROR (error code:
written with the GX exist
3012)" will occur in the host CPU if they 3012)" will occur in the host CPU if they
Developer
do not match. do not match.
STOP RUN is not allowed as a
When a stop error
— "MULTIPLE CPU DOWN (error code:
occurs at CPU No.1
7000)" error will occur in the host CPU.

POINT
After multiple CPU system parameters unavailable with the Motion CPU are
changed for the High Performance model QCPU or PC CPU module in a multiple
CPU system including a Motion CPU, be sure to reset the High Performance model
QCPU for CPU No.1 or turn off and on the CPU. (Otherwise the High Performance
model QCPU or PC CPU module checks consistency with multiple CPU system
parameters of the Motion CPU, causing a "PARAMETER ERROR (error code:
3012)."

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14.2.7 Resetting the multiple CPU system

It is possible to reset the entire multiple CPU system by resetting the CPU No.1.
The CPU modules for CPU No.2 to No.4, I/O modules and intelligent function modules
will be reset when the CPU No.1 is reset.

If a stop error occurs for any of the CPUs on the multiple CPU system, either reset the
CPU No.1 or restart the sequencer (power supply ON OFF ON) after the problem
has been recovered.
(Recovery is not allowed by resetting the CPU modules for CPU No.2 to No.4 for which
stop errors have occurred.)
0 1 2 3 4 5 6 7
CPU No.1 CPU module
CPU No.2 CPU module
CPU No.3 CPU module
CPU No.4 CPU module
Power supply
module

Reset is not allowed with the multiple CPU system.

If a reset is attempted all CPU on the multiple
CPU system will assume the "MULTIPLE CPU DOWN" status.
The entire multiple CPU system can be reset.

POINT
(1) It is not possible to reset the CPU modules for CPU No.2 to No.4 individually in
the multiple CPU system. If an attempt to reset any of the CPU modules for
CPU No.2 to No.4 during operation of the multiple CPU system, a "MULTIPLE
CPU DOWN (error code: 7000)" error will occur for the other CPUs, and the
entire multiple CPU system will be halted. However, depending on the timing in
which the CPU modules have been reset, there are cases where errors other
than the "MULTIPLE CPU DOWN" error will halt the other CPUs.
(2) A "MULTIPLE CPU DOWN (error code: 7000)" error will occur regardless of
the operation mode set at the "Multiple CPU settings" screen within the (PLC)
Parameter dialog box. (stop/continue all other CPUs on the CPU modules for
CPU No.2 to No.4 error) when the CPU modules for CPU No.2 to No.4 are
reset (See Section 14.2.8 for details on the multiple CPU setting operation
modes.)

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14.2.8 Processing when High Performance model QCPU stop errors occur

The operations for the entire system will differ when a CPU No.1 stop error occurs and
when any of CPU No.2 to No.4 stop error occurs in the multiple CPU system.

(1) When a stop error occurs at the CPU No.1

(a) A "MULTIPLE CPU DOWN (error code: 7000)" error occurs for the CPU
modules for CPU No.2 to No.4 and motion CPUS and the multiple CPU
system will be halted when a stop error occurs at the CPU No.1
(See point on the next page for details)
(b) Observe the following procedures to restore the system.
1) Confirm the cause of the CPU No.1 error with the PC diagnosis
function.
2) Remove the cause of the error.
3) Either reset the CPU No.1 or restart the power to the CPU.
All CPUs on the entire multiple CPU system will be reset and the
system restored when the CPU No.1 is reset or the power to the CPU
is restarted.

(2) When a stop error occurs at the CPU No. other than No.1
Whether the entire system is halted or not is determined by the multiple CPU
setting's "Operating Mode" setting when a stop error occurs in the CPU modules
for CPU No.2 to No.4.
The default setting is for all CPUs to be stopped with a stop error.
When you do not want to stop all CPUs at occurrence of a stop error in any of the
CPU modules, click the check box that corresponds to the CPU No. whose error
will not stop all CPUs. (Arrow D)

(a) A "MULTIPLE CPU DOWN (error code: 7000)" error occurs for the CPU
modules and the multiple CPU system will be halted when a stop error is
occurs in CPU modules for which the "All station stop by stop error of CPU
'n' " has been set. (See POINT on the next page for details.)
(b) A "MULTIPLE CPU ERROR (error code: 7010)" error occurs for all other
CPUs but operations will continue when a stop error occurs in CPU
modules for which the " All station stop by stop error of CPU 'n' " has not
been set.

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14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
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POINT
A "MULTIPLE CPU DOWN" stop error will be occur for the CPU on which the error
was detected when a stop error occurs.
There are cases where the timing of error detection will search for the CPU on
which the stop error that has caused the "MULTIPLE CPU DOWN" error occurs,
not the first CPU on which a stop error occurs, and the entire system will assume
the "MULTIPLE CPU DOWN" status.
For example, if a stop error occurs in the CPU No.2 and the CPU No.3 is halted as
a direct consequence of this, there are cases where the CPU No.1 will be halted
because of the stop error on CPU No.3 depending on the timing of error detection.
CPU module No.1 Halted with an "OPERATION ERROR"

CPU module No.2

CPU module No.3

Power supply
module

Halted with stop error detection on CPU No.2

(becomes "MULTIPLE CPU DOWN")
There are cases where the system will be halted
with stop error detected on the CPU No.3
depending on the timing of error detection.
(becomes "MULTIPLE CPU DOWN")

Owing to this, there are cases where a different CPU No. to the CPU that initially
caused the stop error will be stored in the error data's common information
category.
In this event, remove the reason for the error on the CPU that caused the stop error
in addition to the "MULTIPLE CPU DOWN" error when restoring the system.
In the illustration shown below, the cause of the CPU No.2 error that did not cause
the "MULTIPLE CPU DOWN" error is removed.

(c) Observe the following procedures to restore the system.

1) Confirm the cause of the CPU No.1 error with the PLC diagnostics
function.
2) Remove the cause of the error.
3) Either reset the CPU No.1 or restart the power to the PLC.
All CPUs on the entire multiple CPU system will be reset and the system
restored when the CPU No.1 is reset or the power to the CPU is restarted.

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14.2.9 Reducing the time required for multiple CPU system processing

(1) Multiple CPU system processing

A bus (base unit pattern, extension cable) is used by the CPU module when
accessing the I/O module and intelligent function module, and this bus cannot be
used by plural CPU module at the same time.
The CPU modules that attempted buss access afterwards when plural CPU
module use the bus simultaneously will assume the "Standby" status until
processing for the CPU module that executed the procedure first has been
completed.
This "Standby" status (the amount of time the CPU module must wait) will cause
delays in input and output on the multiple CPU system, and result in extended
scan times.
See Chapter 18 for details on extended scan times.

(2) Maximum standby time

The host CPU will reach the maximum standby time in the following cases with a
multiple CPU system.
• When four CPU modules are used on the multiple CPU system.
• When additional base units are in use.
• When intelligent function modules that possess vast quantities of data are
mounted onto additional base units.
• When four CPU modules simultaneously access modules mounted onto
additional base units.

(3) Reducing the time required for multiple CPU system processing
The following methods are available for reducing the amount of time required for
multiple CPU system processing.
• Combine modules with many access points, such as MELSECNET/H and CC-
LINK refresh, etc., together into a main base unit.
• Set modules with many access points, such as MELSECNET/H and CC-LINK
refresh, etc., as control module on a single CPU module, and ensure that
simultaneous access does not occur.
• Reduce the number of MELSECNET/H and CC-LINK refresh access points.
• Reduce the number of automatic refresh points between CPU modules.

POINT
It is possible to reduce scan time by changing the following PLC parameter
settings:
• A Series CPU compatibility setting
• Floating point arithmetic processing
See Section 18.3 for details.

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15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS

15.1 Concept behind Allocating I/O Numbers

Multiple CPU system possess I/O numbers to enable interactive transmission between
the CPU modules and the I/O modules and intelligent function modules, and I/O
numbers to enable interactive transmission between the CPU modules.
15.1.1 I/O modules and intelligent function module I/O numbers
The difference with single CPU systems is the 00H position (slot) of the I/O number
with multiple CPU system.
However, the concept behind the sequence for allocating I/O numbers, the I/O
numbers for each slot, and the I/O numbers for empty slots is the same for both types
of system.
See Chapter 5 (Allocating I/O Numbers) for details on the concept behind the
sequence for allocating I/O numbers, the I/O numbers for each slot, and the I/O
numbers for empty slots.
(1) "00H" position for I/O numbers
(a) The number of slots set with the PLC parameters' multiple CPU settings are
occupied by the CPU modules on the multiple CPU system.
(b) The I/O modules and intelligent function modules are mounted from the
right of the slots occupied by the CPU modules.
(c) I/O number of a system without PC CPU module
The I/O number for the I/O modules and intelligent function modules
mounted from the right of the slots occupied by the CPU modules is set as
15 "00H" and consecutive numbers are then allocated sequentially to the right.
1) Example: Two modules are mounted
0 1 2 3 4 5 6 7
Power supply

CPU module
CPU module
module

I/O number : 00H

2) Example: Three modules are mounted and one empty slot exists
0 1 2 3 4 5 6 7
Power supply

CPU module
CPU module
CPU module
Empty
module

I/O number : 00H

(d) Input/output number of a system with PC CPU module
The PC CPU module occupies two slots. The one on the right side among
the two slots is handled as an empty slot. (16 empty points are occupied
with default setting.) Therefore the I/O number of the slot on the right side
of the PC CPU module is "10H." (Set the empty slot at zero point using I/O
allocation of PLC Parameters dialog box, to assign "00H" to the first I/O
number.)
0 1 2 3
PC CPU module
Power supply

CPU module
CPU module
CPU module
module

CPU count (4)

Empty slot (00H to 0FH: occupied)

REMARK
• If the number of CPU modules mounted on the main base unit is smaller than the
number set at the "Multiple CPU setting" of “(PLC) Parameter" dialog box, the
slot(s) on the right of the actually mounted CPU modules is (are) set as "CPU
(Empty).
• The I/O number for the multiple CPU system can be confirmed with the system
monitor.

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15.1.2 I/O number of High Performance model QCPU, Motion CPU and PC CPU module

I/O numbers are allocated to the CPU modules with the multiple CPU system in order
to allow interactive communications between the CPU modules with the following
commands.
• Multiple CPU commands
• Motion dedicated commands
• Dedicated communication commands between multiple CPUs
The I/O numbers for the CPU modules are fixed for the slots on which they are
mounted and cannot be amended.
The table below shows the I/O number allocated to each CPU module when the
multiple CPU system is composed.
CPU module
CPU slot Slot 0 Slot 1 Slot 2
mounting position
First I/O number 3E00H 3E10H 3E20H 3E30H

The CPU modules I/O numbers are used in the following cases.
• When writing data in the host CPU's CPU shared memory with the S.TO instruction.
1 15
• When reading data from other CPU's CPU shared memory with the FROM
instruction. 1
• When reading data from other CPU's CPU shared memory with the intelligent
function module device (U_\G_). 1
• When specifying the High Performance model QCPU to be accessed with the
Ethernet module. 2
• When specifying the High Performance model QCPU to be accessed with the serial
communication module. 3

REMARK
1: See Chapter 16 for details on among High Performance model QCPU, Motion
CPU and PC CPU module.
2: Refer to the Ethernet module's manual for details on accessing the High
Performance model QCPU with the Ethernet module.
3: Refer to the serial communication module's manual for details on accessing the
High Performance model QCPU with the serial communication module.

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15.2 Purpose of PC Parameter I/O Allocations with GX Developer

Sets up the High Performance model QCPU/Motion CPU/PC CPU module that are to
control the multiple CPU system's I/O modules and intelligent function modules.

(a) Q Series I/O modules and intelligent function modules can be selected as
control CPUs for each slot.
(b) AnS Series I/O modules and intelligent function modules are set as control
CPUs on the same CPU modules.
Q38B
0 1 2 3 4 5 6 7
CPU module
CPU module
CPU module
Power supply
module

Control CPU can be

Q68B selected for each slot.
8 9 10 11 12 13 14 15
Power supply
module

QA1S68B
16 17 18 19 20 21 22 23
Power supply
module

All of the same control

QA1S68B CPU are selected.
24 25 26 27 28 29 30 31
Power supply
module

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16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU

SYSTEM
It is possible to perform the following interactive transmission between each CPU
modules with a multiple CPU system.
• Automatically refreshing the device data between each CPU modules with
multiple CPU system parameter settings.
• Data transfer between other High Performance model QCPU and PC CPU
module via CPU shared memory using multiple CPU instructions
Also, data reading of High Performance model QCPU from CPU shared
memory of Motion CPU using multiple CPU instructions
• Control command from the High Performance model QCPU to the Motion CPU
with Motion dedicated CPU instructions.
• Writing and reading of the device data from the High Performance model
QCPU to the Motion CPU with communication dedicated instructions between
multiple CPUs.
Also, event issuance from High Performance model QCPU to PC CPU module
using instructions dedicated to multiple CPU communication
(1) Automatic refresh of device data
Automatic refresh of the CPU shared memory is a function of automatic data
transfer between CPU modules in END processing of the CPU.
As the device memory data of other CPUs is automatically read when the
automatic refresh function is used, is possible for the host CPU to use the device
data of other CPUs.
CPU No.1 CPU No.2

CPU shared memory CPU shared memory

Host CPU's operation Host CPU's operation
information area information area
System area System area
Reading performed
Automatic refresh area for with the CPU No.2 Automatic refresh area for
writing in the CPU No.1 END process writing in the CPU No.2

User's free area User's free area 16

Writing performed with Writing performed
the CPU No.1 END process with the CPU No.2
END process
Device memory Device memory
For use of the CPU No.1 Reading performed For use of the CPU No.1
For use of the CPU No.2 with the CPU No.1 For use of the CPU No.2
END process

(2) Exchanging data with multiple CPU instructions and instructions

that use Intelligent function module device (U \G )
The CPUs on the multiple CPU system write data into the host CPU's CPU
shared memory with the use of the S. TO instruction/FROM instruction.
The data written to the CPU shared memory of the host CPU with the S. TO
instruction is read by High Performance model QCPU of other CPUs with the use
of the FROM instruction and U \G .
Non-linked device data also read directly when the command is executed.
CPU No.1 CPU No.2
CPU shared memory CPU shared memory
Host CPU's operation Host CPU's operation
information area information area
System area System area
Automatic refresh area for
writing in the CPU No.1
Data written with
the S. TO instruction Read with FROM
instruction or U \G
Written with the S. TO instruction

Sequence program Sequence program

S. TO instruction FROM command
execution execution

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 16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU
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16.1 Automatic Refresh of CPU Shared Memory

(1) Automatic refresh of CPU shared memory

(a) Automatic refresh of the CPU shared memory is a function of automatic
data transfer between CPUs in END processing of the CPU.
As the device memory data of other CPUs is automatically read when the
automatic refresh function is used, is possible for the host CPU to use the
device data of other CPUs.
Data is transmitted between the following parties during automatic refresh
of CPU shared memory.
• Between High Performance model QCPU and High Performance model
QCPU
• Between High Performance model QCPU and Motion CPU
• Between Motion CPU and Motion CPU
• Between High Performance model QCPU and PC CPU module
• Between Motion CPU and PC CPU module
An outline of operations when the CPU No.1 performs automatic refresh on
the 32 points between B0 and B1F, and when the CPU No.2 performs
automatic refresh on the 32 points between B20 and B3F.
CPU No.1 CPU No.2
CPU shared memory CPU shared memory
Host CPU's operation Host CPU's operation
information area information area
System area System area
Automatic refresh area for 3) Reading performed with Automatic refresh area for
writing in the No.1 machine writing in the No.2 machine
the CPU No.2
END process
User's free area User's free area

1) Writing performed with 2) Writing performed

the CPU No.1 END process with the CPU No.2
END process
16 Device memory Device memory
B0 to B1F (For use of the CPU No.1) 4) Reading performed with B0 to B1F (For use of the CPU No.1)
the CPU No.1
B20 to B3F (For use of the CPU No.1) B20 to B3F (For use of the CPU No.1)
END process

The processes performed during the CPU No.1 END process.

1): The B0 to B1F transmission device data for the CPU No.1 is
transferred across to the host CPU shared memory automatic refresh
area.
4): The data in the CPU No.2 CPU shared memory automatic refresh area
is transferred across to B20 to B3F in the host CPU.
The processes performed during the CPU No.2 END process.
2): The B20 to B3F transmission device data for the CPU No.2 is
transferred across to the host CPU shared memory automatic refresh
area.
3): The data in the CPU No.1 CPU shared memory automatic refresh area
is transferred across to B0 to B1F in the host CPU.
(b) Executing automatic refresh
Automatic refresh is executed when the CPU module is in RUN status,
STOP status or PAUSE status. Automatic refresh cannot be performed
when a stop error has been triggered in the CPU module.
If a stop error occurs on one module, the other modules for which an error
has not occurred will save the data prior to the stop error being triggered.
For example, if a stop error occurs in the CPU No.2 when B20 is ON, the
B20 in the CPU No.1 will remain at ON, as shown in the operation outline in
fig. (a).
(c) When automatic refresh is carried out, it is necessary to set the points to be
transmitted by each CPU and the device in which the data is to be stored
(the device that will perform automatic refresh) with the PLC parameter
multiple CPU settings.

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(2) Automatic refresh settings

Set the points to be transmitted by each CPU and the device in which the data is
to be stored with the PLC parameter multiple CPU settings for when automatic
refresh is to performed.
Range of transmission Switching between
setting for each CPU module setting numbers
Sets the header number of
the device for which automatic
refresh is to be performed
(uses consecutive numbers
from the setup device number
to the number of specified points)

(a) Setting switch/range of transmission for each CPU (refresh range)

1): It is possible to set four ranges from Setting 1 to Setting 4 for the
refresh setting with the setting switch. For example, it is possible to set
the refresh function to divide ON/OFF data into bit devices with Setting
1 and other data into word devices with Setting 2.
2): The transmission range for each CPU is set in units of two CPU shared
memory points (two words.) (Becomes 2 points when specifying the
word device with the CPU device, and 32 points when specifying the
bit device.)
Data for which the point is set at "0" with the range of transmission for
each CPU will not be refreshed.
As the bit device becomes 16 points at one point of the CPU shared
memory when refreshing is performed with 32 points between B0 and
B1F on the CPU No.1 and with 32 points between B20 and B3F on the
CPU No.2, the number of transmission points is two for the CPU No.1
and two for the CPU No.2.
3): The number of transmission points is a maximum of 2 k points (2 k
words) with a total of four ranges for each CPU module, making a total
of 8 k points (8 k words) for all CPUs.

• 2 k points (2 k words)
per CPU.
• 8 k points (8 k words)
for all CPUs. The CPU shared memory
• Setting is in units of (CPU share memory)
2 points (2 words). is set in two points, and the
bit device becomes 32 points
when bit device is specified
on the CPU device.

Not refreshed as the number of points for CPU No.3 and CPU No.4 is 0

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4): The CPU shared memory occupied with automatic refresh refreshing
becomes the total of setting 1 to setting 4.
The first and last addresses of the CPU shared memory being used
will be displayed in hexadecimals when the number of transmission
points are set.
The CPU for which the transmission points have been set in setting 1
and setting 2 will become the last address of the setting 2 CPU shared
memory. (Up until 811H is used for CPU No.1 and CPU No.2, and up
until 821H is used for the CPU No.4 in the illustration shown below.)
The CPUs that transmits only setting 1 will become the last address of
the setting 1 CPU shared memory. (CPU No.3 is up to the setting 1
address in the illustration shown below.)

CPU No.1 transmission range

Last CPU device

Last address of each CPU share memory (CPU shared memory)

5): The same number of transmission points must be set for all CPUs on
the multiple CPU system. A "PARAMETER ERROR" occurs if the
number of transmission points for one CPU is different.
(b) CPU devices
The following devices can be used for automatic refresh purposes (other
devices cannot be set up with the GX Developer.)
Settable devices Caution
Data register (D)
• The device in the left column occupies one point for
Link register (W)
every transmission point
File register (R, ZR)
Link relay (B) • Multiples of 0 or 16 are specified for the first number.
Internal relay (M) • The device in the left column occupies one point for
Output (Y) every transmission point.

1) CPU devices use the total amount of transmission point devices

consecutively from the specified device number to the CPU No.1 to
No.4 in the first set range.
Set a device number so that the amount of transmission point devices
can be secured.
Sixteen times the number of transmission points will be set if a bit
device is specified in the CPU device.
For example, If the total number of transmission points for CPU No.1
to No.4 is ten, then 160 points will be set between B0 and B9F when
the B0 link relay is specified.

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2) The CPU devices are set as follows.

• It is possible to change the device and set up settings 1 to 4.
The same devices can also be specified as long as the device range
for settings 1 to 4 are not duplicated.
Setting 1: In the case of link relays

• It is possible to change the device

and set up settings 1 to 4.

Setting 2: In the case of link registers

• The same devices can be specified

for settings 1 to 4. However, as setting
1 in the illustration on the left uses
160 points between B0 and B9F,
BA0 and higher can be used for setting 3.
No part of a device number can be
Setting 3: In the case of link relays duplicated, as shown with B0 to B9F
on setting 1 and B90 to B10F on setting 3.

The first and last will be calculated automatically with the GX Developer

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16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU
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• Each of the setting 1 to setting 4 devices can be set up

independently.
For example, the CPU No.1 can be set up as a link relay, and the
CPU No.2 can be set up as an internal relay.

Refresh setting for CPU No.1

• When the CPU No.1 and CPU No.2 devices

have been set up with different devices

Set the same point for all the CPU.

Refresh setting for CPU No.2

• When the CPU No.1 and CPU No.2 devices

have been set up with the same device

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3) An outline of the operations when the automatic refresh function is

divided into four ranges (Setting 1: Link relay (B), Setting 2: Link
register (W), Setting 3: Data register (D), Setting 4: Internal relay (M))
and then performed is shown in the illustration below.

CPU No.1
Device CPU shared memory
Reading performed Setting 1
B0 Writing during the
Other CPU's with the CPU No.1 CPU No.1 CPU No.1
END process
shared memory END process to transmission transmission
data (No.1) data (No.1)
CPU No.2
CPU No.2 reception CPU No.1
CPU No.2 transmission data (No.1) transmission
data (No.1)
ss data (No.2)
ce
CPU No.2 transmission
CPU No.3 reception
D pro
data (No.1)
data (No.2) EN Maximum
Maximum the CPU No.1
CPU No.4 reception ng transmission 2 k words
2 k words CPU No.2 transmission uri
data (No.1)
gd data (No.3)
data (No.3)
itin
Setting 2 Wr

ss
CPU No.2 transmission CPU No.1

e
W0

oc
data (No.4) CPU No.1 transmission

pr
transmission data (No.4)

D
data (No.2)

EN
CPU No.3

e
th
CPU No.2 reception

ing
CPU No.3 transmission data (No.2) User's free area

r
data (No.1)

du
g

s
CPU No.3 reception

in

es
CPU No.3 transmission data (No.2)

rit

roc
W
data (No.2)
Maximum

Dp
CPU No.4 reception
2 k words CPU No.3 transmission data (No.2)

EN
data (No.3) Maximum
Setting 3

the
CPU No.3 transmission
8 k words

ng
data (No.4) D0 CPU No.1

uri
transmission

gd
data (No.3)

itin
CPU No.4 Wr
CPU No.2 reception
CPU No.4 transmission data (No.3)
data (No.1)
CPU No.3 reception
CPU No.4 transmission data (No.3)
data (No.2)
Maximum
CPU No.4 reception
2 k words CPU No.4 transmission data (No.3)
data (No.3)
Setting 4
CPU No.4 transmission
data (No.4)
M0 CPU No.1
transmission
data (No.4)

CPU No.2 reception

data (No.4)

CPU No.3 reception

data (No.4)

CPU No.4 reception

data (No.4)

(3) Precautions
(a) Device ranges set for the use of the automatic refresh function cannot be
set in local devices.
If the device ranges set for the use of the automatic refresh function are set
in local devices, the settings will not be reflected back onto the refresh data.
(b) Do not set devices for the use of the automatic refresh function in the file
register of all programs.
If devices for the use of the automatic refresh function are set in the file
register of all programs, automatic refresh will be performed on the file
register that corresponds with the last scan execution type program
executed.

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(c) There are cases where old data and new data will become mixed up for
each CPU depending on the timing of refreshing the host CPU and reading
data from other CPUs.
When performing the automatic refresh function, create an interlock
program similar to the one shown below that uses the first device to be
refreshed for each CPU, and do not use the data from other CPUs when
old data does get mixed up with new data.
An example of a program set up with the following multiple CPU setting
refresh settings is shown below.
• CPU device: D0
• CPU No.1 transmission points: 1024 points (D0 to D1023)
• CPU vNo.2 transmission points: 1024 points (D1024 to D2047)

D0 Used for the CPU No.1 interlock

to CPU No.1 transmission device

D1023
D1024 Used for the CPU No.2 interlock

to CPU No.2 transmission device

D2047

Example of a program on the transmission side Example of a program on the reception side
Interlock with b0 of the CPU No.2 Interlock with b0 of the CPU No.1
Writing first device (D1024) first device (D0)
command
D1024.0 D0.0
Operation using the
Transmission data
transmission data
set in D0 to D1023
(D0 to D1023)

D0.0 D1024.0

b0 of the CPU No.1 first device (D0) b0 of the CPU No.2 first device
for the use of the interlock is set at (D1024) for the use of the interlock
ON when transmission data setting has is set at ON when operations using
been completed. the received data have been completed.

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16.2 Communication with Multiple CPU Dedicated Instructions and Intelligent Function
Module Devices
(1) Communication with multiple CPU dedicated instructions (S. TO
instruction / FROM instruction) and intelligent function module
device (U \G )
The High Performance model QCPU of a multiple CPU system can use an S. TO
instruction, FROM instruction and intelligent function module device (U \G ) to
access the CPU shared memory of the High Performance model QCPU, Motion
CPU and PC CPU module.
The data written in the CPU shared memory of the host CPU with a S. TO
instruction can be read by another CPU using a FROM instruction or intelligent
function module device (U \G ).
Contrary to the automatic refresh function for the CPU shared memory, it is
possible to read data directly when this instruction is executed.
An outline of a process where data written in the CPU shared memory of CPU
No.1 with an S. TO instruction is read by the CPU No.2 using an FROM
instruction or intelligent function module device (U \G ) is shown in the figure
below.
CPU No.1 CPU No.2
CPU shared memory CPU shared memory
Host CPU's operation Host CPU's operation
information area information area
System area System area
Automatic refresh area for the
use of No.1 machine writing
2) Read with FROM
Data written with instruction or U \G
the S. TO instruction

1) Writing performed with

the S. TO instruction
Sequence program Sequence program
S. TO instruction FROM instruction
execution execution

CPU No.1 processing

1): Data is written into the user's free area on the CPU No.1 with the S.
TO instruction.
CPU No.2 processing
2): An FROM instruction or the intelligent function module device
(U \G ) is used to read data from the free user area of the CPU No.1
to the designated device.
Refer to the following manual for further details on the S. TO and FROM
instructions.
QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)

POINT
The Motion CPU cannot use the S. TO instruction, FROM instruction or intelligent
function module device.
Use "automatic refresh of the CPU shared memory" or "communication dedicated
instructions between multiple CPUs" to communicate between the High
Performance model QCPU and Motion CPU.
For the accessing method from the PC CPU module to the CPU shared memory,
refer to the manual of the PC CPU module command between multiple CPUs.

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MELSEC-Q

(2) Precautions
(a) The following values are set in the CPU module's first I/O number with the
FROM instruction, the S. TO instruction and instructions that use U \G .
PLC No. PLC No.1 PLC No.2 PLC No.3 PLC No.4
Value set in the first I/O number 3E0H 3E1H 3E2H 3E3H

(b) Do not perform writing as reading in the system area or automatic refresh
area for the CPU shared memory (see Section 16.4).
(c) An error will not occur when CPUs accessed with the FROM instruction, the
S. TO instruction and instructions that use U \G are reset.
However, access execution flag (SM390) will remain OFF when instruction
execution has been completed.
(d) Establish an interlock to prevent simultaneous access during interactive
data communication with the FROM instruction, the S. TO instruction and
instructions that use U \G .
There are cases where old data and new data will be mixed together if
simultaneous access is carried out.
(e) The instruction that uses the S. TO instruction/U \G cannot be used to
write data to the CPU shared memory of other PLCs.
"SP. UNIT ERROR (error code: 2115)" occurs if data is written to the CPU
shared memory of other CPUs with the instruction that uses U \G .
"SP. UNIT ERROR (error code: 2117)" occurs if data is written to the CPU
shared memory of other CPUs with the instruction that uses the S. TO
instruction.
(f) "SP. UNIT ERROR (error code: 2114)" also occurs if data is written into the
CPU shared memory of the host CPU with instructions that use U \G .
( g) "SP. UNIT ERROR (error code: 2114)" occurs if data is read from the CPU
shared memory of the host CPU with the FROM instruction and instructions
that use U \G .
(h) "SP. UNIT ERROR (error code: 2110)" also occurs if access is attempted
on a non-mounted CPU with instructions that use U \G .

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16.3 Interactive Communications between The High Performance model QCPU and Motion
CPU

16.3.1 Control commands from the High Performance model QCPU to the Motion CPU

It is possible to issue control commands from the High Performance model QCPU to
the Motion CPU, and read and write device data with the Motion dedicated CPU
instructions listed below.
(Control commands from Motion CPU to Motion CPU can not be used.)

Instruction name Description

S.SFCS
Requests startup of the motion SFC program.
SP.SFCS
S.SVST
Requests the start of operations for the servo program.
SP.SVST
S.CHGV
Changes the speed of the axes during positioning and JOG operations.
SP.CHGV
S.CHGT Changes the torque control value during operation and suspension when in
SP.CHGV the real mode.
S.CHGA Changes the current values of the halted axes, the synchronized encoder,
SP.CHGA and the cam axes.

For example, it is possible to start up the Motion CPU's motion SFC from the High
Performance model QCPU with the S (P).SFCS instruction.

High Performance model QCPU Motion SFC

Startup
request Motion SFC

S.SFCS instruction

POINT
One High Performance model QCPU module can operate up to 32 " Motion
dedicated CPU instructions " and "communication dedicated commands between
multiple CPUs (omitting the S (P).GINT instruction)" at one time. However, if the
Motion dedicated CPU instructions and communication dedicated instructions
between multiple CPUs (omitting S (P).GINT instruction) are made at the same
time, the instructions will be executed in order from the first instruction accepted. If
there are 33 or more unexecuted instructions, an "OPERATION ERROR (error
code: 4107)" will be triggered.

REMARK
Refer to the Motion CPU Programming manual for details on and the necessity of
use of the motion only instructions.

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16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU
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MELSEC-Q

16.3.2 Reading and writing device data

It is possible to read and write device data into the Motion CPU from the High
Performance model QCPU with the communication dedicated instructions between
multiple CPUs listed in the table below.
(Reading or writing can not take place from the High Performance model QCPU to the
High Performance model QCPU, the High Performance model QCPU to PC CPU
module, Motion CPU to the High Performance model QCPU, or Motion CPU to Motion
CPU.)

CPU module
Instruction name Description Motion PC CPU
CPU module
S.DDWR
Writes host CPU device data into other CPU devices.
SP.DDWR
S.DDRD
Reads other CPU device data into the host CPU.
SP.DDRD
S.GINT
Requests start up of other CPU interruption programs.
SP.GINT

For example, High Performance model QCPU device data can be written into the
Motion CPU's device data with the S.DDWR instruction of the communication
dedicated instruction between multiple CPUs.
High Performance model QCPU Motion CPU

S.DDWR instruction
Writes in the
device memory
Reads the device
memory
Device memory Device memory

POINT
One High Performance model QCPU can operate up to 32 " Motion dedicated CPU
instructions " and "communication dedicated commands between multiple CPUs
(omitting the S (P).GINT instruction)" at one time. However, if the Motion dedicated
CPU instructions and communication dedicated instructions between multiple
CPUs (omitting S (P).GINT instruction) are made at the same time, the instructions
will be executed in order from the first instruction accepted. If there are 33 or more
unexecuted instructions, an "OPERATION ERROR (error code: 4107)" will be
triggered.

REMARK
Refer to the Motion CPU Programming Manual for details on and the necessity of
use of the communication dedicated instructions between multiple CPUs.
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16.4 CPU Shared Memory

The CPU shared memory is for exchanging data between CPU modules, and consists
of 4,096 words between 0H and FFFH.

The CPU shared memory consists of four areas; the host CPU operation information
area, the system area, the automatic refresh area, and the user's free area.
An area consisting of the number of automatic refresh points from 800H is used as the
automatic refresh area when the automatic refresh of device data is set up.
The beginning of the user's free area starts from the address immediately after the end
of the automatic refresh area.
800H to 811H becomes the automatic refresh area if the number of automatic refresh
points is 18 (11H points,) and the area after 812H becomes the user's free area.
The configuration of the CPU shared memory and the necessity of accessing
sequence programs are shown in the illustration below.
Host CPU Other CPUs
CPU shared memory Writing 1 Reading Writing Reading 2

0H
Host CPU operation
to Disable Disable Disable Enable
information area
1FFH
200H
to System area Disable Disable Disable Disable
7FFH
800H
Automatic refresh area Disable Disable Disable Disable

to
User's free area Enable Disable Disable Enable

FFFH

REMARK
1: Use the S. TO instruction to write the free user area of the host CPU from the
High Performance model QCPU.
The Motion CPU is not provided with a S. TO instruction, so that it cannot write
in the free user area of the host CPU.
For the writing method from the PC CPU module to the free user area of the
host PLC, refer to the manual of the PC CPU module.
2: To read from the High Performance model QCPU, use the FROM instruction or
intelligent function module device (U \G ).
Because the Motion CPU is not provided with the FROM instruction or
intelligent function module device, data cannot be read from the Motion CPU.
For reading from the PC CPU module, refer to the manual of the PC CPU
module.

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(1) Host CPU operation information area (0H to 1FFH)

(a) The following information is stored in the host CPU with multiple CPU
system. These will all remain as 0 and will not change in the case of single
CPU system. 1

Table 16.1 List of host CPU operation information area

CPU shared
2 Corresponding
memory Name Detail Description
special register
address
The area to confirm if information is stored in the host CPU's
operation information area (1H to 1FH,) or not.
Information Information • 0: Information not stored in the host CPU's operation
0H —
availability availability flag information area
• 1: Information stored in the host CPU's operation information
area
Diagnostic error
1H Diagnostic error The numbers of errors during diagnostics is stored with BIN. SD0
number
The year and month that the error number was stored in the
2H CPU shared memory's 1H address is stored with two digits of the SD1
BCD code.
The day and time that the error number was stored in the CPU
Time the diagnosis Time the diagnosis
3H shared memory's 1H address is stored with two digits of the BCD SD2
error occurred error occurred
code.
The minutes and seconds that the error number was stored in
4H the CPU shared memory's 1H address is stored with two digits of SD3
the BCD code.
Stores an identification code to determine what error information
Error information Error information
5H has been stored in the common error information and individual SD4
identification code identification code
error information.
6H SD5
Common error Common error The common information corresponding with the number of the
to to
information information error during diagnostic is stored.
10H SD15
11H SD16
Individual error Individual error The individual information corresponding with the number of the
to to
information information error during diagnostic is stored.
1BH SD26
1CH Empty — Cannot be used —
1DH Switch status CPU switch status Stores the CPU module switch status. SD200
1EH LED status CPU-LED status Stores the CPU module's LED bit pattern. SD201
CPU operation CPU operation
1FH Stores the CPU module's operation status. SD203
status status

(b) The host CPU's operation information area is updated when the contents of
the corresponding register change. However, there are times when changes
in the corresponding register are relayed by a maximum of 200ms when the
High Performance model QCPU's scan time is 200ms or less.
There are times when changes in the corresponding register are delayed
by 200ms or more if the High Performance model QCPU's scan time
exceeds 200ms.
(c) The High Performance model QCPU of another CPU can use FROM
instruction or intelligent function module device to read data from the action
data area of the host CPU.
However, because there is a delay in data updating, use the read data for
monitoring purposes.

REMARK
1: For the Motion CPU, 5H to 1CH of the host CPU's operation information area is
not used. If 5H to 1CH of the host CPU's operation information area is read from
the Motion CPU, it will be read as "0."
2: Refer to the corresponding special registers for further details.
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16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU
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(2) System area (200H to 7FFH)

The area used by the High Performance model QCPU, Motion CPU and PC CPU
module systems (OS.) This is used by the OS when communication dedicated
instructions between multiple PLCs are executed.

(3) Automatic refresh area

The area used when the multiple CPU system is automatically refreshed. Writing
is not enabled with the S. TO instruction, and reading is not enabled with the
FROM instruction or intelligent function module device (U \G ).

(4) User's free area

The area for performing communication between CPU modules with the multiple
CPU system's S. TO instruction, FROM instruction and intelligent function
module device (U \G ).
The area used after the number of points set for automatic refresh is used.
(An area between 800H and FFH can be used as the user's free area when
automatic refresh is not being performed.)

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 17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O
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MELSEC-Q

17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O

MODULES AND INTELLIGENT FUNCTION MODULES

17.1 Range of Control CPU Communications

The relationship between control CPUs and control modules (I/O modules, intelligent
function modules, special function modules) is the same as with independent CPU
systems.
There is no restriction to control the control module with the control CPU.

17.2 Range of Non-control CPU Communications

It is possible for non-control CPUs to read the contents of the intelligent function
module's buffer memory.
It is also possible to load non-control module input (X) ON/OFF data and another CPU
module output (Y) ON/OFF data with the CPU parameters.
Input modules, composite I/O module controlled by other CPUs can be used as
interlocks for the host CPU, and the output status to external equipment being
controlled by other CPUs can be confirmed.
However, it is not possible for non-control CPUs to output ON/OFF data to output
modules, composite I/O module or intelligent function modules, or write in the buffer
memory of intelligent function modules.

17

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17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O
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(1) Loading input (X) from input modules and intelligent function
modules
The "Out of group input/output settings" setting in the PLC parameter's multiple
CPU settings determines whether input can be loaded from input modules and
intelligent function modules being controlled by other CPUs.
I/O sharing when using Multiple CPUs
All CPUs can read all inputs
All CPUs can read all outputs

(a) When "Load input condition outside of group" has been set
1) Loads ON/OFF data from the input and intelligent function modules
being controlled by the other CPUs by performing input refresh before
a sequence program calculation starts.
2) Input (X) loading is performed for the modules mounted onto the
following additional base unit slots.
I/O allocation type Mounted module Remarks
Input module —
None
Intelligent function module —
Input module —
Input 17
Output module Loads OFF data
Intelli. Intelligent function module —

3) It is possible to load ON/OFF data from input modules and intelligent

function modules with direct access input.
4) Remote station input, such as empty slots, MELSECNET/H and CC-
Link, cannot be loaded.
Use automatic refresh of device data to use the ON/OFF input data for
MELSECNET/H, CC-Link and other remote stations in other CPUs.
(b) When "Do not load input condition outside of group" has been set
It is not possible to loads ON/OFF data from input modules and intelligent
function modules being controlled by other CPUs (remains at OFF.)

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17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O
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MELSEC-Q

(2) Loading output (Y)

The "Out of group input/output settings" setting in the PLC parameter's multiple
CPU settings determines whether output can be loaded from output modules and
intelligent function modules being controlled by other CPUs.
I/O sharing when using Multiple CPUs
All CPUs can read all inputs
All CPUs can read all outputs

(a) When "Load output condition outside of group" has been set
1) Loads to the host CPU's output (Y) the ON/OFF data that is output to
the output and intelligent function modules by the other CPUs by
performing output refresh before a sequence program calculation
starts.
2) Output (Y) loading is performed for the modules mounted onto the
following additional base unit slots.
I/O allocation type Mounted module
Output module
None
Intelligent function module
Input module
Output Output module
Composite I/O module
Intelli. Intelligent function module

3) It is possible to load output ON/OFF data being controlled by other

CPUs with direct access output.
4) Remote station output, such as empty slots, MELSECNET/H and CC-
Link, cannot be loaded.
Use automatic refresh of CPU shared memory and send the ON/OFF
output data for remote stations to use the ON/OFF output data for
MELSECNET/H, CC-Link and other remote stations in other CPUs.
(b) When "Do not load output condition outside of group" has been set
It is not possible to load ON/OFF data output to output modules and
intelligent function modules by other PLCs into the host CPU's output (Y)
(remains at OFF.)

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(3) Output to output modules and intelligent function modules

It is not possible to output ON/OFF data to non-control modules.
ON/OFF will be performed within the High Performance model QCPU when the
output from output modules and intelligent function modules controlled by other
PLCs, such as sequence programs, have been set to ON/OFF, but this will not
be output to output modules or intelligent function modules.

(4) Accessing the intelligent function module buffer memory

(a) It is possible to read data from the buffer memory of intelligent function
modules being controlled by other CPUs with the commands listed below.
• FROM command
• Commands that use intelligent function module devices (U \G )
0 1 2 3 4 5 6 7 Slot No.
CPU module No.1

CPU module No.2

module

function module

function module
Input module

Input module
Output module

Output module
Power supply

function module
Intelligent

Intelligent

Intelligent
Intelligent
module

function
CPU No.1

CPU No.1

CPU No.1

CPU No.1

CPU No.2

CPU No.2

CPU No.2
Control CPU
settings

Readable from the buffer memory

with the FROM command and U \G

Readable from the buffer memory with the

FROM command and U \G

(b) It is not possible to write in the buffer memory of intelligent function modules
being controlled by other CPUs.
• TO instruction
• Intelligent function module devices (U \G )
• Intelligent function modules dedicated commands
An "SP UNIT ERROR (error code: 2116)" will be triggered if an attempt to
write in the intelligent function module controlled by other CPUs is carried
out.
0 1 2 3 4 5 6 7 Slot No.
CPU module No.1

CPU module No.2

Output module

Output module
function module

function module

function module
Input module

Input module
Power supply

Intelligent

Intelligent

Intelligent
module

CPU No.1

CPU No.1

CPU No.1

CPU No.1

CPU No.2

CPU No.2

CPU No.2

Control CPU
settings

Not writable write in the buffer

memory with the TO command
and U \G

Not writable write in the buffer memory

with the TO command and U \G

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17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O
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(5) Accessing MELSECNET/H modules

Only control PLCs can access MELSECNET/H modules.
Link direct devices cannot be used in MELSECNET/H modules being controlled
by other CPUs.
"OPERATION ERROR (error code: 4102)" occurs if a program that uses link
direct devices is used in MELSECNET/H modules being controlled by other
CPUs.

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18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM HIGH
PERFORMANCE MODEL QCPUs
MELSEC-Q

18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM HIGH

PERFORMANCE MODEL QCPUs

18.1 Concept behind CPU Scanning Time

The concept behind multiple CPU system scanning time is the same as the single CPU
system.
See Section 11.1 for details of the scan time concept.
This chapter provides explanations on the factors to be added to the scan time
calculated as explained in Section 11.1 and the method of calculating processing time
when configuring multiple CPU system.

(1) I/O refresh time

Input refresh time is calculated in accordance with the equation explained in
Section 11.1.
The I/O refresh time for the following values only are prolonged when bus access
overlaps with other CPUs.
(input points + output points)
(Prolonged time) = N3 (number of other CPUs) ( s)
16

Use the following values for N3

N3
CPU type Systems with only a main base Systems that include additional
unit base units
Q02CPU
Q02HCPU, Q06HCPU 8.7 s 21 s
Q12HCPU, Q25HCPU

(2) Total value of command execution time

Refer to the following manual for details on the processing time of special
18
multiple CPU commands, and the processing time for commands that have
different processing times with multiple CPU system.
• QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)

(3) END process

The following tables shows the END processing time.
CPU type END processing time
Q02CPU 0.42 ms
Q02HCPU, Q06HHCPU, Q12HCPU, Q25HCPU 0.19 ms

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PERFORMANCE MODEL QCPUS
MELSEC-Q

18.2 Factor to Prolong the Scan Time

The processing time for multiple CPU system is prolonged in comparison with single
CPU system when the following functions are used.
Add the following values to the values calculated in Sections 11.1 and 18.a to acquire
the amount of time used by these functions.
• Multiple CPU system automatic refresh
• MELSECNET/H refreshing
• CC-Link automatic refresh

(1) Automatic refresh of CPU shared memory

(a) The amount of time required to perform the refresh function set up with the
multiple CPU settings.
This value is the total amount of time required for writing into the host
CPU's CPU shared memory, and the amount of time required to read from
other CPUs' CPU shared memories.
These values are added when setting up the refresh settings with the PLC
parameter multiple CPU settings.
(b) The automatic refresh period of the CPU shared memory is calculated in the
following equation.
(Automatic refresh time) = (N1 + (received word points) N2) (number of other
CPUs) + (N3 + (transmitted word points) N4) ( s)
• The received word points must equal the word points transmitted by other CPUs.
For example, if the host CPU is the CPU No.1, then this value must equal the number of
points transmitted for the CPU No.2 to CPU No.4.
• Use the following values for N1 to N4.

CPU type N1 N2 N3 N4
Q02CPU 82 s 0.52 s 106 s 0.17 s
Q02HCPU, Q06HCPU, Q12CPU, Q25HCPU 27 s 0.44 s 27 s 0.08 s

18 (c) The amount of time required for the automatic refresh process will be
prolonged by the following amount of time when processing is duplicated
with the automatic refresh function on other PLCs.
(Prolonged time) = (transmitted/received word point) N5
(number of other CPUs) ( s)

Use the following values for N5

N5
CPU type Systems with only a main base Systems that include additional
unit base units
Q02CPU
Q02HCPU, Q06HCPU 0.54 s 1.3 s
Q12HCPU, Q25HCPU

18 - 2 18 - 2
18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM HIGH
PERFORMANCE MODEL QCPUS QCPUS
MELSEC-Q

(2) MELSECNET/H refresh

(a) The amount of time required for performing the refresh process between
High Performance model QCPU and MELSECNET/H network modules.
Refer to the following manual for details on the refresh time for
MELSECNET/H.
• Q Corresponding MESLECNET/H Network System Refresh Manual
(b) The amount of time required for the automatic refresh process will be
prolonged only by the following amount of time when requests for
refreshing are issued by other MELSECNET/H modules at the same time
on a multiple CPU system.
(Prolonged time) = (transmitted/received word point) N5
(number of other CPUs) ( s)
The number of words transmitted/received is the total value of the following transferal data.
(LB + LX + LY + SB)
• Link refresh data : + LW
16
(LB + LX + LY + SB)
• Data transferred to the memory card's file register : + LW
16
LB
• Transferal between data links :( + LW) 2
16
Refer to the following table for N5

N5
CPU type Systems with only a Systems that include
main base unit additional base units
Q02CPU
0.54 s 1.30 s
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU

(3) CC-Link automatic refresh

(a) The amount of time required for performing the refresh process between
High Performance model QCPU and CC-Link master local modules.
Refer to the following manual for details on the automatic refresh time for
CC-Link.
• QJ61BT11 CC-Link System Master Local Module User's Manual
(c) The amount of time required for the automatic refresh process will be
prolonged only by the following amount of time when requests for
refreshing are issued by other CC-Link modules at the same time on a
multiple CPU system.
(Prolonged time) = (transmitted/received word point) N5
(number of other CPUs) ( s)
The amount of data transmitted/received is the following transferal data.
(RX + RY + SB)
• Link refresh data : + SW
16
Refer to the following table for N5

N5
CPU type Systems with only a Systems that include
main base unit additional base units
Q02CPU
0.54 s 1.30 s
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU

18 - 3 18 - 3
 19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

19 STARTING UP THE MULTIPLE CPU SYSTEM

This Chapter explains the standard procedures for starting up the multiple CPU
system.

19.1 Flow-chart for Starting Up the Multiple CPU System

Start

Clarification of function sharing in multiple

•••••••••••••••••••• Clarify the control and functions executed by each CPU.
CPU system

Purpose of each device and allocation •••••••••••••••••••• To use automatic refresh of CPU share memory,
reserve continuous refresh points.
For automatic refresh of CPU share memory, see
section 16.1.
Selection of module to be used •••••••••••••••••••• Select the modules for realizing the functions executed in
the multiple CPU system.

Installation of module •••••••••••••••••••• Install the selected module to the main base unit and
expansion base units.

GX Developer startup •••••••••••••••••••• Start the GX Developer Version 6 or later.

For the starting method, refer to the GX Developer
operating manual.
Multiple CPU setting, control CPU setting
and other parameter settings. •••••••••••••••••••• Create parameters and sequence programs for CPU No.1
Creation of sequence programs to No.4. For multiple CPU settings and control CPU
settings, see sections 16.1 and 19.2. For automatic
refresh of device data, see section 16.1.
PLC power-ON •••••••••••••••••••• Select STOP at the RUN/STOP switch of the QCPU and
turn off the RESET/L.CLR switch and turn on the CPU.

Connection of PC and QCPU (CPU No.1) 1 •••••••••••••••••••• Connect the PC from which GX Developer has been
started, and the QCPU with the QCPU of the CPU No.1
using RS-232 cable or USB cable.

Parameter and program writing •••••••••••••••••••• Write parameters and sequence programs to the CPU
No.1. For CPU No.2 to No.4, select and write the
applicable CPU according to the connection destination
19 designation.
CPU No.1 QCPU resetting •••••••••••••••••••• Set the RESET/L. CLR switch of the QCPU of the CPU
No.1 in the RESET position.

1) 1: For systems with a PC CPU module, install GX Developer Version 7 or later

to the PC CPU module to connect the High Performance QCPU with GX
Developer via the bus.
Refer to the GX Developer Version 7 or later operating manual for details.

19 - 1 19 - 1
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

1)

RUN/STOP switch setting of all CPUs •••••••••••••••••••• Select RUN at the RUN/STOP switch of the QCPU for CPU
No.1 to No.4.

Cancellation of resetting of QCPU of

•••••••••••••••••••• Set the RESET/L. CLR switch of the QCPU for the CPU No.1
CPU No.1
in the OFF position to cancel resetting.

Check to see if a RUN status error has occurred with all

Status confirmation of all CPUs •••••••••••••••••••• PLCs on the mulitple CPU system when the reset status
for the CPU No.1 is canceled.

Confirmation and recovery of errors •••••••••••••••••••• If errors occurs, confirm the details and recover the situation
with the GX Developer's system monitor.

All CPUs debugged •••••••••••••••••••• CPU No.1 to CPU No.4 on the multiple CPU system debugged
individually.

Start of actual operations

19

19 - 2 19 - 2
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

19.2 Setting Up the Multiple CPU System Parameters (Multiple CPU Settings, Control CPU
Settings)

This section explains the procedures for setting up the multiple CPU system
parameters with GX Developer.
Refer to the GX Developer's operation manual for details on setting up all other
parameters.

19.2.1 System configuration

The following shows an example procedures for setting up the multiple CPU system
parameters.

GX Developer
Power supply module

No.1 output module

No.2 output module

CPU module No.1

CPU module No.2

CPU module No.3

CPU module No.4

No.1 input module

No.2 input module

function module
No.1 intelligent
Power supply module

No.3 output module

No.4 output module

No.3 input module

No.4 input module

function module
No.2 intelligent

19 - 3 19 - 3
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

19.2.2 Creating new systems

Start

GX Developer started up Refer to GX Developer operating manual

PC parameter window on the Refer to GX Developer operating manual

GX Developer opened

Select "Multiple CPU Settings" to display the multiple CPU

setup window.

Setting the number of CPUs (required item)

• Sets the number of CPU modules to be
mounted onto the main base unit with the
multiple CPU system.

1)

19 - 4 19 - 4
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

1)

Setting the operating mode (optional)

• Selects whether to halt operations for all CPUs
or continue with operations when a stop error occurs.
Default: Stop all PLCs upon a stopping error at CPU
No.2, No.3 or No.4.
(No check).
• For example, if the tick beside the "All station stop by stop
error of CPU2" is removed, the operations for
all other CPUs will continue even when an error occurs
in the CPU No.2.
• The operation mode for the CPU No.1 cannot be changed.

Out of the group input/output settings (optional)

• Sets whether or not the I/O status of non-control
PLCs are acquired.
Default:Default: Do not acquire.
(No check)

Multiple CPU system (optional)

• Sets the device and number of CPU share memory G points
to perform data communications with the automatic refresh
process between CPU modules.
• This is linked from the device number set with the first device to
the number of CPU share memory G points and used.
The 1st CPU share memory G point occupies the points shown
in the table below.
Device Points occupied
B, M, Y 16 points
D, R, ZR 1 point

2)

19 - 5 19 - 5
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

2)

Selects "CPU (Empty)" for the slots on which CPU

modules are not to be mounted by type.
Select "Detailed Settings" on the I/O assignment window
to display the detail settings window.

Control CPU settings (required item)

• Selects the control CPUs (CPU No.1 to No.4) for
each slot.
• Function version A intelligent function modules set the
control CPU No.1.
• Output modules and special function modules that support
the AnS series set a single CPU in all slots.

Setup of parameters other than

the multiple CPU system settings.

Set parameters written onto the hard disk

or floppy disk.

End

19 - 6 19 - 6
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

19.2.3 Using existing preset multiple CPU settings and I/O allocations

Start

GX Developer started up Refer to the GX Developer's operation manual

Opens the GX Developer's PC parameter setup window.

Select "Multiple CPU settings" to display the multiple CPU
setup window.

Transferring multiple CPU settings

Click on "Diversion multiple CPU parameters."

Setting up transferred projects

• Select the project into which existing multiple CPU settings
and I/O allocations are to be transferred.
• Click on "Open."

1)

19 - 7 19 - 7
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q
1)

The multiple CPU settings and I/O Assignment Setting data are
read and written into the specified project when "OK" is selected.

Confirming the multiple CPU settings

When changing the CPU devices in the "Refresh settings",
enter the device number after it has been changed.
(" " indicates the item can be changed.)

Confirm the I/O Assignment and standard settings on the

I/O Allocation Window.
Select "Detailed Settings" to display the detailed
setting window.

Confirm the control CPU settings.

2)

19 - 8 19 - 8
19 STARTING UP THE MULTIPLE CPU SYSTEM
MELSEC-Q

2)

Setup of parameters other than

the multiple CPU system settings.

Set parameters written onto the hard disk

or floppy disk.

End

19 - 9 19 - 9
APPENDICES
MELSEC-Q

APPENDICES

APPENDIX 1 Special Relay List APP

Special relays, SM, are internal relays whose applications are fixed in the PLC.
For this reason, they cannot be used by sequence programs in the same way as the normal
internal relays.
However, they can be turned ON or OFF as needed in order to control the CPU module and
remote I/O modules.

The headings in the table that follows have the following meanings.
Item Function of Item
Number • Indicates the number of the special relay.
Name • Indicates the name of the special relay.
Meaning • Indicates the nature of the special relay.
Explanation • Contains detailed information about the nature of the special relay.
• Indicates whether the relay is set by the system or user, and, if it is set by the system, when
setting is performed.
<Set by>
S : Set by system
U : Set by user (in sequence program or test operation at a GX Developer)
S/U : Set by both system and user
<When set> indicated only if setting is done by system.
Each END : Set during each END processing
Set by (When set)
Initial : Set only during initial processing
(when power supply is turned ON, or when going from STOP to
RUN)
Status change : Set only when there is a change in status
Error : Set when error is generated
Instruction execution : Set when instruction is executed
Request : Set only when there is a user request
(through SM, etc.)
• Indicates special relay M9 corresponding to the ACPU.
Corresponding ACPU (Change and notation when there has been a change in contents)
M9 • Items indicated as "New" have been newly added for High performance model
QCPU/QnACPU.
• Indicates the corresponding CPU type name.
+Rem: Can be applied to all CPU types and MELSECNET/H remote I/O modules.
: Can be applied to all types of CPU
Corresponding CPU QCPU: Can be applied to High Performance model QCPU
QnA: Can be applied to QnA series and Q2ASCPU Series
Remote: Can be applied to the MELSECNET/H remote I/O modules.
Each CPU type name: Can be applied only to the specific CPU. (e.g. Q4ARCPU, Q3ACPU)

For details on the following items, refer to the following manuals:

• Networks • For Q Corresponding MELSECNET/H Network System Reference Manual
(PLC to PLC network)
• For Q Corresponding MELSECNET/H Network System Reference Manual
(Remote I/O network)
• For QnA/Q4AR MELSECNET/10 Network System Reference Manual
• SFC QCPU(Q Mode)/QnACPU Programming Manual (SFC)

POINT
(1) SM1200 to SM1255 are used for QnACPU.
These relays are vacant with QCPU.
(2) Special relays SM1500 and later are dedicated for Q4ARCPU.

App - 1 App - 1
 APPENDICES
MELSEC-Q

Special Relay List

(1) Diagnostic Information
APP Set by
Corresponding
Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
• ON if diagnosis results show error occurrence
(Includes when an annunciator is ON, and when an error
OFF : No error
SM0 Diagnostic errors is detected with CHK instruction) S (Error) New
ON : Error
• Stays ON subsequently even if normal operations
restored
• Comes ON when an error occurs as a result of self-
OFF : No self-diagnosis
Self-diagnosis diagnosis.
SM1 errors S (Error) M9008
error • Stays ON subsequently even if normal operations
ON : Self-diagnosis
restored
OFF : No error common +Rem
Error common information • When SM0 is ON, ON if there is error common
SM5 S (Error) New
information ON : Error common information
information
OFF : No error common
Error individual information • When SM0 is ON, ON if there is error individual
SM16 S (Error) New
information ON : Error common information
information
• Conducts error reset operation
SM50 Error reset OFF ON : Error reset U New
• See section 11.3 for further information
• ON if battery voltage at CPU module or memory card
OFF : Normal drops below rated value. Stays ON subsequently even
SM51 Battery low latch S (Error) M9007
ON : Battery low after normal operation is restored
• Synchronous with BAT. ALA/BAT. LED
OFF : Normal • Same as SM51, but goes OFF subsequently when
SM52 Battery low S (Error) M9006
ON : Battery low battery voltage returns to normal.
• Comes ON it a momentary power interruption of less
than 20ms occurred during use of the AC power supply
module, and reset by turning the power OFF, then ON.
OFF : AC/DC DOWN not • Comes ON if a momentary power interruption of less
AC/DC DOWN detected than 10ms occurred during use of the DC power supply QCPU
SM53 S (Error) M9005
detection ON : AC/DC DOWN module, and reset by turning power OFF, then ON.
detected
• Comes ON if a momentary power interruption of less
than 1ms occurred during use of the DC power supply QnA
module, and reset by turning power OFF, then ON.
• Goes ON if MINI (S3) link error is detected at even one of
OFF : Normal the installed AJ71PT32 (S3) modules.
SM54 MINI link errors S (Error) M9004 QnA
ON : Error Stays ON subsequently even after normal operation is
restored.
• ON when operation error is generated
OFF : Normal
SM56 Operation Errors • Stays ON subsequently even if normal operations S (Error) M9011
ON : Operation error
restored
• Comes ON even if there is only one output module with a
Blown fuse OFF : Normal blown fuse, and remains ON even after return to normal
SM60 S (Error) M9000
detection ON : Module with blown fuse • Blown fuse status is checked even for remote I/O station
output modules.
• Comes ON if there is a discrepancy between the actual +Rem
I/O modules and the registered information when the
I/O module OFF : Normal
SM61 power is turned on S (Error) M9002
verification error ON : Error
• I/O module verification is also conducted for remote I/O
station modules.
S
Annunciator OFF : Not detected
SM62 • Goes ON if even one annunciator F goes ON. (Instruction M9009
detection ON : Detected
execution)
• Goes ON if error is detected by CHK instruction. S
OFF : Not detected
SM80 CHK detection • Stays ON subsequently even after normal operation is (Instruction New
ON : Detected
restored. execution)
SM90 Corresponds to SD90 M9108
SM91 Corresponds to SD91 M9109
SM92 Startup of Corresponds to SD92 M9110
OFF : Not started • Goes ON when measurement of
SM93 watchdog timer Corresponds to SD93 M9111
(watchdog timer reset) step transition watchdog timer is
SM94 for step transition Corresponds to SD94 M9112
ON : Started commenced. U
SM95 (Enabled only Corresponds to SD95 M9113
(watchdog timer • Resets watchdog timer when it
SM96 when SFC Corresponds to SD96 M9114
started) goes OFF.
SM97 program exists) Corresponds to SD97 New
SM98 Corresponds to SD98 New
SM99 Corresponds to SD99 New

App - 2 App - 2
APPENDICES
MELSEC-Q

Special Relay List

(2) System information
Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
LED OFF • When this relay goes from OFF to ON, the LEDs
SM202 OFF ON : LED OFF U New
command corresponding to the individual bits at SD202 go off
S (Status
SM203 STOP contact STOP status • Goes ON at STOP status M9042
change)
S (Status
SM204 PAUSE contact PAUSE status • Goes ON at PAUSE status M9041
change)
STEP-RUN S (Status
SM205 STEP-RUN status • Goes ON at STEP-RUN status M9054
contact change)
PAUSE enable OFF : PAUSE disabled • PAUSE status is entered if this relay is ON when the
U M9040
coil ON : PAUSE enabled remote PAUSE contact goes ON
Device test
SM206 OFF : Device test not yet
request • Comes ON when the device test mode is executed on
executed S (Request) New Remote
acceptance GX Developer.
status ON : Device test executed
• When this relay goes from OFF to ON, clock data being
Clock data set OFF : Ignored
SM210 stored from SD210 to SD213 after execution of END U M9025
request ON : Set request
instruction for changed scan is written to the clock device.
OFF : No error • ON when error is generated in clock data (SD210 to
SM211 Clock data error S (Request) M9026
ON : Error SD213) value, and OFF if no error is detected.
• Displays clock data as month, day, hour, minute, and Q3A
Clock data OFF : Ignored
SM212 second at the LED display at front of CPU module. U M9027 Q4A
display ON : Display
(Enabled only for Q3ACPU and Q4ACPU) Q4AR
Clock data read OFF : Ignored • When this relay is ON, clock data is read to SD210 to
SM213 U M9028 +Rem
request ON : Read request SD213 as BCD values.
• Goes OFF when reset of the PLC No. 1 is canceled.
No. 1 CPU reset OFF : PLC No. 1 reset cancel • Comes ON when the PLC No. 1 is resetting (including
SM240
flag ON : PLC No. 1 resetting the case where the PLC is removed from the base).
The other PLCs are also put in reset status.
• Goes OFF when reset of the PLC No. 2 is canceled.
• Comes ON when the PLC No. 2 is resetting (including
No. 2 CPU reset OFF : PLC No. 2 reset cancel
SM241 the case where the PLC is removed from the base).
flag ON : PLC No. 2 resetting
The other PLCs result in "MULTI CPU DOWN" (error
code: 7000).
• Goes OFF when reset of the PLC No. 3 is canceled.
• Comes ON when the PLC No. 3 is resetting (including
No. 3 CPU reset OFF : PLC No. 3 reset cancel
SM242 the case where the PLC is removed from the base).
flag ON : PLC No. 3 resetting
The other PLCs result in "MULTI CPU DOWN" (error
code: 7000).
• Goes OFF when reset of the PLC No. 4 is canceled. QCPU
S (Status
• Comes ON when the PLC No. 4 is resetting (including New function
No. 4 CPU reset OFF : PLC No. 4 reset cancel change)
SM243 the case where the PLC is removed from the base). Ver. B
flag ON : PLC No. 4 resetting
The other PLCs result in "MULTI CPU DOWN" (error
code: 7000).
OFF : PLC No. 1 normal • Goes OFF when the PLC No. 1 is normal (including a
No. 1 CPU error
SM244 ON : PLC No. 1 during stop continuation error).
flag
error • Comes ON when the PLC No. 1 is during a stop error.
OFF : PLC No. 2 normal • Goes OFF when the PLC No. 2 is normal (including a
No. 2 CPU error
SM245 ON : PLC No. 2 during stop continuation error).
flag
error • Comes ON when the PLC No. 2 is during a stop error.
OFF : PLC No. 3 normal • Goes OFF when the PLC No. 3 is normal (including a
No. 3 CPU error
SM246 ON : PLC No. 3 during stop continuation error).
flag
error • Comes ON when the PLC No. 3 is during a stop error.
OFF : PLC No. 4 normal • Goes OFF when the PLC No. 4 is normal (including a
No. 4 CPU error
SM247 ON : PLC No. 4 during stop continuation error).
flag
error • Comes ON when the PLC No. 4 is during a stop error.

App - 3 App - 3
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
Max. loaded I/O OFF : Ignored • When this relay goes from OFF to ON, maximum loaded
SM250 U New +Rem
read ON : Read I/O number is read to SD250.
• After the head I/O number of the I/O module being
replaced is set in SD251 is set, on-line I/O module
replace ment is enabled when this relay is ON.
(Only one module can be replaced at each setting.)
OFF : No replacement • To replace an I/O module in the RUN status, use the Q2A (S1)
SM251 I/O change flag U (END) M9094
ON : Replacement program or a peripheral device to turn this relay ON; to Q3A
replace an I/O module in the STOP status, turn this relay Q4A
ON in the test mode of a peripheral device. Q4AR
• Do not switch between RUN and STOP status until I/O
module replacement is completed.
OFF : Replacement prohibited
SM252 I/O change OK • Goes ON when I/O replacement is OK. S (END) New
ON : Replacement enabled
• Effective for the batch refresh
All stations OFF : Refresh arrival station (also effective for the low speed cyclic) U (Every
SM254 New QCPU
refresh command ON : Refresh all stations • Designate whether to receive arrival stations only or to END)
receive all slave stations.
• Goes ON for standby network
OFF : Operative network
SM255 (If no designation has been made concerning active or S (Initial) New
ON : Standby network
MELSECNET/10 standby, active is assumed.)
module 1 OFF : Reads • For refresh from link to CPU (B, W, etc.) indicate whether
SM256 U New
information ON : Does not read to read from the link module.
OFF : Writes • For refresh from CPU to link (B, W, etc.), designate
SM257 U New
ON : Does not write whether to write to the link module.
• Goes ON for standby network
OFF : Operative network
SM260 (If no designation has been made concerning active or S (Initial) New
ON : Standby network
MELSECNET/10 standby, active is assumed.)
module 2 OFF : Reads • For refresh from link to CPU (B, W, etc.) indicate whether
SM261 U New
information ON : Does not read to read from the link module.
OFF : Writes • For refresh from CPU to link (B, W, etc.), designate
SM262 U New
ON : Does not write whether to write to the link module.
• Goes ON for standby network
OFF : Operative network
SM265 (If no designation has been made concerning active or S (Initial) New
ON : Standby network
MELSECNET/10 standby, active is assumed.)
module 3 OFF : Reads • For refresh from link to CPU (B, W, etc.) indicate whether
SM266 U New
information ON : Does not read to read from the link module.
OFF : Writes • For refresh from CPU to link (B, W, etc.), designate
SM267 U New
ON : Does not write whether to write to the link module.
• Goes ON for standby network
OFF : Operative network
SM270 (If no designation has been made concerning active or S (Initial) New
ON : Standby network
MELSECNET/10 standby, active is assumed.)
module 4 OFF : Reads • For refresh from link to CPU (B, W, etc.) indicate whether
SM271 U New
information ON : Does not read to read from the link module.
OFF : Writes • For refresh from CPU to link (B, W, etc.), designate
SM272 U New
ON : Does not write whether to write to the link module.
• Goes ON when a CC-Link error is detected in any of the
S (Status QCPU
installed QJ61QBT11. Goes OFF when normal operation New
change) Remote
OFF : Normal is restored.
SM280 CC-Link error
ON : Error • Goes ON when a CC-Link error is detected in any of the
installed A(1S)J61QBT11. Stays ON even after normal S (Error) New QnA
operation is restored.
Presence/absenc • ON if SFC program is correctly registered, and OFF if not
OFF : SFC program absent
SM320 e of SFC registered. S (Initial) M9100
ON : SFC program present
program • Goes OFF if SFC dedicated instruction is not correct.
• Initial value is set at the same value as SM320.
(Goes ON automatically if SFC program is present.)
• SFC program will not execute if this goes OFF prior to
Start/stop SFC OFF : SFC program stop SFC program processing S (Initial) M9101
SM321
program ON : SFC program start • Starts SFC program when this relay goes from OFF to U format change
ON.
• Stops SFC program when this relay goes from ON to
OFF.

App - 4 App - 4
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
• Initial value is set at ON or OFF depending on
parameters.
• When this relay is OFF, all execution status are cleared
from time SFC program was stopped; starts from the
SFC program OFF : Initial start initial step of block where the start request was made. S (Initial) M9102
SM322
start status ON : Restart • When this relay is ON, starts from execution block and U format change
execution step active at time SFC program was stopped.
(ON is enabled only when resumptive start has been
designated at parameters.)
• SM902 is not automatically designated for latch.
• When this relay is OFF, transition occurs at one scan/one
step, for all blocks.
Presence/absenc OFF : Continuous transition
• When this relay is ON, transition occurs continuously for
e of continuous not effective
SM323 all blocks in one scan. U M9103
transition for ON : Continuous transition
• In designation of individual blocks, priority is given to the
entire block effective
continuous transition bit of the block.
(Designation is checked when block starts.)
• When continuous transition is effective, goes ON when
Continuous OFF : When transition is S
continuous transition is not being executed; goes OFF
SM324 transition executed (Instruction M9104
when continuous transition is being executed.
prevention flag ON : When no transition execution)
• Normally ON when continuous transition is not effective.
When block stops, selects active step operation output.
Output mode at OFF : OFF S (Initial)
SM325 • All coil outputs go OFF when this relay is OFF. M9196
block stop ON : Preserves U
• Coil outputs are preserved when this relay is ON.
Selects the device status when the stopped CPU is run
SFC device clear OFF : Clear device
SM326 after the sequence program or SFC program has been U New
mode ON : Preserves device
modified when the SFC program exists.
Selects the output action of the step being held when a
Output during
OFF : OFF block is ended by executing the end step. S (Initial)
SM327 end step New
ON : Preserves • All coil outputs go OFF when this relay is OFF. U
execution
• Coil outputs are preserved when this relay is ON.
• Asynchronous mode
Mode where the operations for the low speed execution
Operation mode
type program are continued during the excess time.
for low speed OFF : Asynchronous mode
SM330 • Synchronous mode U (END) New
execution type ON : Synchronous mode
Mode where the operations for the low speed execution
program
type program are started from the next scan even when
there is the excess time.
Normal SFC Indicates whether the normal SFC program is being
OFF : Not executed
SM331 program executed or not.
ON : Being executed
execution status Used as an SFC control instruction execution interlock. QCPU
Program S (Status serial No.
New
execution Indicates whether the program execution management change) 04122 or
OFF : Not executed
SM332 management SFC program is being executed or not. later
ON : Being executed
SFC program Used as an SFC control instruction execution interlock.
execution status
• The status of the intelligent function module access
ON indicates completion of instruction executed immediately before is stored.
Access execution S (Status
SM390 intelligent function module (This data is overwritten when the intelligent function New QCPU
flag change)
access module access instruction is executed again.)
• Used by the user in a program as a completion bit.

App - 5 App - 5
APPENDICES
MELSEC-Q

Special Relay List

(3) System clocks/counters
Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
S
ON
SM400 Always ON • Normally is ON (Every END M9036
OFF processing)
S
ON
SM401 Always OFF • Normally is OFF (Every END M9037
OFF processing)
• After RUN, ON for 1 scan only. S
ON for 1 scan ON 1 scan
SM402 • This connection can be used for scan execution type (Every END M9038
only after RUN OFF programs only. processing)
• After RUN, OFF for 1 scan only. S
After RUN, OFF ON
SM403 1 scan • This connection can be used for scan execution type (Every END M9039
for 1 scan only OFF programs only. processing)
Low speed
execution type • After RUN, ON for 1 scan only. S
ON
SM404 program 1 scan • This connection can be used for low speed execution (Every END New
ON for 1 scan OFF type programs only. processing)
only after RUN
Low speed
execution type • After RUN, OFF for 1 scan only. S
ON
SM405 program 1 scan • This connection can be used for low speed execution (Every END New
After RUN, OFF OFF type programs only. processing)
for 1 scan only
• Repeatedly changes between ON and OFF at 5-ms
interval.
• When PLC power supply is turned OFF or a CPU module
0.01 second 0.005 sec. S (Status
SM409 0.005 sec. reset is performed, goes from OFF to start. New QCPU
clock change)
• Note that the ON-OFF status changes when the
designated time has elapsed during the execution of the
program.
0.05 sec.
SM410 0.1 second clock 0.05 sec. • Repeatedly changes between ON and OFF at each M9030
0.1sec.
designated time interval.
SM411 0.2 second clock 0.1sec. • When PLC power supply is turned OFF or a CPU module M9031
S (Status
reset is performed, goes from OFF to start.
0.5 sec. change)
SM412 1 second clock 0.5 sec. • Note that the ON-OFF status changes when the M9032
designated time has elapsed during the execution of the
1 sec.
SM413 2 second clock 1 sec. program. M9033
• Goes between ON and OFF in accordance with the
number of seconds designated by SD414.
• When PLC power supply is turned OFF or a CPU module
n sec. S (Status M9034 format
SM414 2n second clock n sec. reset is performed, goes from OFF to start.
change) change
• Note that the ON-OFF status changes when the
designated time has elapsed during the execution of the
program.
• Switches between ON and OFF in accordance with the
number of milliseconds designated by SD415.
• When PLC power supply is turned OFF or a CPU module
n(ms) S (Status
SM415 2n (ms) clock n(ms) reset is performed, goes from OFF to start. New QCPU
change)
• Note that the ON-OFF status changes when the
designated time has elapsed during the execution of the
program.
User timing clock
SM420 M9020
No.0
User timing clock • Relay repeats ON/OFF switching at fixed scan intervals.
SM421 M9021
No.1 • When PLC power supply is turned OFF or a CPU module S
User timing clock reset is performed, goes from OFF to start.
SM422 (Every END M9022
No.2 • The ON/OFF intervals are set with the DUTY instruction. processing)
User timing clock
SM423
No.3
DUTY n1 n2 SM420 M9023
User timing clock n2 n2
SM424 scan scan M9024
No.4
User timing clock n1
SM430 scan
No.5
User timing clock
SM431
No.6
S
User timing clock
SM432 • For use with SM420 to SM424 low speed programs. (Every END New
No.7
processing)
User timing clock
SM433
No.8
User timing clock
SM434
No.9

App - 6 App - 6
APPENDICES
MELSEC-Q

Special Relay List

(4) Scan information
Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
Low speed OFF : Completed or not S
• Goes ON when low speed execution type program is
SM510 program executed (Every END New
executed.
execution flag ON : Execution under way. processing)
• When this relay goes from OFF to ON, the module
Reads module OFF : Ignored
SM551 service interval designated by SD550 is read to SD551 to U New +Rem
service interval ON : Read
SD552.

(5) Memory cards

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
Memory card A OFF : Unusable
SM600 • ON when memory card A is ready for use by user S (Initial) New
usable flags ON : Use enabled
Memory card A OFF : No protect
SM601 • Goes ON when memory card A protect switch is ON S (Initial) New
protect flag ON : Protect
OFF : No drive 1
SM602 Drive 1 flag • Goes ON when drive 1 (card 1 RAM area) is present S (Initial) New
ON : Drive 1 present
OFF : No drive 2
SM603 Drive 2 flag • Goes ON when drive 2 (card 1 ROM area) is present S (Initial) New
ON : Drive 2 present
Memory card A OFF : Not used
SM604 • Goes ON when memory card A is in use S (Initial) New
in-use flag ON : In use
Memory card A OFF : Remove/insert enabled
• Goes ON when memory card A cannot be inserted or
SM605 remove/insert ON : Remove/insert U New
removed
prohibit flag prohibited
• Turned ON by user to enable the removal/insertion of
memory card.
Memory card OFF : Remove/insert
• Turned OFF by the system after the memory card is
SM609 remove/insert prohibited U/S New
removed. QCPU
enable flag ON : Remove/insert enabled
• This contact can be used only when SM604 and SM605
are OFF.
• Always ON S (Initial) New
Q2A (S1)
Memory card B OFF : Unusable
SM620 Q3A
usable flags ON : Use enabled • ON when memory card B is ready for use by user S (Initial) New
Q4A
Q4AR
• Always ON S (Initial) New QCPU
Q2A (S1)
Memory card B OFF : No protect
SM621 Q3A
protect flag ON : Protect • Goes ON when memory card B protect switch is ON S (Initial) New
Q4A
Q4AR
• Always ON S (Initial) New QCPU
Q2A (S1)
OFF : No drive 3
SM622 Drive 3 flag Q3A
ON : Drive 3 present • Goes ON when drive 3 (card 2 RAM area) is present S (Initial) New
Q4A
Q4AR
OFF : No drive 4 • Always ON S (Initial) New QCPU
SM623 Drive 4 flag
ON : Drive 4 present • Goes ON when drive 4 (card 2 ROM area) is present S (Initial) New
Memory card B OFF : Not used Q2A (S1)
SM624 • Goes ON when memory card B is in use S (Initial) New
in-use flag ON : In use Q3A
Memory card B OFF : Remove/insert enabled Q4A
• Goes ON when memory card B cannot be inserted or
SM625 remove/insert ON : Remove/insert U New Q4AR
removed
prohibit flag prohibited
OFF : File register not used S (Status
SM640 File register use • Goes ON when file register is in use New
ON : File register in use change)
OFF : File register not used S (Status
SM650 Comment use • Goes ON when comment file is in use New
ON : File register in use change)
OFF : Internal memory
execution • Goes ON while boot operation is in process S (Status
SM660 Boot operation New
ON : Boot operation in • Goes OFF if boot designation switch is OFF change)
progress
• Goes ON when access is made to area outside the range
Memory card A
OFF : Within access range of file register R of memory card A
SM672 file register S/U New
ON : Outside access range (Set within END processing.)
access range flag
• Reset at user program

App - 7 App - 7
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
• Goes ON when access is made outside the range of file Q2A (S1)
Memory card B
OFF : Within access range registers, R. of memory card B. Q3A
SM673 file register S/U New
ON : Outside access range (Set within END processing.) Q4A
access range flag
• Reset at user program Q4AR

(6) Instruction-Related Special Relays

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
S
OFF : Carry OFF
SM700 Carry flag • Carry flag used in application instruction (Instruction M9012
ON : Carry ON
execution)
• When SM701 is OFF, 16 characters of ASCII code are
Number of output
OFF : 16 characters output output.
SM701 characters U M9049
ON : Outputs until NUL • When SM701 is ON, output conducted until NUL (00H)
selection
code of ASCII code is encountered.
OFF : Search next • Designates method to be used by search instruction.
SM702 Search method U New
ON : 2-part search • Data must be arranged for 2-part search.
• The sort instruction is used to designate whether data
OFF : Ascending order
SM703 Sort order should be sorted in ascending order or in descending U New
ON : Descending order
order.
S
OFF : Non-match found • Goes ON when all data conditions have been met for the
SM704 Block comparison (Instruction New
ON : All match BKCMP instruction.
execution)
Selection of real • When SM707 is OFF, real number instructions are
number OFF : Speed oriented processed at high speed.
SM707 U New Q4AR
instruction ON : Accuracy oriented • When it is ON, real number instructions are processed
processing type with high accuracy.
CHK instruction S
OFF : Conditions priority • Remains as originally set when OFF.
SM710 priority ranking (Instruction New
ON : Pattern priority • CHK priorities updated when ON.
flag execution)
OFF : Other than during
Divided • In processing of AD57(S1), goes ON when screen is split S
divided processing
SM711 transmission for transfer, and goes OFF when split processing is (Instruction M9065
ON : During divided
status completed execution)
processing
Transmission S
OFF : Batch processing • In processing of AD57(S1), goes ON when canvas
SM712 processing (Instruction M9066
ON : Divided processing screen is divided for transfer.
selection execution)
OFF : Communication QnA
request to remote
Communication terminal module
• Used to determine whether communications requests to S
request enabled
SM714 remote terminal modules connected to the AJ71PT32-S3 (Instruction M9081
registration area ON : Communication
can be executed or not. execution)
BUSY signal request to remote
terminal module
disabled
S
OFF : During DI
SM715 EI flag • ON when EI instruction is being executed. (Instruction New
ON : During EI
execution)
OFF : Comment read not
Comment read completed • Switches ON for only one scan when COMRD or PRC S (Status
SM720 New
completion flag ON : Comment read instruction is completed. change)
completed
• Switches ON while a file is being accessed by the
File being OFF : File not accessed S (Status
SM721 S.FWRITE, S.FREAD, COMRD, PRC, or LEDC New QCPU
accessed ON : File being accessed change)
instruction.
OFF : Error detection
BIN/DBIN
performed • Turned ON when "OPERATION ERROR" is suppressed
SM722 instruction error U New
ON : Error detection not for BIN or DBIN instruction.
disabling flag
performed
OFF : Request for
communication with
BUSY signal for
intelligent device
CC-Link • Used for determination whether to enable or disable the S
station enabled
SM730 communication communication request for the intelligent device station (Instruction New QnA
ON : Request for
request connected with A(1S)J61QBT11. execution)
communication with
registration area
intelligent device
station disabled

App - 8 App - 8
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
PKEY instruction OFF : Instruction not • ON when PKEY instruction is being executed. S
SM736 execution in executed Goes OFF when CR is input, or when input character (Instruction New
progress flag ON : Instruction execution string reaches 32 characters. execution)
OFF : Keyboard input
Keyboard input S
reception enabled • Goes ON when keyboard input is being conducted.
SM737 reception flag for (Instruction New
ON : Keyboard input Goes when keyboard input has been stored at the CPU.
PKEY instruction execution)
reception disabled
OFF : Instruction not S
MSG instruction
SM738 executed • Goes ON when MSG instruction is executed. (Instruction New
reception flag
ON : Instruction execution execution)
PID bumpless
processing OFF : Forces match • In manual mode, designates whether or not to force the
SM774 U New
(for complete ON : Does not force match SV value to match the PV value.
derivative)

OFF : Performs link refresh • Selects whether only the general data process is
ON : Performs no link performed for the execution of the COM instruction or the U New
Selection of link
refresh link refresh process is also performed.
refresh
SM775 processing during QCPU
COM instruction OFF : Performs all refresh serial
execution processes • Selects whether all refresh process or the refresh set with
U New number
ON : Performs the refresh SD778 is performed when COM instruction is executed.
04012 or
set the SD778
later
Enable/disable
OFF : Local device disabled • Determines whether to enable/disable the local device in U (Status
SM776 local device at New
ON : Local device enabled the program CALLED at CALL. change)
CALL
Enable/disable
OFF : Local device disabled • Determines whether to enable/disable the local device at U (Status
SM777 local device in New
ON : Local device enabled the execution of interrupt programs. change)
interrupt program
OFF : CC-Link dedicated
CC-Link
instruction executable • Switches ON when the number of the CC-Link dedicated
dedicated U (Status
SM780 ON : CC-Link dedicated instructions that can be executed simultaneously reaches New QnA
instruction change)
instruction not 32. Switches OFF when the number goes below 32.
executable
executable
PID bumpless QCPU
processing OFF : Matched • Specifies whether the set value (SV) will be matched with serial No.
SM794 U New
(for incomplete ON : Not matched the process value (PV) in the manual mode. 05032 or
derivative) later

(7) Debug
Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
S (Status
Trace preparation • Switches ON when the trace preparation is completed. New QCPU
OFF : Not ready change)
SM800
Sampling trace ON : Ready S (Status
• Goes ON when sampling trace is ready New QnA
preparation change)
• Trace is started when this relay switches ON.
Trace start • Trace is suspended when this relay switches OFF. U M9047 QCPU
OFF : Suspend
SM801 (All related special Ms switches OFF.)
ON : Start
Sampling trace • Sampling trace started when this goes ON
U M9047 QnA
start • Suspended when OFF (Related special M all OFF)
Trace execution S (Status
• Switches ON during execution of trace. M9046 QCPU
in progress change)
OFF : Suspend
SM802 Sampling trace
ON : Start S (Status
execution in • Goes ON during execution of sampling trace M9046 QnA
change)
progress
• Trace is triggered when this relay switches from OFF to
Trace trigger U M9044 QCPU
ON. (Identical to TRACE instruction execution status)
SM803 OFF ON: Start • Sampling trace trigger goes ON when this goes from
Sampling trace
OFF to ON (Identical to STRA instruction execution U M9044 QnA
trigger
status)
S (Status
After trace trigger • Switches ON after trace is triggered. New QCPU
OFF : Not after trigger change)
SM804
After sampling ON : After trigger S (Status
• Goes ON after sampling trace trigger New QnA
trace trigger change)

App - 9 App - 9
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
S (Status
Trace completed • Switches ON at completion of trace. 9043 QCPU
OFF : Not completed change)
SM805
Sampling trace ON : End S (Status
• Goes ON at completion of sampling trace 9043 QnA
completed change)
Status latch OFF : Not ready S (Status
SM806 • Goes ON when status latch is ready New
preparation ON : Ready change)
Status latch
SM807 OFF ON: Latch • Runs status latch command U New
command QnA
Status latch OFF : Latch not completed S (Status
SM808 • Comes ON when status latch is completed. 9055
completion ON : Latch completed change)
SM809 Status latch clear OFF ON: Clear • Enable next status latch U New
Program trace OFF : Not ready S (Status
SM810 • Goes ON when program trace is ready New
preparation ON : Ready change)
Start program OFF : Suspend • Program trace started when this goes ON S (Status
SM811 New
trace ON : Start • Suspended when OFF (Related special M all OFF) change)
Program trace
OFF : Suspend
SM812 execution under • ON when program trace execution is underway U New
ON : Start
way QnA
Program trace • Program trace trigger goes ON when this goes from OFF S (Status
SM813 OFF ON: Start New
trigger to ON (Identical to PTRA instruction execution status) change)
After program OFF : Not after trigger S (Status
SM814 • Goes ON after program trace trigger New
trace trigger ON : After trigger change)
Program trace OFF : Not completed S (Status
SM815 • Goes ON at completion of program trace New
completion ON : End change)
Step trace OFF : Not ready
SM820 • Goes ON after program trace registration, at ready. U New
preparation ON : Ready
OFF : Suspend • When this goes ON, step trace is started S (Status M9182 format
SM821 Step trace starts
ON : Start • Suspended when OFF (Related special M all OFF) change) change
Step trace
OFF : Suspend • Goes ON when step trace execution is underway S (Status
SM822 execution M9181
ON : Start • Goes OFF at completion or suspension change)
underway
• Goes ON if even 1 block within the step trace being
After step trace OFF : Not after trigger S (Status
SM823 executed is triggered. New
trigger ON : Is after first trigger change)
• Goes OFF when step trace is commenced.
• Goes ON if all blocks within the step trace being
After Step trace OFF : Is not after all triggers S (Status
SM824 executed are triggered. New
trigger ON : Is after all triggers change)
• Goes OFF when step trace is commenced.
Step OFF : Not completed • Goes ON at step trace completion. S (Status
SM825 M9180
tracecompleted ON : End • Goes OFF when step trace is commenced. change)
S (Status
Trace error • Switches ON if error occurs during execution of trace. New QCPU
OFF : Normal change)
SM826
Sampling trace ON : Errors • Goes ON if error occurs during execution of sampling S (Status
New
error trace. change)
OFF : Normal S (Status
SM827 Status latch error • Goes ON if error occurs during execution of status latch. New QnA
ON : Errors change)
Program trace OFF : Normal • Goes ON if error occurs during execution of program S (Status
SM828 New
error ON : Errors trace. change)

(8) Latch area

Corresponding
Set by Applicable
Number Name Meaning Explanation ACPU
(When Set) CPU
M9
OFF : No power cut file • Goes ON if a file is present during access when power is S/U (Status
SM900 Power cut file New
ON : Power cut file present interrupted. change)
OFF : Keyboard input QnA
S
RKEY notregistered • Goes ON at registration of keyboard input.
SM910 (Instruction New
registration flag ON : Keyboard input OFF if keyboard input is not registered.
execution)
registered

App - 10 App - 10
APPENDICES
MELSEC-Q

(9) A to Q/QnA conversion correspondences

Special relays SM1000 to SM1255 are the relays which correspond to ACPU special relays
M9000 to M9255 after A to Q/QnA conversion.
All of these special relays are controlled by the system so that users cannot turn them
ON/OFF in the program.
If users want to turn these relays ON/OFF, the program should be modified to use
QCPU/QnACPU special relays.
For SM1084 and SM1200 through SM1255, however, if a user can turn ON/OFF some of
special relays M9084 and M9200 through M9255 before conversion, the user can also turn
ON/OFF the corresponding relays among SM1084 and SM1200 through SM1255 after the
conversion.
For details on the ACPU special relays, see the user's manuals for the individual CPUs, and
MELSECNET or MELSECNET/B Data Link System Reference Manuals.

POINT
The processing time may be longer when converted special relays are used with QCPU.
Uncheck "A-series CPU compatibility setting" within the PC system setting in GX Developer
parameters when converted special relays are not used.

REMARK
The following are additional explanations about the Special Relay for Modification column.
1 When a special relay for modification is provided, the device number should be changed to
the provided QCPU/QnACPU special relay.
2 When is provided, the converted special relay can be used for the device number.
3 When is provided, the device number does not work with QCPU/QnACPU.

Special Relay List

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
• Turned on when there is one or more output units of
which fuse has been blown.
OFF: Normal • Remains ON if the condition is restored to normal
M9000 SM1000 Fuse blown
ON : Module with blown fuse thereafter.
• Output modules of remote I/O stations are also checked
fore fuse condition.
• Turned on if the status of I/O module is different form
entered status when power is turned on.
• Remains ON if the condition is restored to normal
I/O module OFF: Normal thereafter.
M9002 SM1002
verification error ON : Error • I/O module verification is done also to remote I/O station
modules.
• Reset is enabled only when special registers SD1116 to
SD1123 are reset.
• Goes ON if MINI (S3) link error is detected at even one of
OFF: Normal the installed AJ71PT32 (S3) modules.
M9004 SM1004 NIMI link error QnA
ON : Error • Remains ON if the condition is restored to normal
thereafter.
• Turns ON if an instantaneous power failure of within
20ms occurs during use of the AC power supply module.
• Reset when power is switched OFF, then ON.
• Turns ON if an instantaneous power failure of within
AC DOWN OFF: AC DOWN not detected 10ms occurs during use of the DC power supply module.
M9005 SM1005
detection ON : AC DOWN detected • Reset when power is switched OFF, then ON.
• Turns ON if an instantaneous power failure of within 1ms
occurs during use of the DC power supply module. QnA
• Reset when power is switched OFF, then ON.

App - 11 App - 11
APPENDICES
MELSEC-Q

Special Relay List (Continued)

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
• Turns ON when the battery voltage drops to or below the
OFF: Normal specified.
M9006 SM1006 Battery low
ON : Battery low • Turns OFF when the battery voltage returns to normal
thereafter.
• Turns ON when the battery voltage drops to or below the
OFF: Normal specified.
M9007 SM1007 Battery low latch
ON : Battery low • Remains ON if the battery voltage returns to normal
thereafter.
Self-diagnosis OFF: No error • Turned on when error is found as a result of self-
M9008 SM1008 SM1
error ON : Error diagnosis.
• Turned on when OUT F of SET F instruction is
Annunciator OFF: No F number detected
M9009 SM1009 SM62 executed.
detection ON : F number detected
• Switched off when SD1124 data is zeroed.
• Turned on when operation error occurs during execution
Operation error OFF: No error of application instruction.
M9011 SM1011 SM56
flag ON : Error • Remains ON if the condition is restored to normal
thereafter.
OFF: Carry OFF
M9012 SM1012 SM700 Carry flag • Carry flag used in application instruction.
ON : Carry ON
• Clears the data memory including the latch range (other
Data memory OFF: lgnored
M9016 SM1016 than special relays and special registers) in remote run
clear flag ON : Output claered
mode from computer, etc. when SM1016 is on.
• Clears the unlatched data memory (other than special
Data memory OFF: lgnored
M9017 SM1017 relays and special egisters) in remote run mode from
clear flag ON : Output claered
computer, etc. when SM1017 is on.
User timing clock
M9020 SM1020
No.0
• Relay which repeats on/off at intervals of predetermined
User timing clock
M9021 SM1021 n2 n2 scan.
No.1 scan scan • When power is turned on or reset is per-formed, the clock
User timing clock starts with off.
M9022 SM1022
No.2 • Set the intervals of on/off by DUTY instruction.
n1
User timing clock scan
M9023 SM1023
No.3 DUTY n1 n2 SM1020
User timing clock
M9024 SM1024
No.4
• Writes clock data from SD1025 to SD1028 to the clock
Clock data set OFF: Ignored
M9025 SM1025 element after the END instruction is executed during the
request ON : Set request present used
scan in which SM1025 has changed from off to on.
OFF: No error
M9026 SM1026 Clock data error • Switched on by clock data (SD1025 to SD1028) error
ON : Error
• Clock data is read from SD1025 to SD1028 and month, Q3A
Clock data OFF: Ignored
M9027 SM1027 day, hour, minute and minute are indicated on the CPU Q4A
display ON : Display
module front LED display. Q4AR
Clock data read OFF: Ignored • Reads clock data to SD1025 to SD1028 in BCD when
M9028 SM1028
request ON : Read request SD1028 is on.
• The SM1029 relay is turned on using a sequence
program to process all data communication requests
accepted during one scan in the END processing of that
Batch processing OFF: Batch processing not
scan.
of data conducted
M9029 SM1029 • The batch processing of the data communication
communications ON : Batch processing
requests can be turned on and off during running.
requests conducted
• The default is OFF (processed one at a time for each
END processing in the order in which data
communication requests are accepted).
0.05
M9030 SM1030 0.1 second clock seconds 0.05
seconds

0.1 • 0.1 second, 0.2 second, 1 second and 2 second, clocks

M9031 SM1031 0.2 second clock seconds 0.1 are generated.
seconds
• Not turned on or off per scan but turned on and off even
0.5 during scan if corresponding time has elapsed.
M9032 SM1032 1 second clock seconds 0.5 • Starts with off when PLC power supply is turned on or
seconds
CPU module reset is performed.
1
M9033 SM1033 2 second clock seconds 1
seconds

: 1 minute clock indicates the name of the special relay (M9034) of the ACPU.

App - 12 App - 12
APPENDICES
MELSEC-Q

Special Relay List (Continued)

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
• Alternates between ON and OFF according to the
seconds specified at SD414. (Default: n = 30)
2n minute clock n • Not turned on or off per scan but turned on and off even
M9034 SM1034 (1 minute seconds n
seconds during scan if corresponding time has elapsed.
clock)
• Starts with off when PLC power supply is turned on or
CPU module reset is performed..
ON
M9036 SM1036 Always ON • Used as dummy contacts of initialization and application
OFF instruction in sequence program.
ON • SM1038 and SM1037 are turned on and off without
M9037 SM1037 Always OFF regard to position of key switch on CPU module front.
OFF
SM1038 and SM1039 are under the same condition as
ON for 1 scan ON RUN status except when the key switch is at STOP
M9038 SM1038 1 scan position, and turned off and on. Switched off if the key
only after RUN OFF
switch is in STOP position. SM1038 is on for one scan
RUN flag(After ON only and SM1039 is off for one scan only if the key switch
M9039 SM1039 RUN, OFF for 1 1 scan is not in STOP position.
scan only)
OFF
PAUSE enable OFF: PAUSE disabled
M9040 SM1040 SM206 • When RUN key switch is at PAUSE position or remote
coil ON : PAUSE enabled
pause contact has turned on and if SM204 is on, PAUSE
USE status OFF: PAUSE not in effect
M9041 SM1041 SM204 mode is set and SM206 is turned on.
contact ON : PAUSE in effect
STOP status OFF: STOP not in effect • Switched on when the RUN key switch or RUN/STOP
M9042 SM1042 SM203
contact ON : STOP in effect switch is in STOP position.
OFF: Sampling trace in • Turned on upon completion of sampling trace performed
Sampling trace progress the number of times preset by parameter after STRA
M9043 SM1043 SM805
completed ON : Sampling trace instruction is executed.
completed Reset when STRAR instruction is executed.
• Turning on/off SM803 can execute STRA / STRAR
instruction.
OFF ON STRA (SM803 is forcibly turned on/off by a peripheral device.)
Same as execution When switched from OFF to ON: STRA instruction
M9044 SM1044 SM803 Sampling trace
ON OFF STRAR When switched from ON to OFF: STRAR instruction
Same as execution The value stored in SD1044 is used as the condition for
the sampling trace.
At scanning, at time → Time (10 ms unit)
• The SM1015 relay is turned on to reset the WDT when
Watchdog timer OFF: Does not reset WDT the ZCOM instruction and data communication request
M9045 SM1045
(WDT) reset ON : Resets WDT batch processing are executed (used when the scan time
exceeds 200 ms).
OFF: Trace not in progress
M9046 SM1046 SM802 Sampling trace • Switched on during sampling trace.
ON : Trace in progress
OFF: Sampling trace • Sampling trace is not executed unless SM801 is turned
Sampling trace
M9047 SM1047 SM801 suspended ON.
preparations
ON : Sampling trace started • Sampling trace is suspended when SM801 goes OFF.
• When SM701 is OFF, characters up to NULL (00H) code
Selection of OFF: Output until NULL code
are output.
M9049 SM1049 SM701 number of encountered
• When SM701 is ON, ASCII codes of 16 characters are
characters output ON : 16 characters output
output.
• Switched ON to disable the CHG instruction.
CHG instruction OFF: Enabled
M9051 SM1051 • Switched ON when program transfer is requested.
execution disable ON : Disable
Automatically switched OFF when transfer is complete.
• When SM1052 is ON, the SEG instruction is executed as
SEG instruction OFF: 7SEG segment display an I/O partial refresh instruction.
M9052 SM1052
switch ON : I/O partial refresh • When SM1052 is OFF, the SEG instruction is executed
as a 7-SEG display instruction.
OFF: STEP RUN not in effect • Switched on when the RUN key switch is in STEP RUN
M9054 SM1054 SM205 STEP RUN flag
ON : STEP RUN in effect position.
QnA
Status latch OFF: Not completed • Turned on when status latch is completed.
M9055 SM1055 SM808
completion flag ON : Completed • Turned off by reset instruction.
OFF: Other than when P, I set
Main side P, I set
M9056 SM1056 being requested • Provides P, I set request after transfer of the other
request
ON : P, I set being requested program (for example subprogram when main program is
OFF: Other than when P, I set being run) is complete during run. Automatically switched
Sub side P, I set
M9057 SM1057 being requested off when P, I setting is complete.
request
ON : P, I set being requested

App - 13 App - 13
APPENDICES
MELSEC-Q

Special Relay List (Continued)

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
Main side P, I set Momentarily ON at P, I set
M9058 SM1058
completion completion • Turned ON once when the P, I set has been completed,
Sub program P, I Momentarily ON at P, I set and then turned OFF again.
M9059 SM1059
set completion completion
• Provides P, I set request after transfer of the other
OFF: Other than when P, I set
Sub program 2 P, program (for example subprogram when main program is
M9060 SM1060 being requested
I set request being run) is complete during run. Automatically switched
ON : P, I set being requested
off when P, I setting is complete.
• Provides P, I set request after transfer of the other
OFF: Other than when P, I set
Sub program 3 P, program (for example subprogram when main program is
M9061 SM1061 being requested
I set request being run) is complete during run. Automatically switched
ON : P, I set being requested
off when P, I setting is complete.
Divided
OFF: Divided processing not • Turned on when canvas screen transfer to
processing
M9065 SM1065 SM711 underway AD57(S1)/AD58 is done by divided processing, and
execution
ON : During divided processing turned off at completion of divided processing.
detection QnA
Divided
OFF: Batch processing • Turned on when canvas screen transfer to
M9066 SM1066 SM712 processing
ON : Divided processing AD57(S1)/AD58 is done by divided processing.
request flag
• Turned ON to shorten the search time in the
A8UPU/A8PUJre A8UPU/A8PUJ.
OFF: Read time not shortened
M9070 SM1070 quired search (In this case, the scan time is extended by 10 %.)
ON : Read time shortened
time The A8UPU/A8PUJ cannot be used in the
QCPU/QnACPU special relays.
OFF: Empty spaces in
Communication communication request
• Indication of communication enable/disable to remote
request registration area
M9081 SM1081 SM714 terminal modules connected to the AJ71PT32-S3, A2C QnA
registration area ON : No empty spaces in
or A52G.
BUSY signal communication request
registration area
• It is set whether the error checks below are performed or
not when the END instruction is processed (to set the
OFF: Error check executed END instruction processing time).
M9084 SM1084 Error check
ON : No error check • Check for breakage of fuse.
• Check of battery
• Collation check of I/O module
• Turns ON when the detail factor of the operation error is
Instruction error OFF: No error stored into SD1091.
M9091 SM1091
flag ON : Error • Remains ON if the condition is restored to normal
thereafter.
• The I/O module can be changed online when SM251 is
turned ON after the head I/O number of the I/O module to
be changed is set to SD251. (One module is only allowed
to be changed by one setting.)
OFF: Replacement • To be switched on in the program or peripheral device
M9094 SM1094 SM251 I/O change flag QnA
ON : No replacement test mode to change the module during CPU RUN. To be
switched on in peripheral device test mode to change the
module during CPU STOP.
• RUN/STOP mode must not be changed until I/O module
change is complete.
Presence/absenc
OFF: SFC programs not used • Turned on if the SFC program is registered, and turned
M9100 SM1100 SM320 e of SFC
ON : SFC programs used off if it is not.
program
• Should be turned on by the program if the SFC program
Start/stop SFC OFF: SFC programs stop is to be started. If turned off, operation output of the
M9101 SM1101 SM321
program ON : SFC programs start execution step is turned off and the SFC program is
stopped.
• Selects the starting step when the SFC program is
restarted using SM322.
ON: All execution conditions when the SFC program
stopped are cleared, and the program is started
with the initial step of block 0.
SFC program OFF: Initial Start OFF: Started with the step of the block being executed
M9102 SM1102 SM322
start status ON : Continue when the program stopped.
• Once turned on, the program is latched in the system and
remains on even if the power is turned off.
Should be turned off by the sequence program when
turning on the power, or when starting with the initial step
of block 0.

App - 14 App - 14
APPENDICES
MELSEC-Q

Special Relay List (Continued)

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
• Selects consecutive or step-by-step transfer of steps of
OFF: Continuous transition not
Presence/absenc which transfer conditions are established when all of the
effective
M9103 SM1103 SM323 e of continuous transfer conditions of consecutive steps are established.
ON : Continuous transition
transition ON: Consecutive transfer is executed.
effective
OFF: One step per one scan is transferred.
• OFF during operation in the continuous transition mode
Continuous OFF: When transition is or during continuous transition, and ON when continuous
M9104 SM1104 SM324 transition completed transition is not executed.
suspension flag ON : When no transition • Always ON during operation in the no continuous
transition mode.
Step transition
watchdog timer
M9108 SM1108 SM90
start (equivalent
of D9108)
Step transition
watchdog timer
M9109 SM1109 SM91
start (equivalent
of D9109)
Step transition
watchdog timer
M9110 SM1110 SM92
start (equivalent
of D9110)
Step transition • Turns ON when the measurement of the step transition
OFF: Watchdog timer reset
watchdog timer watchdog timer is started.
M9111 SM1111 SM93 ON : Watchdog timer reset
start (equivalent Turning this relay OFF resets the step transition
start
of D9111) watchdog timer.
Step transition
watchdog timer
M9112 SM1112 SM94
start (equivalent
of D9112)
Step transition
watchdog timer
M9113 SM1113 SM95
start (equivalent
of D9113)
Step transition
watchdog timer
M9114 SM1114 SM96
start (equivalent
of D9114)
Active step
OFF: Trace started • Set when sampling trace of all specified blocks is
M9180 SM1180 SM825 sampling trace
ON : Trace completed completed. Reset when sampling trace is started.
completion flag
Active step OFF: Trace not being executed
• Set when sampling trace is being executed.
M9181 SM1181 SM822 sampling trace ON : Trace execution under
Reset when sampling trace is completed or suspended.
execution flag way
• Selects sampling trace execution enable/disable.
Active step ON: Sampling trace execution is enabled.
OFF: Trace disable/suspend
M9182 SM1182 SM821 sampling trace OFF: Sampling trace execution is disabled.
ON : Trace enable
permission If turned off during sampling trace execution, trace
is suspended.
• Selects the operation output when block stop is
executed.
ON: Retains the ON/OFF status of the coil being used
Operation output OFF: Coil output OFF by using operation output of the step being
M9196 SM1196 SM325
at block stop ON : Coil output ON executed at block stop.
OFF: All coil outputs are turned off. (Operation output by
the SET instruction is retained regardless of the
ON/OFF status of M9196.)
I/O numbers
SM9197 SM1198 to be
displayed
M9197 SM1197 X/Y
Switch between OFF OFF Switches I/O numbers in the fuse blow module storage
0 to 7F0
blown fuse and registers (SD1100 to SD1107) and I/O module verify error
X/Y
I/O verification ON OFF storage registers (SD1116 to SD1123) according to the
800 to FF0
error display combination of ON/OFF of the SM1197 and SM1198.
X/Y
OFF ON
1000 to 17F0
M9198 SM1198
X/Y
ON ON
1800 to 1FF0

App - 15 App - 15
APPENDICES
MELSEC-Q

Special Relay List (Continued)

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
• Recovers the setting data stored in the CPU module at
Data recovery of
OFF: Data recovery disabled restart when sampling trace/status latch is executed.
M9199 SM1199 online sampling
ON : Data recovery enabled • SM1199 should be ON to execute again. (Unnecessary
trace/status latch
when writing the data again from peripheral devices.)
ZNRD instruction • Depends on whether or not the ZNRD (word device
(LRDP instruction read) instruction has been received.
OFF: Not accepted
M9200 SM1200 for ACPU) • Used in the program as an interlock for the ZNRD
ON : Accepted
reception (for instruction.
master station) • Use the RST instruction to reset.
ZNRD
• Depends on whether or not the ZNRD (word device
instruction (LRDP
read) instruction execution is complete.
instruction for OFF: Not completed
M9201 SM1201 • Used as a condition contact for resetting M9200 and
ACPU) completion ON : End
M9201 after the ZNRD instruction is complete.
(for master
• Use the RST instruction to reset.
station)
ZNWR instruction • Depends on whether or not the ZNWR (word device
(LWTP instruction write) instruction has been received.
OFF: Not accepted
M9202 SM1202 for ACPU) • Used in the program as an interlock for the ZNWR
ON : Accepted
reception (for instruction.
master station) • Use the RST instruction to reset.
ZNWR instruction • Depends on whether or not the ZNWR (word device
(LWTP instruction write) instruction execution is complete.
OFF: Not completed
M9203 SM1203 for ACPU) • Used as a condition contact to reset M9202 and M9203
ON : End
completion (for after the ZNWR instruction is complete.
master station) • Use the RST instruction to reset.
ZNRD
instruction (LRDP
OFF: Not completed On indicates that the ZNRD instruction is complete at the
M9204 SM1204 instruction for
ON : End local station.
ACPU) reception
(for local station)
ZNWR instruction
(LWTP instruction
OFF: Not completed On indicates that the ZNWR instruction is complete at the
M9205 SM1205 for ACPU)
ON : End local station.
recep-tion (for
local station) QnA
Host station link OFF: Normal Depends on whether or not the link parameter setting of
M9206 SM1206
parameter error ON : Abnormal the host is valid.
Depends on whether or not the link parameter setting of
Link parameter OFF: YES the master station in tier two matches that of the master
M9207 SM1207
check results ON : NO station in tier three in a three-tier system.
(Valid for only the master station in a three-tier system.)
Sets master • Depends on whether or not the B and W data controlled
station B and W by higher-link master station (host station) is sent to
OFF: Transmits to tier2 and lower-link local stations (tertiary stations).
transmission
M9208 SM1208 tier 3 • When SM1208 is OFF.......B and W of host station is
range (for lower
ON : Transmits to tier2 only sent to tertiary stations.
link master • When SM1208 is ON.........B and W of host station is
stations only) not sent to tertiary stations.
• Set to ON not to match B and W of the higher and lower
Link parameter
links.
check command OFF: Executing the check
• When SM1209 is ON, the link parameters of the higher
M9209 SM1209 (for lower link function
and lower link are not checked.
master stations ON : Check non-execution
• When SM1209 is OFF, the link parameters of the higher
only)
and lower link are checked.
Link card error (for OFF: Normal Control is performed depending on whether the link card
M9210 SM1210
master station) ON : Abnormal hardware is faulty or not.
Link module error
OFF: Normal Control is performed depending on whether the link card
M9211 SM1211 (for local station
ON : Abnormal hardware is faulty or not.
use)
OFF: Online
Depends on whether the master station is online or offline
M9224 SM1224 Link status ON : Offline,station-to-station
or is in station-to-station test or self-loopback test mode.
test, or self-loopback test
OFF: Normal
M9225 SM1225 Forward loop error Depends on the error condition of the forward loop line.
ON : Abnormal
OFF: Normal
M9226 SM1226 Reverse loop error Depends on the error condition of the reverse loop line.
ON : Abnormal

App - 16 App - 16
APPENDICES
MELSEC-Q

Special Relay List (Continued)

ACPU Special Special
Applicable
Special Relay after Relay for Name Meaning Details
CPU
Relay Conversion Modification
OFF: Not being executed
Depends on whether or not the master station is executing
M9227 SM1227 Loop test status ON : Forward or reverse loop
a forward or a reverse loop test.
test execution underway
OFF: RUN or STEP RUN
Local station Control is performed depending on whether a local station
M9232 SM1232 status
operation status is in the STOP or PAUSE mode.
ON : STOP or PAUSE status
Local station
OFF: No errors Depends on whether or not a local station has detected an
M9233 SM1233 error detect
ON : Error detection error in another station.
status
Local station,
remote I/O
OFF: No errors Depends on whether or not a local or a remote I/O station
M9235 SM1235 station parameter
ON : Error detection has detected any link parameter error in the master station
error detect
status
Local station,
remote I/O OFF: No communications Depends on the results of initial communication between a
M9236 SM1236 station initial ON : Communications local or remote I/O station and the master station.
communications underway (Parameter communication, etc.)
status
Local station,
OFF: Normal Depends on the error condition of a local or remote I/O
M9237 SM1237 remote I/O
ON : Abnormal station.
station error
Local station,
remote I/O OFF: Normal Depends on the error condition of the forward and reverse
M9238 SM1238
station forward or ON : Abnormal loop lines of a local or a remote I/O station.
reverse loop error
OFF: Online
ON : Offline, station-to- Depends on whether the local station is online or offline, or
M9240 SM1240 Link status
stationtest, or self- is in station-to-station test or self-loopback test mode.
loopback test QnA
Forward loop line OFF: Normal
M9241 SM1241 Depends on the error condition of the forward loop line.
error ON : Abnormal
Reverse loop line OFF: Normal
M9242 SM1242 Depends on the error condition of the reverse loop line.
error ON : Abnormal
OFF: Loopback not being
Loopback Depends on whether or not loopback is occurring at the
M9243 SM1243 conducted
implementation local station.
ON : Loopback implementation
OFF: Reception Depends on whether or not data has been received from
M9246 SM1246 Data not received
ON : No reception the master station.
OFF: Reception Depends on whether or not a tier three station has
M9247 SM1247 Data not received
ON : No reception received data from its master station in a three-tier system.
Parameters not OFF: Reception Depends on whether or not link parameters have been
M9250 SM1250
received ON : No reception received from the master station.
OFF: Normal
M9251 SM1251 Link relay Depands on the data link condition at the local station.
ON : Abnormal
OFF: Not being executed
Depends on whether or not the local station is executing a
M9252 SM1252 Loop test status ON : Forward or reverse loop
forward or a reverse loop test.
test execution underway
OFF: RUN or STEP RUN
Master station Control is performed depending on whether the master
M9253 SM1253 status
operation status station is in the STOP or PAUSE mode.
ON : STOP or PAUSE status
Local station
OFF: RUN or STEP RUN
other than host Control is performed depending on whether a local station
M9254 SM1254 status
station operation other than the host is in the STOP or PAUSE mode.
ON : STOP or PAUSE status
status
Local station
OFF: Normal Depends on whether or not a local station other than the
M9255 SM1255 other than host
ON : Abnormal host is in error.
station error

App - 17 App - 17
APPENDICES
MELSEC-Q

Special Relay List

(10) For redundant systems (Host system CPU information 1) for Q4AR only
SM1510 to SM1599 are only valid for redundant systems. All off for standalone systems.
Set by ACPU Applicable
Number Name Meaning Explanation
(When Set) M9 CPU
OFF: No-hold • Specifies whether or not to hold the output value when a
SM1500 Hold mode U New
ON : Hold range over occurs for the S.IN instruction range check.
OFF: No-hold • Specifies whether or not the output value is held when a
SM1501 Hold mode U New
ON : Hold range over occurs for the S.OUT instruction range check.
OFF: Redundant
system backup
mode,
independent • Turns on when the operating mode is redundant system S
SM1510 Operation mode New
system separate. (Each END)
ON : Redundant
system
separate mode
OFF: System A fixed
mode • Turns on when the start mode for a redundant system
Start mode when
SM1511 ON : Previous control when the power is turned on is the previous control system S (Initial) New
power supply is on
system latch latch mode.
mode
Start mode when CPU OFF: Initial start • Turns on when the CPU module operation mode is hot
SM1512 S (Initial) New
is started ON : Hot start start when the redundant system is started up.
Operation status when OFF: Initial start • Turns on when the CPU module operation mode is hot
SM1513 S (Initial) New
CPU is started ON : Hot start start when the redundant system is actually start up.
Operation mode when OFF: Initial start • Turns on when the operation is hot start when the CPU
SM1514 S (Initial) New
CPU is switched ON : Hot start module operation is switched for a redundant system.
OFF: Output reset • Turns on when the output mode during a stop error is S
SM1515 Output hold mode New
ON : Output hold output hold. (Each END)
Operation system OFF: Control system • Turns on when the CPU module operation system status is S (Status
SM1516 New
status ON : Standby system the standby system. change)
OFF: Power supply
on startup • Turns on when the CPU module is started up by the
S (Status
SM1517 CPU startup status ON : Operation operation system switch. New
change) /U
system switch • Reset using the user program.
starup
• When this relay is turned OFF, the start of tracking is Q4AR
delayed until it is executable if the tracking memory is
OFF: Batch operation
Tracking execution being used at END.
SM1518 mode U New
mode • When this relay is turned ON, the start of tracking is carried
ON : Carryover mode
over to next END if the tracking memory is being used at
END.
SM1520 SM1520 Block 1
SM1521 SM1521 Block 2
SM1522 SM1522 Block 3
SM1523 SM1523 Block 4
SM1524 SM1524 Block 5
SM1525 SM1525 Block 6
SM1526 SM1526 Block 7
SM1527 SM1527 Block 8
SM1528 SM1528 Block 9
SM1529 SM1529 Block 10
SM1530 SM1530 Block 11
SM1531 SM1531 Block 12 • Specified the blocks to trigger when
Data tracking
SM1532 OFF: No trigger SM1532 Block 13 the data is transmitted by the data
transmission link U New
SM1533 ON : Trigger SM1533 Block 14 tracking instruction
specification
SM1534 SM1534 Block 15 S. TRUCK.
SM1535 SM1535 Block 16
SM1536 SM1536 Block 17
SM1537 SM1537 Block 18
SM1538 SM1538 Block 19
SM1539 SM1539 Block 20
SM1540 SM1540 Block 21
SM1541 SM1541 Block 22
SM1542 SM1542 Block 23
SM1543 SM1543 Block 24
SM1544 SM1544 Block 25
SM1545 SM1545 Block 26

App - 18 App - 18
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Set by ACPU Applicable
Number Name Meaning Explanation
(When Set) M9 CPU
SM1546 SM1546 Block 27
SM1547 SM1547 Block 28
SM1548 SM1548 Block 29
SM1549 SM1549 Block 30
SM1550 SM1550 Block 31
SM1551 SM1551 Block 32
SM1552 SM1552 Block 33
SM1553 SM1553 Block 34
SM1554 SM1554 Block 35
SM1555 SM1555 Block 36
SM1556 SM1556 Block 37
SM1557 SM1557 Block 38
SM1558 SM1558 Block 39
SM1559 SM1559 Block 40
SM1560 SM1560 Block 41
SM1561 SM1561 Block 42
SM1562 SM1562 Block 43
SM1563 SM1563 Block 44 • Specified the blocks to trigger when
Data tracking
SM1564 OFF: No trigger SM1564 Block 45 the data is transmitted by the data
transmission link U
SM1565 ON : Trigger SM1565 Block 46 tracking instruction
specification
SM1566 SM1566 Block 47 S. TRUCK. New Q4AR
SM1567 SM1567 Block 48
SM1568 SM1568 Block 49
SM1569 SM1569 Block 50
SM1570 SM1570 Block 51
SM1571 SM1571 Block 52
SM1572 SM1572 Block 53
SM1573 SM1573 Block 54
SM1574 SM1574 Block 55
SM1575 SM1575 Block 56
SM1576 SM1576 Block 57
SM1577 SM1577 Block 58
SM1578 SM1578 Block 59
SM1579 SM1579 Block 60
SM1580 SM1580 Block 61
SM1581 SM1581 Block 62
SM1582 SM1582 Block 63
SM1583 SM1583 Block 64
OFF: Normal • Turns ON when switching could not be executed normally
Switching status from S (Error
SM1590 ON : Switching if the network module had detected a network fault and
the network module ocurrs)
unsuccessful issued a switching request to the host CPU module.

App - 19 App - 19
APPENDICES
MELSEC-Q

Special Relay List

(11) For redundant system (Other system CPU information 1) for Q4AR only
SM1600 to SM1650 only valid for the CPU redundant system backup mode, so they cannot
be refreshed during the separate mode.
Either the backup mode or the separate mode is valid for the SM4651 to SM1699.
SM1600 to SM1699 are all turned off for standalone system.
Set by ACPU
Applicable
Number Name Meaning Explanation (When Set) M9
CPU
2
• Turns on if a error occurs in the diagnosis results.
OFF: No error S
SM1600 Diagnosis error (Including external diagnosis) New
ON : Error (Each END)
• Remains on even if returns to normal thereafter.
OFF: No self
• Turns on when an error occurs in the self-diagnosis
diagnosis error S
SM1601 Self diagnosis error results. New
ON : Self diagnosis (Each END)
• Remains on even if returns to normal thereafter.
error
OFF: No error
common
Error common • Turns on when there is error common information and the S
SM1605 information New
information SM1600 is on. (Each END)
ON : Error common
information Q4AR
OFF: No error
individual
Error individual • Turns on when there is error individual information and the S
SM1616 information New
information SM1600 is on. (Each END)
ON : Error individual
information
S
SM1653 STOP contact STOP status • Turns on when in the STOP status. New
(Each END)
S
SM1654 PAUSE contact PAUSE status • Turns on when in the PAUSE status. New
(Each END)
S
SM1655 STEP-RUN contact STEP-RUN status • Turns on when in the STEP-RUN status. New
(Each END)

1 Stores other system CPU diagnostic information and system information.

2 This shows the special relay(SM ) for the host system CPU.

(12) For redundant system (tracking) for Q4AR only

Either the backup mode or the second mode is valid for SM1700 to SM1799. All is turned off
for standalone system.
Set by ACPU Applicable
Number Name Meaning Explanation
(When Set) M9 CPU
OFF: Execution not
Tracking execution possible S (status
SM1700 • Turns on when tracking is executed normally. New
flag ON : Execution change)
possible
SM1712 SM1712 Block 1
SM1713 SM1713 Block 2
SM1714 SM1714 Block 3
SM1715 SM1715 Block 4
SM1716 SM1716 Block 5
SM1717 SM1717 Block 6
SM1718 SM1718 Block 7
SM1719 SM1719 Block 8
SM1720 SM1720 Block 9
Q4AR
SM1721 OFF: Transmission SM1721 Block 10
• One scan turns on when the
SM1722 Transmission trigger uncompleted SM1722 Block 11 S (status
corresponding data transmission New
SM1723 end flag ON : Transmission SM1723 Block 12 change)
has been completed.
SM1724 end SM1724 Block 13
SM1725 SM1725 Block 14
SM1726 SM1726 Block 15
SM1727 SM1727 Block 16
SM1728 SM1728 Block 17
SM1729 SM1729 Block 18
SM1730 SM1730 Block 19
SM1731 SM1731 Block 20
SM1732 SM1732 Block 21
SM1733 SM1733 Block 22

App - 20 App - 20
APPENDICES
MELSEC-Q

Special Relay List (Continued)

Set by ACPU Applicable
Number Name Meaning Explanation
(When Set) M9 CPU
SM1734 SM1734 Block 23
SM1735 SM1735 Block 24
SM1736 SM1736 Block 25
SM1737 SM1737 Block 26
SM1738 SM1738 Block 27
SM1739 SM1739 Block 28
SM1740 SM1740 Block 29
SM1741 SM1741 Block 30
SM1742 SM1742 Block 31
SM1743 SM1743 Block 32
SM1744 SM1744 Block 33
SM1745 SM1745 Block 34
SM1746 SM1746 Block 35
SM1747 SM1747 Block 36
SM1748 SM1748 Block 37
SM1749 SM1749 Block 38
SM1750 SM1750 Block 39
SM1751 SM1751 Block 40
SM1752 SM1752 Block 41
SM1753 OFF: Transmission SM1753 Block 42
• One scan turns on when the
SM1754 Transmission trigger uncompleted SM1754 Block 43 S (status
corresponding data transmission New Q4AR
SM1755 end flag ON : Transmission SM1755 Block 44 change)
has been completed.
SM1756 end SM1756 Block 45
SM1757 SM1757 Block 46
SM1758 SM1758 Block 47
SM1759 SM1759 Block 48
SM1760 SM1760 Block 49
SM1761 SM1761 Block 50
SM1762 SM1762 Block 51
SM1763 SM1763 Block 52
SM1764 SM1764 Block 53
SM1765 SM1765 Block 54
SM1766 SM1766 Block 55
SM1767 SM1767 Block 56
SM1768 SM1768 Block 57
SM1769 SM1769 Block 58
SM1770 SM1770 Block 59
SM1771 SM1771 Block 60
SM1772 SM1772 Block 61
SM1773 SM1773 Block 62
SM1774 SM1774 Block 63
SM1775 SM1775 Block 64

App - 21 App - 21
APPENDICES
MELSEC-Q

APPENDIX 2 Special Register

The special registers, SD, are internal registers with fixed applications in the PLC.
For this reason, it is not possible to use these registers in sequence programs in the same way
that normal registers are used.
However, data can be written as needed in order to control the CPU modules and remote I/O
modules.
Data stored in the special registers are stored as BIN values if no special designation has been
made to the contrary.

The headings in the table that follows have the following meanings.

Item Function of Item

Number • Indicates special register number
Name • Indicates name of special register
Meaning • Indicates contents of special register
Explanation • Discusses contents of special register in more detail
• Indicates whether the relay is set by the system or user, and, if it is set by the system, when
setting is performed.
<Set by>
S : Set by system
U : Set by user (sequence programs or test operations from GX Developer)
S/U : Set by both system and user
<When set> Indicated only for registers set by system
Set by (When set)
Each END : Set during each END processing
Initial : Set only during initial processing (when power supply is turned
ON, or when going from STOP to RUN)
Status change : Set only when there is a change in status
Error : Set when error occurs
Instruction execution : Set when instruction is executed
Request : Set only when there is a user request (through SM, etc.)
• Indicates corresponding special register in ACPU (D9 )(Change and notation when
Corresponding ACPU there has been a change in contents)
M9 • "New" indicates the item that has been newly added to the High Performance model
QCPU/QnACPU.
• Indicates the corresponding CPU module type name.
+Rem: Can be applied to all CPU types and MELSECNET/H remote I/O modules.
: Can be applied to all types of CPU module
Corresponding CPU QCPU: Can be applied to High Performance model QCPU.
QnA: Can be applied to QnA series and Q2ASCPU series
Remote: Can be applied to the MELSECNET/H remote I/O modules.
Each CPU type name: Can be applied only to the specific CPU. (e.g. Q4ARCPU, Q3ACPU)

For details on the following items, refer to the following manuals:

• Networks • For Q Corresponding MELSECNET/H Network System Reference Manual
(PLC to PLC network)
• For Q Corresponding MELSECNET/H Network System Reference Manual
(Remote I/O network)
• For QnA/Q4AR MELSECNET/10 Network System Reference Manual
• SFC QCPU(Q mode)/QnACPU Programming Manual (SFC)

POINT
(1) SD1200 to SD1255 are used for QnACPU.
These relays are vacant with High Performance model QCPU.
(2) Special register SD1500 and later are dedicated for Q4ARCPU.

App - 22 App - 22
APPENDICES
MELSEC-Q

Special Register List

(1) Diagnostic Information
Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
Diagnostic Diagnosis • Error codes for errors found by diagnosis are stored as BIN data. D9008 format
SD0 S (Error)
errors error code • Contents identical to latest fault history information. change
• Year (last two digits) and month that SD0 data was updated is stored
as BCD 2-digit code.
SD1 (Example)
b15 to b8 b7 to b0
: October, 1995
Year (0 to 99) Month (1 to 12)
9510H
• The day and hour that SD0 was updated is stored as BCD 2-digit
Clock time for code.
Clock time for
SD2 diagnosis (Example)
diagnosis error b15 to b8 b7 to b0 S (Error) New
error : 10 p.m. on 25th
occurrence Day (1 to 31) Hour (0 to 23)
occurrence 2510H
• The minute and second that SD0 data was updated is stored as BCD
2-digit code.
b15 to b8 b7 to b0
(Example)
SD3
: 35 min. 48 sec.
Minutes (0 to 59) Seconds (0 to 59)
(past the hour)
3548H
• Category codes which help indicate what type of information is being
stored in the common information areas (SD5 through SD15) and the
individual information areas (SD16 through SD26) are stored here.
b15 to b8 b7 to b0
Individual information Common information
category codes category codes
+Rem

• The common information category codes store the following codes:

0 : No error
1 : Unit/module No./ PLC No./Base No.
2 : File name/Drive name
3 : Time (value set)
4 : Program error location
5 : Switch cause (for Q4AR only)
Error Error
: For a multiple PLC system, the module number or PLC
SD4 information information S (Error) New
number is stored depending on the error that occurred.
categories category code
(Refer to the corresponding error code for which number
has been stored.)
PLC No. 1: 1, PLC No. 2: 2, PLC No. 3: 3, PLC No. 4: 4
• The individual information category codes store the following codes:
0 : No error
1 : (Open)
2 : File name/Drive name
3 : Time (value actually measured)
4 : Program error location
5 : Parameter number
6 : Annunciator number
7 : Check instruction malfunction number

App - 23 App - 23
APPENDICES
MELSEC-Q

Special Register List (Continued)

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
SD5 • Common information corresponding to the error codes (SD0) is stored
SD6 here.
SD7 • The following four types of information are stored here:
1 Slot No.
SD8
Number Meaning
SD9 SD5 Slot No./PLC No./Base No. 1 2
SD10 SD6 I/O No. (Not used for base No.)
SD7
SD11
SD8
SD12 SD9
SD13 SD10
SD11 (Vacant)
SD14
SD12
SD13
SD14
SD15
*1: For a multiple CPU system, the slot number or CPU number is
stored depending on the error that occurred.
Slot 0 in the multiple CPU system is the one on the slot on the
right of the rightmost CPU module.
(Refer to the corresponding error code for which number has
Error been stored.)
Error common
common No. 1 CPU: 1, No. 2 CPU: 2, No. 3 CPU: 3, No. 4 CPU: 4 S (Error) New +Rem
information
information *2: If a fuse blown or I/O verify error occurred in the module loaded
in the MELSECNET/H remote I/O station, the network number is
stored into the upper 8 bits and the station number into the lower
8 bits.
Use the I/O No. to check the module where the fuse blown or I/O
SD15
verify error occurred.
2 File name/Drive name
(Example)
File name=
Number Meaning ABCDEFGH. IJK
SD5 Drive b15 to b8 b7 to b0
SD6 42H(B) 41H(A)
SD7 File name 44H(D) 43H(C)
SD8 (ASCII code: 8 characters) 46H(F) 45H(E)
SD9 48H(H) 47H(G)
SD10 Extension 3 2EH(.) 49H(I) 2EH(.)
SD11 (ASCII code: 3 characters) 4BH(K) 4AH(J)
SD12
SD13 (Vacant)
SD14
SD15

3: Refer to REMARK.

REMARK
1) Extensions are shown below.
SD10 SD11
Extension name File type
Higher8 bits Lower8 bits Higher8 bits
51H 50H 41H QPA Parameters
51H 50H 47H QPG Sequence program/SFC program
51H 43H 44H QCD Device comment
51H 44H 49H QDI Device initial value
51H 44H 52H QDR File register
51H 44H 53H QDS Simulation data
51H 44H 4CH QDL Local device
51H 54H 53H QTS Sampling trace data (For QnA)
51H 54H 4CH QTL Status latch data (For QnA)
51H 54H 50H QTP Program trace data (For QnA)
51H 54H 52H QTR SFC trace file
51H 46H 44H QFD Trouble history data

App - 24 App - 24
APPENDICES
MELSEC-Q

Special Register List (Continued)

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
SD5 3 Time (value set)
SD6 Number Meaning
SD7 SD5 Time : 1 µs units (0 to 999 µs)
SD6 Time : 1 ms units (0 to 65535 ms)
SD8
SD7
SD9 SD8
SD10 SD9
SD10
SD11 SD11 (Vacant)
SD12 SD12
SD13 SD13
SD14
SD14 SD15

4 Program error location

Number Meaning
SD5
SD6 File name S (Error) New +Rem
SD7 (ASCII code: 8 characters)
SD8
SD9 Extension 2EH(.)
SD10 (ASCII code: 3 characters)
SD11 Pattern 4
SD12 Block No.
SD13 Step No./transition No.
SD14 Sequence step No. (L)
SD15 Sequence step No. (H)
4 Contents of pattern data
15 14 to 4 3 2 1 0 (Bit number)
Error
Error common 0 0 to 0 0
common
information SFC block designation present
information (Not used) (1)/absent (0)
SFC step designation present
(1)/absent (0)
SFC transition designation
present (1)/absent (0)
5 Switch cause
SD15
Number Meaning
SD5 Switch cause (0: automatic switch/ 1: manual switch)
Switch direction (0:standby system to control
SD6 system/ 1: control system to standby system)
SD7 Tracking flag 5
SD8
SD9
SD10
SD11
(Vacant)
SD12
SD13
SD14 S (Error) New Q4AR
SD15
5 Tracking flag contents
Shows whether or not the tracking data is valid.
15 14 to 4 3 2 1 0 (Bit number)
0 0 to 0 0
Invalid work data
(Not used) invalid (0) /valid (1)
System data
(SFC active step information)
invalid (0)/ valid (1)
Switching cause invalid (0)/
valid (1)

App - 25 App - 25
APPENDICES
MELSEC-Q

Special Register List (Continued)

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
• Individual information corresponding to error codes (SD0) is stored
here.
SD16
1 File name/Drive name
(Example)
File name=
Number Meaning ABCDEFGH. IJK
SD16 Drive b15 to b8 b7 to b0
SD17 42H(B) 41H(A)
SD17
SD18 File name 44H(D) 43H(C)
SD19 (ASCII code: 8 characters) 46H(F) 45H(E)
SD20 48H(H) 47H(G)
SD21 Extension 2EH(.) 49H(I) 2EH(.)
SD22 (ASCII code: 3 characters) 4BH(K) 4AH(J)
SD18 SD23
SD24 (Vacant)
SD25
SD26
2 Time (value actu1ally measured)
SD19 Number Meaning
SD16 Time : 1 µs units (0 to 999 µs)
SD17 Time : 1 ms units (0 to 65535 ms)
SD18
SD19
SD20
SD20
SD21
SD22 (Vacant)
SD23
SD24
SD25
SD21 SD26
3 Program error location
Number Meaning
SD16
SD17 File name
SD22 SD18 (ASCII code: 8 characters)
Error SD19
Error individual
individual SD20 Extension 2EH(.) S (Error) New +Rem
information SD21 (ASCII code: 3 characters)
information
SD22 Pattern
SD23 SD23 Block No.
SD24 Step No./transition No.
SD25 Sequence step No. (L)
SD26 Sequence step No. (H)

Contents of pattern data

SD24 15 14 to 4 3 2 1 0 (Bit number)
0 0 to 0 0
SFC block designation present
(Not used) (1)/absent (0)
SFC step designation present
(1)/absent (0)
SD25
SFC transition designation
present (1)/absent (0)

4 Parameter number 5 Annunciator 6 Intelligent function

number / CHK module parameter
instruction error
malfunction (for QCPU only)
number
Number Meaning Number Meaning Number Meaning
SD16 Parameter No. 6 SD16 No. SD16 Parameter No. 6
SD17 SD17 SD17 Error code for intelligent
SD18 SD18 function module
SD26 SD19 SD19 SD18
SD20 SD20 SD19
SD21 SD21 SD20
(Vacant) (Vacant)
SD22 SD22 SD21
SD23 SD23 SD22 (Vacant)
SD24 SD24 SD23
SD25 SD25 SD24
SD26 SD26 SD25
SD26

6 For details of the parameter numbers, refer to the user's

manual of the CPU module used.

App - 26 App - 26
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
Error number that
SD50 Error reset • Stores error number that performs error reset U New +Rem
performs error reset
• All corresponding bits go 1(ON) when battery voltage drops.
• Subsequently, these remain 1(ON) even after battery voltage has
been returned to normal.
b4 b3 b2 b1 b0
0<------------------- >
CPU error
Bit pattern Memory card A alarm
Battery low indicating where Memory card A error
SD51 S (Error) New
latch battery voltage drop Memory card B alarm
occurred Memory card B error
• The alarm data can be held within the specified time when batter
low occurs.
• The error indicates the complete discharge of the battery.
• When the QCPU is used, the memory card B is standard and
therefore the corresponding bits always remain OFF.
• Same configuration as SD51 above
Bit pattern
• Turns to 0 (OFF) when the battery voltage returns to normal
indicating where
SD52 Battery low thereafter. S (Error) New
battery voltage drop
• When the QCPU is used, the memory card B is standard and
occurred therefore the corresponding bits always remain OFF.
• Every time the input voltage falls to or below 85% (AC
AC/DC
Number of times for power)/65% (DC power) of the rating during calculation of the
SD53 DOWN CPU module, the value is incremented by 1 and stored in BIN
S (Error) D9005 +Rem
AC/DC DOWN
detection code.
1 When any of X(n+0)/X(n+20), X(n+6)/X(n+26), X(n+7)/X(n+27)
and X(n+8)/X(n+28) of the mounted MINI(-S3) turns ON, the
bit of the corresponding station turns to 1 (ON).
2 Turns to 1 (ON) when communication between the mounted
MINI link Error detection D9004 format
SD54 MINI(-S3) and CPU module cannot be made. S (Error) QnA
errors state b15 to b9 b8 to b0 change
8th 1st 8th 1st
module module module module

Information on 2 Information on 1
Blown fuse Number of module • Value stored here is the lowest station I/O number of the module
SD60 S (Error) D9000
number with blown fuse with the blown fuse.
I/O module I/O module +Rem
• The lowest I/O number of the module where the I/O module
SD61 verification verification error S (Error) D9002
verification number took place.
error number module number
S
Annunciator Annunciator • The first annunciator number (F number) to be detected is stored
SD62 (Instruction D9009
number number here.
execution)
S
Number of Number of
SD63 • Stores the number of annunciators searched. (Instruction D9124
annunciators annunciators
execution)

App - 27 App - 27
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9

SD64 When F goes ON due to OUT F or SET F , the F numbers which D9125
go progressively ON from SD64 through SD79 are registered.
SD65 The F numbers turned OFF by RST F are deleted from SD64 - D9126
SD79, and the F numbers stored after the deleted F numbers are
SD66 shifted to the preceding registers. D9127
Execution of the LEDR instruction shifts the contents of SD64 to
SD67 SD79 up by one. D9128
(This can also be done by using the INDICATOR RESET switch on
SD68 D9129
the of the Q3A/Q4ACPU.)
After 16 annunciators have been detected, detection of the 17th will
SD69 D9130
not be stored from SD64 through SD79.
SET SET SET RST SET SET SET SET SET SET SET
SD70 F50 F25 F99 F25 F15 F70 F65 F38 F110F151 F210 LEDR D9131
Table of SD62 0 50 50 50 50 50 50 50 50 50 50 50 99 ...(Number
SD71 Annunciator detected) S D9132
detected
detection SD63 0 1 2 3 2 3 4 5 6 7 8 9 8 ...(Number of (Instruction
annunciator annunciators
SD72 number detected) execution) New
numbers SD64 0 50 50 50 50 50 50 50 50 50 50 50 99
SD65 0 0 25 25 99 99 99 99 99 99 99 99 15
SD73 SD66 0 0 0 99 0 15 15 15 15 15 15 15 70 New
SD67 0 0 0 0 0 0 70 70 70 70 70 70 65
SD74 SD68 0 0 0 0 0 0 0 65 65 65 65 65 38 New
SD69 0 0 0 0 0 0 0 0 38 38 38 38 110
SD70 0 0 0 0 0 0 0 0 0 110 110 110 151
SD75 New
SD71 0 0 0 0 0 0 0 0 0 0 151 151 210
(Number
SD72 0 0 0 0 0 0 0 0 0 0 0 210 0
SD76 detected) New
SD73 0 0 0 0 0 0 0 0 0 0 0 0 0
SD74 0 0 0 0 0 0 0 0 0 0 0 0 0
SD77 SD75 0 0 0 0 0 0 0 0 0 0 0 0 0 New
SD76 0 0 0 0 0 0 0 0 0 0 0 0 0
SD77 0 0 0 0 0 0 0 0 0 0 0 0 0
SD78 New
SD78 0 0 0 0 0 0 0 0 0 0 0 0 0
SD79 0 0 0 0 0 0 0 0 0 0 0 0 0
SD79 New

S
• Error codes detected by the CHK instruction are stored as BCD
SD80 CHK number CHK number (Instruction New
code.
execution)
SD90 Corresponds to SM90 • Set the annunciator number (F number) that D9108
will be turned ON when the step transition
SD91 Corresponds to SM91 watchdog timer setting or watchdog timer D9109
time limit error occurs.
SD92 Corresponds to SM92 D9110
Step transition b15 to b8 b7 to b0
SD93 Corresponds to SM93 D9111
watchdog
SD94 timer setting F number for Corresponds to SM94 D9112
value timer set value F number setting Timer time limit
U
SD95 (Enabled only and time over Corresponds to SM95 (0 to 255) setting D9113
when SFC error (1 to 255 s:
SD96 Corresponds to SM96 D9114
program (1 s units))
SD97 exists) Corresponds to SM97 New
• Turning ON any of SM90 to SM99 during an
SD98 Corresponds to SM98 active step starts the timer, and if the New
transition condition next to the corresponding
SD99 Corresponds to SM99 step is not met within the timer time limit, the New
set annunciator (F) turns ON.
Stores the
CH1 preset
3 : 300bps, 6 : 600bps, 24 : 2400bps, 48 : 4800bps
transmission transmission QCPU
SD105 96 : 9600bps, 192 : 19.2kbps, 384 : 38.4kbps S New
speed setting speed when Remote
576 : 57.6kbps, 1152 : 115.2kbps
(RS232) GX Developer
is used.

App - 28 App - 28
APPENDICES
MELSEC-Q

Special Register List

(2) System information
Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
• The switch status of the remote I/O module is stored in the following
format.
b15 to b4 b3 to b0
S (Always) New Remote
Vacant 1
1 Remote I/O module switch status Always 1: STOP
• The CPU switch status is stored in the following format:
b15 to b12 b11 to b8 b7 to b4 b3 to b0

3 Vacant 2 1
1 : CPU switch status 0: RUN
1: STOP S(Every
2: L.CLR END New QCPU
2 : Memory card switch Always OFF processing)
3 : DIP switch b8 through b12 correspond to SW1
through SW5 of system setting
switch 1.
0: OFF, 1: ON
Status of Status of CPU b13 through b15 are vacant.
SD200
switch switch
• The CPU switch status is stored in the following format:
b15 to b12b11 to b8 b7 to b4 b3 to b0

3 Vacant 2 1
1 : CPU key 0 : RUN
Status of switch 1 : STOP
2 : L.CLR
2 : Memory cards switch b4 corresponds to memory card A,
S(Every
and b5 corresponds to memory
END New QnA
card B
processing)
OFF at 0; ON at 1
3 : DIP switch b8 through b12 correspond to SW1
through SW5 of system setting
switch 1.
b14 and b15 correspond to SW1
and SW2 of system setting switch
2, respectively.
OFF at 0; ON at 1

App - 29 App - 29
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
• The following bit patterns are used to store the statuses of the LEDs
on the CPU module:
b15 to b12b11 to b8 b7 to b4 b3 to B0

8 7 6 5 4 3 2 1

1 : RUN 5 : BOOT S (Status

New QCPU
2 : ERR. 6 : Vacant change)
3 : USER 7 : Vacant
4 : BAT. 8 : MODE
Bit patterns for MODE
0: OFF, 1: Green, 2:
Status of Orange
SD201 LED status
CPU-LED
• Information concerning which of the following status the LEDs on the
CPU module are in is stored in the following bit patterns:
• 0 is off, 1 is on, and 2 is flicker
b15 to b12 b11 to b8 b7 to b4 b3 to b0

S (Status
8 7 6 5 4 3 2 1 New QnA
change)
1 : RUN 5 : BOOT
2 : ERROR 6 : CARD A (Memory card A)
3 : USER 7 : CARD B (Memory card B)
4 : BAT.ALARM 8 : Vacant

Bit pattern of • Stores bit patterns of LEDs turned off

SD202 LED off LED that is (Only USER and BOOT enabled) U New QnA
turned off • Turned off at 1, not turned off at 0
• The operating status of the remote I/O module is stored in the
following format.
b15 to b4 b3 to b0
S (Always) New Remote
Vacant 1
1 Remote I/O module operating status Always 2: STOP
• The CPU operating status is stored as indicated in the following
figure:
b15 to b12b11 to b8 b7 to b4 b3 to b0

Operating 2 1
Operating
SD203 status of
status of CPU 1 : Operating status of CPU 0 :RUN
CPU
1 :STEP-RUN
2 :STOP S (Every
D9015 format
3 :PAUSE END
change
processing)
2 : STOP/PAUSE cause 0 :RUN/STOP switch
1 :Remote contact
2 : Remote operation from the
GX Developer or Serial
Communication.
3 :Internal program instruction
Note: Priority is earliest first 4 :Errors

0: Test not yet

executed
1: During X
Device test
device test S
SD206 execution • Set when the device test mode is executed on GX Developer. New Remote
2: During Y (Request)
type
device test
3: During X/Y
device test

App - 30 App - 30
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
SD207 Priorities 1 to 4 • When error is generated, the LED display (flicker) is made according D9038
to the error number setting priorities. D3039 format
SD208 Priorities 5 to 8 • The setting areas for priorities are as follows:
change
b15 tob12 b11 to b8 b7 to b4 b3 to b0
SD207 Priority 4 Priority 3 Priority 2 Priority 1
SD208 Priority 8 Priority 7 Priority 6 Priority 5
LED display SD209 Priority 10 Priority 9

priority Default Value SD207=4321H U

ranking SD208=8765H
Priorities 9 to
SD209 SD207=00A9H New
10
• No display is made if "0" is set.
However, even if "0" has been set, information concerning CPU
module operation stop (including parameter settings) errors will be
indicated by the LEDs without conditions.
See Section 7.9.5 REMARK for the priority order.
• The year (last two digits) and month are stored as BCD code at
SD210 as shown below:
Clock data b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example :
SD210 Clock data July 1993 D9025
(year, month)
9307H
Year Month
• The day and hour are stored as BCD code at SD211 as shown
below:
Clock data b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example : S/U
SD211 Clock data 31st, 10 a.m. D9026 +Rem
(day, hour) (Request)
3110H
Day Hour
• The minutes and seconds (after the hour) are stored as BCD code at
SD212 as shown below:
Clock data b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example :
SD212 Clock data (minute, 35 min., 48 sec. D9027
second) 3548H
Minute Second
• Stores the year (two digits) and the day of the week in SD213 in the
BCD code format as shown below.
b15 to b12 b11 to b8 b7 to b4 b3 to b0
Example :
1993, Friday
1905H
Day of week S/U QCPU
0 Sunday
D9028
(Request) Remote
Higher digits 1 Monday
of year (0 to 99) 2 Tuesday
3 Wednesday
4 Thursday
5 Friday
6 Saturday
Clock data
SD213 Clock data
(day of week) • The day of the week is stored as BCD code at SD213 as shown
below:
b15 to b12 b11 to b8 b7 to b4 b3 to b0
Example :
Friday
0005H
Day of week S/U
0 Sunday
D9028 QnA
(Request)
Always set "0" 1 Monday
2 Tuesday
3 Wednesday
4 Thursday
5 Friday
6 Saturday

App - 31 App - 31
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
SD220 • LED display ASCII data (16 characters) stored here.
b15 to b8 b7 to b0
SD221
SD220 15th character from the right 16th character from the right
SD222 SD221 13th character from the right 14th character from the right
SD223 SD222 11th character from the right 12th character from the right
LED display Display indicator S (When
SD223 9th character from the right 10th character from the right New
SD224 data data changed)
SD224 7th character from the right 8th character from the right
SD225 SD225 5th character from the right 6th character from the right
SD226 SD226 3rd character from the right 4th character from the right
SD227 1st character from the right 2nd character from the right
SD227
0: Automatic mode
SD240 Base mode • Stores the base mode. S (Initial) New
1: Detail mode
0: Main base only
No. of
1 to 7: No. of
SD241 extension • Stores the maximum number of the extension bases being installed. S (Initial) New
extension
bases
bases
b7 b2 b1 b0
Base type
Fixed to 0 to
differentiation
Main base
0: QA B is
1st expansion QCPU
A/Q base installed base
SD242 2nd expansion S (Initial) New Remote
differentiation (A mode) base
1: Q B is 0 fixed when the
to base is not installed.
installed
7th expansion
(Q mode) base

b15 to b12 b11 to b8 b7 to b4 b3 to b0

SD243 SD243 Expansion 3 Expansion 2 Expansion 1 Main
No. of base SD244 Expansion 7 Expansion 6 Expansion 5 Expansion 4
No. of base slots S (Initial) New
slots
• As shown above, each area stores the number of slots being
SD244
installed.
S
Loaded Loaded maximum • When SM250 goes from OFF to ON, the upper 2 digits of the final
SD250 (Request New +Rem
maximum I/O I/O No. I/O number plus 1 of the modules loaded are stored as BIN values.
END)
Q2A (S1)
Head I/O Head I/O No. for
• Stores the upper two digits of the first I/O number of an I/O module Q3A
SD251 number for module U D9094
that is removed/replaced in the online status.(default value : 100H) Q4A
replacement replacement
Q4AR
RS422 RS422
• Stores transmission speed of RS422. S (When
SD253 transmission transmission New QnA
0: 9600bps 1: 19.2kbps 2: 38.4kbps changed)
speed speed
Number of • Indicates the number of mounted MELSECNET/10 modules or
SD254
modules installed MELSECNET/H modules.
• I/O number of mounted MELSECNET/10 module or
SD255 I/O No.
MELSECNET/H module
Network • Network No. of mounted MELSECNET/10 module or
SD256
No. MELSECNET/H module
Informa-
Group • Group No. of mounted MELSECNET/10 module or MELSECNET/H
SD257 tion from
number module
1st
Station • Station No. of mounted MELSECNET/10 module or MELSECNET/H
SD258 module No. module
MELSECNET Standby
/10 (H) • In the case of standby stations, the module number of the standby S (Initial) New
SD259 informa-
station is stored. (1 to 4)
information tion
SD260
Information from
to • Configuration is identical to that for the 2nd module.
2nd module
SD264
SD265
Information from
to • Configuration is identical to that for the 3rd module.
3rd module
SD269
SD270
Information from
to • Configuration is identical to that for the 4th module.
4th module
SD274

App - 32 App - 32
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
• When Xn0 of the mounted CC-Link module turns ON, the bit of the
corresponding station turns to 1 (ON).
• When either Xn1 or XnF of the mounted CC-Link module turns OFF,
the bit of the corresponding station turns to 1 (ON).
• Turns to 1 (ON) when communication between the mounted CC-
Link module and CPU module cannot be made.
Information Information Information
of 3 of 2 of 1
b15 to b12 b11 to b8 b7 to b4 b3 to b0 QCPU
S (Error) New
Vacant Remote
1st module
2nd module
3rd module
Error detection 4th module
SD280 CC-Link error
status The above module Nos. n are in order of the head I/O numbers.
(However, the one where parameter setting has not been made is not
counted.)
• When Xn0 of the mounted CC-Link module turns ON, the bit of the
corresponding station turns to 1 (ON).
• When either Xn1 or XnF of the mounted CC-Link module turns OFF,
the bit of the corresponding station turns to 1 (ON).
• Turns to 1 (ON) when communication between the mounted CC-
Link module and CPU module cannot be made. S (Error) New QnA
b15 to b9 b8 to b0
8th 1st 8th 1st
module module module module

Information of 2 Information of 1
Number of
SD290 points • Stores the number of points currently set for X devices
allocated for X
Number of
SD291 points • Stores the number of points currently set for Y devices +Rem
allocated for Y
Number of
SD292 points • Stores the number of points currently set for M devices
allocated for M
Number of
SD293 points • Stores the number of points currently set for L devices
allocated for L
Number of
SD294 points • Stores the number of points currently set for B devices +Rem
allocated for B
Number of
SD295 Device points • Stores the number of points currently set for F devices
allocated for F
allocation
Number of
(Same as S (Initial) New
points
SD296 parameter • Stores the number of points currently set for SB devices +Rem
allocated for
contents) SB
Number of
SD297 points • Stores the number of points currently set for V devices
allocated for V
Number of
SD298 points • Stores the number of points currently set for S devices
allocated for S
Number of
SD299 points • Stores the number of points currently set for T device
allocated for T
Number of
points
SD300 • Stores the number of points currently set for ST devices
allocated for
ST
Number of
SD301 points • Stores the number of points currently set for C devices
allocated for C

App - 33 App - 33
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
Number of points
SD302 Device • Stores the number of points currently set for D devices
allocated for D
allocation
Number of points
SD303 (Same as • Stores the number of points currently set for W devices S (Initial) New +Rem
allocated for W
parameter
Number of points
SD304 contents) • Stores the number of points currently set for SW devices
allocated for SW
Reserves the designated time for communication processing with
GX Developer or other units.
Time The greater the value is designated, the shorter the response time
reserved for Time reserved for for communication with other devices (GX Developer, serial
END
SD315 communicat communication communication units) becomes. New QCPU
processing
ion processing Setting range: 1 to 100 ms
processing If the designated value is out of the range above, it is assumed to
no setting.
The scan time becomes longer by the designated time.
No. of modules
SD340 • Indicates the number of mounted Ethernet module.
installed
SD341 I/O No. • I/O number of mounted Ethernet module
Network
SD342 • Network No. of mounted Ethernet module
No.
SD343 Group No. • Group No. of mounted Ethernet module
Station
SD344 Informa- • Station No. of mounted Ethernet module S (Initial) New
No.
tion of 1st
• Vacant
SD345 to module
Ethernet Vacant (With QCPU, the Ethernet IP address of the 1st module is stored QCPU
SD346
information in buffer memory.) Remote
• Vacant
SD347 Vacant (With QCPU, the Ethernet error code of the 1st module is read
with the ERRORRD instruction.)
SD348 to Information from 2nd
• Configuration is identical to that for the first module.
SD354 module
SD355 to Information from 3rd
• Configuration is identical to that for the first module. S (Initial) New
SD361 module
SD362 to Information from
• Configuration is identical to that for the first module.
SD368 4th module
No. of modules
SD340 • Indicates the number of mounted Ethernet module.
installed
SD341 I/O No. • I/O number of mounted Ethernet module
Network
SD342 • Network No. of mounted Ethernet module
No.
SD343 Informa- Group No. • Group No. of mounted Ethernet module
tion of 1st Station
SD344 Ethernet • Station No. of mounted Ethernet module
module No. S (Initial) New
information
SD345 to
IP address • IP address of mounted Ethernet module
SD346
SD347 Error code • Error code of mounted Ethernet module
SD348 to Information from 2nd
• Configuration is identical to that for the first module.
SD354 module QnA
SD355 to Information from 3rd
• Configuration is identical to that for the first module.
SD361 module
SD362 to Ethernet Information from 4th
• Configuration is identical to that for the first module. S (Initial) New
SD368 information module
b15 to b8 b7 b6 b5 b4 b3 b2 b1 b0
0 to 0
Not used Instruction reception status of channel 1
Instruction reception status of channel 2
Ethernet Instruction reception status of channel 3
instruction Instruction reception Instruction reception status of channel 4
SD380 Instruction reception status of channel 5 S (Initial) New
reception status of 1st module
Instruction reception status of channel 6
status Instruction reception status of channel 7
Instruction reception status of channel 8
ON: Received (Channel is used.)
OFF: Not received (Channel is not used.)

App - 34 App - 34
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
Information from
SD381 • Configuration is identical to that for the first module.
Ethernet 2nd module
instruction Information from
SD382 • Configuration is identical to that for the first module. S (Initial) New
reception 3rd module
status Information from
SD383 • Configuration is identical to that for the first module.
4th module
• Stores the internal system software version in ASCII code.
The data in the lower byte QnA
position is indefinite.
Higher byte Lower byte The software version is stored
Software Internal system in the higher byte position.
SD392 S (Initial) D9060
version software version For version "A", for example, "41H" is stored.
Note: The internal system software version may differ from the
version indicated by the version symbol printed on the
case.
• In a multiple PLC system configuration, the PLC number of the
Multiple PLC Multiple PLC QCPU function
SD395 host CPU is stored. S (Initial) New Ver. B or later
number number
PLC No. 1: 1, PLC No. 2: 2, PLC No. 3: 3, PLC No. 4: 4

(3) System clocks/counters

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
• Following programmable controller CPU module RUN, 1 is
1 second Number of counts in S (Status
SD412 added each second D9022
counter 1-second units change)
• Count repeats from 0 to 32767 to -32768 to 0
2n second
2n second clock • Stores value n of 2n second clock (Default is 30)
SD414 clock U New
units • Setting can be made between 1 and 32767
setting
2nms clock • Stores value n of 2nms clock (Default is 30)
SD415 2nms clock units U New QCPU
setting • Setting can be made between 1 and 32767
• Incremented by 1 for each scan execution after the CPU module S(Every
Scan Number of counts in
SD420 is set to RUN. END New
counter each scan
• Count repeats from 0 to 32767 to -32768 to 0 processing)
• Incremented by 1 for each scan execution after the CPU module
Low speed S(Every
Number of counts in is set to RUN.
SD430 scan END New
each scan • Count repeats from 0 to 32767 to -32768 to 0
counter processing)
• Used only for low speed execution type programs

: Not counted by the scan in an initial execution type program.

App - 35 App - 35
APPENDICES
MELSEC-Q

Special Register List

(4) Scan information
Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
Execution Program No. in • Program number of program currently being executed is S (Status
SD500 New
program No. execution stored as BIN value. change)
Low speed Low speed execution • Program number of low speed excution type program No. S (Every
SD510 excution type type program No. in currently being executed is stored as BIN value. END New
program No. execution • Enabled only when SM510 is ON. processing)
S (Every
Current scan time • Stores current scan time (in 1 ms units) D9017 format
SD520 END
(in 1 ms units) Range from 0 to 65535 change
processing)
• Stores current scan time (in 100 µs units)
Current scan
Range from 00000 to 900
time S (Every
Current scan time (Example)
SD521 END New
(in 100 µs units) A current scan of 23.6 ms would be stored as follows:
processing)
D520=23
D521=600
Initial scan time • Stores the scan time of an initial execution type program into
SD522
(in 1 ms units) SD522 and SD523. (Measurement is made in 100µs units.) S (First
Initial scan
SD522: Stores the ms place. (Storage range: 0 to 65535) END New
time Initial scan time
SD523 SD523: Stores the µs place. (Storage range: 0 to 900) processing)
(in 100 µs units)

S (Every
Minimum scan time • Stores the minimum value of the scan time except that of an D9018 format
SD524 END
(in 1 ms units) initial execution type program into SD524 and SD525. change
Minimum scan processing)
(Measurement is made in 100µs units.)
time S (Every
Minimum scan time SD524: Stores the ms place. (Storage range: 0 to 65535)
SD525 END New
(in 100 µs units) SD525: Stores the µs place. (Storage range: 0 to 900)
processing)
Maximum scan time • Stores the maximum value of the scan time except that of D9019 format
SD526
(in 1 ms units) an initial execution type program into SD526 and SD527. S (Every change
Maximum scan
(Measurement is made in 100µs units.) END
time Maximum scan time
SD527 SD526: Stores the ms place. (Storage range: 0 to 65535) processing) New
(in 100 µs units)
SD527: Stores the µs place. (Storage range: 0 to 900)
Current scan Current scan time • Stores the current scan time of a low speed execution type
SD528
time (in 1 ms units) program into SD528 and SD529. (Measurement is made in S (Every
for low speed 100µs units.) END New
Current scan time
SD529 execution type SD528: Stores the ms place. (Storage range: 0 to 65535) processing)
(in 100 µs units)
programs SD529: Stores the µs place. (Storage range: 0 to 900)
Minimum scan Minimum scan time • Stores the minimum value of the scan time of a low speed
SD532
time for (in 1 ms units) execution type program into SD532 and SD533. S (Every
low speed (Measurement is made in 100µs units.) END New
Minimum scan time
SD533 execution type SD532: Stores the ms place. (Storage range: 0 to 65535) processing)
(in 100 µs units)
programs SD533: Stores the µs place. (Storage range: 0 to 900)
Maximum scan Maximum scan time • Stores the maximum value of the scan time except that of
SD534
time for (in 1 ms units) the first scan of a low speed execution type program into S (Every
low speed SD534 and SD535. (Measurement is made in 100µs units.) END New
Maximum scan time
SD535 execution type SD534: Stores the ms place. (Storage range: 0 to 65535) processing)
(in 100 µs units)
programs SD535: Stores the µs place. (Storage range: 0 to 900)
END processing time • Stores the time from the end of a scan execution type
SD540
END (in 1 ms units) program to the start of the next scan into SD540 and S (Every
processing SD541. (Measurement is made in 100µs units.) END New
END processing time
SD541 time SD540: Stores the ms place. (Storage range: 0 to 65535) processing)
(in 100 µs units)
SD541: Stores the µs place. (Storage range: 0 to 900)
Constant scan wait • Stores the wait time for constant scan setting into SD542
SD542 S (First
Constant scan time (in 1 ms units) and SD543. (Measurement is made in 100µs units.)
END New
wait time Constant scan wait SD542: Stores the ms place. (Storage range: 0 to 65535)
SD543 processing)
time (in 100 µs units) SD543: Stores the µs place. (Storage range: 0 to 900)

App - 36 App - 36
APPENDICES
MELSEC-Q

Special Register List (Continued)

Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
Cumulative
execution time for
SD544 low speed execution • Stores the cumulative execution time of a low speed
Cumulative
type programs execution type program into SD544 and SD545.
execution time S (Every
(in 1 ms units) (Measurement is made in 100µs units.)
for low speed END New
Cumulative SD544: Stores the ms place. (Storage range: 0 to 65535)
execution type processing)
execution time for SD545: Stores the µs place. (Storage range: 0 to 900)
programs
SD545 low speed execution • Cleared to 0 after the end of one low speed scan.
type programs
(in 100 µs units)
Execution time for
low speed execution • Stores the execution time of a low speed execution type
SD546
Execution time type programs program during one scan into SD546 and SD547.
S (Every
for low speed (in 1 ms units) (Measurement is made in 100µs units.)
END New
execution type Execution time for SD546: Stores the ms place. (Storage range: 0 to 65535)
processing)
programs low speed execution SD547: Stores the µs place. (Storage range: 0 to 900)
SD547
type programs • Stored every scan.
(in 100 µs units)
Scan execution type • Stores the execution time of a scan execution type program
SD548 Scan program execution during one scan into SD548 and SD549. (Measurement is
S (Every
execution type time (in 1 ms units) made in 100µs units.)
END New
program Scan execution type SD548: Stores the ms place. (Storage range: 0 to 65535)
processing)
SD549 execution time program execution SD549: Stores the µs place. (Storage range: 0 to 900)
time (in 100 µs units) • Stored every scan.
Service
interval
SD550 Unit/module No. • Sets I/O number for module that measures service interval U New
measurement
module
Module service
• Stores the service interval for the module specified in SD550 +Rem
SD551 interval
into SD551 and SD552 when SM551 is turned ON.
Service (in 1 ms units) S
(Measurement is made in 100µs units.) New
interval time Module service (Request)
SD551: Stores the ms place. (Storage range: 0 to 65535)
SD552 interval
SD552: Stores the µs place. (Storage range: 0 to 900)
(in 100 µs units)

App - 37 App - 37
APPENDICES
MELSEC-Q

Special Register List

(5) Memory card
Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
• Indicates memory card model installed
b15 to b8 b7 to b4 b3 to b0
0

Memory Memory Drive 1 0: Does not exist S (Initial and card

card card (RAM) model 1: SRAM New QCPU
removal)
models models 0: Does not exist
Drive 2 (1: SRAM)
(ROM) model 2: ATA FLASH
3: Flash ROM
SD600
• Indicates memory card A model installed
b15 to b8 b7 to b4 b3 to b0
0

Memory Memory Drive 1 0: Does not exist

S (Initial and card
card A card A (RAM) model 1: SRAM New QnA
removal)
models models 0: Does not exist
Drive 2
(ROM) model 2: EEPROM
3: Flash ROM

S (Initial and card

Drive 1 New QCPU
Drive 1 removal)
SD602 (RAM) • Drive 1 capacity is stored in 1 kbyte units
capacity S (Initial and card
capacity New QnA
removal)
S (Initial and card
Drive 2 New QCPU
Drive 2 removal)
SD603 (ROM) • Drive 2 capacity is stored in 1 kbyte units
capacity S (Initial and card
capacity New QnA
removal)
• The use conditions for memory card (A) are stored as bit patterns
(In use when ON)
• The significance of these bit patterns is indicated below:
b0: Boot operation (QBT) b8: Not used
Memory Memory b1: Parameters (QPA) b9: CPU fault history (QFD)
card use card use b2: Device comments (QCD) b10: Not used S (Status change) New QCPU
conditions conditions b3: Device initial value (QDI) b11: Local device (QDL)
b4: File register R (QDR) b12: Not used
b5: Trace (QTS) b13: Not used
b6: Not used b14: Not used
b7: Not used b15: Not used
SD604
• The use conditions for memory card A are stored as bit patterns
(In use when ON)
• The significance of these bit patterns is indicated below:
b0: Boot operation (QBT) b8: Simulation data (QDS)
Memory
Memory b1: Parameters (QPA) b9: CPU fault history (QFD)
card A
card A use b2: Device comments (QCD) b10: SFC trace (QTR) S (Status change) New QnA
use
conditions b3: Device initial value (QDI) b11: Local device (QDL)
conditions
b4: File register R (QDR) b12: Not used
b5: Sampling trace (QTS) b13: Not used
b6: Status latch (QTL) b14: Not used
b7: Program trace (QTP) b15: Not used

• Indicates the drive 3/4 models.

b15 to b8 b7 to b4 b3 to b0
0

Drive 3/4 Drive 3/4

SD620 Drive 3 S (Initial) New QCPU
models models Fixed at "1".
(Standrd RAM)

Drive 4
Fixed at "3".
(Standrd ROM)

App - 38 App - 38
APPENDICES
MELSEC-Q

Special Register List (Continued)

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
• Indicates memory card B models installed
b15 to b8 b7 to b4 b3 to b0
0
Q2A (S1)
Memory card Memory card Drive 1 0: Does not exist Q3A
SD620 (RAM) model 1: SRAM S (Initial) New
B models B models Q4A
0: Does not exist Q4AR
Drive 2
2: E 2 PROM
(ROM) model
3: Flash ROM

• Drive 3 capacity is stored in 1 kbyte units. S (Initial) New QCPU

Drive 3 Q2A (S1)
Drive 3
SD622 (RAM) Q3A
capacity • Drive 3 capacity is stored in 1 kbyte units S (Initial) New
capacity Q4A
Q4AR
• Drive 4 capacity is stored in 1 kbyte units. S (Initial) New QCPU
Drive 4 Q2A (S1)
Drive 4
SD623 (ROM) Q3A
capacity • Drive 4 capacity is stored in 1 kbyte units S (Initial) New
capacity Q4A
Q4AR
• The conditions for usage for drive 3/4 are stored as bit patterns.
(In use when ON)
• The significance of these bit patterns is indicated below:
b0: Boot operation (QBT) b8: Not used
b1: Parameters (QPA) b9: CPU fault history (QFD)
Drive 3/4 use Drive 3/4 use S (Status
b2: Device comments (QCD) b10: Not used New QCPU
conditions conditions change)
b3: Device initial value (QDI) b11: Local device (QDL)
b4: File R (QDR) b12: Not used
b5: Trace (QTS) b13: Not used
b6: Not used b14: Not used
b7: Not used b15: Not used
SD624
• The use conditions for memory card B are stored as bit patterns
(In use when ON)
• The significance of these bit patterns is indicated below:
b0: Boot operation (QBT) b8: Simulation data (QDS)
Q2A (S1)
Memory card Memory card b1: Parameters (QPA) b9: CPU fault history (QFD)
S (Status Q3A
B use B use b2: Device comments (QCD) b10: SFC trace (QTR) New
change) Q4A
conditions conditions b3: Device initial value (QDI) b11: Local device (QDL)
Q4AR
b4: File R (QDR) b12: Not used
b5: Sampling trace (QTS) b13: Not used
b6: Status latch (QTL) b14: Not used
b7: Program trace (QTP) b15: Not used

File register
SD640 Drive number: • Stores drive number being used by file register S (Initial) New
drive
SD641 • Stores file register file name (with extension) selected at parameters
SD642 or by use of QDRSET instruction as ASCII code.
b15 to b8 b7 to b0
SD643
SD641 Second character First character
SD644 SD642 Fourth character Third character
File register File register
SD645 SD643 Sixth character Fifth character S (Initial) New
file name file name
SD644 Eighth character Seventh character
SD645 First character of extension 2EH(.)
SD646 Second character of
SD646 Third character of extension extension

File register File register • Stores the data capacity of the currently selected file register in 1 k S (Status
SD647 New
capacity capacity word units. change)
File register File register S (Status
SD648 • Stores the currently selected file register block number. D9035
block number block number change)
Comment Comment • Stores the comment drive number selected at the parameters or by S (Status
SD650 New
drive drive number the QCDSET instruction. change)

App - 39 App - 39
APPENDICES
MELSEC-Q

Special Register List (Continued)

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9

SD651 • Stores the comment file name (with extension) selected at the
parameters or by the QCDSET instruction in ASCII code.
SD652 b15 to b8 b7 to b0
SD651 Second character First character
SD653 Comment file Comment file SD652 Fourth character Third character S (Status
SD653 Sixth character Fifth character New
name name change)
SD654 SD654 Eighth character Seventh character
SD655 First character of extension 2EH(.)
SD655
SD656 Third character of extension Second character of
extension
SD656
Boot
designation • Stores the drive number where the boot designation file ( .QBT) is
SD660 S (Initial) New
file drive being stored.
number
SD661 Boot • Stores the file name of the boot designation file ( .QBT).
b15 to b8 b7 to b0
operation
SD662 SD661 Second character First character
designation File name of
SD662 Fourth character Third character
SD663 file boot SD663 Sixth character Fifth character S (Initial) New
SD664 designation SD664 Eighth character Seventh character
file SD665 First character of extension 2EH(.)
SD665 Second character of
SD666 Third character of extension extension
SD666

(6) Instruction-Related Registers

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
• During block operations, turning SM705 ON makes it possible to use
SD705
the mask pattern being stored at SD705 (or at SD705 and SD706 if
Mask pattern Mask pattern U New
double words are being used) to operate on all data in the block with
SD706
the masked values.
Number of
vacant
• Stores the number of vacant blocks in the communications request
communicati S (During
SD714 0 to 32 area for remote terminal modules connected to the M9081 QnA
on request execution)
MELSECNET/MINI-S3.
registration
areas
• Patterns masked by use of the IMASK instruction are stored in the
SD715 following manner:
IMASK b15 to b1 b0
S (During
SD716 instruction Mask pattern SD715 l15 l1 l0 New
execution)
mask pattern SD716 l31 to l17 l16
SD717 SD717 l47 to l33 l32

SD718
Accumulator Accumulator • For use as replacement for accumulators used in A-series programs. S/U New
SD719
Program No. Program No.
• Stores the program number of the program to be loaded by the
designation designation
SD720 PLOAD instruction when designated. U New QCPU
for PLOAD for PLOAD
• Designation range: 1 to 124
instruction instruction
No. of vacant
registration
• Stores the number of vacant registration area for the request for
area for CC- S (During
SD730 0 to 32 communication with the intelligent device station connected to New QnA
Link execution)
A(1S)J61QBT61.
communicati
on request
• Special register that temporarily stores keyboard data input by means S (During
SD736 PKEY input PKEY input New QnA
of the PKEY instruction. execution)

App - 40 App - 40
APPENDICES
MELSEC-Q

Special Register List (Continued)

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
SD738 • Stores the message designated by the MSG instruction.
SD739 b15 to b8 b7 to b0
SD740 SD738 2nd character 1st character
SD741 SD739 4th character 3rd character
SD742 SD740 6th character 5th character
SD743 SD741 8th character 7th character
SD742 10th character 9th character
SD744
SD743 12th character 11th character
SD745
SD744 14th character 13th character
SD746
SD745 16th character 15th character
SD747 SD746 18th character 17th character
SD748 SD747 20th character 19th character
SD749 SD748 22nd character 21st character
SD750 SD749 24th character 23rd character
SD751 SD750 26th character 25th character
SD752 SD751 28th character 27th character
SD753 Message Message SD752 30th character 29th character S (During
SD753 32nd character 31st character New
SD754 storage storage execution)
SD754 34th character 33rd character
SD755
SD755 36th character 35th character
SD756 SD756 38th character 37th character
SD757 SD757 40th character 39th character
SD758 SD758 42nd character 41st character
SD759 SD759 44th character 43rd character
SD760 SD760 46th character 45th character
SD761 SD761 48th character 47th character
SD762 SD762 50th character 49th character
SD763 52nd character 51st character
SD763
SD764 54th character 53rd character
SD764
SD765 56th character 55th character
SD765
SD766 58th character 57th character
SD766 SD767 60th character 59th character
SD767 SD768 62nd character 61st character
SD768 SD769 64th character 63rd character
SD769
• Designate the limit for each PID loop as follows:
PID limit
SD774 b15 to b1 b0
setting 0: Limit set
TO SD774 Loop16 to Loop2 Loop1 U New QCPU
(for complete 1: Limit not set
SD775
derivative) SD775 Loop32 to Loop18 Loop17

b0 to b14:
0:Do not • Selects whether or not the data is refreshed when the COM
refresh instruction is executed.
1:Refresh • Designation of SD778 is made valid when SM775 turns ON.
Refresh
b15 b14 to b5 b4 b3 b2 b1 b0
processing b15 bit
SD778 1/0 0 1/0 1/0 1/0 1/01/0
selection 0: General QCPU
I/O refresh
SD778 when the data U New Serial number
CC-Link refresh
COM processing MELSECNET/H refresh 04012 or later
instruction is executed Automatic refresh of intelligent
executed 1: General function modules

data Automatic refresh of CPU shared

memory
processing
Execution/non-execution of
not general data processing
executed

App - 41 App - 41
APPENDICES
MELSEC-Q

Special Register List

(7) Debug
Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
Remaining
No. of
simultaneous
• Stores the remaining number of simultaneous execution of the CC-
SD780 execution of 0 to 32 U New QnA
Link dedicated instructions.
CC-Link
dedicated
instruction
• Stores the mask patterns masked by the IMASK instruction as
follows:
b15 b1 b0
SD781 l63 to l49 l48
SD781 Mask pattern
S (During
TO of IMASK Mask pattern SD782 l79 to l65 l64 New QCPU
execution)
SD793 instruction
to

SD793 l255 to l241 l240

PID limit
b15 b1 b0 QCPU
SD794 setting
0: Limit set SD794 Loop 16 to Loop 2 Loop 1 Serial No.
TO (for U New
1: Limit not set 05032
SD795 incomplete SD795 Loop 32 to Loop 18 Loop 17 or later
derivative)

SD806 • Stores file name (with extension) from point in time when status latch
was conducted as ASCII code.
b15 to b8 b7 to b0
SD807
SD806 Second character First character
SD807 Fourth character Third character
SD808
Status latch Status latch SD808 Sixth character Fifth character S (During
New
file name file name SD809 Eighth character seventh character execution)
SD809
First character of
SD810 2EH(.)
extension
SD810
Third character of 2nd character of
SD811
extension extension
SD811

• Stores step number from point in time when status latch was
SD812 QnA
conducted.
SD812 Patterm
SD813 Block number
SD813 SD814 Step No./Transition condition No.
SD815 Sequence step No.(L)
Status latch Status latch SD816 Sequence step No.(H) S (During D9055 format
SD814
step step execution) change
Contents of pattern data
15 14 to 4 3 2 1 0 (Bit number)
SD815 0 0 to 0 0

(Not in use) SFC block designation present (1)/absent (0)

SFC block designation present (1)/absent (0)
SD816 SFC transition designation present (1)/absent (0)

App - 42 App - 42
APPENDICES
MELSEC-Q

Special Register List

(8) Latch area
Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
Access file
Drive where
drive number S (Status
SD900 power was • Stores drive number if file was being accessed during power loss. New
during power change)
interrupted
loss

SD901 • Stores file name (with extension) in ASCII code if file was being
accessed during power loss.
b15 to b8 b7 to b0
SD902
SD901 2nd character 1st character
File name Access file
SD902 4th character 3rd character
SD903
SD903 6th character 5th character S (Status
active during name during New
SD904 8th character 7th character change)
SD904 power loss power loss
1st character of
SD905 extension 2EH(.)
SD905
3rd character of 2nd character of
SD906 extension extension
SD906

SD910 • Stored in sequence that PU key code was entered.

b15 to b8 b7 to b0 QnA
SD911
SD912 SD910 2nd character 1st character
SD911 4th character 3rd character
SD913
SD912 6th character 5th character
SD914 SD913 8th character 7th character
SD915 SD914 10th character 9th character
SD916 SD915 12th character 11th character
SD917 SD916 14th character 13th character S (During
RKEY input RKEY input SD917 16th character 15th character New
SD918 execution)
SD918 18th character 17th character
SD919
SD919 20th character 19th character
SD920 SD920 22nd character 21st character
SD921 SD921 24th character 23rd character
SD922 SD922 26th character 25th character
SD923 SD923 28th character 27th character
SD924 30th character 29th character
SD924
SD925 32nd character 31st character
SD925

App - 43 App - 43
APPENDICES
MELSEC-Q

(9) A to Q/QnA conversion correspondences

ACPU special registers D9000 to D9255 correspond to the special registers SD1000 to
SD1255 after A-series to the Q/QnA-series conversion.
These special registers are all set by the system, and users cannot use them to set program
data.
Users who need to set data with these registers should edit the special registers for the
Q/QnA.
However, before conversion users could set data at special registers D9200 to D9255 only,
and after conversion users can also set data at registers 1200 to 1255.
For more detailed information concerning the contents of the ACPU special registers, see
the individual CPU users manual, and the MELSECNET and MELSECNET/B data link
system reference manual.

REMARK

Supplemental explanation on "Special Register for Modification" column

1 For the device numbers for which a special register for modification is specified, modify it to
the special register for QCPU/QnACPU.
2 For the device numbers for which is specified, special register after conversion can be
used.
3 Device numbers for which is specified do not function for QCPU/QnACPU.

Special Register List

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• When fuse blown modules are detected, the first I/O
number of the lowest number of the detected modules is
stored in hexadecimal.
(Example: When fuses of Y50 to 6F output modules have
Number of blown, "50" is stored in hexadecimal) To monitor the
D9000 SD1000 Fuse blown module with number by peripheral devices, perform monitor operation
blown fuse given in hexadecimal.
(Cleared when all contents of SD1100 to SD1107 are reset
to 0.)
• Fuse blow check is executed also to the output modules of
remote I/O stations.
• Stores the module numbers corresponding to setting
switch numbers or base slot numbers when fuse blow
occurred.
I/O module for A0J2 Extension base unit
Setting Base unit
Stored data Stored data
switch slot No.
Number of 0 1 0 5
D9001 SD1001 Fuse blown module with 1 2 1 6
blown fuse
2 3 2 7
3 4 3 8
4 5
5 6
6 7
7 8

App - 44 App - 44
APPENDICES
MELSEC-Q

Special Register List (Continued)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• If I/O modules, of which data are different from data
entered, are detected when the power is turned on,
the first I/O number of the lowest number unit among
the detected units is stored in hexadecimal. (Storing
I/O module method is the same as that of SD1000.)
I/O module
D9002 SD1002 verification error To monitor the number by peripheral devices, perform
verification error
module number monitor operation given in hexadecimal.
(Cleared when all contents of SD1116 to SD1123 are
reset to 0.)
• I/O module verify check is executed also to the
modules of remote I/O terminals.
• Error status of the MINI(S3) link detected on loaded
AJ71PT32(S3) is stored.
b15 to b8 b7 to b0

8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Stores setting
status made at
D9004 SD1004 MINI link errors QnA
parameters Bits which correspond to faulty Bits which correspond to the signals of
AJ71PT32(S3) are turned on. AJ71PT32(S3), shown below, are
(modules 1 to 8) turned on as the signals are turned on.
• Hardware error (X0/X20)
• MINI(S3) link error datection (X6/X26)
• MINI(S3) link communication error
(X7/X27)

When the AC power supply module is used, 1 is added

at occurrence of an instantaneous power failure of
within 20ms.
(The value is stored in BIN code.)It is reset when power
is switched from OFF to ON.
When the DC power supply module is used, 1 is added
at occurrence of an instantaneous power failure of
AC DOWN Number of times for
D9005 SD1005 within 10ms.
counter AC DOWN (The value is stored in BIN code.)It is reset when power
is switched from OFF to ON.
When the DC power supply module is used, 1 is added
at occurrence of an instantaneous power failure of
within 1ms. QnA
(The value is stored in BIN code.)It is reset when power
is switched from OFF to ON.
Self-diagnosis Self-diagnosis error • When error is found as a result of self-diagnosis, error
D9008 SD1008 SD0
error number number is stored in BIN code.
• When one of F0 to 255 is turned on by OUT F or
SET F , the F number, which has been detected
earliest among the F numbers which have turned on,
QCPU
is stored in BIN code.
Q2AS
• SD62 can be cleared by RST F or LEDR
Q2A
instruction. If another F number has been detected,
the clearing of SD62 causes the next number to be
F number at which stored in SD62.
Annunciator
D9009 SD1009 SD62 external failure has • When one of F0 to 255 is turned on by OUT F or
detection
occurred SET F , the F number, which has been detected
earliest among the F numbers which have turned on,
is stored in BIN code. Q3A
• SD62 can be cleared by executing RST F or Q4A
LEDR instruction or moving INDICATOR RESET Q4AR
switch on CPU module front to ON position.
If another F number has been detected, clearing of
SD62 stores the next F number into SD62.
• When operation error has occurred during execution
Step number at of application instruction, the step number, at which
D9010 SD1010 Error step which operation the error has occurred, is stored in BIN code.
error has occurred. Thereafter, each time operation error occurs, the
contents of SD1010 are renewed.

App - 45 App - 45
APPENDICES
MELSEC-Q

Special Register List (Continued)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• When operation error has occurred during execution
of application instruction, the step number, at which
Step number at
the error has occurred, is stored in BIN code. Since
D9011 SD1011 Error step which operation
the step number is stored into SD1011 when SM1011
error has occurred.
turns from OFF to ON, the data of SD1011 is not
updated unless SM1011 is cleared by a user program.
• The I/O control mode set is returned in any of the
following numbers:
I/O control mode
D9014 SD1014 I/O control mode 0. Both input and output in direct mode
number
1. Input in refresh mode, output in direct mode
3. Both input and output in refresh mode
• The operation status of CPU as shown below are
stored in SD203.

Operating status Operating status of

D9015 SD1015 SD203
of CPU CPU

1 When the CPU mdoule is in RUN mode and

SM1040 is off, the CPU module remains in RUN
mode if changed to PAUSE mode.
0: Main program
(ROM)
1: Main program
(RAM)
2: Subprogram 1
(RAM)
3: Subprogram 2
(RAM)
4: Subprogram 3
(RAM)
5: Subprogram 1
Program (ROM) • Indicates which sequence program is run presently.
D9016 SD1016
number 6: Subprogram 2 One value of 0 to B is stored in BIN code.
(ROM)
7: Subprogram 3
(ROM)
8: Main program
(E2PROM)
9: Subprogram 1
(E2PROM)
A: Subprogram 2
(E2PROM)
B: Subprogram 3
(E2PROM)
• If scan time is smaller than the content of SD520, the
Minimum scan time value is newly stored at each END. Namely, the
D9017 SD1017 SD520 Scan time
(10 ms units) minimum value of scan time is stored into SD520 in
BIN code.
Scan time • Scan time is stored in BIN code at each END and
D9018 SD1018 SD524 Scan time
(10 ms units) always rewritten.

App - 46 App - 46
APPENDICES
MELSEC-Q

Special Register List (Continued)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• If scan time is larger than the content of SD526, the
Maximum scan value is newly stored at each END. Namely, the
D9019 SD1019 SD526 Scan time maximum value of scan time is stored into SD526 in
time (10 ms units)
BIN code.
• Sets the interval between consecutive program starts
Constant scan time in multiples of 10 ms.
D9020 SD1020 Constant scan (User sets in 10 ms 0: No setting
units) 1 to 200: Set. Program is executed at intervals of
(set value) × 10 ms.
Scan time • Scan time is stored and updated in BIN code after
D9021 SD1021 Scan time
(1 ms units) every END.
• When the PC CPU starts running, it starts counting 1
every second.
1 second
D9022 SD1022 SD412 Count in units of 1s. • It starts counting up from 0 to 32767, then down to
counter
-32768 and then again up to 0. Counting repeats this
routine.
• Stores the year (2 lower digits) and month in BCD.
b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example:
Clock data 1987, July
D9025 SD1025 SD210 Clock data
(year, month) H8707

Year Month
• Stores the day and hour in BCD.
b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example
Clock data
D9026 SD1026 SD211 Clock data 31th, 10 o'clock
(day, hour) H3110
Day Hour
• Stores the Minute and second in BCD.
b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example:
Clock data
D9027 SD1027 SD212 Clock data 35 minutes,
(minute, second) 48 seconds
Minute Second H3548

• Stores the day of the week in BCD.

b15 to b12 b11 to b8 b7 to b4 b3 to b0 Example:
Friday
H0005

Day of the week

Clock data 0 Sunday
D9028 SD1028 SD213 Clock data
(day of week) 1 Monday
0 must be set. 2 Tuesday
3 Wednesday
4 Thursday
5 Friday
6 Saturday

Extension file • Stores the block No. of the extension file register
D9035 SD1035 SD648 Use block No.
register being used in BCD code.
• Designate the device number for the extension file
register for direct read and write in 2 words at SD1036
and SD1037 in BIN data.
D9036 SD1036 Use consecutive numbers beginning with R0 of block
Device number
No. 1 to designate device numbers.
Extension file when individual Exetension file register
registerfor devices from 0

designation of extension file to Block No.1 area

16383
device number register are directly 16384
accessed to Block No.2 area
D9037 SD1037 SD1037,SD1036
Device No. (BIN data)
to

D9038 SD1038 SD207 Priorities 1 to 4 • Sets priority of ERROR LEDs which illuminate (or
flicker) to indicate errors with error code numbers.
• Configuration of the priority setting areas is as shown
below.
LED display b15 to b12 b11 to b8 b7 to b4 b3 to b0
SD207 Priority 4 Priority 3 Priority 2 Priority 1
D9039 SD1039 SD208 priority ranking Priorities 5 to 7
SD208 Priority 7 Priority 6 Priority 5
• For details, refer to the applicable CPUs User’s
Manual and the ACPU Programming manual
(Fundamentals).

App - 47 App - 47
APPENDICES
MELSEC-Q

Special Register List (Continued)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• Turned on/off with a peripheral device.
For sampling Step or time during At scanning----------0
D9044 SD1044
trace sampling trace At time ----------------Time (10 msec unit)
Stores the value in BIN code.
• Stores the block number of the expansion file register
which is used as the work area for the execution of a
Block number of
Work area for SFC program in a binary value.
D9049 SD1049 extension file
SFC • Stores "0" if an empty area of 16K bytes or smaller,
register
which cannot be expansion file register No. 1, is used
or if SM320 is OFF.
• Stores error code of errors occurred in the SFC
program in BIN code.
0: No error
Error code 80: SFC program parameter error
SFC program
D9050 SD1050 generated by SFC 81: SFC code error
error number
program 82: Number of steps of simultaneous execution
exceeded
83: Block start error
84: SFC program operation error
• Stores the block number in which an error occurred in
Block number
the SFC program in BIN code.
D9051 SD1051 Error block where error
In the case of error 83 the starting block number is
occurred
stored.
• Stores the step number, where error code 84 occurred
in an SFC program, in BIN value.
Step number where
D9052 SD1052 • Stores "0" when error code 80, 81 or 82 occurred.
error occurred
• Stores the block stating step number when error code
83 occurs.
Transition condition • Stores the transition condition number, where error
D9053 SD1053 Error transition number where error code 84 occurred in an SFC program, in BIN value.
occurred Stores "0" when error code 80, 81, 82 or 83 occurred.
Sequence step • Stores the sequence step number of transfer condition
Error sequence
D9054 SD1054 number where error and operation output in which error 84 occurred in the
step
occurred SFC program in BIN code.
• Stores the step number when status latch is executed.
• Stores the step number in a binary value if status latch
is executed in a main sequence program.
• Stores the block number and the step number if status
D9055 SD1055 SD812 Status latch Status latch step latch is executed in a SFC program.
Block No. Step No.
(BIN) (BIN)
Higher 8 bits Lower 8 bits
• Stores the software version of the internal system in
ASCII code.
The data in the lower byte
position is indefinite.
Higher byte Lower byte The software version is stored
Software version of
D9060 SD1060 SD392 Software version in the higher byte position. QnA
internal software
For version "A", for example, "41H" is stored.
Note: The software version of the initial system may
differ from the version indicated by the version
information printed on the rear of the case.
PLC • In the self-loopback test of the serial communication
Computer link data
D9072 SD1072 communications module, the serial communication module writes/reads
check
check data automatically to make communication checks.
Number of Number of empty
• Stores the number of empty blocks in the
empty blocks in blocks in
communication request registration area to the remote
D9081 SD1081 SD714 communications communications QnA
terminal module connected to the MELSECNET/MINI-
request request registration
S3 master unit, A2CCPU or A52GCPU.
registrtion area area

App - 48 App - 48
APPENDICES
MELSEC-Q

Special Register List (Continued)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• Sets the time check time of the data link instructions
(ZNRD, ZNWR) for the MELSECNET/10.
Register for
• Setting range: 1 s to 65535 s (1 to 65535)
D9085 SD1085 setting time Default value 10s
• Setting unit: 1s
check value
• Default value: 10 s (If 0 has been set, default
10 s is applied)
Number of Number of special
• For details, refer to the manual of each microcomputer
D9090 SD1090 special functions functions modules
program package.
modules over over
Detailed error Self-diagnosis
D9091 SD1091 • Stores the detail code of cause of an instruction error.
code detailed error code
Head I/O • Stores the first two digits of the head I/O number of
Head I/O number of the I/O module, which will be dismounted/mounted
number of I/O
D9094 SD1094 SD251 I/O module to be online, in BIN value.
module to be
replaced
replaced Example) Input module X2F0 → H2F
• The DIP switch information of the CPU module is
stored in the following format.
0: OFF
1: ON
b15 b5 b4 b3 b2 b1 b0
DIP switch DIP switch
D9095 SD1095 SD200 D9095 0 QCPU
information information
SW1
SW2
SW3
SW4
SW5

D9100 SD1100 • Output module numbers (in units of 16 points), of

which fuses have blown, are entered in bit pattern.
D9101 SD1101 (Preset output unit numbers when parameter setting
has been performed.)
b15 b14b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D9102 SD1102 1 1
SD1100 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit pattern in units (YCO) (Y80)

D9103 SD1103 of 16 points, SD1101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Fuse blown
indicating the SD1107 0 0 0 0
1
Y7 0 0 0 0 0 0 0
1
0 0 0
module B0
Y7
30
D9104 SD1104 modules whose
fuses have blown Indicates fuse blow.
D9105 SD1105 • Fuse blow check is executed also to the output
module of remote I/O station.
D9106 SD1106 (If normal status is restored, clear is not performed.
Therefore, it is required to perform clear by user
D9107 SD1107 program.)
• Set the set value of the step transition watchdog timer
D9108 SD1108
and the annunciator number (F number) that will turn
on when the watchdog timer times out.
D9109 SD1109 b15 to b8 b7 to b0

D9110 SD1110
Step transfer Timer setting valve Timer setting
D9111 SD1111 monitoring timer and the f number at (1 to 255 s in seconds)
setting time out
F number setting
D9112 SD1112
(By turning on any of MSM708 to SM1114, the
D9113 SD1113 monitoring timer starts. If the transfer condition
following a step which corresponds to the timer is not
established within set time, set annunciator (F) is
D9114 SD1114
tuned on.)

App - 49 App - 49
APPENDICES
MELSEC-Q

Special Register List (Continued)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• When I/O modules, of which data are different from
D9116 SD1116
those entered at power-on, have been detected, the
I/O unit numbers (in units of 16 points) are entered in
D9117 SD1117
bit pattern. (Preset I/O unit numbers when parameter
setting has been performed.)
D9118 SD1118 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1
Bit pattern, in units SD1116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XY
0

D9119 SD1119 of 16 points, SD1117 0 0 0 0 0 0

1
0 0 0 0 0 0 0 0 0
I/O module XY
190
indicating the 1
verification error SD1123 0 0 0 0 XY 0 0 0 0 0 0 0 0 0 0 0
D9120 SD1120 modules with 7B0

verification errors.
Indicates I/O module verify error.
D9121 SD1121
• I/O module verify check is executed also to remote
I/O station modules.
D9122 SD1122 (If normal status is restored, clear is not performed.
Therefore, it is required to perform clear by user
D9123 SD1123 program.)
• When one of F0 to 255 (F0 to 2047 for AuA and AnU)
is turned on by SET F 1 is added to the contents of
SD63. When RST F or LEDR instruction is
executed, 1 is subtracted from the contents of SD63.
Annunciator
Annunciator (If the INDICATOR RESET switch is provided to the
D9124 SD1124 SD63 detection
detection quantity CPU module, pressing the switch can execute the
quantity
same processing.)
• Quantity, which has been turned on by SET F is
stored into SD63 in BIN code. The value of SD63 is
maximum 8.

• When any of F0 to 2047 is turned on by SET F , the

D9125 SD1125 SD64
annunciator numbers (F numbers) that are turned on
in order are registered into D9125 to D9132.
• The F number turned off by RST F is erased from
D9126 SD1126 SD65 any of D9125 to D9132, and the F numbers stored
after the erased F number are shifted to the preceding
registerers.
By executing LEDR instruction, the contents of
SD64 to SD71 are shifted upward by one. (For A3N,
D9127 SD1127 SD66
A3HCPU, it can be performed by use of INDICATOR
RESET switch on front of CPU module.)
When there are 8 annunciator detections, the 9th one
is not stored into SD64 to SD71 even if detected.
D9128 SD1128 SD67
SET SET SET RST SET SET SET SET SET SET SET
Annunciator F50 F25 F99 F25 F15 F70 F65 F38 F110 F151 F210 LEDR
Annunciator
detection
detection number
number SD62 0 50 50 50 50 50 50 50 50 50 50 50 99

D9129 SD1129 SD68 SD63 0 1 2 3 2 3 4 5 6 7 8 8 8

SD64 0 50 50 50 50 50 50 50 50 50 50 50 99

SD65 0 0 25 25 99 99 99 99 99 99 99 99 15
D9130 SD1130 SD69
SD66 0 0 0 99 0 15 15 15 15 15 15 15 70

SD67 0 0 0 0 0 0 70 70 70 70 70 70 65

SD68 0 0 0 0 0 0 0 65 65 65 65 65 38
D9131 SD1131 SD70
SD69 0 0 0 0 0 0 0 0 38 38 38 38 110

SD70 0 0 0 0 0 0 0 0 0 110 110 110 151

SD71 0 0 0 0 0 0 0 0 0 0 151 151 210

D9132 SD1132 SD71

App - 50 App - 50
APPENDICES
MELSEC-Q

Special Register List

(10) Special register list dedicated for QnA
ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
Stores the execution result of the ZNRD (word device
0: Normal end read) instruction
2: ZNRD instruction • ZNRD instruction setting Faulty setting of the
ZNRD
setting fault fault: ZNRD instruction
(LRDP for
3: Error at relevant constant, source,
D9200 SD1200 ACPU)
station and/or destination
processing
4: Relevant station • Corresponding station error: One of the stations is
results
ZNRD execution not communicating.
disabled • ZNRD cannot be executed The specified station is
in the corresponding station: a remote I/O station.
Stores the execution result of the ZNWR (word device
0: Normal end
write) instruction.
2: ZNWR
• ZNWR instruction setting Faulty setting of the
ZNWR instruction setting
(LWTP for fault: ZNWR instruction
fault
D9201 SD1201 ACPU) 3: Error at relevant constant, source,
processing station and/or destination.
results 4: Relevant station • Corresponding station error: One of the stations is
ZNWR execution not communicating.
disabled • ZNWR cannot be executed The specified station is QnA
in the corresponding station: a remote I/O station.
Stores whether the slave station corresponds to
MELSECNET or MELSECNET11.
• Bits corresponding to the MELSECNET 11 stations
Stores conditions become "1."
D9202 SD1202 for up to numbers 1 • Bits corresponding to the MELSECNET stations or
to 16 unconnected become "0."
Device Bit
number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SD1202 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
SD1203 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
Local station link
SD1241 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
type SD1242 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49

• If a local station goes down during the operation, the

contents before going down are retained.
Stores conditions Contents of SD1224 to SD1227 and SD1228 to
D9203 SD1203 for up to numbers SD1231 are ORed. If the corresponding bit is "0", the
17 to 32 corresponding bit of the special register above
becomes valid.
• If the own (master) station goes down, the contents
before going down are also retained.
0: Forward loop,
during data link Stores the present path status of the data link.
1: Reverse loop, • Data link in forward loop
during data link Master
2: Loopback station
Station 1 Station 2 Station n
implemented in
forward/reverse
directions
3: Loopback Forward loop Reverse loop
D9204 SD1204 Link status QnA
implemented
• Data link in reverse loop
only in forward Master
direction station
Station 1 Station 2 Station n
4: Loopback
implemented
only inreverse
direction
5: Data link Forward loop Reverse loop
disabled

App - 51 App - 51
APPENDICES
MELSEC-Q

Special Register List (Continue)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
• Loopback in forward/reverse loops
Master
station
0: Forward loop, Station 1 Station 2 Station 3 Station n
during data link
1: Reverse loop,
during data link
Forward loopback Reverse loopback
2: Loopback
implemented in • Loopback in forward loop only
Master
forward/reverse
station
Station 1 Station 2 Station 3 Station n
directions
D9204 SD1204 Link status
3: Loopback
implemented only
in forward Forward loopback
direction • Loopback in reverse loop only
4: Loopback Master
station
implemented only Station 1 Station 2 Station 3 Station n
inreverse direction
5: Data link disabled

Reverse loopback
Stores the local or remote I/O station number at which QnA
loopback is being executed.
Station Station that Master
D9205 SD1205 implementing implemented forward station
Station 1 Station 2 Station 3 Station n
loopback loopback

Forward loopback Reverse loopback

In the above example, 1 is stored into D9205 and 3
Station Station that
into D9206. If data link returns to normal status (data
D9206 SD1206 implementing implemented reverse
link in forward loop), values in D9205 and D9206
loopback loopback
remain 1 and 3. To return them to "0", therefore, use a
sequence program or perform reset operation.
Stores the number of retry times due to transmission
Number of Stored as cumulative error.
D9210 SD1210
retries value Count stops at maximum of "FFFFH" .
To return the value to "0", perform reset operation.
Stores the number of times the loop line has been
Number of times Stored as cumulative switched to reverse loop or loopback.
D9211 SD1211
loop selected value Count stops at maximum of "FFFFH".
To return the value to "0", perform reset operation.
Stores conditions for Stores the local station numbers which are in STOP or
Local station
D9212 SD1212 up to numbers 1 to PAUSE mode.
operation status Device Bit
16 number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Stores conditions for SD1212 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
Local station SD1213 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
D9213 SD1213 up to numbers 17 to
operation status SD1214 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
32 SD1215 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49

Stores conditions for When a local station is switched to STOP or PAUSE QnA
Local station
D9214 SD1214 up to numbers 33 to mode, the bit corresponding to the station number in
operation status
48 the register becomes "1".
Example: When station 7 switches to STOP mode,
Stores conditions for
Local station b6 in SD1212 becomes "1" , and when
D9215 SD1215 up to numbers 49 to
operation status SD1212 is monitored, its value is "64
64
(40H)".

App - 52 App - 52
APPENDICES
MELSEC-Q

Special Register List (Continue)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
Stores conditions Stores the local station numbers which are in
D9216 SD1216 for up to numbers error.
1 to 16 Bit
Device
Stores conditions number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SD1216 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
D9217 SD1217 for up to numbers
Local station SD1217 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
17 to 32 SD1218 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
error detect
Stores conditions SD1219 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49
status
D9218 SD1218 for up to numbers If a local station detects an error, the bit corresponding to
33 to 48 the station number becomes "1".
Stores conditions Example: When station 6 and 12 detect an error, b5 and
D9219 SD1219 for up to numbers 11 in SD1216 become "1", and when SD1216
49 to 64 is monitored, its value is "2080 (820H)".
Stores conditions Stores the local station numbers which contain
D9220 SD1220 for up to numbers mismatched parameters or of remote station numbers for
1 to 16 which incorrect I/O assignment has been made.
Device Bit
Stores conditions number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D9221 SD1221 for up to numbers SD1220 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1

Local station 17 to 32 SD1221 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
SD1222 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
parameters Stores conditions SD1223 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49
D9222 SD1222 non-conforming; for up to numbers
If a local station acting as the master station of tier three
remote I/O 33 to 48
detects a parameter error or a remote I/O station whose
station I/O I/O assignment is abnormal, the bit of the device number
allocation error corresponding to the station number of that local station
Stores conditions or remote I/O station turns to "1".
D9223 SD1223 for up to numbers Example: When local station 5 and remote I/O station
49 to 64 14 detect an error, b4 and b13 in SD1220
become "1" , and when SD1220 is monitored,
its value is "8208 (2010H) " . QnA
Stores conditions Stores the local or remote station numbers while they are
D9224 SD1224 for up to numbers communicating the initial data with their relevant master
1 to 16 station.
Device Bit
Stores conditions number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D9225 SD1225 for up to numbers SD1224 L/R
16
L/R
15
L/R
14
L/R
13
L/R
12
L/R
11
L/R
10
L/R
9
L/R L/R L/R L/R L/R L/R L/R L/R
8 7 6 5 4 3 2 1
Local station 17 to 32 SD1225 L/R
32
L/R
31
L/R
30
L/R
29
L/R
28
L/R
27
L/R
26
L/R
L/R L/R L/R L/R L/R L/R L/R L/R
25
24 23 22 21 20 19 18 17
L/R L/R L/R L/R L/R L/R L/R L/R
L/R L/R L/R L/R L/R L/R L/R L/R
and remote I/O Stores conditions SD1226 48 47 46 45 44 43 42 41
40 39 38 37 36 35 34 33
L/R L/R L/R L/R L/R L/R L/R L/R
L/R L/R L/R L/R L/R L/R L/R L/R
SD1227 64 63 62 61 60 59 58 57
56 55 54 53 52 51 50 49
D9226 SD1226 station initial for up to numbers
communications 33 to 48 The bit corresponding to the station number which is
underway currently communicating the initial settings becomes "1" .
Example: When stations 23 and 45 are communicating,
Stores conditions b6 of SD1225 and b12 of SD1226 become
D9227 SD1227 for up to numbers "1", and when SD1225 is monitored, its value
49 to 64 is "64 (40H)", and when SD1226 is monitored,
its value is "4096 (1000H)"
Stores conditions Stores the local or remote station numbers which are in
D9228 SD1228 for up to numbers error.
Device Bit
1 to 16 number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Stores conditions SD1228 L/R
16
L/R
15
L/R
14
L/R
13
L/R
12
L/R
11
L/R
10
L/R
9
L/R
8
L/R
7
L/R
6
L/R
5
L/R
4
L/R
3
L/R
2
L/R
1
L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R
D9229 SD1229 for up to numbers SD1229 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R
Local station 17 to 32
SD1230 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R L/R
SD1231 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
and remote I/O Stores conditions
station error The bit corresponding to the station number with the error
D9230 SD1230 for up to numbers
becomes "1" .
33 to 48
Example: When local station 3 and remote I/O station
Stores conditions 14 have an error, b2 and b13 of SD1228
D9231 SD1231 for up to numbers become "1", and when SD1228 is monitored,
49 to 64 its value is "8196 (2004H)".

App - 53 App - 53
APPENDICES
MELSEC-Q

Special Register List (Continue)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
Stores conditions
D9232 SD1232 for up to numbers Stores the local or remote station number at which a
1 to 8 forward or reverse loop error has occurred
Device Bit
Stores conditions number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D9233 SD1233 for up to numbers R F R F R F R F R F R F R F R F
SD1232
9 to 16 L/R8 L/R7 L/R6 L/R5 L/R4 L/R3 L/R2 L/R1
R F R F R F R F R F R F R F R F
Stores conditions SD1233
L/R16 L/R15 L/R14 L/R13 L/R12 L/R11 L/R10 L/R9
D9234 SD1234 for up to numbers R F R F R F R F R F R F R F R F
SD1234
17 to 24 L/R24 L/R23 L/R22 L/R21 L/R20 L/R19 L/R18 L/R17
R F R F R F R F R F R F R F R F
Stores conditions SD1235
L/R32 L/R31 L/R30 L/R29 L/R28 L/R27 L/R26 L/R25
D9235 SD1235 for up to numbers R F R F R F R F R F R F R F R F
Local station and SD1236
L/R40 L/R39 L/R38 L/R37 L/R36 L/R35 L/R34 L/R33
25 to 32
remote I/O station SD1237
R F R F R F R F R F R F R F R F
Stores conditions L/R48 L/R47 L/R46 L/R45 L/R44 L/R43 L/R42 L/R41
loop error
D9236 SD1236 for up to numbers SD1238
R F R F R F R F R F R F R F R F
L/R56 L/R55 L/R54 L/R53 L/R52 L/R51 L/R50 L/R49
33 to 40
R F R F R F R F R F R F R F R F
SD1239
Stores conditions L/R64 L/R63 L/R62 L/R61 L/R60 L/R59 L/R58 L/R57
D9237 SD1237 for up to numbers In the above table, "F" indicates a forward loop line and
41 to 48 "R" a reverse loop line .The bit corresponding to the
Stores conditions station number at which the forward or reverse loop error
D9238 SD1238 for up to numbers has occurred, becomes "1".
49 to 56 Example: When the forward loop line of station 5 has an
Stores conditions error, b8 of SD1232 become "1", and when
D9239 SD1239 for up to numbers SD1232 is monitored, its value is "256 (100H)".
57 to 64
Stores the number of times the following transmission
Number of times Stores errors have been detected:
D9240 SD1240 communications cumulative total CRC, OVER, AB. IF
errors detected of receive errors Count is made to a maximum of FFFFH. To return the
value to "0", perform reset operation. QnA

Stores whether the slave station corresponds to

MELSECNET or MELSECNET11.
• Bits corresponding to the MELSECNET 11 stations
Stores conditions become "1."
D9241 SD1241 for up to numbers • Bits corresponding to the MELSECNET stations or
33 to 48 unconnected become "0."
Device Bit
number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SD1202 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
SD1203 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
Local station link
SD1241 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
type SD1242 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49

• If a local station goes down during the operation, the

contents before going down are retained.
Stores conditions Contents of SD1224 to SD1227 and SD1228 to SD1231
D9242 SD1242 for up to numbers are ORed. If the corresponding bit is "0", the
49 to 64 corresponding bit of the special register above becomes
valid.
• If the own (master) station goes down, the contents
before going down are also retained.
Station number
Stores station
D9243 SD1243 information for host Allows a local station to confirm its own station number
number (0 to 64)
station
Number of link Stores number of
D9244 SD1244 Indicates the number of slave stations in one loop.
device stations slave stations
Stores the number of times the following transmission
Number of times Stores
errors have been detected: CRC, OVER, AB. IF
D9245 SD1245 communications cumulative total
Count is made to a maximum of FFFFH. To return the
errors detected of receive errors
value to "0", perform reset operation.

App - 54 App - 54
APPENDICES
MELSEC-Q

Special Register List (Continue)

ACPU Special Special
Corresponding
Special Register after Register for Name Meaning Details
CPU
Conversion Conversion Modification
Stores conditions Stores the local station number which is in STOP or PAUSE
D9248 SD1248 for up to numbers 1 mode.
Device Bit
to 16 number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Stores conditions SD1248 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
D9249 SD1249 for up to numbers SD1249 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
Local station 17 to 32 SD1250 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
SD1251 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49
operation Stores conditions
status The bit corresponding to the station number which is in
D9250 SD1250 for up to numbers
STOP or PAUSE mode, becomes "1".
33 to 48
Example: When local stations 7 and 15 are in STOP mode,
Stores conditions b6 and b14 of SD1248 become "1", and when
D9251 SD1251 for up to numbers SD1248 is monitored, its value is "16448
49 to 64 (4040H)". QnA
Stores conditions Stores the local station number other than the host, which is
D9252 SD1252 for up to numbers 1 in error.
to 16 Device Bit
number b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Stores conditions
SD1252 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1
D9253 SD1253 for up to numbers SD1253 L32 L31 L30 L29 L28 L27 L26 L25 L24 L23 L22 L21 L20 L19 L18 L17
Local station
17 to 32 SD1254 L48 L47 L46 L45 L44 L43 L42 L41 L40 L39 L38 L37 L36 L35 L34 L33
error SD1255 L64 L63 L62 L61 L60 L59 L58 L57 L56 L55 L54 L53 L52 L51 L50 L49
Stores conditions
conditions
D9254 SD1254 for up to numbers The bit corresponding to the station number which is in error,
33 to 48 becomes "1".
Stores conditions Example: When local station 12 is in error, b11 of SD1252
D9255 SD1255 for up to numbers becomes "1", and when SD1252 is monitored, its
49 to 64 value is "2048 (800H) ".

(11) Fuse blown module

Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
SD1300 • The numbers of output modules whose fuses have blown are D9100
SD1301 input as a bit pattern (in units of 16 points). D9101
SD1302 (If the module numbers are set by parameter, the parameter-set D9102
SD1303 numbers are stored.) D9103
Bit pattern in units
SD1304 • Also detects blown fuse condition at remote station output D9104
of 16 points,
modules
SD1305 indicating the D9105
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SD1306 Fuse blown modules whose 1 1 D9106
SD1300 0 0 0 (YC0) 0 0 0 (Y80) 0 0 0 0 0 0 0 0 S (Error) +Rem
SD1307 module fuses have blown D9107
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
SD1308 0: No blown fuse SD1301 (Y1F0) (Y1A) New
SD1309 1: Blown fuse 1 1
to present SD1331 0 0 0 0 (Y1F B0)
0 0 0 0 0 0 0 (Y1F 0 0 0
30) New to New
SD1330 Indicates a blown fuse
• Not cleared even if the blown fuse is replaced with a new one.
SD1331 New
This flag is cleared by error resetting operation
Bit pattern in units The module number (in units of 16 points) whose external power
of 16 points, supply has been disconnected is input as a bit pattern.
indicating the (If the module numbers are set by parameter, the parameter-set
modules whose numbers are used.)
External b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
external power
power supply
SD1350 supply has been SD1350 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0
disconnected QCPU
to disconnected SD1351 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 S (Error) New
module Remote
SD1381 0: External power
(For future
supply
expansion)
disconnected
1: External power
SD1381 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
supply is not
disconnected Indicates a blown fuse

App - 55 App - 55
APPENDICES
MELSEC-Q

Special Register List (Continue)

(12) I/O module verification
Set by Corresponding
Corresponding
Number Name Meaning Explanation (When ACPU
CPU
set) D9
SD1400 • When the I/O modules whose I/O module information differs from D9116
SD1401 that registered at power on are detected, the numbers of those D9117
SD1402 Bit pattern, in I/O modules are entered in bit pattern. D9118
SD1403 units of 16 points, (If the I/O numbers are set by parameter, the parameter-set D9119
SD1404 indicating the numbers are stored.) D9120
modules with • Also detects I/O module information
SD1405 D9121
I/O module b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SD1406 verification errors. 1 D9122
verification D9116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (X Y) S (Error) +Rem
SD1407 0: No I/O 0
D9123
error 1
SD1408 verification D9117 0 0 0 0 0 0 (X Y) 0 0 0 0 0 0 0 0 0
190 New
errors 1
SD1409
1: I/O verification D9123 0 (1FE0 XY
) 0 0 0 0 0 0 0 0 0 0 0 0 0 0
to New to New
error present Indicates an I/O module verification error
SD1430
• Not cleared even if the blown fuse is replaced with a new one.
SD1431 New
This flag is cleared by error resetting operation

(13) For redundant systems (Host system CPU information 1) for Q4AR only
SD1510 to SD1599 are only valid for redundant systems. They are all set to 0 for standalone
systems.
Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
D9
• Set the basic period (1 second units) use for the process
SD1500 Basic period control instruction using floating point data.
Basic period U New
SD1501 tome
Floating points data = SD1501 SD1500
Process control Process control
• Shows the detailed error contents for the error that occurred S (Error
SD1502 instruction detail instruction detail New
in the process control instruction occurrence)
error code error code
Process control Process control
instruction instruction • Shows the error process block that occurred in the process S (Error Q4AR
SD1503 New
generated error generated error control instruction. occurrence)
location location
Operation mode • Shows the power out time (S) during the automatic switch
Hot start switch
SD1512 during CPU from hot start to initial start in the operation mode when the S (Initial) New
power out time
module start up CPU module is started up.
Switch request Request origin • Stores the request origin at work No. when the SM1590 is S (Error
SD1590 New
network No. network No. turned on. occurrence)

1 Stores the host system CPU information.

App - 56 App - 56
APPENDICES
MELSEC-Q

(14) For redundant systems (Other system CPU information 1) for Q4AR only
SD1600 to SD1659 is only valid during the back up mode for redundant systems, and refresh
cannot be done when in the separate mode. When a standalone system SD1600 to SD1699
are all 0.
Special Register List
Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
SD 2
• Stores as BIN code the error No. of the error that occurred
Diagnosis error S (Each
SD1600 Diagnosis error during the other system CPU module diagnosis. New
No. END)
• Stores the latest error currently occurring.
SD1601 • SD1600 stores the updated date and time.
Diagnosis error
SD1602 Diagnosis error • Stores each of the BCD two digits. S (Each
occurrence New
occurrence time • Refer to SD1 to SD3 for the storage status. END)
SD1603 time
(SD1 SD1601, SD2 SD1602, SD3 SD1603)
Error Error • Stores the error comment information/individual information
S (Each
SD1604 information information classification code. New
END)
classification classification • Refer to SD4 for the storage status.
SD1605
SD1606
SD1607
• Stores the common information for the error code.
SD1608
• Refer to SD5 to SD15 for the storage status.
SD1609
Error common Error common (SD5 SD1605, SD6 SD1606, SD7 SD1607, S (Each
SD1610 New
information information SD8 SD1608, SD9 SD1609, SD10 SD1610, END)
SD1611
SD11 SD1611, SD12 SD1612, SD13 SD1613,
SD1612 SD14 SD1614, SD15 SD1615)
SD1613
SD1614
SD1615 Q4AR
SD1616
SD1617
SD1618
• Stores the individual information for the error code Refer to
SD1619
SD16 to SD26 for the storage status.
SD1620
Error individual Error individual (SD16 SD1616, SD17 SD1617, SD18 SD1618, S (Each
SD1621 New
information information SD19 SD1619, SD20 SD1620, SD21 SD1621, END)
SD1622
SD22 SD1622, SD23 SD1623, SD24 SD1624,
SD1623 SD25 SD1625, SD26 SD1626)
SD1624
SD1625
SD1626
CPU module • Stores the CPU module switch status. S (Each
SD1650 Switch status New
switch status • Refer to SD200 for the storage status. (SD1650 SD200) END)
• Stores the CPU module's LED status.
CPU module - • Shows 0 when turned off, 1 when turned on, and 2 when S (Each
SD1651 LED status New
LED status flicking. END)
• Refer to SD201 for the storage status. (SD1651 SD201)
CPU module
CPU module • Stores the CPU module operation status. Refer to SD203 for S (Each
SD1653 operation New
operation status the storage status. (SD1653 SD203) END)
status
1 Stores other system CPU module self-diagnosis information and system information.
2 Shows the special register (SD ) for the host system CPU module.

(15) For redundant systems (Trucking) for Q4AR only

SD1700 to SD1799 is valid only for redundant systems.
These are all 0 for standalone systems.
Corresponding
Set by Corresponding
Number Name Meaning Explanation ACPU
(When set) CPU
SD 2
Trucking error Trucking error Error
SD1700 • Make it the trucking error detection +1. New Q4AR
detection count detection count occurrence
2 Shows the special register (SD ) for the host system CPU.

App - 57 App - 57
APPENDICES
MELSEC-Q

APPENDIX 3 List of Interrupt Pointer Nos. and Interrupt Factors

I No. Interrupt Factors Priority I No. Interrupt factors Priority

Ranking Ranking
I0 1st point 237 I32 3 Errors that stop operation 1
I1 2nd point 238 I33 Empty ——
I2 3rd point 239 UNIT VERIFY ERR.
I3 4th point 240 I34 FUSE BREAK OFF 2
I4 5th point 241 SP. UNIT ERROR
I5 6th point 242 OPERATION ERROR
I6 QI60/A1SI61 7th point 243 SFCP OPE. ERROR
I35 3
I7 8th point 244 Error factor 4 SFCP ECE. ERROR
interrupt module EX. POWER OFF
I8 9th point 245
factor
I9 10th point 246 I36 ICM. OPE ERROR 4
I10 11th point 247 FILE OPE. ERROR
I11 12th point 248 I37 Empty ——
I12 13th point 249 I38 PRG. TIME OVER 5
I13 14th point 250 I39 CHK instruction execution 6
I14 15th point 251 Anunciator detection
I15 16th point 252
I40 to —— Empty ——
I16 1st point 224 I48
I17 2nd point 225
I18 3rd point 226 I49 Internal timer factor 0, 2 to 1.0mg 5 7
I19 4th point 227
I20 Sequence start 5th point 228
I21 6th point 229
generator module
I22 7th point 230
I23 factor 1 8th point 231
I24 9th point 232 Specifies which intelligent
I50 to Intelligent function
I25 10th point 234 function module is used 18 to 223
I255 module factor 6
I26 11th point 235 with parameters.
I27 12th point 236
I28 100ms 256
I29 Internal timer factor 40ms 255
I30 2 20ms 254
I31 10ms 253

REMARK
1 : 1st to 12th points are allocated in order, beginning from the sequence start
generator module installed closest to the High Performance model QCPU.
2 : The internal times shown are the default setting times.
These times can be designated in 0.5 ms units through a 0.5 to 1000 ms range
set at the "PLC system" tab screen in the “(PLC) Parameter" dialog box.
3 : When an error interruption with "I32 (error that stops operation)" occurs, the
High Performance model QCPU is not stopped until I32 processing is
completed.
4 : Execution of error interruptions is prohibited for the interrupt pointer Nos. I32 to
I39 when the power is turned on and during a High Performance model QCPU
reset. When using interrupt pointer Nos. I32 to I39, set the interruption
permitted status by using the IMASK instruction.
5 : Set the time-out period of the internal timer by choosing "PLC system" -
"System interrupt setting" - "High speed interrupt setting" on the PLC parameter
screen.
Set it in the setting range 0.2 to 1.0ms in 0.1ms increments.
6 : To use the intelligent function module interrupt, the intelligent function module
setting (interrupt points setting) is required at the "PLC system" tab screen in
the “(PLC) Parameter" dialog box.
(For the interrupts from the intelligent function module, see Section 8.2.1.)

POINT
7: When you have set I49 in the PLC parameters, do not execute other interrupt
programs (I0 to I48, I50 to I255) and fixed-cycle programs. If any fixed-cycle
program or like is run, the interrupt program using I49 cannot be executed at
the preset interrupt cycle intervals.

App - 58 App - 58
APPENDICES
MELSEC-Q

APPENDIX 4 Enhancement of the High Performance Model QCPU Functions

The High Performance model QCPU has been updated to add functions and change
the specifications.
The functions and specifications that can be used with the High Performance model
QCPU change depending on the function version and serial No.

APPENDIX 4.1 Specification Comparison

Serial No. of CPU Module Function Version A Function Version B

02091 02092 03051 04012
Specifications ——
or earlier or later or later or later
Q02CPU 64kbyte
Q02HCPU 64kbyte 128kbyte
Standard RAM capacity Q06HCPU 64kbyte 128kbyte
Q12HCPU 64kbyte 256kbyte
Q25HCPU 64kbyte 256kbyte
CPU shared memory
Extended life battery SRAM card
Compatibility with 2Mbyte SRAM card
: Available, : N/A

APPENDIX 4.2 Function comparison

Serial No. of CPU Module Function Version A Function Version B

02091 02092 03051 04012 04122 05032
Added Function ——
or earlier or later or later or later or later or later
Automatic write to standard ROM
Enforced ON/OFF for external I/O
Remote password setting
Compatibility with MELSECNET/H remote
I/O network
Interrupt module (QI60) compatibility
Compatibility with the multiple CPU system
Installation of PC CPU module into the
multiple CPU system
High speed interrupt
Compatibility with index modification for
module designation of dedicated instruction
Selection of refresh item for COM instruction
SFC program online batch change
File memory capacity change
CC-Link remote network additional mode
Incomplete derivative PID operation function
Floating-point comparison instruction speedup
: Available, : N/A

For function details, refer to the High Performance model QCPU (Q mode) User's
Manual (Function Explanation, Program Fundamentals).
App - 59 App - 59
APPENDICES
MELSEC-Q

APPENDIX 4.3 Added functions and the corresponding GX Developer versions

GX Developer
SW4D5C-GPPW-E
SW5D5C-GPPW-E Version Version
Version 6 Version 7 Version 8
Added Function 7.10L 8.03D
Automatic write to standard ROM
External I/O can be turned ON/OFF
forcibly
Remote password setting
Compatibility with MELSECNET/H
remote I/O network
Interrupt module (QI60)
compatibility
Compatibility with the multiple CPU
system
Installation of PC CPU module into
the multiple CPU system
High speed interrupt
Compatibility with index
modification for module designation — — — — — —
of dedicated instruction
Selection of refresh item for COM
— — — — — —
instruction
SFC program online batch change
File memory capacity change
CC-Link remote network additional
mode
Incomplete derivative PID
operation function
Floating-point comparison
— — — — — —
instruction speedup
: Available, : N/A, — : Function not related to GX Developer

App - 60 App - 60
APPENDICES
MELSEC-Q

APPENDIX 5 Transportation Precautions

When transporting lithium batteries, make sure to treat them based on the transport
regulations.

APPENDIX 5.1 Controlled models

The batteries for the High Performance model QCPU (including memory cards) are
classified as follows:

Classification for
Product name Model Product supply status
transportation
Q series battery Q7BAT Lithium battery
Lithium battery with Dangerous goods
Q series battery Q7BAT-SET
holder
Q series battery Q6BAT Lithium battery
Q series memory card battery Q2MEM-BAT Lithium coin battery
Non-dangerous goods
Q2MEM-1MBS Packed with lithium coin
Q series memory card
Q2MEM-2MBS battery (Q2MEM-BAT)

APPENDIX 5.2 Transport guidelines

Comply with IATA Dangerous Goods Regulations, IMDG code and the local transport
regulations when transporting products after unpacking or repacking, while Mitsubishi
ships products with packages to comply with the transport regulations.
Also, contact the transporters.

App - 61 App - 61
 INDEX

Ind
[A] Duty ..............................................................10-25
Accuracy of initial scan time...................... 4-16 DX (Direct access input)..............................10- 6
Accuracy of scan time ............................... 4-18 DY (Direct access output)............................10- 9
Annunciator (F) ........................................ 10-12
ASCII code................................................. 4-51 [E]
ATA card .................................................... 6-11 E (Real numbers).........................................10-62
Auto mode ................................................. 5- 3
Edge relay(V) ...............................................10-16
Automatic write to standard ROM............. 6-14
END processing .............................................4-34
[B] Enforced ON/OFF..........................................7-31
Enforced ON/OFF for external I/O ................1- 4
B (Link relay)............................................ 10-17
Execute type ..................................................4-10
Base mode................................................. 5- 3
BCD (Binary coded decimal)..................... 4-47 Execution time measurement........................7-39
Execution time of the low speed execution type
BIN (Binary code) ...................................... 4-45
program..........................................................4-19
BL (SFC block device)............................. 10-58
Boot Run .................................................... 6-17 Extension.............................................. 6- 2, 6- 4

[C] [F]
C (Counter).................................................. 10-24 F (Annunciator) ............................................10-12
Catalog PLC memory.................................... 6-18 Failure history.................................................7-64
Character string............................................. 4-51 FD (Function register)..................................10-31
Clock function ................................................ 7- 9 File register...................................................10-43
Precision .................................................... 7-11 Access method.........................................10-44
Common pointer.......................................... 10-54 Designation method .................................10-49
Concept of I/O assignment ........................... 5- 8 Registering ...............................................10-45
Concept of I/O assignment using File size ..........................................................6-18
GX Developer................................................ 5-12 Fixed scan execution type program ..............4-31
Constant scan................................................ 7- 2 Flash card.......................................................6-12
Constants..................................................... 10-61 Floating decimal point data............................4-48
Counter (C).................................................. 10-24 Function device (FX, FY, FD)......................10-31
Count processing..................................... 10-24 Function version............................... 13- 5, 14- 4
Maximum counting speed ....................... 10-25 FX (Function input) ......................................10-31
FY (Function output) ....................................10-31
[D]
D (Data register).......................................... 10-28 [G]
Data register (D).......................................... 10-28 Global device ...............................................10-63
Data stored on the memory card .................. 6- 4 GX Configurator ................................. 8- 2, 14-12
Decimal constants (K) ................................. 10-61 GX Developer ............................................... A-18
Device initial value...................................... 10- 69
Device list .................................................... 10- 1 [H]
Direct access input ...................................... 10- 6 H (Hexadecimal constants) .........................10-61
Direct access output.................................... 10- 9 HEX (Hexadecimal) .......................................4-46
Direct mode ................................................... 4-41 Hexadecimal constants (H) .........................10-61
Drive Number. ............................................... 6- 5 high speed interrupt function ........................7-81
High speed retentive timer (ST) ..................10-21

Index - 1 Index - 1
 High speed timer (T) .................................. 10-20 [M]
M (Internal relay)..........................................10-10
[I] Macro instruction argument device (VD).....10-60 Ind
I (Interrupt pointer)....................................... 10-56 Main routine program.....................................4- 3
I/O No. designation device (Un).................. 10-59 Memory card ..................................................6-11
Index register (Z) ......................................... 10-39 Monitor condition setting................................7-25
Initial execution monitor time ........................ 4-16 Monitoring the local devices ..........................7-30
Initial execution type program....................... 4-15
Initial scan time.............................................. 4-16 [N]
Input response time....................................... 7-21 N (Nesting) ...................................................10-52
Intelligent function module device (U \G ). 10-38
Internal relay (M) ......................................... 10-10 [O]
Internal system device ................................ 10-31 Output (Y).....................................................10- 8
Internal user device..................................... 10- 3
Interrupt module ............................................ 5-11 [P]
Interrupt pointer (I)....................................... 10-56 P (Pointer) ....................................................10-53
Interrupt program........................................... 4- 6 Password........................................................7-65
PLOW instruction ...........................................4-14
[J] POFF instruction ............................................4-14
J (Network designation device)................... 10-58 Pointer (P) ....................................................10-53
J \B (Link relay) .................................. 10-35 Precautions for the use of device initial values ..10-71
J \SB (Link special relay) ................... 10-35 Precautions when using timers ...................10-23
J \SW (Link special register) .............. 10-35 Priority of LED ................................................7-76
J \W (Link register) ............................. 10-35 Procedure for using device initial values.....10-70
J \X (Link input) .................................. 10-35 Processing at annunciator OFF...................10-14
J \Y (Link output) ................................ 10-35 Processing at annunciator ON ....................10-12
Program construction.....................................1- 6
[K] Program execute type....................................4-10
K (Decimal constants) ................................. 10-61 Program memory ...........................................6- 6
Program monitor list.......................................7-39
[L] PSCAN instruction .........................................4-14
L (Latch relay).............................................. 10-11 PSTOP instruction .........................................4-14
Latch function ................................................. 7- 5 Purpose of I/O assignment............................5-11
Latch relay (L).............................................. 10-11 Purpose of I/O assignment using
LED display ................................................... 7-74 GX Developer ................................................5-11
Link direct device......................................... 10-35 [Q]
Link register (W) .......................................... 10-29 QCPU ............................................................ A-18
Link relay (B) ............................................... 10-17 QI60...................................................... 2- 4, 7-23
List of Interrupt factors ................................ 10-57 QnCPU .......................................................... A-18
App-55 QnHCPU ....................................................... A-18
Local device................................................. 10-63
Low speed END processing ......................... 4-23 [R]
Low speed execution monitor time............... 4-24 R (File register) ............................................10-43
Low speed execution type program ............. 4-19 Reading from the time data ...........................7- 9
Low speed retentive timer (ST)................... 10-21 Real numbers (E)...........................................4-48
Low speed scan timer ................................... 4-23 10-62
Low speed timer (T) .................................... 10-19 Refresh input................................................10- 6

Index - 2 Index - 2
 Refresh mode................................................ 4-38 ST (Retentive timer: OUT ST ) ................10-21
Refresh output............................................. 10- 9 Stand-by type program ..................................4-25
Remote latch clear ........................................ 7-19 Standard RAM ...............................................6- 9
Remote operation.......................................... 7-12 Standard RAM memory capacity ..................6- 9
Remote PAUSE............................................. 7-15 Standard ROM ...............................................6- 8
Remote password ................................7- 1, 7-67 Step relay (S) ...............................................10-18
Remote RESET............................................. 7-17 Sub-routine program......................................4- 4
Remote RUN/STOP...................................... 7-12 SW (Link special register)............................10-30
Remote station I/O number........................... 5-10 Switch setting of intelligent function module .7-21
Retentive timer (OUT ST )....................... 10-21 System protect ...............................................7-65
RUN status .................................................... 4-35
[T]
[S] T (Timer).......................................................10-19
S (Step relay)............................................... 10-18 Timer (T).......................................................10-19
SB (Link special relay) ................................ 10-18 Accuracy...................................................10-22
Scan execution type program ....................... 4-17 Processing................................................10-22
Scan time....................................................... 4-18 TR (SFC transition device) ..........................10-58
SD (Special register) ................................... 10-34
SD415 (2n-ms clock setting)......................... 8- 9 [U]
SD520, SD521 (Scan time: present value) .. 4-18 U (I/O No. designation device) ....................10-59
SD522, SD523 (Initial scan time) ................. 4-16 U \G (Intelligent function module device)...10-38
SD524, SD525 (Scan time: Maximum value)...... 4-18 User memory..................................................6- 3
SD526, SD527 (Scan time: Minimum value)....... 4-18
SD528, SD529 (Low speed scan time: Present value) [V]
................................................................................... 4-24 V (Edge relay) ..............................................10-16
SD530, SD531 (Low speed scan time: Initial value) VD (Macro instruction argument device).....10-60
............................................................................... 4-24
SD532, SD533 (Low speed scan time: Minimum value) [W]
................................................................................... 4-24 W (Link register)...........................................10-29
SD534, SD535 (Low speed scan time: Maximum Watch dog timer.............................................7-57
value) .............................................................. 4-24 WDT (Watch dog timer).................................7-57
Self-diagnosis function .................................. 7-59 Write during RUN........................7-35, 7-37, 7-55
Sequence program........................................ 4- 1 Writing to the time data .................................7- 9
Serial No. ....................................................... 1- 1
Setting range in the internal user device .... 10- 3 [X]
Setting the number of stages........................ 5- 2 X (Input)........................................................10- 5
SFC block device (BL) ................................ 10-58
SFC transition device (TR).......................... 10-58 [Y]
Single precision floating decimal point data ..... 4-48 Y (Output).....................................................10- 8
Size (File capacity) ........................................ 6- 2
SM (Special relay) ....................................... 10-33 [Z]
SM415 (2n-ms clock) .................................... 8- 9 Z (Index register)..........................................10-39
Link special register (SW) ........................... 10-30 ZR (Serial number access format of file register)
Link special relay (SB) ................................ 10-18 ......................................................................10-49
Special register (SD) ................................... 10-34
Special relay (SM) ....................................... 10-33
SRAM card .................................................... 6-11

Index - 3 Index - 3
WARRANTY
Please confirm the following product warranty details before starting use.

1. Gratis Warranty Term and Gratis Warranty Range

If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product
within the gratis warranty term, the product shall be repaired at no cost via the dealer or Mitsubishi Service Company.
Note that if repairs are required at a site overseas, on a detached island or remote place, expenses to dispatch an
engineer shall be charged for.
[Gratis Warranty Term]
The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated
place.
Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months, and
the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of repair
parts shall not exceed the gratis warranty term before repairs.
[Gratis Warranty Range]
(1) The range shall be limited to normal use within the usage status, usage methods and usage environment, etc.,
which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution labels
on the product.
(2) Even within the gratis warranty term, repairs shall be charged for in the following cases.
1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure caused
by the user's hardware or software design.
2. Failure caused by unapproved modifications, etc., to the product by the user.
3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if functions
or structures, judged as necessary in the legal safety measures the user's device is subject to or as necessary
by industry standards, had been provided.
4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the
instruction manual had been correctly serviced or replaced.
5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by force
majeure such as earthquakes, lightning, wind and water damage.
6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi.
7. Any other failure found not to be the responsibility of Mitsubishi or the user.

2. Onerous repair term after discontinuation of production

(1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is discontinued.
Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc.
(2) Product supply (including repair parts) is not possible after production is discontinued.

3. Overseas service
Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at each FA
Center may differ.

4. Exclusion of chance loss and secondary loss from warranty liability

Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation to damages caused by any cause
found not to be the responsibility of Mitsubishi, chance losses, lost profits incurred to the user by Failures of Mitsubishi
products, damages and secondary damages caused from special reasons regardless of Mitsubishi's expectations,
compensation for accidents, and compensation for damages to products other than Mitsubishi products and other duties.

5. Changes in product specifications

The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice.

6. Product application
(1) In using the Mitsubishi MELSEC programmable logic controller, the usage conditions shall be that the application will
not lead to a major accident even if any problem or fault should occur in the programmable logic controller device, and
that backup and fail-safe functions are systematically provided outside of the device for any problem or fault.
(2) The Mitsubishi general-purpose programmable logic controller has been designed and manufactured for applications
in general industries, etc. Thus, applications in which the public could be affected such as in nuclear power plants and
other power plants operated by respective power companies, and applications in which a special quality assurance
system is required, such as for Railway companies or National Defense purposes shall be excluded from the
programmable logic controller applications.
Note that even with these applications, if the user approves that the application is to be limited and a special quality is
not required, application shall be possible.
When considering use in aircraft, medical applications, railways, incineration and fuel devices, manned transport
devices, equipment for recreation and amusement, and safety devices, in which human life or assets could be greatly
affected and for which a particularly high reliability is required in terms of safety and control system, please consult
with Mitsubishi and discuss the required specifications.
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Other company and product names herein are either trademarks or registered trademarks of their respective owners.
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Fax: +1 847 / 478 22 83 GR-18542 Piraeus Fax: +90 (0) 212 / 320 1649 ul. Bajkalskaja 239, Office 2 - 23
Phone: +302 (0) 10 / 42 10 050 e mail: [email protected] RU-664075 Irkutsk
Fax: +302 (0) 10 / 42 12 033 Phone: +7 3952 / 24 38 16
e mail: [email protected] CSC Automation Ltd. UKRAINE Fax: +7 3952 / 23 02 98
MIDDLE EAST REPRESENTATIVE 15, M. Raskova St., Fl. 10, Office 1010 e mail: [email protected]
Meltrade Automatika Kft. HUNGARY UA-02002 Kiev
TEXEL Electronics Ltd. ISRAEL 55, Harmat St. Phone: +380 (0) 44 / 238-83-16 STC Drive Technique RUSSIA
Box 6272 HU-1105 Budapest Fax: +380 (0) 44 / 238-83-17 Poslannikov Per. 9, str.1
IL-42160 Netanya Phone: +36 (0)1 / 2605 602 e mail: [email protected] RU-107005 Moscow
Phone: +972 (0) 9 / 863 08 91 Fax: +36 (0)1 / 2605 602 Phone: +7 095 / 790-72-10
Fax: +972 (0) 9 / 885 24 30 e mail: [email protected] Fax: +7 095 / 790-72-12
e mail: [email protected] e mail: [email protected]
SIA POWEL LATVIA
Lienes iela 28
LV-1009 Riga
Phone: +371 784 / 22 80 AFRICAN REPRESENTATIVE
Fax: +371 784 / 22 81
e mail: [email protected] CBI Ltd. SOUTH AFRICA
Private Bag 2016
ZA-1600 Isando
Phone: +27 (0) 11/ 928 2000
Fax: +27 (0) 11/ 392 2354
e mail: [email protected]

MITSUBISHI ELECTRIC INDUSTRIAL AUTOMATION

Gothaer Strasse 8 Phone: +49 2102 486-0 Fax: +49 2102 486-7170 www.mitsubishi-automation.de
D-40880 Ratingen Hotline: +49 1805 000-765 [email protected] www.mitsubishi-automation.com