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Practice 7 CMOS Capacitance 2011 12 A

The document discusses CMOS inverter capacitances. It defines the various capacitances in a MOSFET transistor including gate, channel, and diffusion capacitances. It then explains that the output capacitance of a CMOS inverter is the sum of the driver output capacitance, wire capacitance, and input capacitance of the next stage. The input capacitance of the next stage includes the gate, overlap, and diffusion capacitances of both the PMOS and NMOS transistors. An example calculation is then shown to find the output capacitance and switching power of a chain of inverters.

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48 views4 pages

Practice 7 CMOS Capacitance 2011 12 A

The document discusses CMOS inverter capacitances. It defines the various capacitances in a MOSFET transistor including gate, channel, and diffusion capacitances. It then explains that the output capacitance of a CMOS inverter is the sum of the driver output capacitance, wire capacitance, and input capacitance of the next stage. The input capacitance of the next stage includes the gate, overlap, and diffusion capacitances of both the PMOS and NMOS transistors. An example calculation is then shown to find the output capacitance and switching power of a chain of inverters.

Uploaded by

rajesh
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Practice 7: CMOS Capacitance

MOSFET Capacitances
General capacitances in a MOSFET Transistor

Channel Capacitance as a function of Operating Mode:

To Substrate To Diffusions
Gate Capacitance CGB=WLCox in Cutoff CGS=CGD=0.5WLCox in Linear
CGD=0 CGS=0.66WLCox in Saturation
Coverlap=CGDOW+ CGSOW in all modes
Diffusion Capacitance CSB and CDB are given
CMOS Inverter Capacitances

All capacitances are lumped together into one single output capacitance:
Cout  Cout _ driver  Cwire  Cin _ next _ stage
Output capacitance are any capacitances connected to the output node, i.e. the DRAIN of the
pmos and nmos. This includes the Diffusion-to-bulk capacitance of the drain CDB, and the Gate-to
Drain capacitance CGD. The latter is non-linear and changes during the transition, but since the
transition is mostly in saturation (or in cutoff), this can be considered only Overlap capacitance.
Using the Miller effect, we can lump it to the Drain-to-Ground capacitance:
Cout _ driver  CDBn  CDBp  2CGDoverlapW
The input capacitance of an inverter is comprised of the capacitances connected to the gate.
This includes the overlap capacitance the source, the miller overlap capacitance of the drain,
and as the non-linear gate capacitance. The Miller effect can be ignored, as the second stage
doesn’t switch until VM, and we can estimate the gate capacitance to be approximately CoxWL:
Cin_next_stage  CoxWn Ln  CGDOnWn  CGSOnWn  CoxW p L p  CGDOpW p  CGSOpW p
 CoxWn Ln  CoxW p L p
Exercise 1: Inverter Capacitance and Power Calculation
a. Given the following parameters, find the output capacitance of a CMOS inverter driving
4 identical inverters:
CGDOn  CGSOn  0.31fF μm; Cox  6 fF μm2 ; CDBp  1.5fF; CDBn  1.15fF
Wn Ln  0.375 0.25 ; Wp Lp  1.125 0.25 ; Cwire  0.5 fF
b. Find the total power consumption of the above circuit, operating at a frequency of 1GHz
with a 2.5V power supply. (Assume an ideal clock is connected to the input gate).

Solution:
a.
Cout _ driver  CDBn  CDBp  2CGDOnWn  2CGDOpWp 
 1.5 fF  1.15 fF  2  0.31 0.375 fF  2  0.311.125 fF  3.58 fF
Cin_next_stage  N   CoxWn Ln  CGDOnWn  CGSOnWn  CoxWp Lp  CGDOpWp  CGSOpWp  
 4  6  0.375  0.25  2  0.31 0.375  6 1.125  0.25  2  0.31 1.125 fF 
 4  0.795  2.385  fF  12.72 fF
Cout  Cout _ driver  Cwire  Cin _ next _ stage  3.58  0.5  12.72  16.8 fF
b. Static Power is zero (CMOS)
Short Circuit power is zero for first stage (Step input)
Output capacitance of the second stage is:
Cout _ driver  4   CDBn  CDBp  2CGDOnWn  2CGDOpWp  
 4  1.5 fF  1.15 fF  2  0.31 0.375 fF  2  0.311.125 fF   14.32 fF

Dynamic power of the second inv is:


Pdyn  f Cout1  Cout 2 VDD
2
 1109  16.8  14.32 1015  2.52  194.5W
(note: to be exact, we should add miller capacitance of an additional nmos and pmos
overlap capacitance, due to the full swing over the energy calculation).
‫שאלה ממבחן‬
‫מועד ב' תש"ע‪:‬‬

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