EFM32 Leopard Gecko Family

EFM32LG Data Sheet

The EFM32 Leopard Gecko MCUs are the world’s most energy-
KEY FEATURES
friendly microcontrollers.
The EFM32LG offers unmatched performance and ultra-low power consumption in both • ARM Cortex-M3 at 48 MHz
active and sleep modes. EFM32LG devices consume as little as 0.65 μA in Stop mode • Ultra-low power operation
and 211 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip • 0.65 μA current in Stop (EM3), with
and analog integration, and the performance of the industry standard 32-bit ARM Cortex- brown-out detection and RAM retention
M3 processor, making it perfect for battery-powered systems and systems with high-per- • 63 μA/MHz in EM1
formance, low-energy requirements. • 211 μA/MHz in Run mode (EM0)
• Fast wake-up time of 2 µs
EFM32LG applications include the following:
• Hardware cryptography (AES)
• Energy, gas, water and smart metering • Alarm and security systems • Up to 256 kB of flash and 32 kB of RAM
• Health and fitness applications • Industrial and home automation
• Smart accessories

Core / Memory Clock Management Energy Management Security

High Frequency High Frequency Voltage Voltage
TM
ARM Cortex Memory Crystal Oscillator RC Oscillator Regulator Comparator Hardware AES
M3 processor Protection Unit
Auxiliary High Low Freq. Brown-out Power-on
Flash Program Freq. RC Osc. RC Oscillator Detector Reset
Debug w/ ETM
Memory
Low Frequency Ultra Low Freq. Back-up Power
RAM Memory DMA Controller Crystal Oscillator RC Oscillator Domain

32-bit bus
Peripheral Reflex System

Serial Interfaces I/O Ports Timers and Triggers Analog Interfaces

External Bus Timer/Counter LESENSE
USART UART TFT Driver ADC LCD Controller
Interface
Low Energy Timer Real Time Counter
Low Energy External General Operational
I2C DAC
UARTTM Interrupts Purpose I/O Amplifier
Pulse Counter Watchdog Timer
Analog
USB Pin Reset Pin Wakeup Back-up RTC Comparator

Lowest power mode with peripheral operational:

EM0 - Active EM1 - Sleep EM2 – Deep Sleep EM3 - Stop EM4 - Shutoff

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 EFM32LG Data Sheet
Feature List

1. Feature List

• ARM Cortex-M3 CPU platform

• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
• SysTick System Timer
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention
• 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and
CPU retention
• 63 µA/MHz @ 3 V Sleep Mode
• 211 µA/MHz @ 3 V Run Mode, with code executed from flash
• 256/128/64 kB flash
• 32 kB RAM
• Up to 93 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×36 segments
• Voltage boost, adjustable contrast, and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
• External Bus Interface for up to 4x256 MB of external memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• Up to 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host & OTG support
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5 to 3.3 V regulator

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 EFM32LG Data Sheet
Feature List

• Ultra-low power precision analog peripherals

• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single-ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single-ended channels/1 differential channel
• Up to 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Packages:
• BGA112
• BGA120
• CSP81
• LQFP100
• TQFP64
• QFN64
• Full wafer

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 EFM32LG Data Sheet
Ordering Information

2. Ordering Information

The following table shows the available EFM32LG devices.

Table 2.1. Ordering Information

Max Speed Supply Temperature

Ordering Code Flash (kB) RAM (kB) (MHz) Voltage (V) (ºC) Package

EFM32LG230F64G-F-QFN64 64 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG230F128G-F-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG230F256G-F-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG232F64G-F-QFP64 64 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG232F128G-F-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG232F256G-F-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG280F64G-F-QFP1001 64 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG280F128G-F-QFP100 128 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG280F256G-F-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG290F64G-F-BGA1121 64 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG290F128G-F-BGA1121 128 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG290F256G-F-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG295F64G-F-BGA1201 64 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG295F128G-F-BGA1201 128 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG295F256G-F-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG330F64G-F-QFN641 64 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG330F128G-F-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG330F256G-F-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG332F64G-F-QFP641 64 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG332F128G-F-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG332F256G-F-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG360F64G-F-CSP812 64 32 48 1.98 - 3.8 -40 - 85 CSP81

EFM32LG360F128G-F-CSP812 128 32 48 1.98 - 3.8 -40 - 85 CSP81

EFM32LG360F256G-F-CSP81 256 32 48 1.98 - 3.8 -40 - 85 CSP81

EFM32LG380F64G-F-QFP1001 64 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG380F128G-F-QFP1001 128 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG380F256G-F-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG390F64G-F-BGA1121 64 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG390F128G-F-BGA1121 128 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG390F256G-F-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG395F64G-F-BGA1201 64 32 48 1.98 - 3.8 -40 - 85 BGA120

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 EFM32LG Data Sheet
Ordering Information

Max Speed Supply Temperature

Ordering Code Flash (kB) RAM (kB) (MHz) Voltage (V) (ºC) Package

EFM32LG395F128G-F-BGA1201 128 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG395F256G-F-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG840F64G-F-QFN64 64 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG840F128G-F-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG840F256G-F-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG842F64G-F-QFP641 64 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG842F128G-F-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG842F256G-F-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG880F64G-F-QFP100 64 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG880F128G-F-QFP100 128 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG880F256G-F-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG890F64G-F-BGA1121 64 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG890F128G-F-BGA1121 128 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG890F256G-F-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG895F64G-F-BGA1201 64 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG895F128G-F-BGA1201 128 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG895F256G-F-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG900F256G-F-D1I 1 256 32 48 1.98 - 3.8 -40 - 85 Wafer

EFM32LG940F64G-F-QFN641 64 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG940F128G-F-QFN64 128 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG940F256G-F-QFN64 256 32 48 1.98 - 3.8 -40 - 85 QFN64

EFM32LG942F64G-F-QFP641 64 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG942F128G-F-QFP64 128 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG942F256G-F-QFP64 256 32 48 1.98 - 3.8 -40 - 85 TQFP64

EFM32LG980F64G-F-QFP1001 64 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG980F128G-F-QFP1001 128 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG980F256G-F-QFP100 256 32 48 1.98 - 3.8 -40 - 85 LQFP100

EFM32LG990F64G-F-BGA1121 64 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG990F128G-F-BGA1121 128 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG990F256G-F-BGA112 256 32 48 1.98 - 3.8 -40 - 85 BGA112

EFM32LG995F64G-F-BGA1201 64 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG995F128G-F-BGA1201 128 32 48 1.98 - 3.8 -40 - 85 BGA120

EFM32LG995F256G-F-BGA120 256 32 48 1.98 - 3.8 -40 - 85 BGA120

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 EFM32LG Data Sheet
Ordering Information

Max Speed Supply Temperature

Ordering Code Flash (kB) RAM (kB) (MHz) Voltage (V) (ºC) Package

Note:
1. Not recommended for new designs.
2. This OPN is obsolete.

EFM32 LG 995 F 256 G – F – BGA 120 R

Tape and Reel (Optional)

Pin Count
Package
Revision
Temperature Grade – G (-40 to +85 °C)
Memory Size in kB
Memory Type (Flash)
Feature Set Code
Leopard Gecko
Energy Friendly Microcontroller 32-bit

Figure 2.1. Ordering Code Decoder

Adding the suffix 'R' to the part number (e.g. EFM32LGF256G-F-BGA120R) denotes tape and reel.

Visit www.silabs.com for information on global distributors and representatives.

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Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. System Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1.2 Debug Interface (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . .13
3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . . . . . . . . . .13
3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . .13
3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .14
3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .14
3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .14
3.1.10 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . .14
3.1.11 TFT Direct Drive . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.1.12 Universal Serial Bus Controller (USB) . . . . . . . . . . . . . . . . . . . .14
3.1.13 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . .14
3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . .14
3.1.15 Pre-Programmed USB/UART Bootloader . . . . . . . . . . . . . . . . . . .15
3.1.16 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . .15
3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . .15
3.1.18 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1.19 Real Time Counter (RTC) . . . . . . . . . . . . . . . . . . . . . . . .15
3.1.20 Backup Real Time Counter (BURTC) . . . . . . . . . . . . . . . . . . . .15
3.1.21 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .15
3.1.22 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1.23 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .15
3.1.24 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . .15
3.1.25 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .16
3.1.26 Digital to Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . .16
3.1.27 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . .16
3.1.28 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . .16
3.1.29 Backup Power Domain . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1.30 Advanced Encryption Standard Accelerator (AES) . . . . . . . . . . . . . . . .16
3.1.31 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . .16
3.1.32 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . . .16
3.2 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2.1 EFM32LG230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2.2 EFM32LG232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.3 EFM32LG280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2.4 EFM32LG290 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2.5 EFM32LG295 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.2.6 EFM32LG330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.2.7 EFM32LG332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

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 3.2.8 EFM32LG360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2.9 EFM32LG380 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2.10 EFM32LG390 . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.2.11 EFM32LG395 . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2.12 EFM32LG840 . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.2.13 EFM32LG842 . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.2.14 EFM32LG880 . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.2.15 EFM32LG890 . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.2.16 EFM32LG895 . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.2.17 EFM32LG900 . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.2.18 EFM32LG940 . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.2.19 EFM32LG942 . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.2.20 EFM32LG980 . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.2.21 EFM32LG990 . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
3.2.22 EFM32LG995 . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.1.1 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . .63
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .63
4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .63
4.4 Backup Supply Domain . . . . . . . . . . . . . . . . . . . . . . . . . . .64
4.5 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.5.1 EM1 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .67
4.5.2 EM2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .70
4.5.3 EM3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .71
4.5.4 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .71
4.6 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .72
4.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.8 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.9 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . . .74
4.10 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
4.10.1 LFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
4.10.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
4.10.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
4.10.4 HFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
4.10.5 AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.10.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.11 Analog Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . .91
4.11.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . .97
4.12 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . 102
4.13 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . 104

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 4.14 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . 111
4.15 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . . . 119
4.16 EBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
. 20
4.17 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.18 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 26
4.19 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
.
4.20 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . .130

5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.1 EFM32LG230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 31
5.1.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 135
.
5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .140
5.2 EFM32LG232 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . 141
.
5.2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 41
5.2.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 145
.
5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.2.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .150
5.3 EFM32LG280 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .151
5.3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 51
5.3.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 157
.
5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.3.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .164
5.4 EFM32LG290 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . 165
.
5.4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 65
5.4.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 171
.
5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.4.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .178
5.5 EFM32LG295 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . 179
.
5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 79
5.5.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 185
.
5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.5.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .192
5.6 EFM32LG330 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.6.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . 93
5.6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 197
.
5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 202
5.6.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .202
5.7 EFM32LG332 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . 203
.
5.7.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 03
5.7.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 207
.
5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 211
5.7.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .212
5.8 EFM32LG360 (CSP81) . . . . . . . . . . . . . . . . . . . . . . . . . . 213

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 5.8.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 13
5.8.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 218
.
5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.8.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .223
5.9 EFM32LG380 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .224
5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 24
5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 229
.
5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 236
5.9.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .236
5.10 EFM32LG390 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .237
5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .243
5.10.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2
. 50
5.10.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 250
5.11 EFM32LG395 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .251
5.11.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.11.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .257
5.11.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2
. 64
5.11.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 265
5.12 EFM32LG840 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . 266
.
5.12.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.12.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .270
5.12.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2
. 76
5.12.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 276
5.13 EFM32LG842 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .277
5.13.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.13.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .281
5.13.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 2
. 87
5.13.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 287
5.14 EFM32LG880 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 288
5.14.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
5.14.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .294
5.14.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3
. 03
5.14.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 304
5.15 EFM32LG890 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .305
5.15.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.15.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .311
5.15.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3
. 20
5.15.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 321
5.16 EFM32LG895 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .322
5.16.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
5.16.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .328
5.16.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3
. 37
5.16.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 337
5.17 EFM32LG900 (Wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . 338
5.17.1 Padout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

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 5.17.2 Alternate Functionality Padout . . . . . . . . . . . . . . . . . . . . . . 344
5.17.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3 . 53
5.17.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 354
5.18 EFM32LG940 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . 355
.
5.18.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
5.18.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .359
5.18.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3
. 65
5.18.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 365
5.19 EFM32LG942 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .366
5.19.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
5.19.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .370
5.19.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3
. 75
5.19.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 376
5.20 EFM32LG980 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . 377
5.20.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
5.20.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .383
5.20.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 3
. 92
5.20.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 392
5.21 EFM32LG990 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .393
5.21.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
5.21.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .399
5.21.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 4
. 08
5.21.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 408
5.22 EFM32LG995 (BGA120) . . . . . . . . . . . . . . . . . . . . . . . . .409
5.22.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
5.22.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .415
5.22.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . 4
. 24
5.22.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 425

6. BGA112 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .426

6.1 BGA112 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 426
6.2 BGA112 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
6.3 BGA112 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 429

7. BGA120 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .430

7.1 BGA120 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 430
7.2 BGA120 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
7.3 BGA120 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 433

8. CSP81 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . 434

8.1 CSP81 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .434
8.2 CSP81 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . .436
8.3 CSP81 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . 4
. 39
8.4 CSP81 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . 4. 39

9. LQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 440

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 9.1 LQFP100 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .440
9.2 LQFP100 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . 4
. 42
9.3 LQFP100 Package Marking . . . . . . . . . . . . . . . . . . . . . . . 444
.

10. QFN64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .445

10.1 QFN64 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . 445
10.2 QFN64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
10.3 QFN64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . 449

11. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 450

11.1 TQFP64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .450
11.2 TQFP64 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . .452
11.3 TQFP64 Package Marking . . . . . . . . . . . . . . . . . . . . . . . 4. 54

12. Wafer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .455

12.1 Bonding Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 455
.
12.2 Wafer Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4
. 55
12.2.1 Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . .455
12.3 Wafer Storage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 456
12.4 Failure Analysis (FA) Guidelines . . . . . . . . . . . . . . . . . . . . . 456
.

13. Chip Revision, Solder Information, Errata . . . . . . . . . . . . . . . . . . .457

13.1 Chip Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
13.2 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . .457
13.3 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
.

14. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

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 EFM32LG Data Sheet
System Summary

3. System Summary

3.1 System Introduction

The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the
EFM32LG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of
the configuration for the EFM32LG devices. For a complete feature set and in-depth information on the modules, refer to the EFM32LG
Reference Manual.

A block diagram of the EFM32LG is shown in the following figure.

Core / Memory Clock Management Energy Management Security
High Frequency High Frequency Voltage Voltage
ARM CortexTM Memory Crystal Oscillator RC Oscillator Regulator Comparator Hardware AES
M3 processor Protection Unit
Auxiliary High Low Freq. Brown-out Power-on
Flash Program Freq. RC Osc. RC Oscillator Detector Reset
Debug w/ ETM
Memory
Low Frequency Ultra Low Freq. Back-up Power
RAM Memory DMA Controller Crystal Oscillator RC Oscillator Domain

32-bit bus
Peripheral Reflex System

Serial Interfaces I/O Ports Timers and Triggers Analog Interfaces

External Bus Timer/Counter LESENSE
USART UART TFT Driver ADC LCD Controller
Interface
Low Energy Timer Real Time Counter
Low Energy External General Operational
I2C DAC
UARTTM Interrupts Purpose I/O Amplifier
Pulse Counter Watchdog Timer
Analog
USB Pin Reset Pin Wakeup Back-up RTC Comparator

Lowest power mode with peripheral operational:

EM0 - Active EM1 - Sleep EM2 – Deep Sleep EM3 - Stop EM4 - Shutoff

Figure 3.1. Block Diagram

3.1.1 ARM Cortex-M3 Core

The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection
Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while
the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32LG Reference Manual.

3.1.2 Debug Interface (DBG)

This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for
data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data
trace and software-generated messages.

3.1.3 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the EFM32LG microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.

3.1.4 Direct Memory Access Controller (DMA)

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.

3.1.5 Reset Management Unit (RMU)

The RMU is responsible for handling the reset functionality of the EFM32LG.

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 EFM32LG Data Sheet
System Summary

3.1.6 Energy Management Unit (EMU)

The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32LG microcontrollers. Each energy mode man-
ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.

3.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32LG. The CMU provides
the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the
available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not
wasting power on peripherals and oscillators that are inactive.

3.1.8 Watchdog (WDOG)

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may
e.g. be caused by an external event, such as an ESD pulse, or by a software failure.

3.1.9 Peripheral Reflex System (PRS)

The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each
other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex
signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but
edge triggers and other functionality can be applied by the PRS.

3.1.10 External Bus Interface (EBI)

The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-
face is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipu-
lating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number
of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is
limited to asynchronous devices.

3.1.11 TFT Direct Drive

The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller supports programmable display
and port sizes and offers accurate control of frequency and setup and hold timing. Direct Drive is supported for TFT displays which do
not have their own frame buffer. In that case TFT Direct Drive can transfer data from either on-chip memory or from an external memo-
ry device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers through the EBI interface.

3.1.12 Universal Serial Bus Controller (USB)

The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device, On-the-Go (OTG) Dual Role
Device, or Host-only configuration. In OTG mode, the USB supports both Host Negotiation Protocol (HNP) and Session Request Proto-
col (SRP). The device supports both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The USB device includes an internal,
dedicated Descriptor-Based Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0.
The on-chip PHY includes all OTG features, except for the voltage booster for supplying 5V to VBUS when operating as a host.

3.1.13 Inter-Integrated Circuit Interface (I2C)

The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a leader and a follower,
and supports multi-leader buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates
all the way from 10 kbit/s up to 1 Mbit/s. Follower arbitration and timeouts are also provided to allow implementation of an SMBus com-
pliant system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and
close to automatic transfers. Automatic recognition of follower addresses is provided in all energy modes.

3.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-
Cards, IrDA, and I2S devices.

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 EFM32LG Data Sheet
System Summary

3.1.15 Pre-Programmed USB/UART Bootloader

The bootloader presented in application note, AN0042: USB/UART Bootloader, is pre-programmed in the device at factory. The boot-
loader enables users to program the EFM32 through a UART or a USB CDC class virtual UART without the need for a debugger. The
autobaud feature, interface, and commands are described further in the application note.

3.1.16 Universal Asynchronous Receiver/Transmitter (UART)

The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-du-
plex asynchronous UART communication.

3.1.17 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)

The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a
32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support
to make asynchronous serial communication possible with minimum of software intervention and energy consumption.

3.1.18 Timer/Counter (TIMER)

The 16-bit general purpose timer has three compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM)
output. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.

3.1.19 Real Time Counter (RTC)

The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC
oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time
since the RTC is enabled in EM2 where most of the device is powered down.

3.1.20 Backup Real Time Counter (BURTC)

The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz crystal oscillator, a 32.768
kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy Modes and it can also run in backup mode, making it
operational even if the main power should drain out.

3.1.21 Low Energy Timer (LETIMER)

The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0.
Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be
performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of
waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start
counting on compare matches from the RTC.

3.1.22 Pulse Counter (PCNT)

The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either
the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.

3.1.23 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current
consumption can be configured by altering the current supply to the comparator.

3.1.24 Voltage Comparator (VCMP)

The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply
falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by
altering the current supply to the comparator.

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 EFM32LG Data Sheet
System Summary

3.1.25 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per
second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.

3.1.26 Digital to Analog Converter (DAC)

The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,
with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used
for a number of different applications such as sensor interfaces or sound output.

3.1.27 Operational Amplifier (OPAMP)

The EFM32LG features up to three Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with rail-
to-rail differential input and rail-to-rail single-ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin,
OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable
gain using internal resistors etc.

3.1.28 Low Energy Sensor Interface (LESENSE)

The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support for up to 16 individually configu-
rable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and meas-
urement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a pro-
grammable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy
mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.

3.1.29 Backup Power Domain

The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention regis-
ters, available in all energy modes. This power domain can be configured to automatically change power source to a backup battery
when the main power drains out. The backup power domain enables the EFM32LG to keep track of time and retain data, even if the
main power source should drain out.

3.1.30 Advanced Encryption Standard Accelerator (AES)

The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB sub-
ordinate which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations,
i.e. 8- or 16-bit operations are not supported.

3.1.31 General Purpose Input/Output (GPIO)

In the EFM32LG, there are up to 93 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each.
These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive
strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Tim-
er PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asyn-
chronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed
through the Peripheral Reflex System to other peripherals.

3.1.32 Liquid Crystal Display Driver (LCD)

The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage boost function enables it to provide
the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations
on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame
Counter interrupt that can wake-up the device on a regular basis for updating data.

3.2 Configuration Summary

The following sections provide device-specific features of the EFM32LG family of MCUs. These features are subsets of the full feature
set described in the EFM32LG Reference Manual.

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 EFM32LG Data Sheet
System Summary

3.2.1 EFM32LG230

The following table describes device-specific implementation of the EFM32LG230 features.

Table 3.1. EFM32LG230 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

GPIO 56 pins Available pins are shown in 5.1.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.2 EFM32LG232

The following table describes device-specific implementation of the EFM32LG232 features.

Table 3.2. EFM32LG232 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

GPIO 53 pins Available pins are shown in 5.2.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.3 EFM32LG280

The following table describes device-specific implementation of the EFM32LG280 features.

Table 3.3. EFM32LG280 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 85 pins Available pins are shown in 5.3.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.4 EFM32LG290

The following table describes device-specific implementation of the EFM32LG290 features.

Table 3.4. EFM32LG290 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 90 pins Available pins are shown in 5.4.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.5 EFM32LG295

The following table describes device-specific implementation of the EFM32LG295 features.

Table 3.5. EFM32LG295 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 93 pins Available pins are shown in 5.5.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.6 EFM32LG330

The following table describes device-specific implementation of the EFM32LG330 features.

Table 3.6. EFM32LG330 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 53 pins Available pins are shown in 5.6.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.7 EFM32LG332

The following table describes device-specific implementation of the EFM32LG332 features.

Table 3.7. EFM32LG332 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 50 pins Available pins are shown in 5.7.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.8 EFM32LG360

The following table describes device-specific implementation of the EFM32LG360 features.

Table 3.8. EFM32LG360 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 65 pins Available pins are shown in 5.8.3 GPIO Pinout Overview

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 EFM32LG Data Sheet
System Summary

3.2.9 EFM32LG380

The following table describes device-specific implementation of the EFM32LG380 features.

Table 3.9. EFM32LG380 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 83 pins Available pins are shown in 5.9.3 GPIO Pinout Overview

silabs.com | Building a more connected world. Rev. 2.41 | 34

 EFM32LG Data Sheet
System Summary

3.2.10 EFM32LG390

The following table describes device-specific implementation of the EFM32LG390 features.

Table 3.10. EFM32LG390 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 86 pins Available pins are shown in 5.10.3 GPIO Pinout Overview

silabs.com | Building a more connected world. Rev. 2.41 | 36

 EFM32LG Data Sheet
System Summary

3.2.11 EFM32LG395

The following table describes device-specific implementation of the EFM32LG395 features.

Table 3.11. EFM32LG395 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 93 pins Available pins are shown in 5.11.3 GPIO Pinout Overview

silabs.com | Building a more connected world. Rev. 2.41 | 38

 EFM32LG Data Sheet
System Summary

3.2.12 EFM32LG840

The following table describes device-specific implementation of the EFM32LG840 features.

Table 3.12. EFM32LG840 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

silabs.com | Building a more connected world. Rev. 2.41 | 39

 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

GPIO 56 pins Available pins are shown in 5.12.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[19:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

silabs.com | Building a more connected world. Rev. 2.41 | 40

 EFM32LG Data Sheet
System Summary

3.2.13 EFM32LG842

The following table describes device-specific implementation of the EFM32LG842 features.

Table 3.13. EFM32LG842 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:4], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

silabs.com | Building a more connected world. Rev. 2.41 | 41

 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

GPIO 53 pins Available pins are shown in 5.13.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

silabs.com | Building a more connected world. Rev. 2.41 | 42

 EFM32LG Data Sheet
System Summary

3.2.14 EFM32LG880

The following table describes device-specific implementation of the EFM32LG880 features.

Table 3.14. EFM32LG880 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

silabs.com | Building a more connected world. Rev. 2.41 | 43

 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 85 pins Available pins are shown in 5.14.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

silabs.com | Building a more connected world. Rev. 2.41 | 44

 EFM32LG Data Sheet
System Summary

3.2.15 EFM32LG890

The following table describes device-specific implementation of the EFM32LG890 features.

Table 3.15. EFM32LG890 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

silabs.com | Building a more connected world. Rev. 2.41 | 45

 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 90 pins Available pins are shown in 5.15.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

silabs.com | Building a more connected world. Rev. 2.41 | 46

 EFM32LG Data Sheet
System Summary

3.2.16 EFM32LG895

The following table describes device-specific implementation of the EFM32LG895 features.

Table 3.16. EFM32LG895 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

silabs.com | Building a more connected world. Rev. 2.41 | 47

 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 93 pins Available pins are shown in Table 4.3 (p. 70)

LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

silabs.com | Building a more connected world. Rev. 2.41 | 48

 EFM32LG Data Sheet
System Summary

3.2.17 EFM32LG900

The following table describes device-specific implementation of the EFM32LG900 features.

Table 3.17. EFM32LG900 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0], EBI_CS[3:0],

EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC, EBI_NANDREn, EBI_NAND-
WEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

silabs.com | Building a more connected world. Rev. 2.41 | 49

 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px, OPAMP_Nx

AES Full configuration NA

GPIO 93 pins Available pins are shown in 5.17.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N, LCD_BEXT

silabs.com | Building a more connected world. Rev. 2.41 | 50

 EFM32LG Data Sheet
System Summary

3.2.18 EFM32LG940

The following table describes device-specific implementation of the EFM32LG940 features.

Table 3.18. EFM32LG940 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O

ACMP1 Full configuration ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 53 pins Available pins are shown in 5.18.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

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 EFM32LG Data Sheet
System Summary

3.2.19 EFM32LG942

The following table describes device-specific implementation of the EFM32LG942 features.

Table 3.19. EFM32LG942 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:4], ACMP0_O

ACMP1 Full configuration ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 50 pins Available pins are shown in 5.19.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[15:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

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 EFM32LG Data Sheet
System Summary

3.2.20 EFM32LG980

The following table describes device-specific implementation of the EFM32LG980 features.

Table 3.20. EFM32LG980 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 81 pins Available pins are shown in 5.20.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

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 EFM32LG Data Sheet
System Summary

3.2.21 EFM32LG990

The following table describes device-specific implementation of the EFM32LG990 features.

Table 3.21. EFM32LG990 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[3:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 86 pins Available pins are shown in 5.21.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[33:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

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 EFM32LG Data Sheet
System Summary

3.2.22 EFM32LG995

The following table describes device-specific implementation of the EFM32LG995 features.

Table 3.22. EFM32LG995 Configuration Summary

Module Configuration Pin Connections

Cortex-M3 Full configuration NA

DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC Full configuration NA

DMA Full configuration NA

RMU Full configuration NA

EMU Full configuration NA

CMU Full configuration CMU_OUT0, CMU_OUT1

WDOG Full configuration NA

PRS Full configuration NA

USB Full configuration USB_VBUS, USB_VBUSEN, USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

EBI Full configuration EBI_A[27:0], EBI_AD[15:0], EBI_ARDY, EBI_ALE, EBI_BL[1:0],

EBI_CS[3:0], EBI_CSTFT, EBI_DCLK, EBI_DTEN, EBI_HSNC,
EBI_NANDREn, EBI_NANDWEn, EBI_REn, EBI_VSNC, EBI_WEn

I2C0 Full configuration I2C0_SDA, I2C0_SCL

I2C1 Full configuration I2C1_SDA, I2C1_SCL

USART0 Full configuration with IrDA US0_TX, US0_RX. US0_CLK, US0_CS

USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS

USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS

UART0 Full configuration U0_TX, U0_RX

UART1 Full configuration U1_TX, U1_RX

LEUART0 Full configuration LEU0_TX, LEU0_RX

LEUART1 Full configuration LEU1_TX, LEU1_RX

TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

TIMER1 Full configuration TIM1_CC[2:0]

TIMER2 Full configuration TIM2_CC[2:0]

TIMER3 Full configuration TIM3_CC[2:0]

RTC Full configuration NA

BURTC Full configuration NA

LETIMER0 Full configuration LET0_O[1:0]

PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0]

PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0]

PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0]

ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O

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 EFM32LG Data Sheet
System Summary

Module Configuration Pin Connections

ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O

VCMP Full configuration NA

ADC0 Full configuration ADC0_CH[7:0]

DAC0 Full configuration DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP Full configuration Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,

OPAMP_Nx

AES Full configuration NA

GPIO 93 pins Available pins are shown in 5.22.3 GPIO Pinout Overview

LCD Full configuration LCD_SEG[35:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,

LCD_BEXT

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 EFM32LG Data Sheet
System Summary

3.3 Memory Map

The EFM32LG memory map is shown in the following figure, with RAM and flash sizes for the largest memory configuration.

Figure 3.2. System Address Space with Core and Code Space Listing

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 EFM32LG Data Sheet
System Summary

Figure 3.3. System Address Space with Peripheral Listing

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 EFM32LG Data Sheet
Electrical Characteristics

4. Electrical Characteristics

4.1 Test Conditions

4.1.1 Typical Values

The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in 4.3 General Operating Conditions, unless otherwise specified.

4.1.2 Minimum and Maximum Values

The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined
in 4.3 General Operating Conditions, unless otherwise specified.

4.2 Absolute Maximum Ratings

The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond
the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operat-
ing conditions are given in 4.3 General Operating Conditions.

Table 4.1. Absolute Maximum Ratings

Parameter Symbol Test Condition Min Typ Max Unit

Storage temperature range TSTG -40 — 150 °C

Maximum soldering temperature TS Latest IPC/JEDEC J- — — 260 °C

STD-020 Standard

External main supply voltage VDDMAX 0 — 3.8 V

Voltage on any I/O pin VIOPIN -0.3 — VDD+0.3 V

Current per I/O pin (sink) IIOMAX_SINK — — 100 mA

Current per I/O pin (source) IIOMAX_SOURCE — — -100 mA

Junction temperature TJ -G grade devices -40 — 105 °C

4.3 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter Symbol Min Typ Max Unit

Ambient temperature range TAMB -40 — 85 °C

Operating supply voltage VDDOP 1.98 — 3.8 V

Internal APB clock frequency fAPB — — 48 MHz

Internal AHB clock frequency fAHB — — 48 MHz

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 EFM32LG Data Sheet
Electrical Characteristics

4.4 Backup Supply Domain

Table 4.3. Backup Supply Domain

Parameter Symbol Test Condition Min Typ Max Unit

Backup supply voltage range VBU_VIN 1.8 — 3.8 V

PWRRES resistor RPWRRES EMU_PWRCONF_PWRRES = 4234 4485 4786 Ω

RES0

EMU_PWRCONF_PWRRES = 2208 2363 2528 Ω

RES1

EMU_PWRCONF_PWRRES = 1166 1297 1433 Ω

RES2

EMU_PWRCONF_PWRRES = 295 344 399 Ω

RES3

Output impedance between RBU_VOUT EMU_PWRCONF_VOUT- 49 63 80 Ω

BU_VIN and BU_VOUT 1 STRONG = 1,
EMU_PWRCONF_VOUTMED =
0, EMU_PWRCONF_VOUT-
WEAK = 0

EMU_PWRCONF_VOUT- 522 670 844 Ω

STRONG = 0,
EMU_PWRCONF_VOUTMED =
1, EMU_PWRCONF_VOUT-
WEAK = 0

EMU_PWRCONF_VOUT- 5161 6743 7853 Ω

STRONG = 0,
EMU_PWRCONF_VOUTMED =
0, EMU_PWRCONF_VOUT-
WEAK = 1

Supply current IBU_VIN BU_VIN not powering backup do- — 3.4 6.5 nA
main

BU_VIN powering backup domain — 197 1050 nA

Note:
1. BU_VOUT and BU_STAT signals are not available in all package configurations. Check the device pinout for availability.

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 EFM32LG Data Sheet
Electrical Characteristics

4.5 Current Consumption

Table 4.4. Current Consumption

Parameter Symbol Test Condition Min Typ Max Unit

EM0 current. No prescaling. IEM0 48 MHz HFXO, all peripheral clocks disa- — 211 225 µA/MHz
Running prime number calcula- bled, VDD = 3.0 V, TAMB = 25 °C
tion code from Flash. (Produc-
tion test condition = 14 MHz) 48 MHz HFXO, all peripheral clocks disa- — 211 230 µA/MHz
bled, VDD = 3.0 V, TAMB = 85 °C

28 MHz HFRCO, all peripheral clocks disa- — 212 220 µA/MHz

bled, VDD = 3.0 V, TAMB = 25°C

28 MHz HFRCO, all peripheral clocks disa- — 213 223 µA/MHz

bled, VDD = 3.0 V, TAMB = 85°C

21 MHz HFRCO, all peripheral clocks disa- — 214 224 µA/MHz

bled, VDD = 3.0 V, TAMB = 25°C

21 MHz HFRCO, all peripheral clocks disa- — 215 226 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

14 MHz HFRCO, all peripheral clocks disa- — 216 231 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

14 MHz HFRCO, all peripheral clocks disa- — 217 237 µA/MHz

bled, VDD= 3.0 V, TAMB = 85°C

11 MHz HFRCO, all peripheral clocks disa- — 218 239 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

11 MHz HFRCO, all peripheral clocks disa- — 219 239 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

6.6 MHz HFRCO, all peripheral clocks disa- — 224 245 µA/MHz
bled, VDD= 3.0 V, TAMB = 25°C

6.6 MHz HFRCO, all peripheral clocks disa- — 224 258 µA/MHz
bled, VDD = 3.0 V, TAMB = 85°C

1.2 MHz HFRCO, all peripheral clocks disa- — 257 285 µA/MHz
bled, VDD = 3.0 V, TAMB = 25 °C

1.2 MHz HFRCO, all peripheral clocks disa- — 261 293 µA/MHz
bled, VDD = 3.0 V, TAMB = 85 °C

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

EM1 current (Production test IEM1 48 MHz HFXO, all peripheral clocks disa- — 63 75 µA/MHz
condition = 14 MHz) bled, VDD = 3.0 V, TAMB = 25 °C

48 MHz HFXO, all peripheral clocks disa- — 65 76 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

28 MHz HFRCO, all peripheral clocks disa- — 64 75 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

28 MHz HFRCO, all peripheral clocks disa- — 65 77 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

21 MHz HFRCO, all peripheral clocks disa- — 65 76 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

21 MHz HFRCO, all peripheral clocks disa- — 66 78 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

14 MHz HFRCO, all peripheral clocks disa- — 67 79 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

14 MHz HFRCO, all peripheral clocks disa- — 68 82 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

11 MHz HFRCO, all peripheral clocks disa- — 68 81 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

11 MHz HFRCO, all peripheral clocks disa- — 70 83 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

6.6 MHz HFRCO, all peripheral clocks disa- — 74 87 µA/MHz

bled, VDD = 3.0 V, TAMB = 25 °C

6.6 MHz HFRCO, all peripheral clocks disa- — 76 89 µA/MHz

bled, VDD = 3.0 V, TAMB = 85 °C

1.2 MHz HFRCO. all peripheral clocks disa- — 106 120 µA/MHz
bled, VDD = 3.0 V, TAMB = 25 °C

1.2 MHz HFRCO. all peripheral clocks disa- — 112 129 µA/MHz
bled, VDD = 3.0 V, TAMB = 85 °C

EM2 current IEM2 EM2 current with RTC prescaled to 1 Hz, — 0.951 1.71 µA
32.768 kHz LFRCO, VDD = 3.0 V, TAMB =
25 °C

EM2 current with RTC prescaled to 1 Hz, — 3.01 4.01 µA

32.768 kHz LFRCO, VDD = 3.0 V, TAMB =
85 °C

EM3 current IEM3 VDD = 3.0 V, TAMB = 25 °C — 0.65 1.3 µA

VDD = 3.0 V, TAMB = 85 °C — 2.65 4.0 µA

EM4 current IEM4 VDD = 3.0 V, TAMB = 25 °C — 0.020 0.055 µA

VDD = 3.0 V, TAMB = 85 °C — 0.44 0.90 µA

Note:
1. Using backup RTC.

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 EFM32LG Data Sheet
Electrical Characteristics

4.5.1 EM1 Current Consumption

3.15 3.15

3.10 3.10

3.05 3.05
Idd [mA]

Idd [mA]
2.0V
2.2V
3.00 3.00 2.4V
-40°C 2.6V
-15°C 2.8V
5°C 3.0V
2.95 25°C 2.95 3.2V
45°C 3.4V
65°C 3.6V
85°C 3.8V
2.90 2.90
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.1. EM1 Current Consumption with all Peripheral Clocks Disabled and HFXO Running at 48 MHz

1.85 1.85

1.80 1.80

1.75 1.75
Idd [mA]

Idd [mA]

2.0V
2.2V
1.70 1.70 2.4V
-40°C 2.6V
-15°C 2.8V
5°C 3.0V
1.65 25°C 1.65 3.2V
45°C 3.4V
65°C 3.6V
85°C 3.8V
1.60 1.60
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.2. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 28 MHz

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 EFM32LG Data Sheet
Electrical Characteristics

1.42 1.42

1.40 1.40

1.38 1.38

1.36 1.36

1.34 1.34
Idd [mA]

Idd [mA]
2.0V
1.32 1.32 2.2V
2.4V
1.30 -40°C 1.30 2.6V
-15°C 2.8V
5°C 3.0V
1.28 1.28
25°C 3.2V
45°C 3.4V
1.26 65°C 1.26 3.6V
85°C 3.8V
1.24 1.24
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.3. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 21 MHz

0.98 0.98

0.96 0.96

0.94 0.94
Idd [mA]

Idd [mA]

0.92 0.92 2.0V

2.2V
2.4V
0.90 -40°C 0.90 2.6V
-15°C 2.8V
5°C 3.0V
25°C 3.2V
0.88 0.88
45°C 3.4V
65°C 3.6V
85°C 3.8V
0.86 0.86
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.4. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 14 MHz

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 EFM32LG Data Sheet
Electrical Characteristics

0.78 0.78

0.76 0.76
Idd [mA]

Idd [mA]
0.74 0.74 2.0V
2.2V
2.4V
-40°C 2.6V
0.72 -15°C 0.72 2.8V
5°C 3.0V
25°C 3.2V
45°C 3.4V
0.70 65°C 0.70 3.6V
85°C 3.8V
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.5. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 11 MHz

0.52 0.52

0.51 0.51

0.50 0.50

0.49 0.49
Idd [mA]

Idd [mA]

2.0V
2.2V
0.48 0.48
2.4V
-40°C 2.6V
0.47 -15°C 0.47 2.8V
5°C 3.0V
25°C 3.2V
0.46 45°C 0.46 3.4V
65°C 3.6V
85°C 3.8V
0.45 0.45
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.6. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 6.6 MHz

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 EFM32LG Data Sheet
Electrical Characteristics

0.138 0.160
-40°C 2.0V
-15°C 0.155 2.2V
0.136
5°C 2.4V
25°C 2.6V
0.150
0.134 45°C 2.8V
65°C 3.0V
0.145
85°C 3.2V
0.132
3.4V
0.140
Idd [mA]

Idd [mA]
3.6V
0.130 3.8V
0.135

0.128
0.130

0.126
0.125

0.124 0.120

0.122 0.115
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd [V] Temperature [°C]

Figure 4.7. EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 1.2 MHz

4.5.2 EM2 Current Consumption

3.5 3.5
-40.0°C Vdd=2.0V
-15.0°C Vdd=2.2V
5.0°C Vdd=2.4V
3.0 3.0
25.0°C Vdd=2.6V
45.0°C Vdd=2.8V
65.0°C Vdd=3.0V
2.5 2.5
85.0°C Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Idd [uA]

Idd [uA]

2.0 2.0 Vdd=3.8V

1.5 1.5

1.0 1.0

0.5 0.5
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –20 0 20 40 60 80
Vdd [V] Temperature [°C]

Figure 4.8. EM2 Current Consumption, RTC1 prescaled to 1 kHz, 32.768 kHz LFRCO

Note:
1. Using backup RTC.

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Electrical Characteristics

4.5.3 EM3 Current Consumption

3.0 3.0
-40.0°C Vdd=2.0V
-15.0°C Vdd=2.2V
5.0°C Vdd=2.4V
2.5 2.5
25.0°C Vdd=2.6V
45.0°C Vdd=2.8V
65.0°C Vdd=3.0V
2.0 2.0
85.0°C Vdd=3.2V
Vdd=3.4V
Vdd=3.6V
Idd [uA]

Idd [uA]
1.5 1.5 Vdd=3.8V

1.0 1.0

0.5 0.5

0.0 0.0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –20 0 20 40 60 80
Vdd [V] Temperature [°C]

Figure 4.9. EM3 Current Consumption

4.5.4 EM4 Current Consumption

0.7 0.7
-40.0°C Vdd=2.0V
-15.0°C Vdd=2.2V
0.6 5.0°C 0.6 Vdd=2.4V
25.0°C Vdd=2.6V
45.0°C Vdd=2.8V
0.5 65.0°C 0.5 Vdd=3.0V
85.0°C Vdd=3.2V
Vdd=3.4V
0.4 0.4
Vdd=3.6V
Idd [uA]

Idd [uA]

Vdd=3.8V
0.3 0.3

0.2 0.2

0.1 0.1

0.0 0.0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –20 0 20 40 60 80
Vdd [V] Temperature [°C]

Figure 4.10. EM4 Current Consumption

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Electrical Characteristics

4.6 Transition between Energy Modes

The transition times are measured from the trigger to the first clock edge in the CPU.

Table 4.5. Energy Modes Transitions

Parameter Symbol Min Typ Max Unit

Transition time from EM1 to EM0 tEM10 — 0 — HFCORECLK cycles

Transition time from EM2 to EM0 tEM20 — 2 — µs

Transition time from EM3 to EM0 tEM30 — 2 — µs

Transition time from EM4 to EM0 tEM40 — 163 — µs

4.7 Power Management

The EFM32LG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level.
For practical schematic recommendations, see the application note, AN0002.0: EFM32 and EZR32 Wireless MCU Series 0 Hardware
Design Considerations.

Table 4.6. Power Management

Parameter Symbol Test Condition Min Typ Max Unit

BOD threshold on falling exter- VBODextthr- 1.74 — 1.96 V

nal supply voltage

BOD threshold on rising exter- VBODextthr+ — 1.85 1.98 V

nal supply voltage

Power-on Reset (POR) thresh- VPORthr+ — — 1.98 V

old on rising external supply
voltage

Delay from reset is released un- tRESET Applies to Power-on Reset, Brown- — 163 — µs
til program execution starts out Reset and pin reset.

Voltage regulator decoupling CDECOUPLE X5R capacitor recommended. Apply — 1 — µF

capacitor. between DECOUPLE pin and
GROUND

USB voltage regulator out de- CUSB_VREGO X5R capacitor recommended. Apply — 1 — µF
coupling capacitor. between USB_VREGO pin and
GROUND

USB voltage regulator in decou- CUSB_VREGI X5R capacitor recommended. Apply — 4.7 — µF
pling capacitor. between USB_VREGI pin and
GROUND

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Electrical Characteristics

4.8 Flash

Table 4.7. Flash

Parameter Symbol Test Condition Min Typ Max Unit

Flash erase cycles before fail- ECFLASH 20000 — — cycles

ure

Flash word write cycles be- WWCFLASH — — 21 cycles

tween erase

Flash data retention RETFLASH TAMB<150 °C 10000 — — h

TAMB<85 °C 10 — — years

TAMB<70 °C 20 — — years

Word (32-bit) programming time tW_PROG 20 — — µs

Page erase time2 tPERASE 20.7 22.0 24.8 ms

Device erase time3 tDERASE 41.8 45.0 49.2 ms

Erase current IERASE — — 74 mA

Write current IWRITE — — 74 mA

Supply voltage during flash VFLASH 1.98 — 3.8 V

erase and write

Note:
1. There is a maximum of two writes to the same word between each erase due to a physical limitation of the flash. No bit should be
written to ‘0’ more than once between erases. To write a word twice between erases, any bit written to ‘0’ by the first write should
be written to ‘1’ by the second write. This preserves the specified flash write/erase endurance and does not change the ‘0’ written
by the first write.
2. From setting ERASEPAGE bit in MSC_WRITECMD to 1 to reading 1 in ERASE bit in MSC_IF. Internal setup and hold times for
flash control signals are included.
3. From setting DEVICEERASE bit in AAP_CMD to 1 to reading 0 in ERASEBUSY bit in AAP_STATUS. Internal setup and hold
times for flash control signals are included.
4. Measured at 25 °C.

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Electrical Characteristics

4.9 General Purpose Input Output

Table 4.8. GPIO

Parameter Symbol Test Condition Min Typ Max Unit

Input low voltage VIOIL — — 0.30×VDD V

Input high voltage VIOIH 0.70×VDD — — V

Output high voltage (Produc- VIOOH Sourcing 0.1 mA, VDD = 1.98 V, — 0.80×VDD — V
tion test condition = 3.0 V, GPIO_Px_CTRL DRIVEMODE = LOW-
DRIVEMODE = STANDARD) EST

Sourcing 0.1 mA, VDD = 3.0 V, — 0.90×VDD — V

GPIO_Px_CTRL DRIVEMODE = LOW-
EST

Sourcing 1 mA, VDD = 1.98 V, — 0.85×VDD — V

GPIO_Px_CTRL DRIVEMODE = LOW

Sourcing 1 mA, VDD = 3.0 V, — 0.90×VDD — V

GPIO_Px_CTRL DRIVEMODE = LOW

Sourcing 6 mA, VDD = 1.98 V, 0.75×VDD — — V

GPIO_Px_CTRL DRIVEMODE =
STANDARD

Sourcing 6 mA, VDD = 3.0 V, 0.85×VDD — — V

GPIO_Px_CTRL DRIVEMODE =
STANDARD

Sourcing 20 mA, VDD=1.98 V, 0.60×VDD — — V

GPIO_Px_CTRL DRIVEMODE = HIGH

Sourcing 20 mA, VDD = 3.0 V, 0.80×VDD — — V

GPIO_Px_CTRL DRIVEMODE = HIGH

Output low voltage (Produc- VIOOL Sinking 0.1 mA, VDD = 1.98 V, — 0.20×VDD — V
tion test condition = 3.0V, GPIO_Px_CTRL DRIVEMODE = LOW-
DRIVEMODE = STANDARD) EST

Sinking 0.1 mA, VDD = 3.0 V, — 0.10×VDD — V

GPIO_Px_CTRL DRIVEMODE = LOW-
EST

Sinking 1 mA, VDD = 1.98 V, — 0.10×VDD — V

GPIO_Px_CTRL DRIVEMODE = LOW

Sinking 1 mA, VDD = 3.0 V, — 0.05×VDD — V

GPIO_Px_CTRL DRIVEMODE = LOW

Sinking 6 mA, VDD = 1.98 V, — — 0.30×VDD V

GPIO_Px_CTRL DRIVEMODE =
STANDARD

Sinking 6 mA, VDD = 3.0 V, — — 0.20×VDD V

GPIO_Px_CTRL DRIVEMODE =
STANDARD

Sinking 20 mA, VDD = 1.98 V, — — 0.35×VDD V

GPIO_Px_CTRL DRIVEMODE = HIGH

Sinking 20 mA, VDD = 3.0 V, — — 0.25×VDD V

GPIO_Px_CTRL DRIVEMODE = HIGH

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Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Input leakage current IIOLEAK VSS < Vin < VDD; pin configured as in- -40 ±0.1 40 nA
put or disabled, pullup and pull-down are
disabled

I/O pin pull-up resistor RPU — 40 — kΩ

I/O pin pull-down resistor RPD — 40 — kΩ

Internal ESD series resistor RIOESD — 200 — Ω

Pulse width of pulses to be re- tIO- 10 — 50 ns

moved by the glitch suppres- GLITCH
sion filter

Output fall time tIOOF GPIO_Px_CTRL DRIVEMODE = LOW- 20+0.1×CL — 250 ns

EST and load capacitance CL = 12.5-2
5pF.

GPIO_Px_CTRL DRIVEMODE = LOW 20+0.1×CL — 250 ns

and load capacitance CL = 350 -600 pF

I/O pin hysteresis (VIOTHR+ - VIOHYST VDD = 1.98 - 3.8 V 0.10×VDD — — V

VIOTHR-)

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Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW

0.20 5

4
0.15
Low-Level Output Current [mA]

Low-Level Output Current [mA]

3

0.10

0.05
1

-40°C -40°C
25°C 25°C
85°C 85°C
0.00 0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
Low-Level Output Voltage [V] Low-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH

20 45

40

35
15

30
Low-Level Output Current [mA]

Low-Level Output Current [mA]

25

10

20

15

5
10

-40°C 5 -40°C
25°C 25°C
85°C 85°C
0 0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
Low-Level Output Voltage [V] Low-Level Output Voltage [V]

Figure 4.11. Typical Low-Level Output Current, 2 V Supply Voltage

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Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW

0.00 0.0
-40°C -40°C
25°C 25°C
85°C 85°C

–0.5
–0.05
High-Level Output Current [mA]

High-Level Output Current [mA]

–1.0

–0.10

–1.5

–0.15
–2.0

–0.20 –2.5
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
High-Level Output Voltage [V] High-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH

0 0
-40°C -40°C
25°C 25°C
85°C 85°C

–10
–5
High-Level Output Current [mA]

High-Level Output Current [mA]

–20

–10

–30

–15

–40

–20
–50
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0
High-Level Output Voltage [V] High-Level Output Voltage [V]

Figure 4.12. Typical High-Level Output Current, 2 V Supply Voltage

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 EFM32LG Data Sheet
Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW

0.5 10

0.4 8
Low-Level Output Current [mA]

Low-Level Output Current [mA]

0.3 6

0.2 4

0.1 2

-40°C -40°C
25°C 25°C
85°C 85°C
0.0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low-Level Output Voltage [V] Low-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH

40 50

35

40
30
Low-Level Output Current [mA]

Low-Level Output Current [mA]

25
30

20

20
15

10
10

5
-40°C -40°C
25°C 25°C
85°C 85°C
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Low-Level Output Voltage [V] Low-Level Output Voltage [V]

Figure 4.13. Typical Low-Level Output Current, 3 V Supply Voltage

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Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW

0.0 0
-40°C -40°C
25°C 25°C
85°C 85°C

–1
–0.1

–2
High-Level Output Current [mA]

High-Level Output Current [mA]

–0.2

–3

–0.3

–4

–0.4
–5

–0.5 –6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
High-Level Output Voltage [V] High-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH

0 0
-40°C -40°C
25°C 25°C
85°C 85°C

–10 –10
High-Level Output Current [mA]

High-Level Output Current [mA]

–20 –20

–30 –30

–40 –40

–50 –50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
High-Level Output Voltage [V] High-Level Output Voltage [V]

Figure 4.14. Typical High-Level Output Current, 3 V Supply Voltage

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Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW

0.8 14

0.7
12

0.6
10
Low-Level Output Current [mA]

Low-Level Output Current [mA]

0.5

0.4

0.3

4
0.2

2
0.1
-40°C -40°C
25°C 25°C
85°C 85°C
0.0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low-Level Output Voltage [V] Low-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH

50 50

40 40
Low-Level Output Current [mA]

Low-Level Output Current [mA]

30 30

20 20

10 10

-40°C -40°C
25°C 25°C
85°C 85°C
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Low-Level Output Voltage [V] Low-Level Output Voltage [V]

Figure 4.15. Typical Low-Level Output Current, 3.8 V Supply Voltage

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Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST GPIO_Px_CTRL DRIVEMODE = LOW

0.0 0
-40°C -40°C
25°C 25°C
85°C –1 85°C
–0.1

–2
–0.2

–3
High-Level Output Current [mA]

High-Level Output Current [mA]

–0.3

–4

–0.4

–5

–0.5
–6

–0.6
–7

–0.7
–8

–0.8 –9
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High-Level Output Voltage [V] High-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD GPIO_Px_CTRL DRIVEMODE = HIGH

0 0
-40°C -40°C
25°C 25°C
85°C 85°C

–10 –10
High-Level Output Current [mA]

High-Level Output Current [mA]

–20 –20

–30 –30

–40 –40

–50 –50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
High-Level Output Voltage [V] High-Level Output Voltage [V]

Figure 4.16. Typical High-Level Output Current, 3.8 V Supply Voltage

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Electrical Characteristics

4.10 Oscillators

4.10.1 LFXO

Table 4.9. LFXO

Parameter Symbol Test Condition Min Typ Max Unit

Supported nominal crystal fLFXO — 32.768 — kHz

frequency

Supported crystal equivalent ESRLFXO — 30 120 kΩ

series resistance (ESR)

Supported crystal external CLFXOL X1 — 25 pF

load range

Current consumption for core ILFXO ESR = 30 kΩ, CL = 10 pF, LFXO- — 190 — nA
and buffer after startup. BOOST in CMU_CTRL is 1

Start- up time. tLFXO ESR = 30 kΩ, CL = 10 pF, 40% - 60% — 400 — ms

duty cycle has been reached, LFXO-
BOOST in CMU_CTRL is 1

Note:
1. See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio.

For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capaci-
tance and software settings for using the LFXO. For details regarding the crystal configuration, refer to the application note, AN0016:
EFM32 Oscillator Design Consideration.

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Electrical Characteristics

4.10.2 HFXO

Table 4.10. HFXO

Parameter Symbol Test Condition Min Typ Max Unit

Supported nominal crystal fHFXO 4 — 48 MHz

Frequency

Supported crystal equivalent ESRHFXO Crystal frequency 48 MHz — — 50 Ω

series resistance (ESR)
Crystal frequency 32 MHz — 30 60 Ω

Crystal frequency 4 MHz — 400 1500 Ω

The transconductance of the gmHFXO HFXOBOOST in CMU_CTRL equals 20 — — mS

HFXO input transistor at crys- 0b11
tal startup

Supported crystal external CHFXOL 5 — 25 pF

load range

Current consumption for IHFXO 4 MHz: ESR = 400 Ω, CL = 20 pF, — 85 — µA

HFXO after startup HFXOBOOST in CMU_CTRL equals
0b11

32 MHz: ESR = 30 Ω, CL = 10 pF, — 165 — µA

HFXOBOOST in CMU_CTRL equals
0b11

Startup time tHFXO 32 MHz: ESR = 30 Ω, CL = 10 pF, — 400 — µs

HFXOBOOST in CMU_CTRL equals
0b11

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Electrical Characteristics

4.10.3 LFRCO

Table 4.11. LFRCO

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation frequency fLFRCO VDD = 3.0 V, TAMB = 25 °C 31.29 32.768 34.28 kHz

Over full supply and temperature range 26.0 32.768 46.2 kHz

Startup time not including tLFRCO — 150 — µs

software calibration

Current consumption ILFRCO — 300 — nA

Frequency step for LSB TUNESTEPLFRCO — 1.5 — %

change in TUNING value

Voltage drift VDRIFT — -123291 — ppm/V

Temperature drift TDRIFT — 610 — ppm/°C

Figure 4.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage

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Electrical Characteristics

4.10.4 HFRCO

Table 4.12. HFRCO

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation frequency, all fHFRCO fHFRCO = 28 MHz 27.5 28.0 28.5 MHz
packages except CSP, VDD=
3.0 V, TAMB=25°C fHFRCO = 21 MHz 20.6 21.0 21.4 MHz

fHFRCO = 14 MHz 13.7 14.0 14.3 MHz

fHFRCO = 11 MHz 10.8 11.0 11.2 MHz

fHFRCO = 6.6 MHz 6.481 6.61 6.721 MHz

fHFRCO = 1.2 MHz 1.152 1.22 1.252 MHz

Oscillation frequency, all fHFRCO fHFRCO = 28 MHz 24.9 28.0 31.1 MHz
packages except CSP, over
full supply and temperature fHFRCO = 21 MHz 18.8 21.0 23.3 MHz
range
fHFRCO = 14 MHz 12.4 14.0 15.6 MHz

fHFRCO = 11 MHz 9.9 11.0 12.2 MHz

fHFRCO = 6.6 MHz 5.91 6.61 7.41 MHz

fHFRCO = 1.2 MHz 0.82 1.22 1.62 MHz

Oscillation frequency, CSP fHFRCO fHFRCO = 28 MHz — 28.0 — MHz

devices, VDD= 3.0 V,
TAMB=25°C fHFRCO = 21 MHz — 21.0 — MHz

fHFRCO = 14 MHz — 14.0 — MHz

fHFRCO = 11 MHz — 11.0 — MHz

fHFRCO = 6.6 MHz — 6.61 — MHz

fHFRCO = 1.2 MHz — 1.22 — MHz

Oscillation frequency, CSP fHFRCO fHFRCO = 28 MHz — 28.0 — MHz

devices, over full supply and
temperature range fHFRCO = 21 MHz — 21.0 — MHz

fHFRCO = 14 MHz — 14.0 — MHz

fHFRCO = 11 MHz — 11.0 — MHz

fHFRCO = 6.6 MHz — 6.61 — MHz

fHFRCO = 1.2 MHz — 1.22 — MHz

Settling time after start-up tHFRCO_settling fHFRCO = 14 MHz — 0.6 — Cycles

Current consumption IHFRCO fHFRCO = 28 MHz — 165 215 µA

fHFRCO = 21 MHz — 134 175 µA

fHFRCO = 14 MHz — 106 140 µA

fHFRCO = 11 MHz — 94 125 µA

fHFRCO = 6.6 MHz — 77 105 µA

fHFRCO = 1.2 MHz — 25 40 µA

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Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Voltage drift VHFRCO_DRIFT fHFRCO = 28 MHz — 10768 — ppm/V

fHFRCO = 21 MHz — 8939 — ppm/V

fHFRCO = 14 MHz — 8040 — ppm/V

fHFRCO = 11 MHz — 7719 — ppm/V

fHFRCO = 6.6 MHz — 8491 — ppm/V

fHFRCO = 1.2 MHz — -124035 — ppm/V

Temperature drift THFRCO_DRIFT fHFRCO = 28 MHz — 91 — ppm/°C

fHFRCO = 21 MHz — 88 — ppm/°C

fHFRCO = 14 MHz — 43 — ppm/°C

fHFRCO = 11 MHz — 50 — ppm/°C

fHFRCO = 6.6 MHz — -50 — ppm/°C

fHFRCO = 1.2 MHz — 83 — ppm/°C

Frequency step for LSB TUNESTEPHFRCO — 0.33 — %

change in TUNING value

Note:
1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature.
By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and
the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating condi-
tions.

Figure 4.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature

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Electrical Characteristics

Figure 4.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature

Figure 4.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature

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Electrical Characteristics

Figure 4.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature

Figure 4.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature

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Electrical Characteristics

Figure 4.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature

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Electrical Characteristics

4.10.5 AUXHFRCO

Table 4.13. AUXHFRCO

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation frequency, all fAUXHFRCO fAUXHFRCO = 28 MHz 27.5 28.0 28.5 MHz
packages except CSP, VDD=
3.0 V, TAMB = 25 °C fAUXHFRCO = 21 MHz 20.6 21.0 21.4 MHz

fAUXHFRCO = 14 MHz 13.7 14.0 14.3 MHz

fAUXHFRCO = 11 MHz 10.8 11.0 11.2 MHz

fAUXHFRCO = 6.6 MHz 6.481 6.601 6.721 MHz

fAUXHFRCO = 1.2 MHz 1.152 1.202 1.252 MHz

Oscillation frequency, CSP fAUXHFRCO fAUXHFRCO = 28 MHz — 28.0 — MHz

devices, VDD = 3.0 V, TAMB =
25 °C fAUXHFRCO = 21 MHz — 21.0 — MHz

fAUXHFRCO = 14 MHz — 14.0 — MHz

fAUXHFRCO = 11 MHz — 11.0 — MHz

fAUXHFRCO = 6.6 MHz — 6.601 — MHz

fAUXHFRCO = 1.2 MHz — 1.202 — MHz

Settling time after start-up tAUXHFRCO_settling fAUXHFRCO = 14 MHz — 0.6 — Cycles

Frequency step for LSB TUNE- — 0.33 — %

change in TUNING value STEPAUXHFRCO

Note:
1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough
adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and
temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUN-
ING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz
across operating conditions.

4.10.6 ULFRCO

Table 4.14. ULFRCO

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation frequency fULFRCO 25 °C, 3 V 0.7 — 1.75 kHz

Temperature coefficient TCULFRCO — 0.05 — %/°C

Supply voltage coefficient VCULFRCO — -18.2 — %/V

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4.11 Analog Digital Converter (ADC)

Table 4.15. ADC

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range VADCIN Single-ended 0 — VREF V

Differential -VREF/2 — VREF/2 V

Input range of external refer- VADCREFIN 1.25 — VDD V

ence voltage, single-ended and
differential

Input range of external negative VADCREFIN_CH7 See VADCREFIN 0 — VDD - 1.1 V

reference voltage on channel 7

Input range of external positive VADCREFIN_CH6 See VADCREFIN 0.625 — VDD V

reference voltage on channel 6

Common mode input range VADCCMIN 0 — VDD V

Input current IADCIN 2 pF sampling capacitors — <100 — nA

Analog input common mode re- CMRRADC — 65 — dB

jection ratio

Average active current IADC 1 MSamples/s, 12-bit, external — 351 1 — µA

reference

10 kSamples/s 12-bit, internal — 67 1 — µA

1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00

10 kSamples/s 12-bit, internal — 63 1 — µA

1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01

10 kSamples/s 12-bit, internal — 64 1 — µA

1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10

Input capacitance CADCIN — 2 — pF

Input ON resistance RADCIN 300 — 800 Ω

Input RC filter resistance RADCFILT — 10 — kΩ

Input RC filter/decoupling ca- CADCFILT — 250 — fF

pacitance

Input bias current IADCBIASIN VSS < VIN < VDD -40 — 40 nA

Input offset current IADCOFFSETIN VSS < VIN < VDD -40 — 40 nA

ADC Clock Frequency fADCCLK — — 13 MHz

Conversion time tADCCONV 6-bit 7 — — ADCCLK

Cycles

8-bit 11 — — ADCCLK
Cycles

12-bit 13 — — ADCCLK
Cycles

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Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Acquisition time tADCACQ Programmable 1 — 256 ADCCLK

Cycles

Required acquisition time for tADCACQVDD3 2 — — µs

VDD/3 reference

Startup time of reference gener- tADCSTART NORMAL mode — 5 — µs

ator and ADC core
KEEPADCWARM mode — 1 — µs

Signal-to-Noise Ratio (SNR) SNRADC 1 MSamples/s, 12-bit, single- — 59 — dB

ended, internal 1.25 V reference

1 MSamples/s, 12-bit, single- — 63 — dB

ended, internal 2.5 V reference

1 MSamples/s, 12-bit, single- — 65 — dB

ended, VDD reference

1 MSamples/s, 12-bit, differen- — 60 — dB

tial, internal 1.25 V reference

1 MSamples/s, 12-bit, differen- — 65 — dB

tial, internal 2.5 V reference

1 MSamples/s, 12-bit, differen- — 54 — dB

tial, 5 V reference

1 MSamples/s, 12-bit, differen- — 67 — dB

tial, VDD reference

1 MSamples/s, 12-bit, differen- — 69 — dB

tial, 2xVDD reference

200 kSamples/s, 12-bit, single- — 62 — dB

ended, internal 1.25 V reference

200 kSamples/s, 12-bit, single- — 63 — dB

ended, internal 2.5 V reference

200 kSamples/s, 12-bit, single- — 67 — dB

ended, VDD reference

200 kSamples/s, 12-bit, differ- — 63 — dB

ential, internal 1.25 V reference

200 kSamples/s, 12-bit, differ- — 66 — dB

ential, internal 2.5 V reference

200 kSamples/s, 12-bit, differ- — 66 — dB

ential, 5 V reference

200 kSamples/s, 12-bit, differ- 63 66 — dB

ential, VDD reference

200 kSamples/s, 12-bit, differ- — 70 — dB

ential, 2xVDD reference

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Parameter Symbol Test Condition Min Typ Max Unit

Signal-to-Noise And Distortion SINADADC 1 MSamples/s, 12-bit, single- — 58 — dB

Ratio (SINAD) ended, internal 1.25 V reference

1 MSamples/s, 12-bit, single- — 62 — dB

ended, internal 2.5 V reference

1 MSamples/s, 12-bit, single- — 64 — dB

ended, VDD reference

1 MSamples/s, 12-bit, differen- — 60 — dB

tial, internal 1.25 V reference

1 MSamples/s, 12-bit, differen- — 64 — dB

tial, internal 2.5 V reference

1 MSamples/s, 12-bit, differen- — 54 — dB

tial, 5 V reference

1 MSamples/s, 12-bit, differen- — 66 — dB

tial, VDD reference

1 MSamples/s, 12-bit, differen- — 68 — dB

tial, 2xVDD reference

200 kSamples/s, 12-bit, single- — 61 — dB

ended, internal 1.25 V reference

200 kSamples/s, 12-bit, single- — 65 — dB

ended, internal 2.5 V reference

200 kSamples/s, 12-bit, single- — 66 — dB

ended, VDD reference

200 kSamples/s, 12-bit, differ- — 63 — dB

ential, internal 1.25 V reference

200 kSamples/s, 12-bit, differ- — 66 — dB

ential, internal 2.5 V reference

200 kSamples/s, 12-bit, differ- — 66 — dB

ential, 5V reference

200 kSamples/s, 12-bit, differ- 62 66 — dB

ential, VDD reference

200 kSamples/s, 12-bit, differ- — 69 — dB

ential, 2xVDD reference

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Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Spurious-Free Dynamic Range SFDRADC 1 MSamples/s, 12-bit, single- — 64 — dBc

(SFDR) ended, internal 1.25 V reference

1 MSamples/s, 12-bit, single- — 76 — dBc

ended, internal 2.5 V reference

1 MSamples/s, 12-bit, single- — 73 — dBc

ended, VDD reference

1 MSamples/s, 12-bit, differen- — 66 — dBc

tial, internal 1.25 V reference

1 MSamples/s, 12-bit, differen- — 77 — dBc

tial, internal 2.5 V reference

1 MSamples/s, 12-bit, differen- — 76 — dBc

tial, VDD reference

1 MSamples/s, 12-bit, differen- — 75 — dBc

tial, 2xVDD reference

1 MSamples/s, 12-bit, differen- — 69 — dBc

tial, 5 V reference

200 kSamples/s, 12-bit, single- — 75 — dBc

ended, internal 1.25 V reference

200 kSamples/s, 12-bit, single- — 75 — dBc

ended, internal 2.5 V reference

200 kSamples/s, 12-bit, single- — 76 — dBc

ended, VDD reference

200 kSamples/s, 12-bit, differ- — 79 — dBc

ential, internal 1.25 V reference

200 kSamples/s, 12-bit, differ- — 79 — dBc

ential, internal 2.5 V reference

200 kSamples/s, 12-bit, differ- — 78 — dBc

ential, 5 V reference

200 kSamples/s, 12-bit, differ- 68 79 — dBc

ential, VDD reference

200 kSamples/s, 12-bit, differ- — 79 — dBc

ential, 2xVDD reference

Offset voltage VADCOFFSET After calibration, single-ended -3.5 0.3 3 mV

After calibration, differential — 0.3 — mV

Thermometer output gradient TGRADADCTH — -1.92 — mV/°C

— -6.3 — ADC Co-

des/°C

Differential non-linearity (DNL) DNLADC VDD= 3.0 V, external 2.5 V ref- -1 ±0.7 4 LSB
erence

Integral non-linearity (INL), End INLADC VDD= 3.0 V, external 2.5 V ref- — ±1.2 ±3 LSB
point method erence

Missing codes MCADC 11.999 2 12 — bits

Gain error drift GAINED 1.25 V reference — 0.01 3 0.033 4 %/°C

2.5 V reference — 0.01 3 0.03 4 %/°C

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Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Offset error drift OFFSETED 1.25 V reference — 0.2 3 0.7 4 LSB/°C

2.5 V reference — 0.2 3 0.62 4 LSB/°C

VREF voltage VREF 1.25 V reference 1.2 1.25 1.3 V

2.5 V reference 2.4 2.5 2.6 V

VREF voltage drift VREF_VDRIFT 1.25 V reference -12.4 2.9 18.2 mV/V

2.5 V reference, VDD > 2.5 V -24.6 5.7 35.2 mV/V

VREF temperature drift VREF_TDRIFT 1.25 V reference -132 272 677 µV/°C

2.5 V reference -231 545 1271 µV/°C

VREF current consumption IVREF 1.25 V reference — 67 97 µA

2.5 V reference — 55 72 µA

ADC and DAC VREF matching VREF_MATCH 1.25 V reference — 99.85 — %

2.5 V reference — 100.01 — %

Note:
1. Includes required contribution from the voltage reference.
2. On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbor codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full-scale
input for chips that have the missing code issue.
3. Typical numbers given by abs(Mean) / (85 - 25).
4. Max number given by (abs(Mean) + 3x stddev) / (85 - 25).

The integral non-linearity (INL) and differential non-linearity parameters are explained in the following two figures.

Digital output code

INL=|[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N- 1

4095

4094
Actual ADC
4093 tranfer function
before offset and
4092 gain correction Actual ADC
tranfer function
after offset and
gain correction

INL Error
(End Point INL)

3 Ideal transfer
curve
2

1
VOFFSET
0

Analog Input

Figure 4.24. Integral Non-Linearity (INL)

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Electrical Characteristics

Digital
output
code
DNL=|[(VD+1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N- 2

4095 Full Scale Range

4094
Example: Adjacent
4093 input value VD+1
corrresponds to digital
output code D+1 Actual transfer
4092
Example: Input value function with one
VDcorrresponds to missing code.
digital output code D

Code width =2 LSB

Ideal transfer DNL=1 LSB
curve

0.5
LSB Ideal spacing
5
between two
4 adjacent codes
VLSBIDEAL=1 LSB
3
Ideal 50%
2 Transition Point

1 Ideal Code Center

0
Analog Input

Figure 4.25. Differential Non-Linearity (DNL)

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Electrical Characteristics

4.11.1 Typical Performance

1.25V Reference 2.5V Reference

2XVDDVSS Reference 5VDIFF Reference

VDD Reference

Figure 4.26. ADC Frequency Spectrum, VDD = 3 V, Temp = 25 °C

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Electrical Characteristics

1.25V Reference 2.5V Reference

2XVDDVSS Reference 5VDIFF Reference

VDD Reference

Figure 4.27. ADC Integral Linearity Error vs Code, VDD = 3 V, Temp = 25 °C

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Electrical Characteristics

1.25V Reference 2.5V Reference

2XVDDVSS Reference 5VDIFF Reference

VDD Reference

Figure 4.28. ADC Differential Linearity Error vs Code, VDD = 3 V, Temp = 25 °C

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Electrical Characteristics

Offset vs Supply Voltage, Temp = 25°C Offset vs Temperature, VDD = 3V

5 2.0
Vref=1V25 VRef=1V25
4 Vref=2V5 VRef=2V5
Vref=2XVDDVSS VRef=2XVDDVSS
1.5
Vref=5VDIFF VRef=5VDIFF
3
Vref=VDD VRef=VDD

2 1.0
Actual Offset [LSB]

Actual Offset [LSB]

1
0.5
0

–1 0.0

–2
–0.5
–3

–4 –1.0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 –40 –15 5 25 45 65 85
Vdd (V) Temp (C)

Figure 4.29. ADC Absolute Offset, Common Mode = VDD/2

Signal to Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR)

71 79.4

2XVDDVSS
70 1V25
79.2
Vdd
69
79.0

68 Vdd
2V5
78.8
SFDR [dB]
SNR [dB]

67

5VDIFF 78.6
66 2V5 2XVDDVSS

78.4
65

78.2
64

5VDIFF
1V25
63 78.0
–40 –15 5 25 45 65 85 –40 –15 5 25 45 65 85
Temperature [°C] Temperature [°C]

Figure 4.30. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3 V

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Electrical Characteristics

2600
Vdd=2.0
Vdd=3.0
Vdd=3.8
2500

2400

Sensor readout
2300

2200

2100
–40 –25 –15 –5 5 15 25 35 45 55 65 75 85
Temperature [°C]

Figure 4.31. ADC Temperature Sensor Readout

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Electrical Characteristics

4.12 Digital Analog Converter (DAC)

Table 4.16. DAC

Parameter Symbol Test Condition Min Typ Max Unit

Output voltage range VDACOUT VDD voltage reference, single-ended 0 — VDD V

VDD voltage reference, differential -VDD — VDD V

Output common mode voltage VDACCM 0 — VDD V

range

Average active current IDAC 500 kSamples/s, 12-bit, internal 1.25 V — 4001 — µA
reference, Continuous Mode

100 kSamples/s, 12-bit, internal 1.25 V — 2001 — µA

reference, Sample/Hold Mode

1 kSamples/s 12-bit, internal 1.25 V ref- — 171 — µA

erence, Sample/Off Mode

Sample rate SRDAC — — 500 ksamples/

s

DAC clock frequency fDAC Continuous Mode — — 1000 kHz

Sample/Hold Mode — — 250 kHz

Sample/Off Mode — — 250 kHz

Clock cycles per conversion CYCDAC- — 2 — cycles

CONV

Conversion time tDACCONV 2 — — µs

Settling time tDACSET- — 5 — µs

TLE

Signal-to-Noise Ratio (SNR) SNRDAC 500 kSamples/s, 12-bit, single-ended, — 58 — dB

internal 1.25 V reference

500 kSamples/s, 12-bit, single-ended, — 59 — dB

internal 2.5 V reference

500 kSamples/s, 12-bit, differential, in- — 58 — dB

ternal 1.25 V reference

500 kSamples/s, 12-bit, differential, in- — 58 — dB

ternal 2.5V reference

500 kSamples/s, 12-bit, differential, — 59 — dB

VDD reference

Signal-to-Noise plus Distortion SNDRDAC 500 kSamples/s, 12-bit, single-ended, — 57 — dB

Ratio (SNDR) internal 1.25 V reference

500 kSamples/s, 12-bit, single-ended, — 54 — dB

internal 2.5 V reference

500 kSamples/s, 12-bit, differential, in- — 56 — dB

ternal 1.25 V reference

500 kSamples/s, 12-bit, differential, in- — 53 — dB

ternal 2.5 V reference

500 kSamples/s, 12-bit, differential, — 55 — dB

VDD reference

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Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Spurious-Free Dynamic Range SFDRDAC 500 kSamples/s, 12-bit, single-ended, — 62 — dBc

(SFDR) internal 1.25 V reference

500 kSamples/s, 12-bit, single-ended, — 56 — dBc

internal 2.5 V reference

500 kSamples/s, 12-bit, differential, in- — 61 — dBc

ternal 1.25 V reference

500 kSamples/s, 12-bit, differential, in- — 55 — dBc

ternal 2.5 V reference

500 kSamples/s, 12-bit, differential, — 60 — dBc

VDD reference

Offset voltage, all packages ex- VDACOFF- After calibration, single-ended — 2 9 mV

cept CSP SET
After calibration, differential — 2 — mV

Offset voltage, CSP devices VDACOFF- After calibration, single-ended — 2 — mV

SET
After calibration, differential — 2 — mV

Differential non-linearity DNLDAC — ±1 — LSB

Integral non-linearity INLDAC — ±5 — LSB

No missing codes MCDAC — 12 — bits

Load current ILOAD_DC — — 11 mA

VREF voltage VREF 1.25 V reference 1.2 1.25 1.3 V

2.5 V reference 2.4 2.5 2.6 V

VREF voltage drift VREF_VDR 1.25 V reference -12.4 2.3 18.2 mV/V
IFT
2.5 V reference, VDD > 2.5 V -24.6 5.3 35.2 mV/V

VREF temperature drift VREF_TDR 1.25 V reference -132 242 677 µV/°C
IFT
2.5 V reference -231 507 1271 µV/°C

VREF current consumption IVREF 1.25 V reference — 67 97 µA

2.5 V reference — 55 72 µA

ADC and DAC VREF matching VREF_MAT 1.25 V reference — 99.85 — %

CH
2.5 V reference — 100.01 — %

Note:
1. Measured with a static input code and no loading on the output. Includes required contribution from the voltage reference.

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Electrical Characteristics

4.13 Operational Amplifier (OPAMP)

Table 4.17. OPAMP

Parameter Symbol Test Condition Min Typ Max Unit

Active Current IOPAMP (OPA2)BIASPROG=0xF,(OPA2)HALF- — 370 460 µA

BIAS=0x0, Unity Gain

(OPA2)BIASPROG=0x7,(OPA2)HALF- — 95 135 µA
BIAS=0x1, Unity Gain

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 13 25 µA
BIAS=0x1, Unity Gain

(OPA2)BIASPROG=0x4,(OPA2)HALF- — 63 87 µA
BIAS=0x1, UnityGain

(OPA0)BIASPROG=0x0,(OPA0)HALF- — 18 27 µA
BIAS=0x1, UnityGain

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 68 96 µA
BIAS=0x1, UnityGain

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 18 27 µA
BIAS=0x1, UnityGain

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 67 96 µA
BIAS=0x1, UnityGain

Open Loop Gain GOL (OPA2)BIASPROG=0xF,(OPA2)HALF- — 101 — dB

BIAS=0x0

(OPA2)BIASPROG=0x7,(OPA2)HALF- — 98 — dB
BIAS=0x1

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 91 — dB
BIAS=0x1

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Parameter Symbol Test Condition Min Typ Max Unit

Gain Bandwidth GBWOPAMP (OPA0)BIASPROG=0x0,(OPA0)HALF- — 0.3931 — MHz

Product BIAS=0x1, DC bias = 0.3 V

(OPA0)BIASPROG=0x0,(OPA0)HALF- — 0.4871 — MHz

BIAS=0x1, DC bias = 1 V

(OPA0)BIASPROG=0x0,(OPA0)HALF- — 0.3921 — MHz

BIAS=0x1, DC bias = 2 V

(OPA0)BIASPROG=0x0,(OPA0)HALF- — 0.3181 — MHz

BIAS=0x1, DC bias = 2.7 V

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 1.5951 — MHz

BIAS=0x1, DC bias = 0.3 V

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 2.6611 — MHz

BIAS=0x1, DC bias = 1 V

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 2.5661 — MHz

BIAS=0x1, DC bias = 2 V

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 1.7871 — MHz

BIAS=0x1, DC bias = 2.7 V

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 0.4601 — MHz

BIAS=0x1, DC bias = 0.3 V

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 0.4471 — MHz

BIAS=0x1, DC bias = 1 V

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 0.3721 — MHz

BIAS=0x1, DC bias = 2 V

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 0.2951 — MHz

BIAS=0x1, DC bias = 2.7 V

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 1.8901 — MHz

BIAS=0x1, DC bias = 0.3 V

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 2.8491 — MHz

BIAS=0x1, DC bias = 1 V

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 2.5611 — MHz

BIAS=0x1, DC bias = 2 V

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 1.7051 — MHz

BIAS=0x1, DC bias = 2.7 V

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 0.3391 — MHz

BIAS=0x1, DC bias = 0.3 V

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 0.4321 — MHz

BIAS=0x1, DC bias = 1 V

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 0.3471 — MHz

BIAS=0x1, DC bias = 2 V

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 0.2861 — MHz

BIAS=0x1, DC bias = 2.7 V

(OPA2)BIASPROG=0x4,(OPA2)HALF- — 1.2711 — MHz

BIAS=0x1, DC bias = 0.3 V

(OPA2)BIASPROG=0x4,(OPA2)HALF- — 1.4291 — MHz

BIAS=0x1, DC bias = 1 V

(OPA2)BIASPROG=0x4,(OPA2)HALF- — 1.2831 — MHz

BIAS=0x1, DC bias = 2 V

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Parameter Symbol Test Condition Min Typ Max Unit

Gain Bandwidth GBWOPAMP (OPA2)BIASPROG=0x4,(OPA2)HALF- — 1.1361 — MHz

Product BIAS=0x1, DC bias = 2.7 V

(OPA2)BIASPROG=0xF,(OPA2)HALF- — 6.12 — MHz

BIAS=0x0, DC bias = 1.5 V

(OPA2)BIASPROG=0x7,(OPA2)HALF- — 1.82 — MHz

BIAS=0x1, DC bias = 1.5 V

Phase Margin PMOPAMP (OPA2)BIASPROG=0xF,(OPA2)HALF- — 64 — º

BIAS=0x0, CL = 75 pF

(OPA2)BIASPROG=0x7,(OPA2)HALF- — 58 — º
BIAS=0x1, CL = 75 pF

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 58 — º
BIAS=0x1, CL = 75 pF

Input Resistance RINPUT — 100 — MΩ

Load Resistance RLOAD OPA0/1 200 — — Ω

OPA/2 1000 — — Ω

DC Load Current ILOAD_DC — — 11 mA

Input Voltage VINPUT OPAxHCMDIS=0 VSS — VDD V

OPAxHCMDIS=1 VSS — VDD-1.2 V

Output Voltage VOUTPUT VSS — VDD V

Input Offset Voltage, VOFFSET (OPA0) Unity Gain, VSS<Vin<VDD, -13 0 11 mV

all packages except OPAxHCMDIS=0
CSP
(OPA1) Unity Gain, VSS<Vin<VDD, -13 0.1 11 mV
OPAxHCMDIS=0

(OPA2) Unity Gain, VSS<Vin<VDD, -13 0 11 mV

OPAxHCMDIS=0

(OPA2) Unity Gain, — 1 — mV

VSS<Vin<VDD-1.2,OPAxHCMDIS=1

Input Offset Voltage, VOFFSET (OPA0) Unity Gain, VSS<Vin<VDD, — 0 — mV

CSP devices OPAxHCMDIS=0

(OPA1) Unity Gain, VSS<Vin<VDD, — 0.1 — mV

OPAxHCMDIS=0

(OPA2) Unity Gain, VSS<Vin<VDD, -13 0 11 mV

OPAxHCMDIS=0

(OPA2) Unity Gain, — 1 — mV

VSS<Vin<VDD-1.2,OPAxHCMDIS=1

Input Offset Voltage VOFFSET_DRIFT — — 0.02 mV/°C

Drift

Input bias current I OPAMPBIASIN VSS < VIN < VDD -40 — 40 nA

Input offset current I OPAMPOFFSETI VSS < VIN < VDD -40 — 40 nA

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Slew Rate SROPAMP (OPA2)BIASPROG=0xF,(OPA2)HALF- — 3.2 — V/µs

BIAS=0x0, 70 pF load Rising (Simulated at
25 C and VDD=3 V)

(OPA2)BIASPROG=0x7,(OPA2)HALF- — 0.8 — V/µs

BIAS=0x1, 70 pF load, Rising (Simulated at
25 °C and VDD = 3 V)

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 178 — V/µs

BIAS=0x1, 70 pF load, Rising

(OPA2)BIASPROG=0x0,(OPA2)HALF- — 198 — V/µs

BIAS=0x1, 70 pF load, Falling

(OPA2)BIASPROG=0x4,(OPA2)HALF- — 969 — V/µs

BIAS=0x1, 70 pF load, Rising

(OPA2)BIASPROG=0x4,(OPA2)HALF- — 969 — V/µs

BIAS=0x1, 70 pF load, Falling

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 166 — V/µs

BIAS=0x1, 70 pF load, Rising

(OPA1)BIASPROG=0x0,(OPA1)HALF- — 180 — V/µs

BIAS=0x1, 70 pF load, Falling

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 918 — V/µs

BIAS=0x1, 70 pF load, Rising

(OPA1)BIASPROG=0x4,(OPA1)HALF- — 937 — V/µs

BIAS=0x1, 70 pF load, Falling

(OPA0)BIASPROG=0x0,(OPA0)HALF- — 173 — V/µs

BIAS=0x1, 70 pF load, Rising

(OPA0)BIASPROG=0x0,(OPA0)HALF- — 191 — V/µs

BIAS=0x1, 70 pF load, Falling

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 935 — V/µs

BIAS=0x1, 70 pF load, Rising

(OPA0)BIASPROG=0x4,(OPA0)HALF- — 950 — V/µs

BIAS=0x1, 70 pF load, Falling

Voltage Noise NOPAMP Vout = 1 V, RESSEL=0, 0.1 Hz<f<10 kHz, — 101 — µVRMS
OPAxHCMDIS=0

Vout = 1 V, RESSEL=0, 0.1 Hz<f<10 kHz, — 141 — µVRMS

OPAxHCMDIS=1

Vout=1V, RESSEL=0, 0.1 Hz<f<1 MHz, — 196 — µVRMS

OPAxHCMDIS=0

Vout=1V, RESSEL=0, 0.1 Hz<f<1 MHz, — 229 — µVRMS

OPAxHCMDIS=1

RESSEL=7, 0.1 Hz<f<10 kHz, OPAxHCM- — 1230 — µVRMS

DIS=0

RESSEL=7, 0.1 Hz<f<10 kHz, OPAxHCM- — 2130 — µVRMS

DIS=1

RESSEL=7, 0.1 Hz<f<1 MHz, OPAxHCM- — 1630 — µVRMS

DIS=0

RESSEL=7, 0.1 Hz<f<1 MHz, OPAxHCM- — 2590 — µVRMS

DIS=1

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Note:
1. Measured with 70 pF load capacitance, 25 ºC, and 3 V, using a 100 mV p-p amplitude on the input signal.
2. Simulated with 70 pF load capacitance, 25 ºC, and 3 V, using a 1 mV p-p amplitude on the input signal.

Figure 4.32. OPAMP Common Mode Rejection Ratio

Figure 4.33. OPAMP Positive Power Supply Rejection Ratio

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 EFM32LG Data Sheet
Electrical Characteristics

Figure 4.34. OPAMP Negative Power Supply Rejection Ratio

Figure 4.35. OPAMP Voltage Noise Spectral Density(Unity Gain) Vout=1V

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 EFM32LG Data Sheet
Electrical Characteristics

Figure 4.36. OPAMP Voltage Noise Spectral Density(Non-Unity Gain)

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 EFM32LG Data Sheet
Electrical Characteristics

4.14 Analog Comparator (ACMP)

Table 4.18. ACMP

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range VACMPIN 0 — VDD V

Input bias current I ACMPBIASIN VSS < VIN < VDD -40 — 40 nA

Input offset current IACMPOFFSETIN VSS < VIN < VDD -40 — 40 nA

ACMP Common Mode voltage VACMPCM 0 — VDD V

range

Active current IACMP BIASPROG=0b0000, FULL- — 0.11 0.41 µA

BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register

BIASPROG=0b1111, FULL- — 2.871 151 µA

BIAS= 0 and HALFBIAS=0 in
ACMPn_CTRL register

BIASPROG=0b1111, FULL- — 1951 5201 µA

BIAS= 1 and HALFBIAS=0 in
ACMPn_CTRL register

BIASPROG=0b0100, FULL- — 0.81 2.21 µA

BIAS=0, HALFBIAS=1 in
ACMPn_CTRL register

BIASPROG=0b1111, FULL- — 2.71 8.11 µA

BIAS=0, HALFBIAS=1 in-
ACMPn_CTRL register

Current consumption of internal IACMPREF Internal voltage reference off. — 0 — µA

voltage reference Using external voltage refer-
ence

Internal voltage reference — 5 — µA

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Negative response time t RESPONSE_N BIASPROG=0b1111, FULL- — 353 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=0

BIASPROG=0b1111, FULL- — 547 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=1

BIASPROG=0b1111, FULL- — 578 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=2

BIASPROG=0b1111, FULL- — 627 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=3

BIASPROG=0b1111, FULL- — 670 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=4

BIASPROG=0b1111, FULL- — 741 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=5

BIASPROG=0b1111, FULL- — 811 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=6

BIASPROG=0b1111, FULL- — 926 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=7

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Negative response time t RESPONSE_N BIASPROG=0b0100, FULL- — 843 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=0

BIASPROG=0b0100, FULL- — 1499 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=1

BIASPROG=0b0100, FULL- — 1590 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=2

BIASPROG=0b0100, FULL- — 1746 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=3

BIASPROG=0b0100, FULL- — 1876 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=4

BIASPROG=0b0100, FULL- — 2104 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=5

BIASPROG=0b0100, FULL- — 2323 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=6

BIASPROG=0b0100, FULL- — 2691 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=7

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Positive response time t RESPONSE_P BIASPROG=0b1111, FULL- — 451 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=0

BIASPROG=0b1111, FULL- — 643 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=1

BIASPROG=0b1111, FULL- — 679 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=2

BIASPROG=0b1111, FULL- — 725 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=3

BIASPROG=0b1111, FULL- — 761 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=4

BIASPROG=0b1111, FULL- — 826 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=5

BIASPROG=0b1111, FULL- — 909 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=6

BIASPROG=0b1111, FULL- — 1021 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=7

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Positive response time t RESPONSE_P BIASPROG=0b0100, FULL- — 1014 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=0

BIASPROG=0b0100, FULL- — 1671 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=1

BIASPROG=0b0100, FULL- — 1786 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=2

BIASPROG=0b0100, FULL- — 1933 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=3

BIASPROG=0b0100, FULL- — 2046 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=4

BIASPROG=0b0100, FULL- — 2262 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=5

BIASPROG=0b0100, FULL- — 2531 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=6

BIASPROG=0b0100, FULL- — 2907 — ns

BIAS=0, HALFBIAS=1, Over-
drive = 100 mV, LPREF=0,
HYSTSEL=7

Offset voltage VACMPOFFSET BIASPROG= 0b1010, FULL- -12 0 12 mV

BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register

BIASPROG= 0b0100, FULL- -14.4 0.4 14.8 mV

BIAS=0, HALFBIAS=1, and
LPREF=0 in ACMPn_CTRL
register

BIASPROG= 0b1111, FULL- -13.3 0.3 13.2 mV

BIAS=0, HALFBIAS=1, and
LPREF=0 in ACMPn_CTRL
register

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Negative hysteresis VACMPHYST_N BIASPROG=0b1111, FULL- -0.3 1.2 4.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=0

BIASPROG=0b1111, FULL- -18.0 -12.2 -4.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=1

BIASPROG=0b1111, FULL- -25.0 -17.6 -9.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=2

BIASPROG=0b1111, FULL- -33.0 -22.8 -13.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=3

BIASPROG=0b1111, FULL- -40.0 -27.8 -16.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=4

BIASPROG=0b1111, FULL- -46.0 -33.4 -21.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=5

BIASPROG=0b1111, FULL- -56.0 -39.9 -25.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=6

BIASPROG=0b1111, FULL- -65.0 -46.4 -29.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=7

Positive hysteresis VACMPHYST_P BIASPROG=0b1111, FULL- -0.3 1.2 4.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=0

BIASPROG=0b1111, FULL- 4.0 12.2 21.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=1

BIASPROG=0b1111, FULL- 9.0 17.1 25.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=2

BIASPROG=0b1111, FULL- 13.0 22.3 33.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=3

BIASPROG=0b1111, FULL- 17.0 28.2 42.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=4

BIASPROG=0b1111, FULL- 20.0 34.0 49.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=5

BIASPROG=0b1111, FULL- 25.0 39.8 58.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=6

BIASPROG=0b1111, FULL- 29.4 46.4 68.0 mV

BIAS=0, HALF-
BIAS=1,LPREF=0, HYSTSEL=7

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Capacitive Sense Internal Re- RCSRES CSRESSEL=0b00 in — 39 — kΩ

sistance ACMPn_INPUTSEL

CSRESSEL=0b01 in — 71 — kΩ
ACMPn_INPUTSEL

CSRESSEL=0b10 in — 104 — kΩ
ACMPn_INPUTSEL

CSRESSEL=0b11 in — 136 — kΩ
ACMPn_INPUTSEL

Startup time tACMPSTART — — 10 µs

VDD_SCALED input accuracy V VDDSCALED VDD_SCALED=9,BIA- — -10.8 — mV

SPROG=0b1111, FULLBIAS=0,
HALFBIAS=1, HYSTSEL=0,
LPREF=0

VDD_SCALED=9,BIA- — 1.3 — mV
SPROG=0b0000, FULLBIAS=0,
HALFBIAS=1, HYSTSEL=0,
LPREF=1

Note:
1. Reference current not included.

The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in in the following
equation. IACMPREF is zero if an external voltage reference is used.

I ACMPTOTAL = I ACMP + I ACMPREF

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 EFM32LG Data Sheet
Electrical Characteristics

Current Consumption, HYSTSEL = 4 Response Time

2.5 4.5
HYSTSEL=0.0
4.0 HYSTSEL=2.0
HYSTSEL=4.0
2.0 HYSTSEL=6.0
3.5

3.0

Response Time [us]

1.5
Current [uA]

2.5

2.0
1.0
1.5

1.0
0.5

0.5

0.0 0.0
0 4 8 12 0 2 4 6 8 10 12 14
ACMP_CTRL_BIASPROG ACMP_CTRL_BIASPROG

Hysteresis
100
BIASPROG=0.0
BIASPROG=4.0
BIASPROG=8.0
80 BIASPROG=12.0
Hysteresis [mV]

60

40

20

0
0 1 2 3 4 5 6 7
ACMP_CTRL_HYSTSEL

Figure 4.37. ACMP Characteristics, Vdd = 3 V, Temp = 25 °C, FULLBIAS = 0, HALFBIAS = 1

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 EFM32LG Data Sheet
Electrical Characteristics

4.15 Voltage Comparator (VCMP)

Table 4.19. VCMP

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range VVCMPIN — VDD — V

VCMP Common Mode voltage VVCMPCM — VDD — V

range

Active current IVCMP BIASPROG=0b0000 and HALF- — 0.31 0.61 µA

BIAS=1 in VCMPn_CTRL regis-
ter

BIASPROG=0b1111 and HALF- — 221 351 µA

BIAS=0 in VCMPn_CTRL regis-
ter. LPREF=0.

Startup time reference genera- tVCMPREF NORMAL — 10 — µs

tor

Offset voltage VVCMPOFFSET Single-ended — 10 — mV

Differential — 10 — mV

Negative hysteresis VVCMPHYST_N BIASPROG=0b0000, HALF- -46.6 -15.6 11.4 mV

BIAS=1, LPREF=1

Positive hysteresis VVCMPHYST_P BIASPROG=0b0000, HALF- -7.5 23.4 46.6 mV

BIAS=1, LPREF=1

Hysteresis delta VVCMPHYST_DELTA BIASPROG=0b0000, HALF- 4.2 35.2 70.0 mV

BIAS=1, LPREF=1

Startup time tVCMPSTART — — 10 µs

Negative response time tRESPONSE_N BIASPROG=0b0000, HALF- — 372.3 — µs

BIAS=1, LPREF=1, HYS-
TSEL=0

Positive response time t RESPONSE_P BIASPROG=0b0000, HALF- — 865.7 — µs

BIAS=1, LPREF=1, HYS-
TSEL=0

Note:
1. Includes required contribution from the voltage reference.

The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following
equation:

V DD Trigger Level = 1.667V + 0.034 × TRIGLEVEL

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 EFM32LG Data Sheet
Electrical Characteristics

4.16 EBI

WRSETUP WRSTRB WRHOLD

(0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...)

EBI_BL[N-1:0] EBI_BL Z

tOSU_WEn tOH_WEn

EBI_A[N-1:0] EBI_A Z

tOSU_WEn tOH_WEn

EBI_AD[15:0] DATA[15:0] Z

tOSU_WEn tOH_WEn

EBI_CSn

tOSU_WEn tOH_WEn
tWIDTH_WEn
EBI_WEn

Figure 4.38. EBI Write Enable Timing

Table 4.20. EBI Write Enable Timing

Parameter Symbol Min Typ Max Unit

Output hold time, from trailing EBI_WEn/EBI_NAND- tOH_WEn 1 2 3 4 -6.00 + (WRHOLD × tHFCORECLK) — — ns
WEn edge to EBI_AD, EBI_A, EBI_CSn, EBI_BLn
invalid

Output setup time, from EBI_AD, EBI_A, EBI_CSn, tOSU_WEn 1 2 3 4 5 -14.00 + (WRSETUP × tHFCORECLK) — — ns
EBI_BLn valid to leading EBI_WEn/EBI_NANDWEn
edge

EBI_WEn/EBI_NANDWEn pulse width tWIDTH_WEn 1 2 3 4 -7.00 + ((WRSTRB + 1) × tHFCORECLK) — — ns

5

Note:
1. Applies for all addressing modes (figure only shows D16 addressing mode)
2. Applies for both EBI_WEn and EBI_NANWEn (figure only shows EBI_WEn)
3. Applies for all polarities (figure only shows active low signals)
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge of
EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length of
tOSU_WEn by 1/2 × tHFCLKNODIV.

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 EFM32LG Data Sheet
Electrical Characteristics

ADDRSETUP ADDRHOLD WRSETUP WRSTRB WRHOLD

(1, 2, 3, ...) (0, 1, 2, ...) (0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...)

EBI_AD[15:0] ADDR[16:1] DATA[15:0] Z

tWIDTH_ALEn
EBI_ALE
tOSU_ALEn tWIDTH_ALEn

EBI_CSn

EBI_WEn

Figure 4.39. EBI Address Latch Enable Related Output Timing

Table 4.21. EBI Address Latch Enable Related Output Timing

Parameter Symbol Min Typ Max Unit

Output hold time, from trailing tOH_ALEn 1 2 3 4 -6.00 + (ADDRHOLD5 × tHFCORECLK) — — ns

EBI_ALE edge to EBI_AD in-
valid

Output setup time, from tOSU_ALEn 1 2 4 -13.00 + (0 × tHFCORECLK) — — ns

EBI_AD valid to leading
EBI_ALE edge

EBI_ALEn pulse width tWIDTH_ALEn 1 2 3 4 -7.00 + ((ADDRSETUP + 1) × tHFCORECLK) — — ns

Note:
1. Applies to addressing modes D8A24ALE and D16A16ALE (figure only shows D16A16ALE)
2. Applies for all polarities (figure only shows active low signals)
3. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge of
EBI_ALE can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length of
tOH_ALEn by tHFCORECLK - 1/2 × tHFCLKNODIV.
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5. Figure only shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state
instead of via the ADDRHOLD state.

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 EFM32LG Data Sheet
Electrical Characteristics

RDSETUP RDSTRB RDHOLD

(0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...)

EBI_BL[1:0] EBI_BL Z

tSU_REn tH_REn

EBI_A[27:0] EBI_A Z

tSU_REn tH_REn

EBI_AD[15:8] ADDR[7:0] Z

tSU_REn tH_REn

EBI_CSn

tSU_REn tH_REn

EBI_AD[7:0] Z DATA[7:0] Z

tWIDTH_REn
EBI_REn

Figure 4.40. EBI Read Enable Related Output Timing

Table 4.22. EBI Read Enable Related Output Timing

Parameter Symbol Min Typ Max Unit

Output hold time, from trailing tOH_REn 1 2 3 4 -10.00 + (RDHOLD × tHFCORECLK) — — ns

EBI_REn/EBI_NANDREn edge to
EBI_AD, EBI_A, EBI_CSn,
EBI_BLn invalid

Output setup time, from EBI_AD, tOSU_REn 1 2 3 4 5 -10.00 + (RDSETUP × tHFCORECLK) — — ns

EBI_A, EBI_CSn, EBI_BLn valid
to leading EBI_REn/
EBI_NANDREn edge

EBI_REn pulse width tWIDTH_REn 1 2 3 4 5 6 -9.00 + ((RDSTRB + 1) × tHFCORECLK) — — ns

Note:
1. Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing
modes D8A24ALE and D16A16ALE)
2. Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3. Applies for all polarities (figure only shows active low signals)
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5. The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge of
EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length of
tOSU_REn by 1/2 × tHFCLKNODIV.
6. When page mode is used, RDSTRB is replaced by RDPA for page hits.

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Electrical Characteristics

RDSETUP RDSTRB RDHOLD

(0, 1, 2, ...) (1, 2, 3, ...) (0, 1, 2, ...)

EBI_A[N-1:0] ADDR[N:1] Z

EBI_AD[15:0] Z DATA[15:0] Z

EBI_CSn

tSU_REn
EBI_REn
tH_REn

Figure 4.41. EBI Read Enable Related Timing Requirements

Table 4.23. EBI Read Enable Related Timing Requirements

Parameter Symbol Min Typ Max Unit

Setup time, from EBI_AD valid to tSU_REn 1 2 3 4 37 — — ns

trailing EBI_REn edge

Hold time, from trailing EBI_REn tH_REn 1 2 3 4 -1 — — ns

edge to EBI_AD invalid

Note:
1. Applies for all addressing modes (figure only shows D16A8).
2. Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3. Applies for all polarities (figure only shows active low signals)
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)

RDSETUP RDSTRB SYNC RDHOLD

(0, 1, 2, ...) (1, 2, 3, ...) (3) (0, 1, 2, ...)

EBI_RDY

EBI_AD[15:0] Z DATA[15:0]

EBI_CSn

tSU_ARDY
EBI_REn
tH_ARDY

Figure 4.42. EBI Ready/Wait Related Timing Requirements

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Electrical Characteristics

Table 4.24. EBI Ready/Wait Related Timing Requirements

Parameter Symbol Min Typ Max Unit

Setup time, from EBI_ARDY valid tSU_ARDY 1 2 3 4 37 + (3 × tHFCORECLK) — — ns

to trailing EBI_REn, EBI_WEn
edge

Hold time, from trailing EBI_REn, tH_ARDY 1 2 3 4 -1 + (3 × tHFCORECLK) — — ns

EBI_WEn edge to EBI_ARDY in-
valid

Note:
1. Applies for all addressing modes (figure only shows D16A8.)
2. Applies for EBI_REn, EBI_WEn (figure only shows EBI_REn)
3. Applies for all polarities (figure only shows active low signals)
4. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)

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 EFM32LG Data Sheet
Electrical Characteristics

4.17 LCD

Table 4.25. LCD

Parameter Symbol Test Condition Min Typ Max Unit

Frame rate fLCDFR 30 — 200 Hz

Number of segments supported NUMSEG — 36×8 — seg

LCD supply voltage range VLCD Internal boost circuit enabled 2.0 — 3.8 V

Steady state current consumption. ILCD Display disconnected, static — 250 — nA

mode, framerate 32 Hz, all
segments on.

Display disconnected, quad- — 550 — nA

ruplex mode, framerate 32
Hz, all segments on, bias
mode to ONETHIRD in
LCD_DISPCTRL register.

Steady state Current contribution ILCDBOOST Internal voltage boost off — 0 — µA

of internal boost.
Internal voltage boost on, — 8.4 — µA
boosting from 2.2 V to 3.0 V.

Boost Voltage VBOOST VBLEV of LCD_DISPCTRL — 3.02 — V

register to LEVEL0

VBLEV of LCD_DISPCTRL — 3.15 — V

register to LEVEL1

VBLEV of LCD_DISPCTRL — 3.28 — V

register to LEVEL2

VBLEV of LCD_DISPCTRL — 3.41 — V

register to LEVEL3

VBLEV of LCD_DISPCTRL — 3.54 — V

register to LEVEL4

VBLEV of LCD_DISPCTRL — 3.67 — V

register to LEVEL5

VBLEV of LCD_DISPCTRL — 3.73 — V

register to LEVEL6

VBLEV of LCD_DISPCTRL — 3.74 — V

register to LEVEL7

The total LCD current is given by the following equation. ILCDBOOST is zero if internal boost is off.

I LCDTOTAL = I LCD + I LCDBOOST

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 EFM32LG Data Sheet
Electrical Characteristics

4.18 I2C

Table 4.26. I2C Standard-mode (Sm)

Parameter Symbol Min Typ Max Unit

SCL clock frequency fSCL 0 — 1001 kHz

SCL clock low time tLOW 4.7 — — µs

SCL clock high time tHIGH 4.0 — — µs

SDA set-up time tSU,DAT 250 — — ns

SDA hold time tHD,DAT 8 — 34502,3 ns

Repeated START condition set-up time tSU,STA 4.7 — — µs

(Repeated) START condition hold time tHD,STA 4.0 — — µs

STOP condition set-up time tSU,STO 4.0 — — µs

Bus free time between a STOP and a START condition tBUF 4.7 — — µs

Note:
1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32LG Reference Manual.
2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).

Table 4.27. I2C Fast-mode (Fm)

Parameter Symbol Min Typ Max Unit

SCL clock frequency fSCL 0 4001 kHz

SCL clock low time tLOW 1.3 µs

SCL clock high time tHIGH 0.6 µs

SDA set-up time tSU,DAT 100 ns

SDA hold time tHD,DAT 8 9002,3 ns

Repeated START condition set-up time tSU,STA 0.6 µs

(Repeated) START condition hold time tHD,STA 0.6 µs

STOP condition set-up time tSU,STO 0.6 µs

Bus free time between a STOP and a START condition tBUF 1.3 µs

Note:
1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32LG Reference Manual.
2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).

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Electrical Characteristics

Table 4.28. I2C Fast-mode Plus (Fm+)

Parameter Symbol Min Typ Max Unit

SCL clock frequency fSCL 0 10001 kHz

SCL clock low time tLOW 0.5 µs

SCL clock high time tHIGH 0.26 µs

SDA set-up time tSU,DAT 50 ns

SDA hold time tHD,DAT 8 ns

Repeated START condition set-up time tSU,STA 0.26 µs

(Repeated) START condition hold time tHD,STA 0.26 µs

STOP condition set-up time tSU,STO 0.26 µs

Bus free time between a STOP and a START condition tBUF 0.5 µs

Note:
1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32LG Reference Manual.

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Electrical Characteristics

4.19 USART SPI

CS tCS_MO
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1

MOSI
tSU_MI tH_MI

MISO

Figure 4.43. SPI Main Timing

Table 4.29. SPI Main Timing

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period tSCLK1 2 2 × tHFPERCLK — — ns

CS to MOSI tCS_MO 1 2 -2.00 — 2.00 ns

SCLK to MOSI tSCLK_MO 1 2 -1.00 — 3.00 ns

MISO setup time tSU_MI 1 2 IOVDD = 3.0 V 36.00 — — ns

MISO hold time tH_MI 1 2 -6.00 — — ns

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)

Table 4.30. SPI Main Timing with SSSEARLY and SMSDELAY

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period tSCLK1 2 2 × tHFPERCLK — — ns

CS to MOSI tCS_MO 1 2 -2.00 — 2.00 ns

SCLK to MOSI tSCLK_MO 1 2 -1.00 — 3.00 ns

MISO setup time tSU_MI 1 2 IOVDD = 3.0 V -32.00 — — ns

MISO hold time tH_MI 1 2 63.00 — — ns

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)

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 EFM32LG Data Sheet
Electrical Characteristics

CS tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI tSCLK_LO
SCLK
CLKPOL = 1 tSU_MO
tSCLK
tH_MO
MOSI
tSCLK_MI

MISO

Figure 4.44. SPI Secondary Timing

Table 4.31. SPI Secondary Timing

Parameter Symbol Min Typ Max Unit

SCKL period tSCLK_sl1 2 6 × tHFPERCLK — — ns

SCLK high period tSCLK_hi 1 2 3 × tHFPERCLK — — ns

SCLK low period tSCLK_lo 1 2 3 × tHFPERCLK — — ns

CS active to MISO tCS_ACT_MI 1 2 5.00 — 35.00 ns

CS disable to MISO high-im- tCS_DIS_MI 1 2 5.00 — 35.00 ns

pedance

MOSI setup time tSU_MO 1 2 5.00 — — ns

MOSI hold time tH_MO 1 2 2 + 2 × tHFPERCLK — — ns

SCLK to MISO tSCLK_MI 1 2 7 + tHFPERCLK — 42 + 2 × tHFPERCLK ns

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)

Table 4.32. SPI Secondary Timing with SSSEARLY and SMSDELAY

Parameter Symbol Min Typ Max Unit

SCKL period tSCLK_sl1 2 6 × tHFPERCLK — — ns

SCLK high period tSCLK_hi 1 2 3 × tHFPERCLK — — ns

SCLK low period tSCLK_lo 1 2 3 × tHFPERCLK — — ns

CS active to MISO tCS_ACT_MI 1 2 5.00 — 35.00 ns

CS disable to MISO tCS_DIS_MI 1 2 5.00 — 35.00 ns

MOSI setup time tSU_MO 1 2 5.00 — — ns

MOSI hold time tH_MO 1 2 2 + 2 × tHFPERCLK — — ns

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 EFM32LG Data Sheet
Electrical Characteristics

Parameter Symbol Min Typ Max Unit

SCLK to MISO tSCLK_MI 1 2 -264 + tHFPERCLK — -234 + 2 × tHFPERCLK ns

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)

4.20 Digital Peripherals

Table 4.33. Digital Peripherals

Parameter Symbol Test Condition Min Typ Max Unit

USART current IUSART USART idle current, clock enabled — 4.0 — µA/MHz

UART current IUART UART idle current, clock enabled — 3.8 — µA/MHz

LEUART current ILEUART LEUART idle current, clock enabled — 194.0 — nA

I2C current II2C I2C idle current, clock enabled — 7.6 — µA/MHz

TIMER current ITIMER TIMER_0 idle current, clock enabled — 6.5 — µA/MHz

LETIMER current ILETIMER LETIMER idle current, clock enabled — 85.8 — nA

PCNT current IPCNT PCNT idle current, clock enabled — 91.4 — nA

RTC current IRTC RTC idle current, clock enabled — 54.6 — nA

LCD current ILCD LCD idle current, clock enabled — 72.7 — nA

AES current IAES AES idle current, clock enabled — 1.8 — µA/MHz

GPIO current IGPIO GPIO idle current, clock enabled — 3.4 — µA/MHz

EBI current IEBI EBI idle current, clock enabled — 6.5 — µA/MHz

PRS current IPRS PRS idle current — 3.9 — µA/MHz

DMA current IDMA Clock enable — 10.9 — µA/MHz

LE Peripheral Interface Clock ILFCLK Using LFXO, LFA clock tree — 12.2 — µA/MHz
current
Using LFXO, LFB clock tree — 4.3 — µA/MHz

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 EFM32LG Data Sheet
Pin Definitions

5. Pin Definitions

Note: Refer to the application note, AN0002.0: EFM32 and EZR32 Wireless MCU Series 0 Hardware Design Considerations for guide-
lines on designing Printed Circuit Boards (PCBs) for the EFM32LG.

5.1 EFM32LG230 (QFN64)

5.1.1 Pinout

The EFM32LG230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.1. EFM32LG230 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.1. Device Pinout

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

0 VSS Ground.

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

ACMP0_CH0
TIM0_CC1 #4 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
9 PC0 DAC0_OUT0ALT #0/
PCNT0_S0IN #2 I2C0_SDA #4 #0
OPAMP_OUT0ALT

ACMP0_CH1
TIM0_CC2 #4 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
10 PC1 DAC0_OUT0ALT #1/
PCNT0_S1IN #2 I2C0_SCL #4 #0
OPAMP_OUT0ALT

ACMP0_CH2
11 PC2 DAC0_OUT0ALT #2/ TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
OPAMP_OUT0ALT

ACMP0_CH3
12 PC3 DAC0_OUT0ALT #3/ TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
OPAMP_OUT0ALT

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA8 TIM2_CC0 #0

18 PA9 TIM2_CC1 #0

19 PA10 TIM2_CC2 #0

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

DAC0_OUT1 /
22 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0

ACMP1_CH4
CMU_CLK0 #1
45 PC12 DAC0_OUT1ALT #0/
LES_CH12 #0
OPAMP_OUT1ALT

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

TIM0_CDTI0 #1/3
ACMP1_CH5
TIM1_CC0 #0
46 PC13 DAC0_OUT1ALT #1/ LES_CH13 #0
TIM1_CC2 #4
OPAMP_OUT1ALT
PCNT0_S0IN #0

ACMP1_CH6 TIM0_CDTI1 #1/3

47 PC14 DAC0_OUT1ALT #2/ TIM1_CC1 #0 US0_CS #3 LES_CH14 #0
OPAMP_OUT1ALT PCNT0_S1IN #0

ACMP1_CH7
TIM0_CDTI2 #1/3 LES_CH15 #0
48 PC15 DAC0_OUT1ALT #3/ US0_CLK #3
TIM1_CC2 #0 DBG_SWO #1
OPAMP_OUT1ALT

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
51 PF2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

PRS_CH0 #1 ETM_TD3
52 PF3 TIM0_CDTI0 #2/5
#1

53 PF4 TIM0_CDTI1 #2/5 PRS_CH1 #1

54 PF5 TIM0_CDTI2 #2/5 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 PE8 PCNT2_S0IN #1 PRS_CH3 #1

57 PE9 PCNT2_S1IN #1

58 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
59 PE11 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

60 PE12 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
61 PE13 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

62 PE14 TIM3_CC0 #0 LEU0_TX #2

63 PE15 TIM3_CC1 #0 LEU0_RX #2

64 PA15 TIM3_CC2 #0

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Pin Definitions

5.1.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.2. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2.

US0_CLK PE12 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 USART2 clock input / output.

US2_CS PC5 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

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 EFM32LG Data Sheet
Pin Definitions

5.1.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG230 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.3. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 — — — — PA10 PA9 PA8 — PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PA12 PB11 — — PB8 PB7 — — — — — — —

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 — — — — — — — —

Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0

5.1.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG230 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.2. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.2 EFM32LG232 (TQFP64)

5.2.1 Pinout

The EFM32LG232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.3. EFM32LG232 Pinout (top view, not to scale)

Table 5.4. Device Pinout

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 TIM0_CC2 #0/1
ETM_TD0 #3

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LES_ALTEX2 #0
4 PA3 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

7 IOVDD_0 Digital IO power supply 0.

8 VSS Ground.

ACMP0_CH0
TIM0_CC1 #4 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
9 PC0 DAC0_OUT0ALT #0/
PCNT0_S0IN #2 I2C0_SDA #4 #0
OPAMP_OUT0ALT

ACMP0_CH1
TIM0_CC2 #4 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
10 PC1 DAC0_OUT0ALT #1/
PCNT0_S1IN #2 I2C0_SCL #4 #0
OPAMP_OUT0ALT

ACMP0_CH2
11 PC2 DAC0_OUT0ALT #2/ TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
OPAMP_OUT0ALT

ACMP0_CH3
12 PC3 DAC0_OUT0ALT #3/ TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
OPAMP_OUT0ALT

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA8 TIM2_CC0 #0

18 PA9 TIM2_CC1 #0

19 PA10 TIM2_CC2 #0

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

22 VSS Ground.

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0

ACMP1_CH4
CMU_CLK0 #1
45 PC12 DAC0_OUT1ALT #0/
LES_CH12 #0
OPAMP_OUT1ALT

TIM0_CDTI0 #1/3
ACMP1_CH5
TIM1_CC0 #0
46 PC13 DAC0_OUT1ALT #1/ LES_CH13 #0
TIM1_CC2 #4
OPAMP_OUT1ALT
PCNT0_S0IN #0

ACMP1_CH6 TIM0_CDTI1 #1/3

47 PC14 DAC0_OUT1ALT #2/ TIM1_CC1 #0 US0_CS #3 LES_CH14 #0
OPAMP_OUT1ALT PCNT0_S1IN #0

ACMP1_CH7
TIM0_CDTI2 #1/3 LES_CH15 #0
48 PC15 DAC0_OUT1ALT #3/ US0_CLK #3
TIM1_CC2 #0 DBG_SWO #1
OPAMP_OUT1ALT

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
51 PF2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

PRS_CH0 #1 ETM_TD3
52 PF3 TIM0_CDTI0 #2/5
#1

53 PF4 TIM0_CDTI1 #2/5 PRS_CH1 #1

54 PF5 TIM0_CDTI2 #2/5 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 VSS Ground.

57 PE8 PCNT2_S0IN #1 PRS_CH3 #1

58 PE9 PCNT2_S1IN #1

59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
60 PE11 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

61 PE12 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
62 PE13 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

63 PE14 TIM3_CC0 #0 LEU0_TX #2

64 PE15 TIM3_CC1 #0 LEU0_RX #2

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 EFM32LG Data Sheet
Pin Definitions

5.2.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.5. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 I2C1 Serial Clock Line input / output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

I2C1_SDA PC4 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

US0_CLK PE12 PC9 PC15 PB13 PB13 USART0 clock input / output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

US0_CS PE13 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 USART2 clock input / output.

US2_CS PC5 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.2.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG232 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.6. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A — — — — — PA10 PA9 PA8 — — PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 — PB11 — — PB8 PB7 — — — — — — —

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 — — — — — — — —

Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.2.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG232 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.4. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.3 EFM32LG280 (LQFP100)

5.3.1 Pinout

The EFM32LG280 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.5. EFM32LG280 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.7. Device Pinout

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LEU0_RX #4 PRS_CH0 #0
1 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

9 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2

10 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2

11 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2

12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

14 PB5 EBI_A21 #0/1/2 US2_CLK #1

15 PB6 EBI_A22 #0/1/2 US2_CS #1

16 VSS Ground.

17 IOVDD_1 Digital IO power supply 1.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
18 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
19 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
20 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
21 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
22 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
23 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

US0_TX #4
24 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

US0_RX #4
25 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

26 PA7 EBI_CSTFT #0/1/2

27 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0

28 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0

29 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0

30 PA11 EBI_HSNC #0/1/2

31 IOVDD_2 Digital IO power supply 2.

32 VSS Ground.

33 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1

34 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1

35 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
36 RESETn
during reset, and let the internal pull-up ensure that reset is released.

37 PB9 EBI_A03 #0/1/2 U1_TX #2

38 PB10 EBI_A04 #0/1/2 U1_RX #2

DAC0_OUT0 / TIM1_CC2 #3 LE-

39 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
40 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

41 AVDD_1 Analog power supply 1.

US0_CLK #4/5
42 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
43 PB14 HFXTAL_N
LEU0_RX #1

44 IOVDD_3 Digital IO power supply 3.

45 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT
46 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
47 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

48 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

ADC0_CH3
49 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
50 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

ADC0_CH5
51 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
52 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
53 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

54 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 LES_CH6 #0
55 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
56 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

57 VDD_DREG Power supply for on-chip voltage regulator.

58 VSS Ground.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
59 DECOUPLE
pin.

TIM3_CC0 #1 U0_TX #1
60 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
61 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

64 PE4 EBI_A11 #0/1/2 US0_CS #1

65 PE5 EBI_A12 #0/1/2 US0_CLK #1

66 PE6 EBI_A13 #0/1/2 US0_RX #1

67 PE7 EBI_A14 #0/1/2 US0_TX #1

68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
72 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
73 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
74 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
75 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
76 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
77 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
78 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

PRS_CH0 #1
79 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

80 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

81 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1

82 IOVDD_5 Digital IO power supply 5.

83 VSS Ground.

84 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

85 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

86 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

87 PF9 EBI_REn #1 ETM_TD0 #1

88 PD9 EBI_CS0 #0/1/2

89 PD10 EBI_CS1 #0/1/2

90 PD11 EBI_CS2 #0/1/2

91 PD12 EBI_CS3 #0/1/2

92 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

93 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1

94 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
95 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

US0_RX #3
CMU_CLK1 #2
96 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

US0_TX #3 LES_ALTEX7 #0
97 PE13 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

98 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

99 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

100 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.3.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.8. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3 PC14
in half duplex communication.

U1_RX PC13 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PC12 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.3.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG280 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.9. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

5.3.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG280 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.6. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.4 EFM32LG290 (BGA112)

5.4.1 Pinout

The EFM32LG290 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.7. EFM32LG290 Pinout (top view, not to scale)

Table 5.10. Device Pinout

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A4 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD10 EBI_CS1 #0/1/2

A6 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A7 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1

A8 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

A9 PE4 EBI_A11 #0/1/2 US0_CS #1

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
A10 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
A11 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

B1 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD11 EBI_CS2 #0/1/2

B6 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B7 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

PRS_CH0 #1
B8 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

B9 PE5 EBI_A12 #0/1/2 US0_CLK #1

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
B10 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
B11 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

CMU_CLK1 #0
C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 PD12 EBI_CS3 #0/1/2

C6 PF9 EBI_REn #1 ETM_TD0 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

C7 VSS Ground.

ACMP1_O #0
C8 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

C9 PE6 EBI_A13 #0/1/2 US0_RX #1

C10 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

C11 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

LES_ALTEX2 #0
D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

CMU_CLK0 #0
D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D4 VSS Ground.

D5 IOVDD_6 Digital IO power supply 6.

D6 PD9 EBI_CS0 #0/1/2

D7 IOVDD_5 Digital IO power supply 5.

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
D8 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

D9 PE7 EBI_A14 #0/1/2 US0_TX #1

D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

ETM_TCLK #3
E1 PA6 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E4 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
E8 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

TIM3_CC0 #1 U0_TX #1
E9 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
E10 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

E11 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

F1 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2

F2 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2

F3 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

F4 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

F8 VDD_DREG Power supply for on-chip voltage regulator.

F9 VSS_DREG Ground for on-chip voltage regulator.

F10 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
F11 DECOUPLE
pin.

G1 PB5 EBI_A21 #0/1/2 US2_CLK #1

G2 PB6 EBI_A22 #0/1/2 US2_CS #1

G3 VSS Ground.

G4 IOVDD_0 Digital IO power supply 0.

G8 IOVDD_4 Digital IO power supply 4.

G9 VSS Ground.

LEU1_TX #0 LES_CH6 #0
G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
H1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
H2 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

H3 PD14 I2C0_SDA #3

H4 PA7 EBI_CSTFT #0/1/2

H5 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0

H6 VSS Ground.

H7 IOVDD_3 Digital IO power supply 3.

H8 PD8 BU_VIN CMU_CLK1 #1

ADC0_CH5
H9 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
H10 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
H11 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
J1 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
J2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

J3 PD15 I2C0_SCL #3

J4 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1

J5 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0

J6 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0

J7 PB9 EBI_A03 #0/1/2 U1_TX #2

J8 PB10 EBI_A04 #0/1/2 U1_RX #2

J9 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

ADC0_CH3
J10 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
J11 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

US0_TX #4
K1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
K2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

K3 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1

K4 VSS Ground.

K5 PA11 EBI_HSNC #0/1/2

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
K6 RESETn
during reset, and let the internal pull-up ensure that reset is released.

K7 AVSS_1 Analog ground 1.

K8 AVDD_2 Analog power supply 2.

K9 AVDD_1 Analog power supply 1.

K10 AVSS_0 Analog ground 0.

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
K11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

US0_RX #4
L1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
L2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

L3 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1

L4 IOVDD_1 Digital IO power supply 1.

DAC0_OUT0 / TIM1_CC2 #3 LE-

L5 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

DAC0_OUT1 /
L6 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

L7 AVSS_2 Analog ground 2.

US0_CLK #4/5
L8 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
L9 PB14 HFXTAL_N
LEU0_RX #1

L10 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT
L11 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

5.4.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.11. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3 PC14
in half duplex communication.

U1_RX PC13 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PC12 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.4.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG290 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.12. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

5.4.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG290 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.8. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.5 EFM32LG295 (BGA120)

5.5.1 Pinout

The EFM32LG295 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.9. EFM32LG295 Pinout (top view, not to scale)

Table 5.13. Device Pinout

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A4 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD11 EBI_CS2 #0/1/2

A6 PD9 EBI_CS0 #0/1/2

A7 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A8 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1

A9 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

ACMP1_O #0
A10 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

A11 USB_VREGI Input to internal 3.3V USB regulator

A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator

A13 PF11 U1_RX #1

B1 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD12 EBI_CS3 #0/1/2

B6 PD10 EBI_CS1 #0/1/2

B7 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B8 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

PRS_CH0 #1
B9 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
B10 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

B11 PF12

B12 USB_VBUS USB 5.0 V VBUS input.

B13 PF10 U1_TX #1

CMU_CLK1 #0
C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 VSS Ground.

C6 IOVDD_0 Digital IO power supply 0.

C7 PF9 EBI_REn #1 ETM_TD0 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

C8 VSS Ground.

C9 IOVDD_1 Digital IO power supply 1.

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
C10 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

C11 PE4 EBI_A11 #0/1/2 US0_CS #1

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
C12 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
C13 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

LES_ALTEX2 #0
D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

CMU_CLK0 #0
D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D11 PE5 EBI_A12 #0/1/2 US0_CLK #1

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
D12 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
D13 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

ETM_TCLK #3
E1 PA6 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E11 PE6 EBI_A13 #0/1/2 US0_RX #1

E12 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

E13 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

F1 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2

F2 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2

F3 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2

F11 PE7 EBI_A14 #0/1/2 US0_TX #1

F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

G1 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

G2 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

G3 IOVDD_2 Digital IO power supply 2.

TIM3_CC0 #1 U0_TX #1
G11 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
G12 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

G13 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

H1 PB5 EBI_A21 #0/1/2 US2_CLK #1

H2 PB6 EBI_A22 #0/1/2 US2_CS #1

H3 VSS Ground.

H11 VDD_DREG Power supply for on-chip voltage regulator.

H12 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

LEU1_RX #0 LES_CH7 #0
H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

J1 PD14 I2C0_SDA #3

J2 PD15 I2C0_SCL #3

J3 VSS Ground.

J11 IOVDD_3 Digital IO power supply 3.

LEU1_TX #0 LES_CH6 #0
J12 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
J13 DECOUPLE
pin.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
K1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
K2 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

K3 IOVDD_4 Digital IO power supply 4.

K11 VSS Ground.

K12 VSS Ground.

K13 PD8 BU_VIN CMU_CLK1 #1

ACMP0_CH2
DAC0_OUT0ALT
L1 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
L2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

L3 PA7 EBI_CSTFT #0/1/2

L4 IOVDD_5 Digital IO power supply 5.

L5 VSS Ground.

L6 VSS Ground.

L7 IOVDD_6 Digital IO power supply 6.

L8 PB9 EBI_A03 #0/1/2 U1_TX #2

L9 PB10 EBI_A04 #0/1/2 U1_RX #2

ADC0_CH0
DAC0_OUT0ALT
L10 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
L11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

ADC0_CH4
L12 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
L13 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

US0_TX #4
M1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
M2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

M3 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0

M4 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0

M5 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1

M6 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
M7 RESETn
during reset, and let the internal pull-up ensure that reset is released.

M8 AVSS_1 Analog ground 1.

M9 AVDD_2 Analog power supply 2.

M10 AVDD_1 Analog power supply 1.

M11 AVSS_0 Analog ground 0.

ADC0_CH3
M12 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
M13 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

US0_RX #4
N1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
N2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

N3 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0

N4 PA11 EBI_HSNC #0/1/2

N5 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1

DAC0_OUT0 / TIM1_CC2 #3 LE-

N6 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
N7 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

N8 AVSS_2 Analog ground 2.

US0_CLK #4/5
N9 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
N10 PB14 HFXTAL_N
LEU0_RX #1

N11 AVDD_0 Analog power supply 0.

N12 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

ADC0_CH5
N13 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.5.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.14. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT / Digital to Analog Converter DAC0_OUT0ALT /

PC0 PC1 PC2 PC3 PD0
OPAMP_OUT0ALT OPAMP alternative output for channel 0.

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT / Digital to Analog Converter DAC0_OUT1ALT /

PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1ALT OPAMP alternative output for channel 1.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of re-
set, and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of re-
set, and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset,
and must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready

EBI_ARDY PF2 PF2 PF2
Control input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchro-

EBI_VSNC PA10 PA10 PA10
nization pin.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive

LEU0_TX PD4 PB13 PE14 PF0 PF2
input in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive

LEU1_TX PC6 PA5
input in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) neg-

LFXTAL_N PB8 ative pin. Also used as an optional external clock
input pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive in-

U0_TX PF6 PE0 PA3 PC14
put in half duplex communication.

U1_RX PC13 PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive in-

U1_TX PC12 PF10 PB9 PE2
put in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.5.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG295 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.15. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

5.5.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG295 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.10. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.6 EFM32LG330 (QFN64)

5.6.1 Pinout

The EFM32LG330 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.11. EFM32LG330 Pinout (top view, not to scale)

Table 5.16. Device Pinout

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

0 VSS Ground.

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

CMU_CLK0 #0
3 PA2 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

ACMP0_CH0
TIM0_CC1 #4 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
9 PC0 DAC0_OUT0ALT #0/
PCNT0_S0IN #2 I2C0_SDA #4 #0
OPAMP_OUT0ALT

ACMP0_CH1
TIM0_CC2 #4 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
10 PC1 DAC0_OUT0ALT #1/
PCNT0_S1IN #2 I2C0_SCL #4 #0
OPAMP_OUT0ALT

ACMP0_CH2
11 PC2 DAC0_OUT0ALT #2/ TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
OPAMP_OUT0ALT

ACMP0_CH3
12 PC3 DAC0_OUT0ALT #3/ TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
OPAMP_OUT0ALT

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA8 TIM2_CC0 #0

18 PA9 TIM2_CC1 #0

19 PA10 TIM2_CC2 #0

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
22 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

USB_DMPU #0
30 PD2 ADC0_CH2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0

45 USB_VREGI Input to internal 3.3V USB regulator

46 USB_VREGO Output and decoupling for internal 3.3V USB regulator

47 PF10 USB_DM

48 PF11 USB_DP

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ACMP1_O #0
51 PF2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

52 USB_VBUS USB 5.0 V VBUS input.

53 PF12 USB_ID

54 PF5 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 PE8 PCNT2_S0IN #1 PRS_CH3 #1

57 PE9 PCNT2_S1IN #1

58 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
59 PE11 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

60 PE12 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
61 PE13 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

62 PE14 TIM3_CC0 #0 LEU0_TX #2

63 PE15 TIM3_CC1 #0 LEU0_RX #2

64 PA15 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.6.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.17. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC2
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC3
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2.

US0_CLK PE12 PC9 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PC8 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 USART2 clock input / output.

US2_CS PC5 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

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 EFM32LG Data Sheet
Pin Definitions

5.6.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG330 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.18. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 — — — — PA10 PA9 PA8 — PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 — — PB8 PB7 — — — — — — —

Port C — — — — PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 — — — — — — — —

Port F — — — PF12 PF11 PF10 — — — — PF5 — — PF2 PF1 PF0

5.6.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG330 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.12. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.7 EFM32LG332 (TQFP64)

5.7.1 Pinout

The EFM32LG332 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.13. EFM32LG332 Pinout (top view, not to scale)

Table 5.19. Device Pinout

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 TIM0_CC2 #0/1
ETM_TD0 #3

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LES_ALTEX2 #0
4 PA3 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

7 IOVDD_0 Digital IO power supply 0.

8 VSS Ground.

ACMP0_CH0
TIM0_CC1 #4 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
9 PC0 DAC0_OUT0ALT #0/
PCNT0_S0IN #2 I2C0_SDA #4 #0
OPAMP_OUT0ALT

ACMP0_CH1
TIM0_CC2 #4 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
10 PC1 DAC0_OUT0ALT #1/
PCNT0_S1IN #2 I2C0_SCL #4 #0
OPAMP_OUT0ALT

ACMP0_CH2
11 PC2 DAC0_OUT0ALT #2/ TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
OPAMP_OUT0ALT

ACMP0_CH3
12 PC3 DAC0_OUT0ALT #3/ TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
OPAMP_OUT0ALT

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA8 TIM2_CC0 #0

18 PA9 TIM2_CC1 #0

19 PA10 TIM2_CC2 #0

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

22 VSS Ground.

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

USB_DMPU #0
30 PD2 ADC0_CH2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
42 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

43 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

44 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0

45 USB_VREGI Input to internal 3.3V USB regulator

46 USB_VREGO Output and decoupling for internal 3.3V USB regulator

47 PF10 USB_DM

48 PF11 USB_DP

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
51 PF2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

52 USB_VBUS USB 5.0 V VBUS input.

53 PF12 USB_ID

54 PF5 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 VSS Ground.

57 PE8 PCNT2_S0IN #1 PRS_CH3 #1

58 PE9 PCNT2_S1IN #1

59 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
60 PE11 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

61 PE12 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
62 PE13 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

63 PE14 TIM3_CC0 #0 LEU0_TX #2

64 PE15 TIM3_CC1 #0 LEU0_RX #2

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 EFM32LG Data Sheet
Pin Definitions

5.7.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.20. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PCNT0_S0IN PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC2
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC3
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

US0_CLK PE12 PC9 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PC8 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 USART2 clock input / output.

US2_CS PC5 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.7.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG332 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.21. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A - - - - - PA10 PA9 PA8 - - PA5 PA4 PA3 PA2 PA1 PA0

Port B - PB14 PB13 - PB11 - - PB8 PB7 - - - - - - -

Port C - - - - PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D - - - - - - - PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 - - - - - - - -

Port F - - - PF12 PF11 PF10 - - - - PF5 - - PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.7.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG332 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.14. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.8 EFM32LG360 (CSP81)

5.8.1 Pinout

The EFM32LG360 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.15. EFM32LG360 Pinout (top view, not to scale)

Table 5.22. Device Pinout

CSP81 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

A1 PF10 U1_TX #1 USB_DM

A2 PF11 U1_RX #1 USB_DP

ACMP1_O #0
A3 PF2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

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 EFM32LG Data Sheet
Pin Definitions

CSP81 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

A4 VSS Ground.

A5 IOVDD_5 Digital IO power supply 5.

A6 PE9 PCNT2_S1IN #1

LES_ALTEX5 #0
A7 PE11 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

A8 PE12 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

A9 PA15 TIM3_CC2 #0

B1 USB_VREGI Input to internal 3.3V USB regulator

B2 USB_VBUS USB 5.0 V VBUS input.

ACMP1_CH7
TIM0_CDTI2 #1/3 LES_CH15 #0
B3 PC15 DAC0_OUT1ALT #3/ US0_CLK #3 U0_RX #3
TIM1_CC2 #0 DBG_SWO #1
OPAMP_OUT1ALT

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

B4 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

B5 PF5 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

B6 PE8 PCNT2_S0IN #1 PRS_CH3 #1

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
B7 PE13 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

B8 PA0 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK0 #0
B9 PA2 TIM0_CC2 #0/1
ETM_TD0 #3

C1 USB_VREGO Output and decoupling for internal 3.3V USB regulator

TIM0_CDTI0 #1/3
ACMP1_CH5
TIM1_CC0 #0
C2 PC13 DAC0_OUT1ALT #1/ U1_RX #0 LES_CH13 #0
TIM1_CC2 #4
OPAMP_OUT1ALT
PCNT0_S0IN #0

ACMP1_CH6 TIM0_CDTI1 #1/3

C3 PC14 DAC0_OUT1ALT #2/ TIM1_CC1 #0 US0_CS #3 U0_TX #3 LES_CH14 #0
OPAMP_OUT1ALT PCNT0_S1IN #0

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

C4 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

C5 PF12 USB_ID

C6 PE10 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C7 PE14 TIM3_CC0 #0 LEU0_TX #2

CMU_CLK1 #0
C8 PA1 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LES_ALTEX2 #0
C9 PA3 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

D1 PC10 ACMP1_CH2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

D2 PC11 ACMP1_CH3 US0_TX #2 LES_CH11 #0

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 EFM32LG Data Sheet
Pin Definitions

CSP81 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ACMP1_CH4
CMU_CLK0 #1
D3 PC12 DAC0_OUT1ALT #0/ U1_TX #0
LES_CH12 #0
OPAMP_OUT1ALT

LES_CH9 #0
D4 PC9 ACMP1_CH1 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

D5 PC8 ACMP1_CH0 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_ALTEX3 #0
D6 PA4 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

LES_ALTEX4 #0
D7 PA5 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
D8 PA6 LEU1_RX #1
GPIO_EM4WU1

D9 IOVDD_0 Digital IO power supply 0.

E1 PE4 US0_CS #1

E2 PE5 US0_CLK #1

E3 PE3 BU_STAT U1_RX #3 ACMP1_O #1

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

E4 PC7 ACMP0_CH7
#2 #2

E5 PE15 TIM3_CC1 #0 LEU0_RX #2

E6 PB5 US2_CLK #1

E7 PB3 PCNT1_S0IN #1 US2_TX #1

E8 PB4 PCNT1_S1IN #1 US2_RX #1

E9 VSS Ground.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
F1 DECOUPLE
at this pin.

F2 PE2 BU_VOUT TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

F3 PC6 ACMP0_CH6
#2 ETM_TCLK #2

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
F4 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

ADC0_CH0
DAC0_OUT0ALT #4/
F5 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

F6 PA8 TIM2_CC0 #0

ACMP0_CH2
F7 PC2 DAC0_OUT0ALT #2/ TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
OPAMP_OUT0ALT

ACMP0_CH0
TIM0_CC1 #4 US0_TX #5 US1_TX #0 LES_CH0 #0 PRS_CH2
F8 PC0 DAC0_OUT0ALT #0/
PCNT0_S0IN #2 I2C0_SDA #4 #0
OPAMP_OUT0ALT

F9 PB6 US2_CS #1

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 EFM32LG Data Sheet
Pin Definitions

CSP81 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

G1 VDD_DREG Power supply for on-chip voltage regulator.

G2 VSS_DREG Ground for on-chip voltage regulator.

G3 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

G4 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

DAC0_OUT1 /
G5 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

DAC0_OUT0 / TIM1_CC2 #3 LE-

G6 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

G7 PA9 TIM2_CC1 #0

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
G8 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH1
TIM0_CC2 #4 US0_RX #5 US1_RX #0 LES_CH1 #0 PRS_CH3
G9 PC1 DAC0_OUT0ALT #1/
PCNT0_S1IN #2 I2C0_SCL #4 #0
OPAMP_OUT0ALT

H1 PD8 BU_VIN CMU_CLK1 #1

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
H2 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

USB_DMPU #0
H3 PD2 ADC0_CH2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

H4 VSS Ground.

H5 AVSS_0 Analog ground 0.

H6 AVDD_0 Analog power supply 0.

H7 PA10 TIM2_CC2 #0

ACMP0_CH5 /
LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL
H8 PC5 DAC0_N0 / LES_CH5 #0
PCNT1_S1IN #0 #0
PD6OPAMP_N0

ACMP0_CH3
H9 PC3 DAC0_OUT0ALT #3/ TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
OPAMP_OUT0ALT

ADC0_CH5
J1 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH1
TIM0_CC0 #3
J2 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

J3 IOVDD_3 Digital IO power supply 3.

US0_CS #4/5 LEU0_RX

J4 PB14 HFXTAL_N
#1

US0_CLK #4/5
J5 PB13 HFXTAL_P
LEU0_TX #1

J6 AVDD_1 Analog power supply 1.

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
J7 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

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 EFM32LG Data Sheet
Pin Definitions

CSP81 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

J8 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

US0_TX #4 US1_CLK
J9 PB7 LFXTAL_P TIM1_CC0 #3
#0

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 EFM32LG Data Sheet
Pin Definitions

5.8.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.23. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel

TIM0_CDTI0 PA3 PC13 PC13 PC2
0.

Timer 0 Complimentary Deat Time Insertion channel

TIM0_CDTI1 PA4 PC14 PC14 PC3
1.

Timer 0 Complimentary Deat Time Insertion channel

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
2.

TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PC8 Timer 2 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM2_CC1 PA9 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PA3 PC14
in half duplex communication.

U1_RX PC13 PF11 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PC12 PF10 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.8.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG360 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.24. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 - - - - PA10 PA9 PA8 - PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B - PB14 PB13 PB12 PB11 - - PB8 PB7 PB6 PB5 PB4 PB3 - - -

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D - - - - - - - PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 - - PE5 PE4 PE3 PE2 - -

Port F - - - PF12 PF11 PF10 - - - - PF5 - - PF2 PF1 PF0

5.8.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG360 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.16. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.9 EFM32LG380 (LQFP100)

5.9.1 Pinout

The EFM32LG380 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.17. EFM32LG380 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.25. Device Pinout

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LEU0_RX #4 PRS_CH0 #0
1 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

9 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2

10 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2

11 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2

12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

14 PB5 EBI_A21 #0/1/2 US2_CLK #1

15 PB6 EBI_A22 #0/1/2 US2_CS #1

16 VSS Ground.

17 IOVDD_1 Digital IO power supply 1.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
18 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
19 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
20 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
21 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
22 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
23 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

US0_TX #4
24 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

US0_RX #4
25 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

26 PA7 EBI_CSTFT #0/1/2

27 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0

28 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0

29 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0

30 PA11 EBI_HSNC #0/1/2

31 IOVDD_2 Digital IO power supply 2.

32 VSS Ground.

33 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1

34 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1

35 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
36 RESETn
during reset, and let the internal pull-up ensure that reset is released.

37 PB9 EBI_A03 #0/1/2 U1_TX #2

38 PB10 EBI_A04 #0/1/2 U1_RX #2

DAC0_OUT0 / TIM1_CC2 #3 LE-

39 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
40 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

41 AVDD_1 Analog power supply 1.

US0_CLK #4/5
42 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
43 PB14 HFXTAL_N
LEU0_RX #1

44 IOVDD_3 Digital IO power supply 3.

45 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT
46 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
47 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

USB_DMPU #0
48 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

ADC0_CH3
49 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
50 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

ADC0_CH5
51 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
52 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
53 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

54 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 LES_CH6 #0
55 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
56 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

57 VDD_DREG Power supply for on-chip voltage regulator.

58 VSS Ground.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
59 DECOUPLE
pin.

TIM3_CC0 #1 U0_TX #1
60 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
61 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

64 PE4 EBI_A11 #0/1/2 US0_CS #1

65 PE5 EBI_A12 #0/1/2 US0_CLK #1

66 PE6 EBI_A13 #0/1/2 US0_RX #1

67 PE7 EBI_A14 #0/1/2 US0_TX #1

68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

72 USB_VREGI Input to internal 3.3V USB regulator

73 USB_VREGO Output and decoupling for internal 3.3V USB regulator

74 PF10 U1_TX #1 USB_DM

75 PF11 U1_RX #1 USB_DP

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
76 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
77 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
78 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

79 USB_VBUS USB 5.0 V VBUS input.

80 PF12 USB_ID

81 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

82 IOVDD_5 Digital IO power supply 5.

83 VSS Ground.

84 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

85 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

86 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

87 PF9 EBI_REn #1 ETM_TD0 #1

88 PD9 EBI_CS0 #0/1/2

89 PD10 EBI_CS1 #0/1/2

90 PD11 EBI_CS2 #0/1/2

91 PD12 EBI_CS3 #0/1/2

92 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

93 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1

94 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
95 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3
CMU_CLK1 #2
96 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

US0_TX #3 LES_ALTEX7 #0
97 PE13 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

98 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

99 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

100 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.9.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.26. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF8 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC2
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC3
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3
in half duplex communication.

U1_RX PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PF10 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.9.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG380 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.27. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C — — — — PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 — — PF2 PF1 PF0

5.9.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG380 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.18. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.10 EFM32LG390 (BGA112)

5.10.1 Pinout

The EFM32LG390 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.19. EFM32LG390 Pinout (top view, not to scale)

Table 5.28. Device Pinout

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A4 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD10 EBI_CS1 #0/1/2

A6 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A7 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

A8 PF12 USB_ID

A9 PE4 EBI_A11 #0/1/2 US0_CS #1

A10 PF10 U1_TX #1 USB_DM

A11 PF11 U1_RX #1 USB_DP

B1 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD11 EBI_CS2 #0/1/2

B6 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B7 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

B8 USB_VBUS USB 5.0 V VBUS input.

B9 PE5 EBI_A12 #0/1/2 US0_CLK #1

B10 USB_VREGI Input to internal 3.3 V USB regulator

B11 USB_VREGO Output and decoupling for internal 3.3 V USB regulator

CMU_CLK1 #0
C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 PD12 EBI_CS3 #0/1/2

C6 PF9 EBI_REn #1 ETM_TD0 #1

C7 VSS Ground.

ACMP1_O #0
C8 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

C9 PE6 EBI_A13 #0/1/2 US0_RX #1

C10 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

C11 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

LES_ALTEX2 #0
D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

CMU_CLK0 #0
D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D4 VSS Ground.

D5 IOVDD_6 Digital IO power supply 6.

D6 PD9 EBI_CS0 #0/1/2

D7 IOVDD_5 Digital IO power supply 5.

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
D8 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

D9 PE7 EBI_A14 #0/1/2 US0_TX #1

D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

ETM_TCLK #3
E1 PA6 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E4 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
E8 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

TIM3_CC0 #1 U0_TX #1
E9 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
E10 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

E11 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

F1 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2

F2 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2

F3 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

F4 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

F8 VDD_DREG Power supply for on-chip voltage regulator.

F9 VSS_DREG Ground for on-chip voltage regulator.

F10 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
F11 DECOUPLE
pin.

G1 PB5 EBI_A21 #0/1/2 US2_CLK #1

G2 PB6 EBI_A22 #0/1/2 US2_CS #1

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

G3 VSS Ground.

G4 IOVDD_0 Digital IO power supply 0.

G8 IOVDD_4 Digital IO power supply 4.

G9 VSS Ground.

LEU1_TX #0 LES_CH6 #0
G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
H1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
H2 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

H3 PD14 I2C0_SDA #3

H4 PA7 EBI_CSTFT #0/1/2

H5 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0

H6 VSS Ground.

H7 IOVDD_3 Digital IO power supply 3.

H8 PD8 BU_VIN CMU_CLK1 #1

ADC0_CH5
H9 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
H10 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
H11 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
J1 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
J2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

J3 PD15 I2C0_SCL #3

J4 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1

J5 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0

J6 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0

J7 PB9 EBI_A03 #0/1/2 U1_TX #2

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

J8 PB10 EBI_A04 #0/1/2 U1_RX #2

USB_DMPU #0
J9 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

ADC0_CH3
J10 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
J11 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

US0_TX #4
K1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
K2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

K3 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1

K4 VSS Ground.

K5 PA11 EBI_HSNC #0/1/2

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
K6 RESETn
during reset, and let the internal pull-up ensure that reset is released.

K7 AVSS_1 Analog ground 1.

K8 AVDD_2 Analog power supply 2.

K9 AVDD_1 Analog power supply 1.

K10 AVSS_0 Analog ground 0.

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
K11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

US0_RX #4
L1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
L2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

L3 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1

L4 IOVDD_1 Digital IO power supply 1.

DAC0_OUT0 / TIM1_CC2 #3 LE-

L5 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
L6 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

L7 AVSS_2 Analog ground 2.

US0_CLK #4/5
L8 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
L9 PB14 HFXTAL_N
LEU0_RX #1

L10 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH0
DAC0_OUT0ALT
L11 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

5.10.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.29. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF8 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC2
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC3
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3
in half duplex communication.

U1_RX PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PF10 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.10.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG390 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.30. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C — — — — PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 — — PF2 PF1 PF0

5.10.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG390 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2
PD3 OUT2
-

PD6 + OUT1ALT
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.20. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.11 EFM32LG395 (BGA120)

5.11.1 Pinout

The EFM32LG395 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.21. EFM32LG395 Pinout (top view, not to scale)

Table 5.31. Device Pinout

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A4 PE9 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD11 EBI_CS2 #0/1/2

A6 PD9 EBI_CS0 #0/1/2

A7 PF7 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A8 PF5 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

A9 PF4 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

ACMP1_O #0
A10 PF2 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

A11 USB_VREGI Input to internal 3.3V USB regulator

A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator

A13 PF11 U1_RX #1 USB_DP

B1 PA15 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD12 EBI_CS3 #0/1/2

B6 PD10 EBI_CS1 #0/1/2

B7 PF8 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B8 PF6 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

PRS_CH0 #1
B9 PF3 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
B10 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

B11 PF12 USB_ID

B12 USB_VBUS USB 5.0 V VBUS input.

B13 PF10 U1_TX #1 USB_DM

CMU_CLK1 #0
C1 PA1 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 VSS Ground.

C6 IOVDD_0 Digital IO power supply 0.

C7 PF9 EBI_REn #1 ETM_TD0 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

C8 VSS Ground.

C9 IOVDD_1 Digital IO power supply 1.

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
C10 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

C11 PE4 EBI_A11 #0/1/2 US0_CS #1

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
C12 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
C13 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

LES_ALTEX2 #0
D1 PA3 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

CMU_CLK0 #0
D2 PA2 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D11 PE5 EBI_A12 #0/1/2 US0_CLK #1

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
D12 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
D13 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

ETM_TCLK #3
E1 PA6 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E11 PE6 EBI_A13 #0/1/2 US0_RX #1

E12 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

E13 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

F1 PB0 EBI_A16 #0/1/2 TIM1_CC0 #2

F2 PB1 EBI_A17 #0/1/2 TIM1_CC1 #2

F3 PB2 EBI_A18 #0/1/2 TIM1_CC2 #2

F11 PE7 EBI_A14 #0/1/2 US0_TX #1

F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

G1 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

G2 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

G3 IOVDD_2 Digital IO power supply 2.

TIM3_CC0 #1 U0_TX #1
G11 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
G12 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

G13 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

H1 PB5 EBI_A21 #0/1/2 US2_CLK #1

H2 PB6 EBI_A22 #0/1/2 US2_CS #1

H3 VSS Ground.

H11 VDD_DREG Power supply for on-chip voltage regulator.

H12 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

LEU1_RX #0 LES_CH7 #0
H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

J1 PD14 I2C0_SDA #3

J2 PD15 I2C0_SCL #3

J3 VSS Ground.

J11 IOVDD_3 Digital IO power supply 3.

LEU1_TX #0 LES_CH6 #0
J12 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
J13 DECOUPLE
pin.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
K1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
K2 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

K3 IOVDD_4 Digital IO power supply 4.

K11 VSS Ground.

K12 VSS Ground.

K13 PD8 BU_VIN CMU_CLK1 #1

ACMP0_CH2
DAC0_OUT0ALT
L1 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
L2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

L3 PA7 EBI_CSTFT #0/1/2

L4 IOVDD_5 Digital IO power supply 5.

L5 VSS Ground.

L6 VSS Ground.

L7 IOVDD_6 Digital IO power supply 6.

L8 PB9 EBI_A03 #0/1/2 U1_TX #2

L9 PB10 EBI_A04 #0/1/2 U1_RX #2

ADC0_CH0
DAC0_OUT0ALT
L10 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
L11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

ADC0_CH4
L12 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
L13 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

US0_TX #4
M1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
M2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

M3 PA8 EBI_DCLK #0/1/2 TIM2_CC0 #0

M4 PA10 EBI_VSNC #0/1/2 TIM2_CC2 #0

M5 PA13 EBI_A01 #0/1/2 TIM2_CC1 #1

M6 PA14 EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
M7 RESETn
during reset, and let the internal pull-up ensure that reset is released.

M8 AVSS_1 Analog ground 1.

M9 AVDD_2 Analog power supply 2.

M10 AVDD_1 Analog power supply 1.

M11 AVSS_0 Analog ground 0.

ADC0_CH3
M12 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
M13 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

US0_RX #4
N1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
N2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

N3 PA9 EBI_DTEN #0/1/2 TIM2_CC1 #0

N4 PA11 EBI_HSNC #0/1/2

N5 PA12 EBI_A00 #0/1/2 TIM2_CC0 #1

DAC0_OUT0 / TIM1_CC2 #3 LE-

N6 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
N7 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

N8 AVSS_2 Analog ground 2.

US0_CLK #4/5
N9 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
N10 PB14 HFXTAL_N
LEU0_RX #1

N11 AVDD_0 Analog power supply 0.

USB_DMPU #0
N12 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

ADC0_CH5
N13 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.11.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.32. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT / Digital to Analog Converter DAC0_OUT0ALT /

PC0 PC1 PC2 PC3 PD0
OPAMP_OUT0ALT OPAMP alternative output for channel 0.

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT / Digital to Analog Converter DAC0_OUT1ALT /

PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1ALT OPAMP alternative output for channel 1.

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of re-
set, and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of re-
set, and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset,
and must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready

EBI_ARDY PF2 PF2 PF2
Control input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchro-

EBI_VSNC PA10 PA10 PA10
nization pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LEUART0 Transmit output. Also used as receive

LEU0_TX PD4 PB13 PE14 PF0 PF2
input in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive

LEU1_TX PC6 PA5
input in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) neg-

LFXTAL_N PB8 ative pin. Also used as an optional external clock
input pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive in-

U0_TX PF6 PE0 PA3 PC14
put in half duplex communication.

U1_RX PC13 PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive in-

U1_TX PC12 PF10 PB9 PE2
put in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_
USB_VBUS USB 5 V VBUS input.
VBUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_
USB_VREGI USB Input to internal 3.3 V regulator
VREGI

USB_
USB Decoupling for internal 3.3 V USB regulator
USB_VREGO VRE-
and regulator output
GO

5.11.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG395 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.33. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.11.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG395 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.22. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.12 EFM32LG840 (QFN64)

5.12.1 Pinout

The EFM32LG840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.23. EFM32LG840 Pinout (top view, not to scale)

Table 5.34. Device Pinout

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

0 VSS Ground.

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 LCD_SEG13 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

CMU_CLK0 #0
3 PA2 LCD_SEG15 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 LCD_SEG16 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 LCD_SEG17 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 LCD_SEG19 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

LCD_SEG20/
9 PB3 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
10 PB4 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

LCD_SEG22/
11 PB5 US2_CLK #1
LCD_COM6

LCD_SEG23/
12 PB6 US2_CS #1
LCD_COM7

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA12 LCD_BCAP_P TIM2_CC0 #1

18 PA13 LCD_BCAP_N TIM2_CC1 #1

19 PA14 LCD_BEXT TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
22 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PE4 LCD_COM0 US0_CS #1

42 PE5 LCD_COM1 US0_CLK #1

43 PE6 LCD_COM2 US0_RX #1

44 PE7 LCD_COM3 US0_TX #1

ACMP1_CH4
CMU_CLK0 #1
45 PC12 DAC0_OUT1ALT #0/
LES_CH12 #0
OPAMP_OUT1ALT

TIM0_CDTI0 #1/3
ACMP1_CH5
TIM1_CC0 #0
46 PC13 DAC0_OUT1ALT #1/ LES_CH13 #0
TIM1_CC2 #4
OPAMP_OUT1ALT
PCNT0_S0IN #0

ACMP1_CH6 TIM0_CDTI1 #1/3

47 PC14 DAC0_OUT1ALT #2/ TIM1_CC1 #0 US0_CS #3 LES_CH14 #0
OPAMP_OUT1ALT PCNT0_S1IN #0

ACMP1_CH7
TIM0_CDTI2 #1/3 LES_CH15 #0
48 PC15 DAC0_OUT1ALT #3/ US0_CLK #3
TIM1_CC2 #0 DBG_SWO #1
OPAMP_OUT1ALT

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

PRS_CH0 #1 ETM_TD3
52 PF3 LCD_SEG1 TIM0_CDTI0 #2/5
#1

53 PF4 LCD_SEG2 TIM0_CDTI1 #2/5 PRS_CH1 #1

54 PF5 LCD_SEG3 TIM0_CDTI2 #2/5 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 PE8 LCD_SEG4 PCNT2_S0IN #1 PRS_CH3 #1

57 PE9 LCD_SEG5 PCNT2_S1IN #1

58 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
59 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

60 PE12 LCD_SEG8 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
61 PE13 LCD_SEG9 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

62 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2

63 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2

64 PA15 LCD_SEG12 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.12.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.35. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 1. Segments 0, 1, 2 and 3 are

LCD_SEG1 PF3
controlled by SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are

LCD_SEG2 PF4
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2.

US0_CLK PE12 PE5 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PE12 PB8 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PE13 PB7
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

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 EFM32LG Data Sheet
Pin Definitions

5.12.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG840 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.36. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 — — — — — PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 — — PB8 PB7 PB6 PB5 PB4 PB3 — — —

Port C PC15 PC14 PC13 PC12 — — — — PC7 PC6 PC5 PC4 — — — —

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 — — — —

Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0

5.12.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG840 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
OPA0
OUT0
PC5 -

PD4 +
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.24. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.13 EFM32LG842 (TQFP64)

5.13.1 Pinout

The EFM32LG842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.25. EFM32LG842 Pinout (top view, not to scale)

Table 5.37. Device Pinout

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 LCD_SEG13 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 LCD_SEG15 TIM0_CC2 #0/1
ETM_TD0 #3

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LES_ALTEX2 #0
4 PA3 LCD_SEG16 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 LCD_SEG17 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

7 IOVDD_0 Digital IO power supply 0.

8 VSS Ground.

LCD_SEG20/
9 PB3 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
10 PB4 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

LCD_SEG22/
11 PB5 US2_CLK #1
LCD_COM6

LCD_SEG23/
12 PB6 US2_CS #1
LCD_COM7

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA12 LCD_BCAP_P TIM2_CC0 #1

18 PA13 LCD_BCAP_N TIM2_CC1 #1

19 PA14 LCD_BEXT TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

22 VSS Ground.

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

30 PD2 ADC0_CH2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PE4 LCD_COM0 US0_CS #1

42 PE5 LCD_COM1 US0_CLK #1

43 PE6 LCD_COM2 US0_RX #1

44 PE7 LCD_COM3 US0_TX #1

ACMP1_CH4
CMU_CLK0 #1
45 PC12 DAC0_OUT1ALT #0/
LES_CH12 #0
OPAMP_OUT1ALT

TIM0_CDTI0 #1/3
ACMP1_CH5
TIM1_CC0 #0
46 PC13 DAC0_OUT1ALT #1/ LES_CH13 #0
TIM1_CC2 #4
OPAMP_OUT1ALT
PCNT0_S0IN #0

ACMP1_CH6 TIM0_CDTI1 #1/3

47 PC14 DAC0_OUT1ALT #2/ TIM1_CC1 #0 US0_CS #3 LES_CH14 #0
OPAMP_OUT1ALT PCNT0_S1IN #0

ACMP1_CH7
TIM0_CDTI2 #1/3 LES_CH15 #0
48 PC15 DAC0_OUT1ALT #3/ US0_CLK #3
TIM1_CC2 #0 DBG_SWO #1
OPAMP_OUT1ALT

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ACMP1_O #0
51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

PRS_CH0 #1 ETM_TD3
52 PF3 LCD_SEG1 TIM0_CDTI0 #2/5
#1

53 PF4 LCD_SEG2 TIM0_CDTI1 #2/5 PRS_CH1 #1

54 PF5 LCD_SEG3 TIM0_CDTI2 #2/5 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 VSS Ground.

57 PE8 LCD_SEG4 PCNT2_S0IN #1 PRS_CH3 #1

58 PE9 LCD_SEG5 PCNT2_S1IN #1

59 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
60 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

61 PE12 LCD_SEG8 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
62 PE13 LCD_SEG9 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

63 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2

64 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2

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 EFM32LG Data Sheet
Pin Definitions

5.13.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.38. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 1. Segments 0, 1, 2 and 3 are

LCD_SEG1 PF3
controlled by SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are

LCD_SEG2 PF4
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

US0_CLK PE12 PE5 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PE12 PB8 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PE13 PB7
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

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 EFM32LG Data Sheet
Pin Definitions

5.13.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG842 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.39. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A — PA14 PA13 PA12 — — — — — — PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 — PB11 — — PB8 PB7 PB6 PB5 PB4 PB3 — — —

Port C PC15 PC14 PC13 PC12 — — — — PC7 PC6 PC5 PC4 — — — —

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 — — — —

Port F — — — — — — — — — — PF5 PF4 PF3 PF2 PF1 PF0

5.13.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG842 is shown in the following figure.
PB11

PC4 + OUT0ALT
OPA0
OUT0
PC5 -

PD4 +
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.26. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.14 EFM32LG880 (LQFP100)

5.14.1 Pinout

The EFM32LG880 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.27. EFM32LG880 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.40. Device Pinout

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LEU0_RX #4 PRS_CH0 #0
1 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

9 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

10 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

11 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

LCD_SEG20/
12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

LCD_SEG22/
14 PB5 EBI_A21 #0/1/2 US2_CLK #1
LCD_COM6

LCD_SEG23/
15 PB6 EBI_A22 #0/1/2 US2_CS #1
LCD_COM7

16 VSS Ground.

17 IOVDD_1 Digital IO power supply 1.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
18 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
19 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
20 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
21 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
22 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
23 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

US0_TX #4
24 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

US0_RX #4
25 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

26 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

27 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

28 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

29 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

30 PA11 LCD_SEG39 EBI_HSNC #0/1/2

31 IOVDD_2 Digital IO power supply 2.

32 VSS Ground.

33 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

34 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

35 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
36 RESETn
during reset, and let the internal pull-up ensure that reset is released.

37 PB9 EBI_A03 #0/1/2 U1_TX #2

38 PB10 EBI_A04 #0/1/2 U1_RX #2

DAC0_OUT0 / TIM1_CC2 #3 LE-

39 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
40 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

41 AVDD_1 Analog power supply 1.

US0_CLK #4/5
42 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
43 PB14 HFXTAL_N
LEU0_RX #1

44 IOVDD_3 Digital IO power supply 3.

45 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH0
DAC0_OUT0ALT
46 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
47 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

48 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

ADC0_CH3
49 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
50 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

ADC0_CH5
51 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
52 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
53 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

54 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 LES_CH6 #0
55 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
56 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

57 VDD_DREG Power supply for on-chip voltage regulator.

58 VSS Ground.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
59 DECOUPLE
pin.

TIM3_CC0 #1 U0_TX #1
60 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
61 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

64 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

65 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

66 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

67 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LES_CH9 #0
69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
72 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
73 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
74 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
75 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
76 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
77 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
78 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

PRS_CH0 #1
79 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

80 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

81 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1

82 IOVDD_5 Digital IO power supply 5.

83 VSS Ground.

84 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

85 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

86 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

87 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

88 PD9 LCD_SEG28 EBI_CS0 #0/1/2

89 PD10 LCD_SEG29 EBI_CS1 #0/1/2

90 PD11 LCD_SEG30 EBI_CS2 #0/1/2

91 PD12 LCD_SEG31 EBI_CS3 #0/1/2

92 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

93 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

94 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
95 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3
CMU_CLK1 #2
96 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

US0_TX #3 LES_ALTEX7 #0
97 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

98 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

99 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

100 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.14.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.41. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG1 PF3
controlled by SEGEN0.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG2 PF4
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3 PC14
in half duplex communication.

U1_RX PC13 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PC12 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.14.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG880 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.42. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.14.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG880 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2
PD3 OUT2
-

PD6 + OUT1ALT
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.28. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.15 EFM32LG890 (BGA112)

5.15.1 Pinout

The EFM32LG890 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.29. EFM32LG890 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.43. Device Pinout

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD10 LCD_SEG29 EBI_CS1 #0/1/2

A6 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A7 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1

A8 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

A9 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
A10 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
A11 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD11 LCD_SEG30 EBI_CS2 #0/1/2

B6 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B7 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

PRS_CH0 #1
B8 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

B9 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
B10 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
B11 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

CMU_CLK1 #0
C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 PD12 LCD_SEG31 EBI_CS3 #0/1/2

C6 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

C7 VSS Ground.

ACMP1_O #0
C8 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

C9 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

C10 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

C11 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

LES_ALTEX2 #0
D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

CMU_CLK0 #0
D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D4 VSS Ground.

D5 IOVDD_6 Digital IO power supply 6.

D6 PD9 LCD_SEG28 EBI_CS0 #0/1/2

D7 IOVDD_5 Digital IO power supply 5.

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
D8 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

D9 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

ETM_TCLK #3
E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E4 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
E8 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

TIM3_CC0 #1 U0_TX #1
E9 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
E10 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

E11 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

F1 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

F2 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

LCD_SEG20/
F3 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
F4 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

F8 VDD_DREG Power supply for on-chip voltage regulator.

F9 VSS_DREG Ground for on-chip voltage regulator.

F10 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
F11 DECOUPLE
pin.

LCD_SEG22/
G1 PB5 EBI_A21 #0/1/2 US2_CLK #1
LCD_COM6

LCD_SEG23/
G2 PB6 EBI_A22 #0/1/2 US2_CS #1
LCD_COM7

G3 VSS Ground.

G4 IOVDD_0 Digital IO power supply 0.

G8 IOVDD_4 Digital IO power supply 4.

G9 VSS Ground.

LEU1_TX #0 LES_CH6 #0
G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
H1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
H2 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

H3 PD14 I2C0_SDA #3

H4 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

H5 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

H6 VSS Ground.

H7 IOVDD_3 Digital IO power supply 3.

H8 PD8 BU_VIN CMU_CLK1 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH5
H9 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
H10 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
H11 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
J1 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
J2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

J3 PD15 I2C0_SCL #3

J4 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

J5 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

J6 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

J7 PB9 EBI_A03 #0/1/2 U1_TX #2

J8 PB10 EBI_A04 #0/1/2 U1_RX #2

J9 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

ADC0_CH3
J10 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
J11 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

US0_TX #4
K1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
K2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

K3 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

K4 VSS Ground.

K5 PA11 LCD_SEG39 EBI_HSNC #0/1/2

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
K6 RESETn
during reset, and let the internal pull-up ensure that reset is released.

K7 AVSS_1 Analog ground 1.

K8 AVDD_2 Analog power supply 2.

K9 AVDD_1 Analog power supply 1.

K10 AVSS_0 Analog ground 0.

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
K11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

US0_RX #4
L1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
L2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

L3 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

L4 IOVDD_1 Digital IO power supply 1.

DAC0_OUT0 / TIM1_CC2 #3 LE-

L5 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
L6 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

L7 AVSS_2 Analog ground 2.

US0_CLK #4/5
L8 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
L9 PB14 HFXTAL_N
LEU0_RX #1

L10 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT
L11 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

5.15.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.44. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PC12 PC13 PC14 PC15 PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD_SEG1 PF3 LCD segment line 1. Segments 0, 1, 2 and 3 are

controlled by SEGEN0.

LCD_SEG2 PF4 LCD segment line 2. Segments 0, 1, 2 and 3 are

controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3 PC14
in half duplex communication.

U1_RX PC13 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PC12 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.15.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG890 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.45. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — — — — PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.15.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG890 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.30. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.16 EFM32LG895 (BGA120)

5.16.1 Pinout

The EFM32LG895 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.31. EFM32LG895 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.46. Device Pinout

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD11 LCD_SEG30 EBI_CS2 #0/1/2

A6 PD9 LCD_SEG28 EBI_CS0 #0/1/2

A7 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A8 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 PRS_CH2 #1

A9 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

ACMP1_O #0
A10 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

A11 USB_VREGI Input to internal 3.3V USB regulator

A12 USB_VREGO Output and decoupling for internal 3.3V USB regulator

A13 PF11 U1_RX #1

B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD12 LCD_SEG31 EBI_CS3 #0/1/2

B6 PD10 LCD_SEG29 EBI_CS1 #0/1/2

B7 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B8 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

PRS_CH0 #1
B9 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
B10 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

B11 PF12

B12 USB_VBUS USB 5.0 V VBUS input.

B13 PF10 U1_TX #1

CMU_CLK1 #0
C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LEU0_RX #4 PRS_CH0 #0
C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 VSS Ground.

C6 IOVDD_0 Digital IO power supply 0.

C7 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

C8 VSS Ground.

C9 IOVDD_1 Digital IO power supply 1.

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
C10 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

C11 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
C12 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
C13 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

LES_ALTEX2 #0
D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

CMU_CLK0 #0
D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D11 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
D12 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
D13 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

ETM_TCLK #3
E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E11 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

E12 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

E13 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

F1 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

F2 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

F3 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

F11 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

LCD_SEG20/
G1 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
G2 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

G3 IOVDD_2 Digital IO power supply 2.

TIM3_CC0 #1 U0_TX #1
G11 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
G12 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

G13 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

LCD_SEG22/
H1 PB5 EBI_A21 #0/1/2 US2_CLK #1
LCD_COM6

LCD_SEG23/
H2 PB6 EBI_A22 #0/1/2 US2_CS #1
LCD_COM7

H3 VSS Ground.

H11 VDD_DREG Power supply for on-chip voltage regulator.

H12 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

LEU1_RX #0 LES_CH7 #0
H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

J1 PD14 I2C0_SDA #3

J2 PD15 I2C0_SCL #3

J3 VSS Ground.

J11 IOVDD_3 Digital IO power supply 3.

LEU1_TX #0 LES_CH6 #0
J12 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
J13 DECOUPLE
pin.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
K1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
K2 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

K3 IOVDD_4 Digital IO power supply 4.

K11 VSS Ground.

K12 VSS Ground.

K13 PD8 BU_VIN CMU_CLK1 #1

ACMP0_CH2
DAC0_OUT0ALT
L1 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
L2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

L3 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

L4 IOVDD_5 Digital IO power supply 5.

L5 VSS Ground.

L6 VSS Ground.

L7 IOVDD_6 Digital IO power supply 6.

L8 PB9 EBI_A03 #0/1/2 U1_TX #2

L9 PB10 EBI_A04 #0/1/2 U1_RX #2

ADC0_CH0
DAC0_OUT0ALT
L10 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
L11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

ADC0_CH4
L12 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
L13 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

US0_TX #4
M1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
M2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

M3 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

M4 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

M5 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

M6 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
M7 RESETn
during reset, and let the internal pull-up ensure that reset is released.

M8 AVSS_1 Analog ground 1.

M9 AVDD_2 Analog power supply 2.

M10 AVDD_1 Analog power supply 1.

M11 AVSS_0 Analog ground 0.

ADC0_CH3
M12 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
M13 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

US0_RX #4
N1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
N2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

N3 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

N4 PA11 LCD_SEG39 EBI_HSNC #0/1/2

N5 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

DAC0_OUT0 / TIM1_CC2 #3 LE-

N6 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
N7 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

N8 AVSS_2 Analog ground 2.

US0_CLK #4/5
N9 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
N10 PB14 HFXTAL_N
LEU0_RX #1

N11 AVDD_0 Analog power supply 0.

N12 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 US1_CLK #1 DBG_SWO #3

ADC0_CH5
N13 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.16.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.47. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT / Digital to Analog Converter DAC0_OUT0ALT /

PC0 PC1 PC2 PC3 PD0
OPAMP_OUT0ALT OPAMP alternative output for channel 0.

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT / Digital to Analog Converter DAC0_OUT1ALT /

PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1ALT OPAMP alternative output for channel 1.

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of re-
set, and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of re-
set, and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset,
and must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready

EBI_ARDY PF2 PF2 PF2
Control input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchro-

EBI_VSNC PA10 PA10 PA10
nization pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster,
LCD_BCAP_N PA13
connect a 22 nF capacitor between LCD_BCAP_N
and LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N
and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF ca-
pacitor between this pin and VSS.

An external LCD voltage may also be applied to

LCD_BEXT PA14
this pin if the booster is not enabled.

If AVDD is used directly as the LCD supply volt-

age, this pin may be left unconnected or used as a
GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 1. Segments 0, 1, 2 and 3 are

LCD_SEG1 PF3
controlled by SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are

LCD_SEG2 PF4
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11

LCD_SEG10 PE14
are controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11

LCD_SEG11 PE15
are controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive

LEU0_TX PD4 PB13 PE14 PF0 PF2
input in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive

LEU1_TX PC6 PA5
input in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) neg-

LFXTAL_N PB8 ative pin. Also used as an optional external clock
input pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive in-

U0_TX PF6 PE0 PA3 PC14
put in half duplex communication.

U1_RX PC13 PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive in-

U1_TX PC12 PF10 PB9 PE2
put in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

5.16.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG895 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.48. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

5.16.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG895 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.32. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.17 EFM32LG900 (Wafer)

5.17.1 Padout

The EFM32LG900 padout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pad are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

usb_vbus
iovdd_6

iovdd_5
iovss_6

iovss_5

iovss_7
PD13
PD12
PD11
PD10
PB15
PA15
PE15
PE14
PE13
PE12

PE11
PE10

PF12
PD9
PE9
PE8

PF9
PF8
PF7
PF6

PF5

PF4

PF3
PF2
PF1
PF0
NC
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102

101
100
99
98
97
96
PA0 1 95 PF11
94 PC15
PA1 2 93 PF10
PA2 3 92 PC14
PA3 4 91 usb_vrego_1
90 usb_vrego_0
PA4 5 89 usb_vregi_1
88 usb_vregi_0
PA5 6
87 PC13
PA6 7 86 PC12
iovdd_0 8 85 PC11
84 PC10
83 PC9
iovss_0 9 82 PC8
PD14 10 81 PE7
PD15 11
80 PE6
PB0 12
79 PE5
PB1 13
78 PE4
PB2 14 77 PE3
76 PE2
NC 15
75 PE1
PB3 16 74 PE0
73 iovss_4
PB4 17 72 NC
PB5 18
PB6 19
iovss_1 20
iovdd_1 21 71 dec_2
70 dec_1
PC0 22 69 dec_0
PC1 23 68 iovdd_4
PC2 24 67 vdd_dreg
PC3 25 66 vss_dreg
65 PC7
PC4 26 64 PC6
PC5 27 63 PD8
62 PD7
PB7 28
61 PD6
PB8 29
60 PD5
30
31
32
33
34
35
36
37
38
39
40
41
42

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
PA7
PA8
PA9
PA10
PA11
iovdd_2
iovss_2
PA12
PA13
PA14
reset
PB9
PB10

PB11
PB12
avss_2
avdd_2
avdd_1
avss_1
PB13
PB14
iovss_3
iovdd_3
avss_0
avdd_0
PD0
PD1
PD2
PD3
PD4

Figure 5.33. EFM32LG900 Padout (top view, not to scale)

Table 5.49. Device Padout

Water Pads Pad Alternative Functionality / Description

Pad Pad Name Analog EBI Timers Communication Other

#

1 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4 LEU0_RX #4 PRS_CH0 #0

I2C0_SDA #0 GPIO_EM4WU0

2 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0 CMU_CLK1 #0

PRS_CH1 #0

3 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1 CMU_CLK0 #0

ETM_TD0 #3

4 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2 LES_ALTEX2 #0

ETM_TD1 #3

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 EFM32LG Data Sheet
Pin Definitions

Water Pads Pad Alternative Functionality / Description

Pad Pad Name Analog EBI Timers Communication Other

#

5 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2 LES_ALTEX3 #0

ETM_TD2 #3

6 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1 LES_ALTEX4 #0

ETM_TD3 #3

7 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1 ETM_TCLK #3

GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

9 IOVSS_0 Digital IO ground 0.

10 PD14 I2C0_SDA #3

11 PD15 I2C0_SCL #3

12 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

13 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

14 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

15 NC Do not connect.

16 PB3 LCD_SEG20/ EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1

LCD_COM4

17 PB4 LCD_SEG21/ EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1

LCD_COM5

18 PB5 LCD_SEG22/ EBI_A21 #0/1/2 US2_CLK #1

LCD_COM6

19 PB6 LCD_SEG23/ EBI_A22 #0/1/2 US2_CS #1

LCD_COM7

20 IOVSS_1 Digital IO ground 1.

21 IOVDD_1 Digital IO power supply 1.

22 PC0 ACMP0_CH0 EBI_A23 #0/1/2 TIM0_CC1 #4 US0_TX #5 LES_CH0 #0

DAC0_OUT0ALT PCNT0_S0IN #2 US1_TX #0 PRS_CH2 #0
#0/ I2C0_SDA #4
OPAMP_OUT0ALT

23 PC1 ACMP0_CH1 EBI_A24 #0/1/2 TIM0_CC2 #4 US0_RX #5 LES_CH1 #0

DAC0_OUT0ALT PCNT0_S1IN #2 US1_RX #0 PRS_CH3 #0
#1/ I2C0_SCL #4
OPAMP_OUT0ALT

24 PC2 ACMP0_CH2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0

DAC0_OUT0ALT
#2/
OPAMP_OUT0ALT

25 PC3 ACMP0_CH3 EBI_NANDREn TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0

DAC0_OUT0ALT #0/1/2
#3/
OPAMP_OUT0ALT

26 PC4 ACMP0_CH4 / EBI_A26 #0/1/2 TIM0_CDTI2 #4 US2_CLK #0 LES_CH4 #0

DAC0_P0 / LETIM0_OUT0 #3 I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

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 EFM32LG Data Sheet
Pin Definitions

Water Pads Pad Alternative Functionality / Description

Pad Pad Name Analog EBI Timers Communication Other

#

27 PC5 ACMP0_CH5 / EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0 LES_CH5 #0

DAC0_N0 / #0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

28 PB7 LFXTAL_P TIM1_CC0 #3 US0_TX #4

US1_CLK #0

29 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4

US1_CS #0

30 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

31 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

32 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

33 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

34 PA11 LCD_SEG39 EBI_HSNC #0/1/2

35 IOVDD_2 Digital IO power supply 2.

36 IOVSS_2 Digital IO ground 2.

37 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

38 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

39 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

40 RESETn Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.

41 PB9 EBI_A03 #0/1/2 U1_TX #2

42 PB10 EBI_A04 #0/1/2 U1_RX #2

43 PB11 DAC0_OUT0 / TIM1_CC2 #3 LE- I2C1_SDA #1

OPAMP_OUT0 TIM0_OUT0 #1

44 PB12 DAC0_OUT1 / LETIM0_OUT1 #1 I2C1_SCL #1

OPAMP_OUT1

45 AVSS_2 Analog ground 2.

46 AVDD_2 Analog power supply 2.

47 AVDD_1 Analog power supply 1.

48 AVSS_1 Analog ground 1.

49 PB13 HFXTAL_P US0_CLK #4/5

LEU0_TX #1

50 PB14 HFXTAL_N US0_CS #4/5

LEU0_RX #1

51 IOVSS_3 Digital IO ground 3.

52 IOVDD_3 Digital IO power supply 3.

53 AVSS_0 Analog ground 0.

54 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

Water Pads Pad Alternative Functionality / Description

Pad Pad Name Analog EBI Timers Communication Other

#

55 PD0 ADC0_CH0 PCNT2_S0IN #0 US1_TX #1

DAC0_OUT0ALT
#4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1

56 PD1 ADC0_CH1 TIM0_CC0 #3 US1_RX #1 DBG_SWO #2

DAC0_OUT1ALT PCNT2_S1IN #0
#4/
OPAMP_OUT1ALT

57 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 USB_DMPU #0 DBG_SWO #3

US1_CLK #1

58 PD3 ADC0_CH3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

OPAMP_N2

59 PD4 ADC0_CH4 LEU0_TX #0 ETM_TD2 #0/2

OPAMP_P2

60 PD5 ADC0_CH5 LEU0_RX #0 ETM_TD3 #0/2

OPAMP_OUT2 #0

61 PD6 ADC0_CH6 / TIM1_CC0 #4 LE- US1_RX #2 LES_ALTEX0 #0

DAC0_P1 / TIM0_OUT0 #0 I2C0_SDA #1 ACMP0_O #2
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

62 PD7 ADC0_CH7 / TIM1_CC1 #4 LE- US1_TX #2 CMU_CLK0 #2

DAC0_N1 / TIM0_OUT1 #0 I2C0_SCL #1 LES_ALTEX1 #0
OPAMP_N1 PCNT0_S1IN #3 ACMP1_O #2
ETM_TCLK #0

63 PD8 BU_VIN CMU_CLK1 #1

64 PC6 ACMP0_CH6 EBI_A05 #0/1/2 LEU1_TX #0 LES_CH6 #0

I2C0_SDA #2 ETM_TCLK #2

65 PC7 ACMP0_CH7 EBI_A06 #0/1/2 LEU1_RX #0 LES_CH7 #0

I2C0_SCL #2 ETM_TD0 #2

66 VSS_DREG Ground for on-chip voltage regulator.

67 VDD_DREG Power supply for on-chip voltage regulator.

68 IOVDD_4 Digital IO power supply 4.

69 DEC_0 Decouple output for on-chip voltage regulator.

70 DEC_1 Decouple output for on-chip voltage regulator.

71 DEC_2 Decouple output for on-chip voltage regulator.

72 NC Do not connect.

73 IOVSS_4 Digital IO ground 4.

74 PE0 EBI_A07 #0/1/2 TIM3_CC0 #1 U0_TX #1

PCNT0_S0IN #1 I2C1_SDA #2

75 PE1 EBI_A08 #0/1/2 TIM3_CC1 #1 U0_RX #1

PCNT0_S1IN #1 I2C1_SCL #2

76 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

77 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

78 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

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 EFM32LG Data Sheet
Pin Definitions

Water Pads Pad Alternative Functionality / Description

Pad Pad Name Analog EBI Timers Communication Other

#

79 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

80 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

81 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

82 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

83 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2 LES_CH9 #0

GPIO_EM4WU2

84 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

85 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

86 PC12 ACMP1_CH4 U1_TX #0 CMU_CLK0 #1

DAC0_OUT1ALT LES_CH12 #0
#0/
OPAMP_OUT1ALT

87 PC13 ACMP1_CH5 TIM0_CDTI0 #1/3 U1_RX #0 LES_CH13 #0

DAC0_OUT1ALT TIM1_CC0 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

88 USB_VREGI_0 Input to internal 3.3V USB regulator

89 USB_VREGI_1 Input to internal 3.3V USB regulator

90 USB_VREGO_0 Output and decoupling for internal 3.3V USB regulator

91 USB_VREGO_1 Output and decoupling for internal 3.3V USB regulator

92 PC14 ACMP1_CH6 TIM0_CDTI1 #1/3 US0_CS #3 U0_TX LES_CH14 #0

DAC0_OUT1ALT TIM1_CC1 #0 #3
#2/ PCNT0_S1IN #0
OPAMP_OUT1ALT

93 PF10 U1_TX #1
USB_DM

94 PC15 ACMP1_CH7 TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0

DAC0_OUT1ALT TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
#3/
OPAMP_OUT1ALT

95 PF11 U1_RX #1
USB_DP

96 IOVSS_7 Digital IO ground 7.

97 PF0 TIM0_CC0 #5 LE- US1_CLK #2 DBG_SWCLK

TIM0_OUT0 #2 LEU0_TX #3 #0/1/2/3
I2C0_SDA #5

98 PF1 TIM0_CC1 #5 LE- US1_CS #2 DBG_SWDIO

TIM0_OUT1 #2 LEU0_RX #3 #0/1/2/3
I2C0_SCL #5 GPIO_EM4WU3

99 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 ACMP1_O #0

DBG_SWO #0
GPIO_EM4WU4

100 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5 PRS_CH0 #1

ETM_TD3 #1

101 USB_VBUS USB 5.0 V VBUS input.

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 EFM32LG Data Sheet
Pin Definitions

Water Pads Pad Alternative Functionality / Description

Pad Pad Name Analog EBI Timers Communication Other

#

102 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

103 PF12 USB_ID

104 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

105 IOVSS_5 Digital IO ground 5.

106 IOVDD_5 Digital IO power supply 5.

107 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

108 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

109 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

110 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

111 NC Do not connect.

112 PD9 LCD_SEG28 EBI_CS0 #0/1/2

113 PD10 LCD_SEG29 EBI_CS1 #0/1/2

114 PD11 LCD_SEG30 EBI_CS2 #0/1/2

115 PD12 LCD_SEG31 EBI_CS3 #0/1/2

116 PD13 ETM_TD1 #1

117 PB15 ETM_TD2 #1

118 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

119 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

120 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

121 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0 LES_ALTEX5 #0

BOOT_RX

122 IOVDD_6 Digital IO power supply 6.

123 IOVSS_6 Digital IO ground 6.

124 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_RX #3 CMU_CLK1 #2

US0_CLK #0 LES_ALTEX6 #0
I2C0_SDA #6

125 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_TX #3 LES_ALTEX7 #0

US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

126 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

127 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

128 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.17.2 Alternate Functionality Padout

A wide selection of alternate functionality is available for multiplexing to various pads. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the padout
is shown in the column corresponding to LOCATION 0.

Table 5.50. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 / OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT / Digital to Analog Converter DAC0_OUT0ALT /

PC0 PC1 PC2 PC3 PD0
OPAMP_OUT0ALT OPAMP alternative output for channel 0.

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT / Digital to Analog Converter DAC0_OUT1ALT /

PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1ALT OPAMP alternative output for channel 1.

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of re-
set, and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of re-
set, and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset,
and must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready

EBI_ARDY PF2 PF2 PF2
Control input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchro-

EBI_VSNC PA10 PA10 PA10
nization pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster,
LCD_BCAP_N PA13
connect a 22 nF capacitor between LCD_BCAP_N
and LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N
and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF ca-
pacitor between this pin and VSS.

An external LCD voltage may also be applied to

LCD_BEXT PA14
this pin if the booster is not enabled.

If AVDD is used directly as the LCD supply volt-

age, this pin may be left unconnected or used as a
GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 1. Segments 0, 1, 2 and 3 are

LCD_SEG1 PF3
controlled by SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are

LCD_SEG2 PF4
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11

LCD_SEG10 PE14
are controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11

LCD_SEG11 PE15
are controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive

LEU0_TX PD4 PB13 PE14 PF0 PF2
input in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive

LEU1_TX PC6 PA5
input in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) neg-

LFXTAL_N PB8 ative pin. Also used as an optional external clock
input pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Deat Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Deat Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive in-

U0_TX PF6 PE0 PA3 PC14
put in half duplex communication.

U1_RX PC13 PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive in-

U1_TX PC12 PF10 PB9 PE2
put in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_
USB_VBUS USB 5 V VBUS input.
VBUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_
USB_VREGI USB Input to internal 3.3 V regulator
VREGI

USB_
USB Decoupling for internal 3.3 V USB regulator
USB_VREGO VRE-
and regulator output
GO

5.17.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG900 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.51. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.17.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG900 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.34. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.18 EFM32LG940 (QFN64)

5.18.1 Pinout

The EFM32LG940 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.35. EFM32LG940 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.52. Device Pinout

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

0 VSS Ground.

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 LCD_SEG13 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 LCD_SEG15 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 LCD_SEG16 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 LCD_SEG17 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 LCD_SEG19 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

LCD_SEG20/
9 PB3 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
10 PB4 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

LCD_SEG22/
11 PB5 US2_CLK #1
LCD_COM6

LCD_SEG23/
12 PB6 US2_CS #1
LCD_COM7

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA12 LCD_BCAP_P TIM2_CC0 #1

18 PA13 LCD_BCAP_N TIM2_CC1 #1

19 PA14 LCD_BEXT TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
22 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

USB_DMPU #0
30 PD2 ADC0_CH2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PE4 LCD_COM0 US0_CS #1

42 PE5 LCD_COM1 US0_CLK #1

43 PE6 LCD_COM2 US0_RX #1

44 PE7 LCD_COM3 US0_TX #1

45 USB_VREGI Input to internal 3.3V USB regulator

46 USB_VREGO Output and decoupling for internal 3.3V USB regulator

47 PF10 USB_DM

48 PF11 USB_DP

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 EFM32LG Data Sheet
Pin Definitions

QFN64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

52 USB_VBUS USB 5.0 V VBUS input.

53 PF12 USB_ID

54 PF5 LCD_SEG3 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

56 PE8 LCD_SEG4 PCNT2_S0IN #1 PRS_CH3 #1

57 PE9 LCD_SEG5 PCNT2_S1IN #1

58 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
59 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

60 PE12 LCD_SEG8 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
61 PE13 LCD_SEG9 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

62 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2

63 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2

64 PA15 LCD_SEG12 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.18.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.53. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 Timer 3 Capture Compare input / output channel 2.

US0_CLK PE12 PE5 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PB14 PB14 USART0 chip select input / output.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PE12 PB8 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PE13 PB7
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

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 EFM32LG Data Sheet
Pin Definitions

5.18.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG940 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.54. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 — — — — — PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 — — PB8 PB7 PB6 PB5 PB4 PB3 — — —

Port C — — — — — — — — PC7 PC6 PC5 PC4 — — — —

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 — — — —

Port F — — — PF12 PF11 PF10 — — — — PF5 — — PF2 PF1 PF0

5.18.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG940 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
OPA0
OUT0
PC5 -

PD4 +
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.36. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.19 EFM32LG942 (TQFP64)

5.19.1 Pinout

The EFM32LG942 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.37. EFM32LG942 Pinout (top view, not to scale)

Table 5.55. Device Pinout

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LEU0_RX #4 I2C0_SDA PRS_CH0 #0

1 PA0 LCD_SEG13 TIM0_CC0 #0/1/4
#0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 LCD_SEG14 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 LCD_SEG15 TIM0_CC2 #0/1
ETM_TD0 #3

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

LES_ALTEX2 #0
4 PA3 LCD_SEG16 TIM0_CDTI0 #0
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 LCD_SEG17 TIM0_CDTI1 #0
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 LCD_SEG18 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

7 IOVDD_0 Digital IO power supply 0.

8 VSS Ground.

LCD_SEG20/
9 PB3 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
10 PB4 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

LCD_SEG22/
11 PB5 US2_CLK #1
LCD_COM6

LCD_SEG23/
12 PB6 US2_CS #1
LCD_COM7

TIM0_CDTI2 #4 LE-
ACMP0_CH4 / US2_CLK #0 I2C1_SDA
13 PC4 TIM0_OUT0 #3 LES_CH4 #0
DAC0_P0 / OPAMP_P0 #0
PCNT1_S0IN #0

ACMP0_CH5 / LETIM0_OUT1 #3 US2_CS #0 I2C1_SCL

14 PC5 LES_CH5 #0
DAC0_N0 / OPAMP_N0 PCNT1_S1IN #0 #0

US0_TX #4 US1_CLK
15 PB7 LFXTAL_P TIM1_CC0 #3
#0

16 PB8 LFXTAL_N TIM1_CC1 #3 US0_RX #4 US1_CS #0

17 PA12 LCD_BCAP_P TIM2_CC0 #1

18 PA13 LCD_BCAP_N TIM2_CC1 #1

19 PA14 LCD_BEXT TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
20 RESETn
low during reset, and let the internal pull-up ensure that reset is released.

DAC0_OUT0 / TIM1_CC2 #3 LE-

21 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

22 VSS Ground.

23 AVDD_1 Analog power supply 1.

US0_CLK #4/5
24 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5 LEU0_RX

25 PB14 HFXTAL_N
#1

26 IOVDD_3 Digital IO power supply 3.

27 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT #4/
28 PD0 PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

ADC0_CH1
TIM0_CC0 #3
29 PD1 DAC0_OUT1ALT #4/ US1_RX #1 DBG_SWO #2
PCNT2_S1IN #0
OPAMP_OUT1ALT

USB_DMPU #0
30 PD2 ADC0_CH2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

31 PD3 ADC0_CH3 OPAMP_N2 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2

32 PD4 ADC0_CH4 OPAMP_P2 LEU0_TX #0 ETM_TD2 #0/2

ADC0_CH5
33 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

TIM1_CC0 #4 LE- LES_ALTEX0 #0

ADC0_CH6 / US1_RX #2 I2C0_SDA
34 PD6 TIM0_OUT0 #0 ACMP0_O #2
DAC0_P1 / OPAMP_P1 #1
PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
TIM1_CC1 #4 LE-
ADC0_CH7 / US1_TX #2 I2C0_SCL LES_ALTEX1 #0
35 PD7 TIM0_OUT1 #0
DAC0_N1 / OPAMP_N1 #1 ACMP1_O #2
PCNT0_S1IN #3
ETM_TCLK #0

36 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 I2C0_SDA LES_CH6 #0

37 PC6 ACMP0_CH6
#2 ETM_TCLK #2

LEU1_RX #0 I2C0_SCL LES_CH7 #0 ETM_TD0

38 PC7 ACMP0_CH7
#2 #2

39 VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
40 DECOUPLE
at this pin.

41 PE4 LCD_COM0 US0_CS #1

42 PE5 LCD_COM1 US0_CLK #1

43 PE6 LCD_COM2 US0_RX #1

44 PE7 LCD_COM3 US0_TX #1

45 USB_VREGI Input to internal 3.3V USB regulator

46 USB_VREGO Output and decoupling for internal 3.3V USB regulator

47 PF10 USB_DM

48 PF11 USB_DP

TIM0_CC0 #5 LE- US1_CLK #2 LEU0_TX

49 PF0 DBG_SWCLK #0/1/2/3
TIM0_OUT0 #2 #3 I2C0_SDA #5

TIM0_CC1 #5 LE- US1_CS #2 LEU0_RX DBG_SWDIO #0/1/2/3

50 PF1
TIM0_OUT1 #2 #3 I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
51 PF2 LCD_SEG0 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

52 USB_VBUS USB 5.0 V VBUS input.

53 PF12 USB_ID

54 PF5 LCD_SEG3 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

55 IOVDD_5 Digital IO power supply 5.

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 EFM32LG Data Sheet
Pin Definitions

QFP64 Pin# and Name Pin Alternate Functionality / Description

Pin # Pin Name Analog Timers Communication Other

56 VSS Ground.

57 PE8 LCD_SEG4 PCNT2_S0IN #1 PRS_CH3 #1

58 PE9 LCD_SEG5 PCNT2_S1IN #1

59 PE10 LCD_SEG6 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
60 PE11 LCD_SEG7 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3 US0_CLK CMU_CLK1 #2

61 PE12 LCD_SEG8 TIM1_CC2 #1
#0 I2C0_SDA #6 LES_ALTEX6 #0

LES_ALTEX7 #0
US0_TX #3 US0_CS #0
62 PE13 LCD_SEG9 ACMP0_O #0
I2C0_SCL #6
GPIO_EM4WU5

63 PE14 LCD_SEG10 TIM3_CC0 #0 LEU0_TX #2

64 PE15 LCD_SEG11 TIM3_CC1 #0 LEU0_RX #2

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 EFM32LG Data Sheet
Pin Definitions

5.19.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.56. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PD6 Analog comparator ACMP0, digital output.

ACMP1_O PF2 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

BU_VIN PD8 Battery input for Backup Power Domain

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

ETM_TCLK PD7 PC6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

PCNT0_S0IN PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PD2 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PD3 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PE11 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA12 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA13 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA14 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 Timer 3 Capture Compare input / output channel 1.

US0_CLK PE12 PE5 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PE12 PB8 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PE13 PB7
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.19.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG942 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.57. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A — PA14 PA13 PA12 — — — — — — PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 — PB11 — — PB8 PB7 PB6 PB5 PB4 PB3 — — —

Port C — — — — — — — — PC7 PC6 PC5 PC4 — — — —

Port D — — — — — — — PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 — — — —

Port F — — — PF12 PF11 PF10 — — — — PF5 — — PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.19.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG942 is shown in the following figure.
PB11

PC4 + OUT0ALT
OPA0
OUT0
PC5 -

PD4 +
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.38. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.20 EFM32LG980 (LQFP100)

5.20.1 Pinout

The EFM32LG980 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.39. EFM32LG980 Pinout (top view, not to scale)

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 EFM32LG Data Sheet
Pin Definitions

Table 5.58. Device Pinout

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LEU0_RX #4 PRS_CH0 #0
1 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

CMU_CLK1 #0
2 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

CMU_CLK0 #0
3 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

LES_ALTEX2 #0
4 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

LES_ALTEX3 #0
5 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

LES_ALTEX4 #0
6 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

ETM_TCLK #3
7 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

8 IOVDD_0 Digital IO power supply 0.

9 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

10 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

11 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

LCD_SEG20/
12 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
13 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

LCD_SEG22/
14 PB5 EBI_A21 #0/1/2 US2_CLK #1
LCD_COM6

LCD_SEG23/
15 PB6 EBI_A22 #0/1/2 US2_CS #1
LCD_COM7

16 VSS Ground.

17 IOVDD_1 Digital IO power supply 1.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
18 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
19 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
20 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
21 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
22 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
23 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

US0_TX #4
24 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

US0_RX #4
25 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

26 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

27 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

28 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

29 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

30 PA11 LCD_SEG39 EBI_HSNC #0/1/2

31 IOVDD_2 Digital IO power supply 2.

32 VSS Ground.

33 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

34 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

35 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
36 RESETn
during reset, and let the internal pull-up ensure that reset is released.

37 PB9 EBI_A03 #0/1/2 U1_TX #2

38 PB10 EBI_A04 #0/1/2 U1_RX #2

DAC0_OUT0 / TIM1_CC2 #3 LE-

39 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
40 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

41 AVDD_1 Analog power supply 1.

US0_CLK #4/5
42 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
43 PB14 HFXTAL_N
LEU0_RX #1

44 IOVDD_3 Digital IO power supply 3.

45 AVDD_0 Analog power supply 0.

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH0
DAC0_OUT0ALT
46 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
47 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

USB_DMPU #0
48 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

ADC0_CH3
49 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
50 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

ADC0_CH5
51 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
52 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
53 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

54 PD8 BU_VIN CMU_CLK1 #1

LEU1_TX #0 LES_CH6 #0
55 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
56 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

57 VDD_DREG Power supply for on-chip voltage regulator.

58 VSS Ground.

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
59 DECOUPLE
pin.

TIM3_CC0 #1 U0_TX #1
60 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
61 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

62 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

63 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

64 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

65 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

66 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

67 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

68 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LES_CH9 #0
69 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

70 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

71 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

72 USB_VREGI Input to internal 3.3V USB regulator

73 USB_VREGO Output and decoupling for internal 3.3V USB regulator

74 PF10 U1_TX #1 USB_DM

75 PF11 U1_RX #1 USB_DP

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
76 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
77 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

ACMP1_O #0
78 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

79 USB_VBUS USB 5.0 V VBUS input.

80 PF12 USB_ID

81 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

82 IOVDD_5 Digital IO power supply 5.

83 VSS Ground.

84 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

85 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

86 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

87 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

88 PD9 LCD_SEG28 EBI_CS0 #0/1/2

89 PD10 LCD_SEG29 EBI_CS1 #0/1/2

90 PD11 LCD_SEG30 EBI_CS2 #0/1/2

91 PD12 LCD_SEG31 EBI_CS3 #0/1/2

92 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

93 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

94 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

LES_ALTEX5 #0
95 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

US0_RX #3
CMU_CLK1 #2
96 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

LQFP100 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

US0_TX #3 LES_ALTEX7 #0
97 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

98 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

99 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

100 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.20.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.59. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF8 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC2
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC3
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3
in half duplex communication.

U1_RX PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PF10 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.20.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG980 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.60. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B — PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C — — — — PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D — — — PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 — — PF2 PF1 PF0

5.20.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG980 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2
PD3 OUT2
-

PD6 + OUT1ALT
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.40. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.21 EFM32LG990 (BGA112)

5.21.1 Pinout

The EFM32LG990 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.41. EFM32LG990 Pinout (top view, not to scale)

Table 5.61. Device Pinout

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD10 LCD_SEG29 EBI_CS1 #0/1/2

A6 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A7 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

A8 PF12 USB_ID

A9 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

A10 PF10 U1_TX #1 USB_DM

A11 PF11 U1_RX #1 USB_DP

B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD11 LCD_SEG30 EBI_CS2 #0/1/2

B6 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B7 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

B8 USB_VBUS USB 5.0 V VBUS input.

B9 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

B10 USB_VREGI Input to internal 3.3V USB regulator

B11 USB_VREGO Output and decoupling for internal 3.3V USB regulator

CMU_CLK1 #0
C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 PD12 LCD_SEG31 EBI_CS3 #0/1/2

C6 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

C7 VSS Ground.

ACMP1_O #0
C8 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

C9 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

C10 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

C11 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

LES_ALTEX2 #0
D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

CMU_CLK0 #0
D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D4 VSS Ground.

D5 IOVDD_6 Digital IO power supply 6.

D6 PD9 LCD_SEG28 EBI_CS0 #0/1/2

D7 IOVDD_5 Digital IO power supply 5.

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
D8 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

D9 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

D10 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
D11 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

ETM_TCLK #3
E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E4 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
E8 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

TIM3_CC0 #1 U0_TX #1
E9 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
E10 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

E11 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

F1 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

F2 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

LCD_SEG20/
F3 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
F4 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

F8 VDD_DREG Power supply for on-chip voltage regulator.

F9 VSS_DREG Ground for on-chip voltage regulator.

F10 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
F11 DECOUPLE
pin.

LCD_SEG22/
G1 PB5 EBI_A21 #0/1/2 US2_CLK #1
LCD_COM6

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LCD_SEG23/
G2 PB6 EBI_A22 #0/1/2 US2_CS #1
LCD_COM7

G3 VSS Ground.

G4 IOVDD_0 Digital IO power supply 0.

G8 IOVDD_4 Digital IO power supply 4.

G9 VSS Ground.

LEU1_TX #0 LES_CH6 #0
G10 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

LEU1_RX #0 LES_CH7 #0
G11 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
H1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH2
DAC0_OUT0ALT
H2 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

H3 PD14 I2C0_SDA #3

H4 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

H5 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

H6 VSS Ground.

H7 IOVDD_3 Digital IO power supply 3.

H8 PD8 BU_VIN CMU_CLK1 #1

ADC0_CH5
H9 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
H10 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
H11 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
J1 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
J2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

J3 PD15 I2C0_SCL #3

J4 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

J5 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

J6 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

J7 PB9 EBI_A03 #0/1/2 U1_TX #2

J8 PB10 EBI_A04 #0/1/2 U1_RX #2

USB_DMPU #0
J9 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

ADC0_CH3
J10 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

ADC0_CH4
J11 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

US0_TX #4
K1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
K2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

K3 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

K4 VSS Ground.

K5 PA11 LCD_SEG39 EBI_HSNC #0/1/2

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
K6 RESETn
during reset, and let the internal pull-up ensure that reset is released.

K7 AVSS_1 Analog ground 1.

K8 AVDD_2 Analog power supply 2.

K9 AVDD_1 Analog power supply 1.

K10 AVSS_0 Analog ground 0.

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
K11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

US0_RX #4
L1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
L2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

L3 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

L4 IOVDD_1 Digital IO power supply 1.

DAC0_OUT0 / TIM1_CC2 #3 LE-

L5 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
L6 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

L7 AVSS_2 Analog ground 2.

US0_CLK #4/5
L8 PB13 HFXTAL_P
LEU0_TX #1

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 EFM32LG Data Sheet
Pin Definitions

BGA112 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

US0_CS #4/5
L9 PB14 HFXTAL_N
LEU0_RX #1

L10 AVDD_0 Analog power supply 0.

ADC0_CH0
DAC0_OUT0ALT
L11 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

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 EFM32LG Data Sheet
Pin Definitions

5.21.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.62. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT /
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP_OUT0A PC0 PC1 PC2 PC3 PD0
OPAMP alternative output for channel 0.
LT

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 /OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT /
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP_OUT1A PD1
OPAMP alternative output for channel 1.
LT

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of reset,
and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of reset,
and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PD1 PD2 Note that this function is not enabled after reset, and
must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready Con-

EBI_ARDY PF2 PF2 PF2
trol input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchroni-

EBI_VSNC PA10 PA10 PA10
zation pin.

EBI_WEn PF8 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster, con-
LCD_BCAP_N PA13
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.

LCD_BEXT PA14 An external LCD voltage may also be applied to this

pin if the booster is not enabled.

If AVDD is used directly as the LCD supply voltage,

this pin may be left unconnected or used as a GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are

LCD_SEG10 PE14
controlled by SEGEN2.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 11. Segments 8, 9, 10 and 11 are

LCD_SEG11 PE15
controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LEUART0 Transmit output. Also used as receive in-

LEU0_TX PD4 PB13 PE14 PF0 PF2
put in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive in-

LEU1_TX PC6 PA5
put in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) nega-

LFXTAL_N PB8 tive pin. Also used as an optional external clock in-
put pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC2
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC3
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PF5 PC4 PF5
nel 2.

TIM1_CC0 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

TIM1_CC1 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PE12 PB2 PB11 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 UART0 Receive input.

UART0 Transmit output. Also used as receive input

U0_TX PF6 PE0 PA3
in half duplex communication.

U1_RX PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive input

U1_TX PF10 PB9 PE2
in half duplex communication.

US0_CLK PE12 PE5 PC9 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_V
USB_VBUS USB 5 V VBUS input.
BUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_V
USB_VREGI USB Input to internal 3.3 V regulator
REGI

USB_V USB Decoupling for internal 3.3 V USB regulator

USB_VREGO
REGO and regulator output

5.21.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG990 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.63. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C — — — — PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 — — PF2 PF1 PF0

5.21.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG990 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2
PD3 OUT2
-

PD6 + OUT1ALT
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.42. Opamp Pinout

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 EFM32LG Data Sheet
Pin Definitions

5.22 EFM32LG995 (BGA120)

5.22.1 Pinout

The EFM32LG995 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-
ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.

Figure 5.43. EFM32LG995 Pinout (top view, not to scale)

Table 5.64. Device Pinout

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A1 PE15 LCD_SEG11 EBI_AD07 #0/1/2 TIM3_CC1 #0 LEU0_RX #2

A2 PE14 LCD_SEG10 EBI_AD06 #0/1/2 TIM3_CC0 #0 LEU0_TX #2

US0_RX #3
CMU_CLK1 #2
A3 PE12 LCD_SEG8 EBI_AD04 #0/1/2 TIM1_CC2 #1 US0_CLK #0
LES_ALTEX6 #0
I2C0_SDA #6

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

A4 PE9 LCD_SEG5 EBI_AD01 #0/1/2 PCNT2_S1IN #1

A5 PD11 LCD_SEG30 EBI_CS2 #0/1/2

A6 PD9 LCD_SEG28 EBI_CS0 #0/1/2

A7 PF7 LCD_SEG25 EBI_BL1 #0/1/2 TIM0_CC1 #2 U0_RX #0

A8 PF5 LCD_SEG3 EBI_REn #0/2 TIM0_CDTI2 #2/5 USB_VBUSEN #0 PRS_CH2 #1

A9 PF4 LCD_SEG2 EBI_WEn #0/2 TIM0_CDTI1 #2/5 PRS_CH1 #1

ACMP1_O #0
A10 PF2 LCD_SEG0 EBI_ARDY #0/1/2 TIM0_CC2 #5 LEU0_TX #4 DBG_SWO #0
GPIO_EM4WU4

A11 USB_VREGI Input to internal 3.3 V USB regulator

A12 USB_VREGO Output and decoupling for internal 3.3 V USB regulator

A13 PF11 U1_RX #1 USB_DP

B1 PA15 LCD_SEG12 EBI_AD08 #0/1/2 TIM3_CC2 #0

US0_TX #3 LES_ALTEX7 #0
B2 PE13 LCD_SEG9 EBI_AD05 #0/1/2 US0_CS #0 ACMP0_O #0
I2C0_SCL #6 GPIO_EM4WU5

LES_ALTEX5 #0
B3 PE11 LCD_SEG7 EBI_AD03 #0/1/2 TIM1_CC1 #1 US0_RX #0
BOOT_RX

B4 PE8 LCD_SEG4 EBI_AD00 #0/1/2 PCNT2_S0IN #1 PRS_CH3 #1

B5 PD12 LCD_SEG31 EBI_CS3 #0/1/2

B6 PD10 LCD_SEG29 EBI_CS1 #0/1/2

B7 PF8 LCD_SEG26 EBI_WEn #1 TIM0_CC2 #2 ETM_TCLK #1

B8 PF6 LCD_SEG24 EBI_BL0 #0/1/2 TIM0_CC0 #2 U0_TX #0

PRS_CH0 #1
B9 PF3 LCD_SEG1 EBI_ALE #0 TIM0_CDTI0 #2/5
ETM_TD3 #1

US1_CS #2 DBG_SWDIO
TIM0_CC1 #5 LE-
B10 PF1 LEU0_RX #3 #0/1/2/3
TIM0_OUT1 #2
I2C0_SCL #5 GPIO_EM4WU3

B11 PF12 USB_ID

B12 USB_VBUS USB 5.0 V VBUS input.

B13 PF10 U1_TX #1 USB_DM

CMU_CLK1 #0
C1 PA1 LCD_SEG14 EBI_AD10 #0/1/2 TIM0_CC1 #0/1 I2C0_SCL #0
PRS_CH1 #0

LEU0_RX #4 PRS_CH0 #0
C2 PA0 LCD_SEG13 EBI_AD09 #0/1/2 TIM0_CC0 #0/1/4
I2C0_SDA #0 GPIO_EM4WU0

C3 PE10 LCD_SEG6 EBI_AD02 #0/1/2 TIM1_CC0 #1 US0_TX #0 BOOT_TX

C4 PD13 ETM_TD1 #1

C5 VSS Ground.

C6 IOVDD_0 Digital IO power supply 0.

C7 PF9 LCD_SEG27 EBI_REn #1 ETM_TD0 #1

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

C8 VSS Ground.

C9 IOVDD_1 Digital IO power supply 1.

US1_CLK #2
TIM0_CC0 #5 LE- DBG_SWCLK
C10 PF0 LEU0_TX #3
TIM0_OUT0 #2 #0/1/2/3
I2C0_SDA #5

C11 PE4 LCD_COM0 EBI_A11 #0/1/2 US0_CS #1

ACMP1_CH6
TIM0_CDTI1 #1/3
DAC0_OUT1ALT US0_CS #3 U0_TX
C12 PC14 TIM1_CC1 #0 LES_CH14 #0
#2/ #3
PCNT0_S1IN #0
OPAMP_OUT1ALT

ACMP1_CH7
DAC0_OUT1ALT TIM0_CDTI2 #1/3 US0_CLK #3 LES_CH15 #0
C13 PC15
#3/ TIM1_CC2 #0 U0_RX #3 DBG_SWO #1
OPAMP_OUT1ALT

LES_ALTEX2 #0
D1 PA3 LCD_SEG16 EBI_AD12 #0/1/2 TIM0_CDTI0 #0 U0_TX #2
ETM_TD1 #3

CMU_CLK0 #0
D2 PA2 LCD_SEG15 EBI_AD11 #0/1/2 TIM0_CC2 #0/1
ETM_TD0 #3

D3 PB15 ETM_TD2 #1

D11 PE5 LCD_COM1 EBI_A12 #0/1/2 US0_CLK #1

ACMP1_CH4
DAC0_OUT1ALT CMU_CLK0 #1
D12 PC12 U1_TX #0
#0/ LES_CH12 #0
OPAMP_OUT1ALT

ACMP1_CH5 TIM0_CDTI0 #1/3

DAC0_OUT1ALT TIM1_CC0 #0
D13 PC13 U1_RX #0 LES_CH13 #0
#1/ TIM1_CC2 #4
OPAMP_OUT1ALT PCNT0_S0IN #0

ETM_TCLK #3
E1 PA6 LCD_SEG19 EBI_AD15 #0/1/2 LEU1_RX #1
GPIO_EM4WU1

LES_ALTEX4 #0
E2 PA5 LCD_SEG18 EBI_AD14 #0/1/2 TIM0_CDTI2 #0 LEU1_TX #1
ETM_TD3 #3

LES_ALTEX3 #0
E3 PA4 LCD_SEG17 EBI_AD13 #0/1/2 TIM0_CDTI1 #0 U0_RX #2
ETM_TD2 #3

E11 PE6 LCD_COM2 EBI_A13 #0/1/2 US0_RX #1

E12 PC10 ACMP1_CH2 EBI_A10 #1/2 TIM2_CC2 #2 US0_RX #2 LES_CH10 #0

E13 PC11 ACMP1_CH3 EBI_ALE #1/2 US0_TX #2 LES_CH11 #0

F1 PB0 LCD_SEG32 EBI_A16 #0/1/2 TIM1_CC0 #2

F2 PB1 LCD_SEG33 EBI_A17 #0/1/2 TIM1_CC1 #2

F3 PB2 LCD_SEG34 EBI_A18 #0/1/2 TIM1_CC2 #2

F11 PE7 LCD_COM3 EBI_A14 #0/1/2 US0_TX #1

F12 PC8 ACMP1_CH0 EBI_A15 #0/1/2 TIM2_CC0 #2 US0_CS #2 LES_CH8 #0

LES_CH9 #0
F13 PC9 ACMP1_CH1 EBI_A09 #1/2 TIM2_CC1 #2 US0_CLK #2
GPIO_EM4WU2

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

LCD_SEG20/
G1 PB3 EBI_A19 #0/1/2 PCNT1_S0IN #1 US2_TX #1
LCD_COM4

LCD_SEG21/
G2 PB4 EBI_A20 #0/1/2 PCNT1_S1IN #1 US2_RX #1
LCD_COM5

G3 IOVDD_2 Digital IO power supply 2.

TIM3_CC0 #1 U0_TX #1
G11 PE0 EBI_A07 #0/1/2
PCNT0_S0IN #1 I2C1_SDA #2

TIM3_CC1 #1 U0_RX #1
G12 PE1 EBI_A08 #0/1/2
PCNT0_S1IN #1 I2C1_SCL #2

G13 PE3 BU_STAT EBI_A10 #0 U1_RX #3 ACMP1_O #1

LCD_SEG22/
H1 PB5 EBI_A21 #0/1/2 US2_CLK #1
LCD_COM6

LCD_SEG23/
H2 PB6 EBI_A22 #0/1/2 US2_CS #1
LCD_COM7

H3 VSS Ground.

H11 VDD_DREG Power supply for on-chip voltage regulator.

H12 PE2 BU_VOUT EBI_A09 #0 TIM3_CC2 #1 U1_TX #3 ACMP0_O #1

LEU1_RX #0 LES_CH7 #0
H13 PC7 ACMP0_CH7 EBI_A06 #0/1/2
I2C0_SCL #2 ETM_TD0 #2

J1 PD14 I2C0_SDA #3

J2 PD15 I2C0_SCL #3

J3 VSS Ground.

J11 IOVDD_3 Digital IO power supply 3.

LEU1_TX #0 LES_CH6 #0
J12 PC6 ACMP0_CH6 EBI_A05 #0/1/2
I2C0_SDA #2 ETM_TCLK #2

Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this
J13 DECOUPLE
pin.

ACMP0_CH0
US0_TX #5
DAC0_OUT0ALT TIM0_CC1 #4 LES_CH0 #0
K1 PC0 EBI_A23 #0/1/2 US1_TX #0
#0/ PCNT0_S0IN #2 PRS_CH2 #0
I2C0_SDA #4
OPAMP_OUT0ALT

ACMP0_CH1
US0_RX #5
DAC0_OUT0ALT TIM0_CC2 #4 LES_CH1 #0
K2 PC1 EBI_A24 #0/1/2 US1_RX #0
#1/ PCNT0_S1IN #2 PRS_CH3 #0
I2C0_SCL #4
OPAMP_OUT0ALT

K3 IOVDD_4 Digital IO power supply 4.

K11 VSS Ground.

K12 VSS Ground.

K13 PD8 BU_VIN CMU_CLK1 #1

ACMP0_CH2
DAC0_OUT0ALT
L1 PC2 EBI_A25 #0/1/2 TIM0_CDTI0 #4 US2_TX #0 LES_CH2 #0
#2/
OPAMP_OUT0ALT

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ACMP0_CH3
DAC0_OUT0ALT EBI_NANDREn
L2 PC3 TIM0_CDTI1 #4 US2_RX #0 LES_CH3 #0
#3/ #0/1/2
OPAMP_OUT0ALT

L3 PA7 LCD_SEG35 EBI_CSTFT #0/1/2

L4 IOVDD_5 Digital IO power supply 5.

L5 VSS Ground.

L6 VSS Ground.

L7 IOVDD_6 Digital IO power supply 6.

L8 PB9 EBI_A03 #0/1/2 U1_TX #2

L9 PB10 EBI_A04 #0/1/2 U1_RX #2

ADC0_CH0
DAC0_OUT0ALT
L10 PD0 #4/ PCNT2_S0IN #0 US1_TX #1
OPAMP_OUT0ALT
OPAMP_OUT2 #1

ADC0_CH1
DAC0_OUT1ALT TIM0_CC0 #3
L11 PD1 US1_RX #1 DBG_SWO #2
#4/ PCNT2_S1IN #0
OPAMP_OUT1ALT

ADC0_CH4
L12 PD4 LEU0_TX #0 ETM_TD2 #0/2
OPAMP_P2

CMU_CLK0 #2
ADC0_CH7 / TIM1_CC1 #4 LE-
US1_TX #2 LES_ALTEX1 #0
L13 PD7 DAC0_N1 / TIM0_OUT1 #0
I2C0_SCL #1 ACMP1_O #2
OPAMP_N1 PCNT0_S1IN #3
ETM_TCLK #0

US0_TX #4
M1 PB7 LFXTAL_P TIM1_CC0 #3
US1_CLK #0

ACMP0_CH4 / TIM0_CDTI2 #4 LE-

US2_CLK #0
M2 PC4 DAC0_P0 / EBI_A26 #0/1/2 TIM0_OUT0 #3 LES_CH4 #0
I2C1_SDA #0
OPAMP_P0 PCNT1_S0IN #0

M3 PA8 LCD_SEG36 EBI_DCLK #0/1/2 TIM2_CC0 #0

M4 PA10 LCD_SEG38 EBI_VSNC #0/1/2 TIM2_CC2 #0

M5 PA13 LCD_BCAP_N EBI_A01 #0/1/2 TIM2_CC1 #1

M6 PA14 LCD_BEXT EBI_A02 #0/1/2 TIM2_CC2 #1

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low
M7 RESETn
during reset, and let the internal pull-up ensure that reset is released.

M8 AVSS_1 Analog ground 1.

M9 AVDD_2 Analog power supply 2.

M10 AVDD_1 Analog power supply 1.

M11 AVSS_0 Analog ground 0.

ADC0_CH3
M12 PD3 TIM0_CC2 #3 US1_CS #1 ETM_TD1 #0/2
OPAMP_N2

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 EFM32LG Data Sheet
Pin Definitions

BGA120 Pin# and

Pin Alternate Functionality / Description
Name

Pin # Pin Name Analog EBI Timers Communication Other

ADC0_CH6 / TIM1_CC0 #4 LE- LES_ALTEX0 #0

US1_RX #2
M13 PD6 DAC0_P1 / TIM0_OUT0 #0 ACMP0_O #2
I2C0_SDA #1
OPAMP_P1 PCNT0_S0IN #3 ETM_TD0 #0

US0_RX #4
N1 PB8 LFXTAL_N TIM1_CC1 #3
US1_CS #0

ACMP0_CH5 /
EBI_NANDWEn LETIM0_OUT1 #3 US2_CS #0
N2 PC5 DAC0_N0 / LES_CH5 #0
#0/1/2 PCNT1_S1IN #0 I2C1_SCL #0
OPAMP_N0

N3 PA9 LCD_SEG37 EBI_DTEN #0/1/2 TIM2_CC1 #0

N4 PA11 LCD_SEG39 EBI_HSNC #0/1/2

N5 PA12 LCD_BCAP_P EBI_A00 #0/1/2 TIM2_CC0 #1

DAC0_OUT0 / TIM1_CC2 #3 LE-

N6 PB11 I2C1_SDA #1
OPAMP_OUT0 TIM0_OUT0 #1

DAC0_OUT1 /
N7 PB12 LETIM0_OUT1 #1 I2C1_SCL #1
OPAMP_OUT1

N8 AVSS_2 Analog ground 2.

US0_CLK #4/5
N9 PB13 HFXTAL_P
LEU0_TX #1

US0_CS #4/5
N10 PB14 HFXTAL_N
LEU0_RX #1

N11 AVDD_0 Analog power supply 0.

USB_DMPU #0
N12 PD2 ADC0_CH2 EBI_A27 #0/1/2 TIM0_CC1 #3 DBG_SWO #3
US1_CLK #1

ADC0_CH5
N13 PD5 LEU0_RX #0 ETM_TD3 #0/2
OPAMP_OUT2 #0

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 EFM32LG Data Sheet
Pin Definitions

5.22.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.

Table 5.65. Alternate Functionality Overview

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

ACMP0_CH0 PC0 Analog comparator ACMP0, channel 0.

ACMP0_CH1 PC1 Analog comparator ACMP0, channel 1.

ACMP0_CH2 PC2 Analog comparator ACMP0, channel 2.

ACMP0_CH3 PC3 Analog comparator ACMP0, channel 3.

ACMP0_CH4 PC4 Analog comparator ACMP0, channel 4.

ACMP0_CH5 PC5 Analog comparator ACMP0, channel 5.

ACMP0_CH6 PC6 Analog comparator ACMP0, channel 6.

ACMP0_CH7 PC7 Analog comparator ACMP0, channel 7.

ACMP0_O PE13 PE2 PD6 Analog comparator ACMP0, digital output.

ACMP1_CH0 PC8 Analog comparator ACMP1, channel 0.

ACMP1_CH1 PC9 Analog comparator ACMP1, channel 1.

ACMP1_CH2 PC10 Analog comparator ACMP1, channel 2.

ACMP1_CH3 PC11 Analog comparator ACMP1, channel 3.

ACMP1_CH4 PC12 Analog comparator ACMP1, channel 4.

ACMP1_CH5 PC13 Analog comparator ACMP1, channel 5.

ACMP1_CH6 PC14 Analog comparator ACMP1, channel 6.

ACMP1_CH7 PC15 Analog comparator ACMP1, channel 7.

ACMP1_O PF2 PE3 PD7 Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel

ADC0_CH0 PD0
number 0.

Analog to digital converter ADC0, input channel

ADC0_CH1 PD1
number 1.

Analog to digital converter ADC0, input channel

ADC0_CH2 PD2
number 2.

Analog to digital converter ADC0, input channel

ADC0_CH3 PD3
number 3.

Analog to digital converter ADC0, input channel

ADC0_CH4 PD4
number 4.

Analog to digital converter ADC0, input channel

ADC0_CH5 PD5
number 5.

Analog to digital converter ADC0, input channel

ADC0_CH6 PD6
number 6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

Analog to digital converter ADC0, input channel

ADC0_CH7 PD7
number 7.

BOOT_RX PE11 Bootloader RX.

BOOT_TX PE10 Bootloader TX.

Backup Power Domain status, whether or not the

BU_STAT PE3
system is in backup mode

BU_VIN PD8 Battery input for Backup Power Domain

BU_VOUT PE2 Power output for Backup Power Domain

CMU_CLK0 PA2 PC12 PD7 Clock Management Unit, clock output number 0.

CMU_CLK1 PA1 PD8 PE12 Clock Management Unit, clock output number 1.

DAC0_OUT0 / Digital to Analog Converter DAC0_OUT0 /OPAMP

PB11
OPAMP_OUT0 output channel number 0.

DAC0_OUT0ALT / Digital to Analog Converter DAC0_OUT0ALT /

PC0 PC1 PC2 PC3 PD0
OPAMP_OUT0ALT OPAMP alternative output for channel 0.

DAC0_OUT1 / Digital to Analog Converter DAC0_OUT1 / OPAMP

PB12
OPAMP_OUT1 output channel number 1.

DAC0_OUT1ALT / Digital to Analog Converter DAC0_OUT1ALT /

PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1ALT OPAMP alternative output for channel 1.

Debug-interface Serial Wire clock input.

DBG_SWCLK PF0 PF0 PF0 PF0 Note that this function is enabled to pin out of re-
set, and has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO PF1 PF1 PF1 PF1 Note that this function is enabled to pin out of re-
set, and has a built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO PF2 PC15 PD1 PD2 Note that this function is not enabled after reset,
and must be enabled by software to be used.

EBI_A00 PA12 PA12 PA12 External Bus Interface (EBI) address output pin 00.

EBI_A01 PA13 PA13 PA13 External Bus Interface (EBI) address output pin 01.

EBI_A02 PA14 PA14 PA14 External Bus Interface (EBI) address output pin 02.

EBI_A03 PB9 PB9 PB9 External Bus Interface (EBI) address output pin 03.

EBI_A04 PB10 PB10 PB10 External Bus Interface (EBI) address output pin 04.

EBI_A05 PC6 PC6 PC6 External Bus Interface (EBI) address output pin 05.

EBI_A06 PC7 PC7 PC7 External Bus Interface (EBI) address output pin 06.

EBI_A07 PE0 PE0 PE0 External Bus Interface (EBI) address output pin 07.

EBI_A08 PE1 PE1 PE1 External Bus Interface (EBI) address output pin 08.

EBI_A09 PE2 PC9 PC9 External Bus Interface (EBI) address output pin 09.

EBI_A10 PE3 PC10 PC10 External Bus Interface (EBI) address output pin 10.

EBI_A11 PE4 PE4 PE4 External Bus Interface (EBI) address output pin 11.

EBI_A12 PE5 PE5 PE5 External Bus Interface (EBI) address output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

EBI_A13 PE6 PE6 PE6 External Bus Interface (EBI) address output pin 13.

EBI_A14 PE7 PE7 PE7 External Bus Interface (EBI) address output pin 14.

EBI_A15 PC8 PC8 PC8 External Bus Interface (EBI) address output pin 15.

EBI_A16 PB0 PB0 PB0 External Bus Interface (EBI) address output pin 16.

EBI_A17 PB1 PB1 PB1 External Bus Interface (EBI) address output pin 17.

EBI_A18 PB2 PB2 PB2 External Bus Interface (EBI) address output pin 18.

EBI_A19 PB3 PB3 PB3 External Bus Interface (EBI) address output pin 19.

EBI_A20 PB4 PB4 PB4 External Bus Interface (EBI) address output pin 20.

EBI_A21 PB5 PB5 PB5 External Bus Interface (EBI) address output pin 21.

EBI_A22 PB6 PB6 PB6 External Bus Interface (EBI) address output pin 22.

EBI_A23 PC0 PC0 PC0 External Bus Interface (EBI) address output pin 23.

EBI_A24 PC1 PC1 PC1 External Bus Interface (EBI) address output pin 24.

EBI_A25 PC2 PC2 PC2 External Bus Interface (EBI) address output pin 25.

EBI_A26 PC4 PC4 PC4 External Bus Interface (EBI) address output pin 26.

EBI_A27 PD2 PD2 PD2 External Bus Interface (EBI) address output pin 27.

External Bus Interface (EBI) address and data in-

EBI_AD00 PE8 PE8 PE8
put / output pin 00.

External Bus Interface (EBI) address and data in-

EBI_AD01 PE9 PE9 PE9
put / output pin 01.

External Bus Interface (EBI) address and data in-

EBI_AD02 PE10 PE10 PE10
put / output pin 02.

External Bus Interface (EBI) address and data in-

EBI_AD03 PE11 PE11 PE11
put / output pin 03.

External Bus Interface (EBI) address and data in-

EBI_AD04 PE12 PE12 PE12
put / output pin 04.

External Bus Interface (EBI) address and data in-

EBI_AD05 PE13 PE13 PE13
put / output pin 05.

External Bus Interface (EBI) address and data in-

EBI_AD06 PE14 PE14 PE14
put / output pin 06.

External Bus Interface (EBI) address and data in-

EBI_AD07 PE15 PE15 PE15
put / output pin 07.

External Bus Interface (EBI) address and data in-

EBI_AD08 PA15 PA15 PA15
put / output pin 08.

External Bus Interface (EBI) address and data in-

EBI_AD09 PA0 PA0 PA0
put / output pin 09.

External Bus Interface (EBI) address and data in-

EBI_AD10 PA1 PA1 PA1
put / output pin 10.

External Bus Interface (EBI) address and data in-

EBI_AD11 PA2 PA2 PA2
put / output pin 11.

External Bus Interface (EBI) address and data in-

EBI_AD12 PA3 PA3 PA3
put / output pin 12.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

External Bus Interface (EBI) address and data in-

EBI_AD13 PA4 PA4 PA4
put / output pin 13.

External Bus Interface (EBI) address and data in-

EBI_AD14 PA5 PA5 PA5
put / output pin 14.

External Bus Interface (EBI) address and data in-

EBI_AD15 PA6 PA6 PA6
put / output pin 15.

External Bus Interface (EBI) Address Latch Enable

EBI_ALE PF3 PC11 PC11
output.

External Bus Interface (EBI) Hardware Ready

EBI_ARDY PF2 PF2 PF2
Control input.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL0 PF6 PF6 PF6
0.

External Bus Interface (EBI) Byte Lane/Enable pin

EBI_BL1 PF7 PF7 PF7
1.

EBI_CS0 PD9 PD9 PD9 External Bus Interface (EBI) Chip Select output 0.

EBI_CS1 PD10 PD10 PD10 External Bus Interface (EBI) Chip Select output 1.

EBI_CS2 PD11 PD11 PD11 External Bus Interface (EBI) Chip Select output 2.

EBI_CS3 PD12 PD12 PD12 External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Chip Select output

EBI_CSTFT PA7 PA7 PA7
TFT.

EBI_DCLK PA8 PA8 PA8 External Bus Interface (EBI) TFT Dot Clock pin.

EBI_DTEN PA9 PA9 PA9 External Bus Interface (EBI) TFT Data Enable pin.

External Bus Interface (EBI) TFT Horizontal Syn-

EBI_HSNC PA11 PA11 PA11
chronization pin.

External Bus Interface (EBI) NAND Read Enable

EBI_NANDREn PC3 PC3 PC3
output.

External Bus Interface (EBI) NAND Write Enable

EBI_NANDWEn PC5 PC5 PC5
output.

EBI_REn PF5 PF9 PF5 External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) TFT Vertical Synchro-

EBI_VSNC PA10 PA10 PA10
nization pin.

EBI_WEn PF4 PF8 PF4 External Bus Interface (EBI) Write Enable output.

ETM_TCLK PD7 PF8 PC6 PA6 Embedded Trace Module ETM clock .

ETM_TD0 PD6 PF9 PC7 PA2 Embedded Trace Module ETM data 0.

ETM_TD1 PD3 PD13 PD3 PA3 Embedded Trace Module ETM data 1.

ETM_TD2 PD4 PB15 PD4 PA4 Embedded Trace Module ETM data 2.

ETM_TD3 PD5 PF3 PD5 PA5 Embedded Trace Module ETM data 3.

GPIO_EM4WU0 PA0 Pin can be used to wake the system up from EM4

GPIO_EM4WU1 PA6 Pin can be used to wake the system up from EM4

GPIO_EM4WU2 PC9 Pin can be used to wake the system up from EM4

GPIO_EM4WU3 PF1 Pin can be used to wake the system up from EM4

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

GPIO_EM4WU4 PF2 Pin can be used to wake the system up from EM4

GPIO_EM4WU5 PE13 Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as

HFXTAL_N PB14
external optional clock input pin.

HFXTAL_P PB13 High Frequency Crystal positive pin.

I2C0_SCL PA1 PD7 PC7 PD15 PC1 PF1 PE13 I2C0 Serial Clock Line input / output.

I2C0_SDA PA0 PD6 PC6 PD14 PC0 PF0 PE12 I2C0 Serial Data input / output.

I2C1_SCL PC5 PB12 PE1 I2C1 Serial Clock Line input / output.

I2C1_SDA PC4 PB11 PE0 I2C1 Serial Data input / output.

LCD voltage booster (optional), boost capacitor,

negative pin. If using the LCD voltage booster,
LCD_BCAP_N PA13
connect a 22 nF capacitor between LCD_BCAP_N
and LCD_BCAP_P.

LCD voltage booster (optional), boost capacitor,

positive pin. If using the LCD voltage booster, con-
LCD_BCAP_P PA12
nect a 22 nF capacitor between LCD_BCAP_N
and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If us-

ing the LCD voltage booster, connect a 1 uF ca-
pacitor between this pin and VSS.

An external LCD voltage may also be applied to

LCD_BEXT PA14
this pin if the booster is not enabled.

If AVDD is used directly as the LCD supply volt-

age, this pin may be left unconnected or used as a
GPIO.

LCD_COM0 PE4 LCD driver common line number 0.

LCD_COM1 PE5 LCD driver common line number 1.

LCD_COM2 PE6 LCD driver common line number 2.

LCD_COM3 PE7 LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are

LCD_SEG0 PF2
controlled by SEGEN0.

LCD segment line 1. Segments 0, 1, 2 and 3 are

LCD_SEG1 PF3
controlled by SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are

LCD_SEG2 PF4
controlled by SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are

LCD_SEG3 PF5
controlled by SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are

LCD_SEG4 PE8
controlled by SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are

LCD_SEG5 PE9
controlled by SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are

LCD_SEG6 PE10
controlled by SEGEN1.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 7. Segments 4, 5, 6 and 7 are

LCD_SEG7 PE11
controlled by SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are

LCD_SEG8 PE12
controlled by SEGEN2.

LCD segment line 9. Segments 8, 9, 10 and 11 are

LCD_SEG9 PE13
controlled by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11

LCD_SEG10 PE14
are controlled by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11

LCD_SEG11 PE15
are controlled by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15

LCD_SEG12 PA15
are controlled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15

LCD_SEG13 PA0
are controlled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15

LCD_SEG14 PA1
are controlled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15

LCD_SEG15 PA2
are controlled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19

LCD_SEG16 PA3
are controlled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19

LCD_SEG17 PA4
are controlled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19

LCD_SEG18 PA5
are controlled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19

LCD_SEG19 PA6
are controlled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23

LCD_SEG20/
PB3 are controlled by SEGEN5. This pin may also be
LCD_COM4
used as LCD COM line 4

LCD segment line 21. Segments 20, 21, 22 and 23

LCD_SEG21/
PB4 are controlled by SEGEN5. This pin may also be
LCD_COM5
used as LCD COM line 5

LCD segment line 22. Segments 20, 21, 22 and 23

LCD_SEG22/
PB5 are controlled by SEGEN5. This pin may also be
LCD_COM6
used as LCD COM line 6

LCD segment line 23. Segments 20, 21, 22 and 23

LCD_SEG23/
PB6 are controlled by SEGEN5. This pin may also be
LCD_COM7
used as LCD COM line 7

LCD segment line 24. Segments 24, 25, 26 and 27

LCD_SEG24 PF6
are controlled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27

LCD_SEG25 PF7
are controlled by SEGEN6.

LCD segment line 26. Segments 24, 25, 26 and 27

LCD_SEG26 PF8
are controlled by SEGEN6.

LCD segment line 27. Segments 24, 25, 26 and 27

LCD_SEG27 PF9
are controlled by SEGEN6.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LCD segment line 28. Segments 28, 29, 30 and 31

LCD_SEG28 PD9
are controlled by SEGEN7.

LCD segment line 29. Segments 28, 29, 30 and 31

LCD_SEG29 PD10
are controlled by SEGEN7.

LCD segment line 30. Segments 28, 29, 30 and 31

LCD_SEG30 PD11
are controlled by SEGEN7.

LCD segment line 31. Segments 28, 29, 30 and 31

LCD_SEG31 PD12
are controlled by SEGEN7.

LCD segment line 32. Segments 32, 33, 34 and 35

LCD_SEG32 PB0
are controlled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35

LCD_SEG33 PB1
are controlled by SEGEN8.

LCD segment line 34. Segments 32, 33, 34 and 35

LCD_SEG34 PB2
are controlled by SEGEN8.

LCD segment line 35. Segments 32, 33, 34 and 35

LCD_SEG35 PA7
are controlled by SEGEN8.

LCD segment line 36. Segments 36, 37, 38 and 39

LCD_SEG36 PA8
are controlled by SEGEN9.

LCD segment line 37. Segments 36, 37, 38 and 39

LCD_SEG37 PA9
are controlled by SEGEN9.

LCD segment line 38. Segments 36, 37, 38 and 39

LCD_SEG38 PA10
are controlled by SEGEN9.

LCD segment line 39. Segments 36, 37, 38 and 39

LCD_SEG39 PA11
are controlled by SEGEN9.

LES_ALTEX0 PD6 LESENSE alternate exite output 0.

LES_ALTEX1 PD7 LESENSE alternate exite output 1.

LES_ALTEX2 PA3 LESENSE alternate exite output 2.

LES_ALTEX3 PA4 LESENSE alternate exite output 3.

LES_ALTEX4 PA5 LESENSE alternate exite output 4.

LES_ALTEX5 PE11 LESENSE alternate exite output 5.

LES_ALTEX6 PE12 LESENSE alternate exite output 6.

LES_ALTEX7 PE13 LESENSE alternate exite output 7.

LES_CH0 PC0 LESENSE channel 0.

LES_CH1 PC1 LESENSE channel 1.

LES_CH2 PC2 LESENSE channel 2.

LES_CH3 PC3 LESENSE channel 3.

LES_CH4 PC4 LESENSE channel 4.

LES_CH5 PC5 LESENSE channel 5.

LES_CH6 PC6 LESENSE channel 6.

LES_CH7 PC7 LESENSE channel 7.

LES_CH8 PC8 LESENSE channel 8.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

LES_CH9 PC9 LESENSE channel 9.

LES_CH10 PC10 LESENSE channel 10.

LES_CH11 PC11 LESENSE channel 11.

LES_CH12 PC12 LESENSE channel 12.

LES_CH13 PC13 LESENSE channel 13.

LES_CH14 PC14 LESENSE channel 14.

LES_CH15 PC15 LESENSE channel 15.

LETIM0_OUT0 PD6 PB11 PF0 PC4 Low Energy Timer LETIM0, output channel 0.

LETIM0_OUT1 PD7 PB12 PF1 PC5 Low Energy Timer LETIM0, output channel 1.

LEU0_RX PD5 PB14 PE15 PF1 PA0 LEUART0 Receive input.

LEUART0 Transmit output. Also used as receive

LEU0_TX PD4 PB13 PE14 PF0 PF2
input in half duplex communication.

LEU1_RX PC7 PA6 LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive

LEU1_TX PC6 PA5
input in half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) neg-

LFXTAL_N PB8 ative pin. Also used as an optional external clock
input pin.

Low Frequency Crystal (typically 32.768 kHz) posi-

LFXTAL_P PB7
tive pin.

OPAMP_N0 /
PC5 Operational Amplifier 0 external negative input.
DAC0_N0

OPAMP_N1 /
PD7 Operational Amplifier 1 external negative input.
DAC0_N1

OPAMP_N2 PD3 Operational Amplifier 2 external negative input.

OPAMP_OUT2 PD5 PD0 Operational Amplifier 2 output.

OPAMP_P0 /
PC4 Operational Amplifier 0 external positive input.
DAC0_P0

OPAMP_P1 /
PD6 Operational Amplifier 1 external positive input.
DAC0_P1

OPAMP_P2 PD4 Operational Amplifier 2 external positive input.

PCNT0_S0IN PC13 PE0 PC0 PD6 Pulse Counter PCNT0 input number 0.

PCNT0_S1IN PC14 PE1 PC1 PD7 Pulse Counter PCNT0 input number 1.

PCNT1_S0IN PC4 PB3 Pulse Counter PCNT1 input number 0.

PCNT1_S1IN PC5 PB4 Pulse Counter PCNT1 input number 1.

PCNT2_S0IN PD0 PE8 Pulse Counter PCNT2 input number 0.

PCNT2_S1IN PD1 PE9 Pulse Counter PCNT2 input number 1.

PRS_CH0 PA0 PF3 Peripheral Reflex System PRS, channel 0.

PRS_CH1 PA1 PF4 Peripheral Reflex System PRS, channel 1.

PRS_CH2 PC0 PF5 Peripheral Reflex System PRS, channel 2.

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

PRS_CH3 PC1 PE8 Peripheral Reflex System PRS, channel 3.

TIM0_CC0 PA0 PA0 PF6 PD1 PA0 PF0 Timer 0 Capture Compare input / output channel 0.

TIM0_CC1 PA1 PA1 PF7 PD2 PC0 PF1 Timer 0 Capture Compare input / output channel 1.

TIM0_CC2 PA2 PA2 PF8 PD3 PC1 PF2 Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI0 PA3 PC13 PF3 PC13 PC2 PF3
nel 0.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI1 PA4 PC14 PF4 PC14 PC3 PF4
nel 1.

Timer 0 Complimentary Dead Time Insertion chan-

TIM0_CDTI2 PA5 PC15 PF5 PC15 PC4 PF5
nel 2.

TIM1_CC0 PC13 PE10 PB0 PB7 PD6 Timer 1 Capture Compare input / output channel 0.

TIM1_CC1 PC14 PE11 PB1 PB8 PD7 Timer 1 Capture Compare input / output channel 1.

TIM1_CC2 PC15 PE12 PB2 PB11 PC13 Timer 1 Capture Compare input / output channel 2.

TIM2_CC0 PA8 PA12 PC8 Timer 2 Capture Compare input / output channel 0.

TIM2_CC1 PA9 PA13 PC9 Timer 2 Capture Compare input / output channel 1.

TIM2_CC2 PA10 PA14 PC10 Timer 2 Capture Compare input / output channel 2.

TIM3_CC0 PE14 PE0 Timer 3 Capture Compare input / output channel 0.

TIM3_CC1 PE15 PE1 Timer 3 Capture Compare input / output channel 1.

TIM3_CC2 PA15 PE2 Timer 3 Capture Compare input / output channel 2.

U0_RX PF7 PE1 PA4 PC15 UART0 Receive input.

UART0 Transmit output. Also used as receive in-

U0_TX PF6 PE0 PA3 PC14
put in half duplex communication.

U1_RX PC13 PF11 PB10 PE3 UART1 Receive input.

UART1 Transmit output. Also used as receive in-

U1_TX PC12 PF10 PB9 PE2
put in half duplex communication.

US0_CLK PE12 PE5 PC9 PC15 PB13 PB13 USART0 clock input / output.

US0_CS PE13 PE4 PC8 PC14 PB14 PB14 USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX PE11 PE6 PC10 PE12 PB8 PC1 USART0 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART0 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US0_TX PE10 PE7 PC11 PE13 PB7 PC0
USART0 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US1_CLK PB7 PD2 PF0 USART1 clock input / output.

US1_CS PB8 PD3 PF1 USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX PC1 PD1 PD6 USART1 Synchronous mode Main Input / Secon-
dary Output (MISO).

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 EFM32LG Data Sheet
Pin Definitions

Alternate LOCATION

Functionality 0 1 2 3 4 5 6 Description

USART1 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US1_TX PC0 PD0 PD7
USART1 Synchronous mode Main Output / Secon-
dary Input (MOSI).

US2_CLK PC4 PB5 USART2 clock input / output.

US2_CS PC5 PB6 USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX PC3 PB4 USART2 Synchronous mode Main Input / Secon-
dary Output (MISO).

USART2 Asynchronous Transmit.Also used as re-

ceive input in half duplex communication.
US2_TX PC2 PB3
USART2 Synchronous mode Main Output / Secon-
dary Input (MOSI).

USB_DM PF10 USB D- pin.

USB_DMPU PD2 USB D- Pullup control.

USB_DP PF11 USB D+ pin.

USB_ID PF12 USB ID pin. Used in OTG mode.

USB_
USB_VBUS USB 5 V VBUS input.
VBUS

USB_VBUSEN PF5 USB 5 V VBUS enable.

USB_
USB_VREGI USB Input to internal 3.3 V regulator
VREGI

USB_
USB Decoupling for internal 3.3 V USB regulator
USB_VREGO VRE-
and regulator output
GO

5.22.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32LG995 are shown in the following table. Each GPIO port is organized as 16-bit ports indica-
ted by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.66. GPIO Pinout

Port Pin Pin Pin Pin Pin Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
15 14 13 12 11 10

Port A PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Port C PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Port D PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Port E PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Port F — — — PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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 EFM32LG Data Sheet
Pin Definitions

5.22.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32LG995 is shown in the following figure.
PB11
PB12
PC4 + OUT0ALT
PC0
OPA0
OUT0 PC1
PC5 -
PC2
+ PC3
PD4
OPA2 PC12
PD3 OUT2
- PC13
PC14
PD6 + OUT1ALT
PC15
OPA1
OUT1 PD0
PD7 -
PD1
PD5

Figure 5.44. Opamp Pinout

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 EFM32LG Data Sheet
BGA112 Package Specifications

6. BGA112 Package Specifications

6.1 BGA112 Package Dimensions

Rev: 97SPP01315A_X03_06Jun11
TOP VIEW BOTTOM VIEW

SIDE VIEW

Figure 6.1. BGA112

Note:
1. The dimensions in parenthesis are reference.
2. Datum 'C' and seating plane are defined by the crown of the solder balls.
3. All dimensions are in millimeters.

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 EFM32LG Data Sheet
BGA112 Package Specifications

6.2 BGA112 PCB Layout

a
e

Figure 6.2. BGA112 PCB Land Pattern

Table 6.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 0.35

b 0.80

d 8.00

e 8.00

a
e

Figure 6.3. BGA112 PCB Solder Mask

Table 6.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 0.48

b 0.80

d 8.00

e 8.00

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 EFM32LG Data Sheet
BGA112 Package Specifications

a
e

Figure 6.4. BGA112 PCB Stencil Design

Table 6.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 0.33

b 0.80

d 8.00

e 8.00

Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.

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 EFM32LG Data Sheet
BGA112 Package Specifications

6.3 BGA112 Package Marking

In the illustration below package fields and position are shown.

Figure 6.5. Example Chip Marking (Top View)

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 EFM32LG Data Sheet
BGA120 Package Specifications

7. BGA120 Package Specifications

7.1 BGA120 Package Dimensions

Rev: 97SPP01321A_XO1_06APR2011
Figure 7.1. BGA120

Note:
1. The dimensions in parenthesis are reference.
2. Datum "C" and seating plane are defined by the crown of the soldier balls.
3. All dimensions are in millimeters.

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 EFM32LG Data Sheet
BGA120 Package Specifications

7.2 BGA120 PCB Layout

a
e

Figure 7.2. BGA120 PCB Land Pattern

Table 7.1. BGA120 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 0.25

b 0.50

d 6.00

e 6.00

a
e

Figure 7.3. BGA120 PCB Solder Mask

Table 7.2. BGA120 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 0.35

b 0.50

d 6.00

e 6.00

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 EFM32LG Data Sheet
BGA120 Package Specifications

a
e

Figure 7.4. BGA120 PCB Stencil Design

Table 7.3. BGA120 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 0.25

b 0.50

d 6.00

e 6.00

Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.

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 EFM32LG Data Sheet
BGA120 Package Specifications

7.3 BGA120 Package Marking

In the illustration below package fields and position are shown.

Figure 7.5. Example Chip Marking (Top View)

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 EFM32LG Data Sheet
CSP81 Package Specifications

8. CSP81 Package Specifications

8.1 CSP81 Package Dimensions

Figure 8.1. CSP81

Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Primary datum “C” and seating plane are defined by the spherical crowns of the solder balls.
4. Dimension “b” is measured at the maximum solder bump diameter, parallel to primary datum “C”.
5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.

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 EFM32LG Data Sheet
CSP81 Package Specifications

Table 8.1. CSP81 (Dimensions in mm)

Symbol Min Nom Max

A 0.491 0.55 0.609

A1 0.17 — 0.23

A2 0.036 — 0.044

b 0.23 — 0.29

S 0.3075 0.31 0.3125

D 4.355 BSC.

E 4.275 BSC.

e 0.40 BSC.

D1 3.20 BSC.

E1 3.20 BSC.

n 81

aaa 0.05

bbb 0.10

ccc 0.075

ddd 0.15

eee 0.05

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 EFM32LG Data Sheet
CSP81 Package Specifications

8.2 CSP81 PCB Layout

Figure 8.2. CSP81 PCB Land Pattern

Table 8.2. CSP81 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol Dim. (mm)

X 0.20

C1 3.20

C2 3.20

E1 0.40

E2 0.40

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 EFM32LG Data Sheet
CSP81 Package Specifications

Figure 8.3. CSP81 PCB Solder Mask

Table 8.3. CSP81 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol Dim. (mm)

X 0.26

C1 3.20

C2 3.20

E1 0.40

E2 0.40

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 EFM32LG Data Sheet
CSP81 Package Specifications

Figure 8.4. CSP81 PCB Stencil Design

Table 8.4. CSP81 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol Dim. (mm)

X 0.20

C1 3.20

C2 3.20

E1 0.40

E2 0.40

Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.

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 EFM32LG Data Sheet
CSP81 Package Specifications

8.3 CSP81 Package Marking

In the illustration below package fields and position are shown.

Figure 8.5. Example Chip Marking (Top View)

8.4 CSP81 Environmental

WLCSP devices can be handled and soldered using industry standard surface mount assembly techniques. However, because WLCSP
devices are essentially a piece of silicon and are not encapsulated in plastic, they are susceptible to mechanical damage and may be
sensitive to light. When WLCSPs must be used in an environment exposed to light, it may be necessary to cover the top and sides
withan opaque material.

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 EFM32LG Data Sheet
LQFP100 Package Specifications

9. LQFP100 Package Specifications

9.1 LQFP100 Package Dimensions

Rev: 98A0100QP043_03MAY2007
Figure 9.1. LQFP100

Note:
1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H'
2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'.
3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include
mold mismatch and are determined at datum plane datum 'H'.
4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maxi-
mum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm.
5. Exact shape of each corner is optional.

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 EFM32LG Data Sheet
LQFP100 Package Specifications

Table 9.1. LQFP100 (Dimensions in mm)

SYMBOL MIN NOM MAX

total thickness A — — 1.6

stand off A1 0.05 — 0.15

mold thickness A2 1.35 1.4 1.45

lead width (plating) b 0.17 0.2 0.27

lead width b1 0.17 — 0.23

L/F thickness (plating) c 0.09 — 0.2

lead thickness c1 0.09 — 0.16

x D 16 BSC

y E 16 BSC

x D1 14 BSC
body size
y E1 14 BSC

lead pitch e 0.5 BSC

L 0.45 0.6 0.75

footprint L1 1 REF

θ 0º 3.5º 7º

θ1 0º — —

θ2 11º 12º 13º

θ3 11º 12º 13º

R1 0.08 — —

R1 0.08 — 0.2

S 0.2 — —

package edge tolerance aaa 0.2

lead edge tolerance bbb 0.2

coplanarity ccc 0.08

lead offset ddd 0.08

mold flatness eee 0.05

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 EFM32LG Data Sheet
LQFP100 Package Specifications

9.2 LQFP100 PCB Layout

p8 p7

p1 p6

e
c

p2 p5

p3 p4

Figure 9.2. LQFP100 PCB Land Pattern

Table 9.2. LQFP100 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number

a 1.45 P1 1 P6 75

b 0.30 P2 25 P7 76

c 0.50 P3 26 P8 100

d 15.40 P4 50

e 15.40 P5 51

e
c

Figure 9.3. LQFP100 PCB Solder Mask

Table 9.3. LQFP100 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 1.57

b 0.42

c 0.50

d 15.40

e 15.40

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 EFM32LG Data Sheet
LQFP100 Package Specifications

e
c

Figure 9.4. LQFP100 PCB Stencil Design

Table 9.4. LQFP100 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 1.35

b 0.20

c 0.50

d 15.40

e 15.40

Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.

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 EFM32LG Data Sheet
LQFP100 Package Specifications

9.3 LQFP100 Package Marking

In the illustration below package fields and position are shown.

Figure 9.5. Example Chip Marking (Top View)

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 EFM32LG Data Sheet
QFN64 Package Specifications

10. QFN64 Package Specifications

10.1 QFN64 Package Dimensions

49 64

48 1

Rev: 98SPP64048A_XO1_08MAR2011
33 16

32 17

m
m

Figure 10.1. QFN64

Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. Dimension L1
represents terminal full back from package edge up to 0.1 mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.

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 EFM32LG Data Sheet
QFN64 Package Specifications

Table 10.1. QFN64 (Dimensions in mm)

Symbol Min Nom Max

A 0.80 0.85 0.90

A1 0.00 — 0.05

A3 0.203 REF

b 0.20 0.25 0.30

D 9.00 BSC

E 9.00 BSC

D2 7.10 7.20 7.30

E2 7.10 7.20 7.30

e 0.50 BSC

L 0.40 0.45 0.50

L1 0.00 — 0.10

aaa 0.10

bbb 0.10

ccc 0.10

ddd 0.05

eee 0.08

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 EFM32LG Data Sheet
QFN64 Package Specifications

10.2 QFN64 PCB Layout

p8 p7

b p1 p6

p9 g e

c
p2 p5

p3 p4

f
d

Figure 10.2. QFN64 PCB Land Pattern

Table 10.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number

a 0.85 P1 1 P8 64

b 0.30 P2 16 P9 0

c 0.50 P3 17

d 8.90 P4 32

e 8.90 P5 33

f 7.20 P6 48

g 7.20 P7 49

g e

f
d

Figure 10.3. QFN64 PCB Solder Mask

Table 10.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol Dim. (mm) Symbol Dim. (mm)

a 0.97 e 8.90

b 0.42 f 7.32

c 0.50 g 7.32

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 EFM32LG Data Sheet
QFN64 Package Specifications

Symbol Dim. (mm) Symbol Dim. (mm)

d 8.90 - -

b
x y
e

c z

Figure 10.4. QFN64 PCB Stencil Design

Table 10.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol Dim. (mm) Symbol Dim. (mm)

a 0.75 e 8.90

b 0.22 x 2.70

c 0.50 y 2.70

d 8.90 z 0.80

Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.

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 EFM32LG Data Sheet
QFN64 Package Specifications

10.3 QFN64 Package Marking

In the illustration below package fields and position are shown.

Figure 10.5. Example Chip Marking (Top View)

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 EFM32LG Data Sheet
TQFP64 Package Specifications

11. TQFP64 Package Specifications

11.1 TQFP64 Package Dimensions

Rev: 98SPP64023A_XO1_17MAR2011
F

CL

Figure 11.1. TQFP64

Note:
1. All dimensions & tolerancing confirm to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package body size.
3. Datum 'A,B', and 'B' to be determined at datum plane 'H'.
4. To be determined at seating place 'C'.
5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side. 'D1' and 'E1' are maximum plas-
tic body size dimension including mold mismatch. Dimension 'D1' and 'E1' shall be determined at datum plane 'H'.
6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.
7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maxi-
mum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm.
8. Exact shape of each corner is optional.
9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10. All dimensions are in millimeters.

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 EFM32LG Data Sheet
TQFP64 Package Specifications

Table 11.1. QFP64 (Dimensions in mm)

DIM MIN NOM MAX DIM MIN NOM MAX

A — 1.10 1.20 L1 —

A1 0.05 — 0.15 R1 0.08 — —

A2 0.95 1.00 1.05 R2 0.08 — 0.20

b 0.17 0.22 0.27 S 0.20 — —

b1 0.17 0.20 0.23 θ 0° 3.5° 7°

c 0.09 — 0.20 θ1 0° — —

C1 0.09 — 0.16 θ2 11° 12° 13°

D 12.0 BSC θ3 11° 12° 13°

D1 10.0 BSC

e 0.50 BSC

E 12.0 BSC

E1 10.0 BSC

L 0.45 0.60 0.75

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 EFM32LG Data Sheet
TQFP64 Package Specifications

11.2 TQFP64 PCB Layout

p8 p7

p1 p6

e
c

p2 p5

p3 p4

Figure 11.2. TQFP64 PCB Land Pattern

Table 11.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol Dim. (mm) Symbol Pin Number Symbol Pin Number

a 1.60 P1 1 P6 48

b 0.30 P2 16 P7 49

c 0.50 P3 17 P8 64

d 11.50 P4 32

e 11.50 P5 33

e
c

Figure 11.3. TQFP64 PCB Solder Mask

Table 11.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 1.72

b 0.42

c 0.50

d 11.50

e 11.50

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 EFM32LG Data Sheet
TQFP64 Package Specifications

e
c

Figure 11.4. TQFP64 PCB Stencil Design

Table 11.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol Dim. (mm)

a 1.50

b 0.20

c 0.50

d 11.50

e 11.50

Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.

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 EFM32LG Data Sheet
TQFP64 Package Specifications

11.3 TQFP64 Package Marking

In the illustration below package fields and position are shown.

Figure 11.5. Example Chip Marking (Top View)

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 EFM32LG Data Sheet
Wafer Specifications

12. Wafer Specifications

12.1 Bonding Instructions

All pads should be bonded out, with the exception of the pads labeled “NC” and listed as “Do not connect” in Padout. Gold bond wires
are recommended for these devices.

All three voltage regulator output decouple pads (DEC_0, DEC_1, DEC_2) must be bonded out and electrically connected on the PCB.
In the packaged devices, these three pads are all bonded to a single DECOUPLE pin.

If the USB feature of EFM32LG900 will be used, all of the USB pads must be bonded out, and
• both USB_VREGO_0 and USB_VREGO_1 must be bonded out and electrically connected on the PCB. In the packaged devices,
these two pads are both bonded to a single USB_VREGO pin.
• both USB_VREGI_0 and USB_VREGI_1 must be bonded out and electrically connected on the PCB. In the packaged devices,
these two pads are both bonded to a single USB_VREGI pin.

12.2 Wafer Description

Table 12.1. Wafer and Die Information

Parameter Value

Device Family EFM32LG (Leopard Gecko)

Wafer Diameter 8 in

Die Dimensions (Outer edge of seal ring) Contact sales for information

Wafer Thickness (No backgrind) 725 µm ±15 µm (28.54 mil ±1 mil)

Wafer Identification Notch

Scribe Street Width 80 µm × 160 µm

Die Per Wafer1 Contact sales for information

Passivation Standard

Wafer Packaging Detail Wafer Jar

Bond Pad Dimensions 65 µm (parallel to die edge) × 66 µm

Bond Pad Pitch Minimum 76 µm

Maximum Processing Temperature 250 °C

Electronic Die Map Format .txt

Note:
1. This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).

12.2.1 Environmental

Bare silicon die are susceptible to mechanical damage and may be sensitive to light. When bare die must be used in an environment
exposed to light, it may be necessary to cover the top and sides with an opaque material.

For additional quality and environmental information, see: http://www.silabs.com/support/quality/pages/default.aspx.

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 EFM32LG Data Sheet
Wafer Specifications

12.3 Wafer Storage Guidelines

It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.
• Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
• Wafers must be stored at a temperature of 18 - 24 °C.
• Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%.
• Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).

12.4 Failure Analysis (FA) Guidelines

Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in wafer form.
• In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories must be provided with die as-
sembled in an industry standard package that is pin compatible with existing packages Silicon Laboratories offers for the device.
Initial response time for FA requests that meet these requirements will follow the standard FA guidelines for packaged parts.
• If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer. Silicon Laboratories cannot
retest any wafers that have been sawed, diced, backgrind or are on tape. Initial response time for FA requests that meet these re-
quirements will be three weeks.

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 EFM32LG Data Sheet
Chip Revision, Solder Information, Errata

13. Chip Revision, Solder Information, Errata

13.1 Chip Revision

The revision of a chip can be determined from the "Revision" field in the package marking.

13.2 Soldering Information

The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.

13.3 Errata

See the errata document for description and resolution of device errata. This document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit

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 EFM32LG Data Sheet
Revision History

14. Revision History

Revision 2.41

May, 2023
• Updated 2. Ordering Information to note OPNs that are obsolete.

Revision 2.40

November, 2022
• Updated 2. Ordering Information to note OPNs that are not recommended for new designs.
• Updated terminology according to Silicon Labs’ Inclusive Lexicon Project.

Revision 2.30

November, 2019
• Updated Ordering Information for the release of revision F devices.
• In Flash Electrical Specifications – Added word write cycles between erase (WWCFLASH) specification.
• In Table 4.15 Analog Digital Converter (ADC) on page 91 Electrical Specifications – Updated ADC input ON resistance (RADCIN).
• In Alternate Functionality Overview tables, restored DAC0_P0, DAC0_P1, DAC0_N0 and DAC0_N1 alternate functionalities for all
the devices.
• Removed PB11 as the 1st alternate location of I2C1_SDA in Alternate Functionality Overview tables for:
• EFM32LG232
• EFM32LG332
• EFM32LG842
• EFM32LG942
• Removed MSL information (Moisture Sensitivity Level). Instead, MSL information can be found in the Qual report that is available on
the Silicon Labs website.
• Consolidated revision history with new format.

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 EFM32LG Data Sheet
Revision History

Revision 2.20

April 2019
• Key Features stop mode current changed to match value specified in 4.5 Current Consumption.
• 2. Ordering Information corrected to show that the package for the EFM32LG942 is the TQFP64 and not the BGA120.
• Spelling and punctuation errors fixed in 3.1.12 Universal Serial Bus Controller (USB).
• Corrected available ACMP0 and ACMP1 channels in the following Configuration Summary sections:
• 3.2.6 EFM32LG330
• 3.2.7 EFM32LG332
• 3.2.9 EFM32LG380
• 3.2.10 EFM32LG390
• 3.2.12 EFM32LG840
• 3.2.13 EFM32LG842
• 3.2.18 EFM32LG940
• 3.2.19 EFM32LG942
• 3.2.20 EFM32LG980
• 3.2.21 EFM32LG990
• GPIO count in Table 3.6 EFM32LG330 Configuration Summary on page 27 increased from 52 to 53.
• GPIO count in Table 3.18 EFM32LG940 Configuration Summary on page 51 increased from 52 to 53.
• Added TJ parameter to Table 4.1 Absolute Maximum Ratings on page 63.
• Added 4.4 Backup Supply Domain specifications to 4. Electrical Characteristics.
• Capitalization of figure titles made consistent in 4.5.1 EM1 Current Consumption.
• Restored figure title for Figure 4.7 EM1 Current Consumption with all Peripheral Clocks Disabled and HFRCO Running at 1.2 MHz
on page 70.
• Restored note to 4.5.2 EM2 Current Consumption indicating use of Backup RTC (BURTC).
• Updated the following 4.8 Flash specifications and added relevant notes:
• Page erase time (tPERASE)
• Device erase time (tDERASE)
• Added load current (ILOAD_DC) maximum to 4.12 Digital Analog Converter (DAC) specifications.
• Updated the load resistance (RLOAD) in 4.13 Operational Amplifier (OPAMP) specifications.
• Corrected the following 4.16 EBI parameters:
• Minimum tOH_ALEn equation to use ADDRHOLD instead of WRHOLD.
• Minimum tH_ARDY equation to include addition of (3 * tHFCORECLK) term.
• Title of Figure 4.44 SPI Secondary Timing on page 129 corrected to specify secondary (not main) timing.
• Restored the analog description of USB_VREGI and USB_VREGO as follows:
• Pins A11 and A12 in the Table 5.13 Device Pinout on page 179 for EFM32LG295.
• Pin s 45 and 46 in the Table 5.13 Device Pinout on page 179 for EFM32LG330.
• Pin s 45 and 46 in the Table 5.19 Device Pinout on page 203 for EFM32LG332.
• Pins A11 and A12 in the Table 5.64 Device Pinout on page 409 for EFM32LG995.
• Pins B1 and C1 in the Table 5.22 Device Pinout on page 213 for EFM32LG360.
• Pins 72 and 73 in the Table 5.25 Device Pinout on page 225 for EFM32LG380.
• Pins B10 and B11 in the Table 5.28 Device Pinout on page 237 for EFM32LG390.
• Pins A11 and A12 in the Table 5.31 Device Pinout on page 251 for EFM32LG395.
• Pins A11 and A12 in the Table 5.46 Device Pinout on page 323 for EFM32LG895.
• Pins 45 and 46 in the Table 5.52 Device Pinout on page 356 for EFM32LG940.
• Pins 45 and 46 in the Table 5.55 Device Pinout on page 366 for EFM32LG942.
• Pins 72 and 73 in the Table 5.58 Device Pinout on page 378 for EFM32LG980.
• Pins B10 and B11 in the Table 5.61 Device Pinout on page 393 for EFM32LG990.
• Pins A11 and A12 in the Table 5.64 Device Pinout on page 409 for EFM32LG995.
• Changed pin #8 in Table 5.1 Device Pinout on page 132 from VSS to IOVDD_0 to match Figure 5.1 EFM32LG232 on page 131.
• Restored PC1 and PC0 as 4th alternate locations of I2C0_SCL and I2C0_SDA, respectively in 5.2.2 Alternate Functionality Pinout
for the EFM32LG232.
• Removed USB_DMPU #0 from the Communication column of pin 48 in Table 5.7 Device Pinout on page 152 for the EFM32LG280.

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 EFM32LG Data Sheet
Revision History

• Restored PC15 as the 1st alternate location of DBG_SWO in 5.4.2 Alternate Functionality Pinout for the EFM32LG290.
• Corrected 5.5.3 GPIO Pinout Overview text to reflect that the information shown is for the EFM32LG295 and not the EFM32LG395.
• Restored the signal descriptions of DAC0_OUT1 /OPAMP_OUT1 in 5.6.2 Alternate Functionality Pinout for the EFM32LG330.
• Restored the following signals in 5.12.2 Alternate Functionality Pinout for the EFM32LG840:
• GPIO_EM4WU1
• PA6 as 4th location of ETM_CLK
• PC13 as the 4th location of TIM1_CC2
• Restored PC13 as the 4th location of TIM1_CC2 in 5.13.2 Alternate Functionality Pinout for the EFM32LG842.
• Removed USB_DMPU #0 from the Communication column of pin 48 in Table 5.40 Device Pinout on page 289 for the EFM32LG880.
• Restored PF3 as the 0th (primary) location of EBI_ALE in 5.14.2 Alternate Functionality Pinout for the EFM32LG880.
• Restored PC15 as the 1st location of DBG_SWO in 5.15.2 Alternate Functionality Pinout for the EFM32LG890.
• Restored U1_RX #1 to the Communication column of pin A13 in Table 5.46 Device Pinout on page 323 for the EFM32LG895.
• Pad 117 changed from PD15 to PB15 in Table 5.49 Device Padout on page 338 for the EFM32LG900.
• Added TIM3_CC2 to 5.19.2 Alternate Functionality Pinout for the EFM32LG940.
• Restored moisture sensitivity information to 13.2 Soldering Information.
• Corrected symbol b in 10.1 QFN64 Package Dimensions.
• Corrected the pin number for symbol P9 in 10.2 QFN64 PCB Layout.
• Statements regarding packaging materials have been removed. The most current device quality and environmental information can
be found at http://www.silabs.com/support/quality/pages/default.aspx.

Revision 2.10

September 20th, 2017

• In 4.10.5 AUXHFRCO, updated test conditions for oscillation frequency.
• In 4.11 Analog Digital Converter (ADC):
• Added footnote for average active current.
• Updated conditions for INL and DNL.
• Updated parameter description for VREF.
• Updated VREF current consumption max for 1.25V and 2.5V reference.
• In 4.12 Digital Analog Converter (DAC):
• Updated parameter description and test conditions for IDAC.
• Updated parameter description for VREF.
• Corrected pinout diagram for EFM32LG230 in 5.1.1 Pinout.
• Spelling and formatting updates throughout.

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 EFM32LG Data Sheet
Revision History

Revision 2.00

April 17th, 2017

• Consolidated all EFM32LG data sheets:
• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG360
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG900
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995
• Added a Feature List section.
• 2. Ordering Information – Added ordering code decoder.
• 3.3 Memory Map – Separated the Memory Map into two figures – one for core and code space listing and one for peripheral listing.
• 4.2 Absolute Maximum Ratings – Removed the footnote about storage temperature and added max source/sink current per I/O pin.
• Environmental – Removed this section. Environmental specifications are available in the qualification report.
• 4.5 Current Consumption - Added maximum current specifications for the highest energy mode, IEM0.
• 4.9 General Purpose Input Output – Reduced maximum input leakage current (IIOLEAK, max).
• 4.10.1 LFXO – Replaced “energyAware Designer” with “Configurator tool”.
• 4.10.3 LFRCO – Added (min, typ, max) specifications for oscillation frequency over full power supply and full temperature range.
Also added typical voltage drift and temperature drift specs.
• 4.10.3 LFRCO – Updated graphs for calibrated LFRCO Frequency vs. Temperature and Supply Range, and also fixed y-axis unit
[kHz].
• 4.10.4 HFRCO – Added specifications for oscillation frequency over full power supply and temperature range, added typical voltage
drift and temperature drift specs at each frequency band, and removed the duty cycle spec (DCHFRCO).
• 4.10.4 HFRCO – Updated all HFRCO graphs (various frequency bands).
• 4.10.6 ULFRCO – Removed the duty cycle spec for AUXHFRCO (DCAUXHFRCO).
• 4.11 Analog Digital Converter (ADC) – Added the following specs:
• Input bias current (IADCBIASIN) – added max (source and sink).
• Input offset current (IADCOFFSETIN) – added max (source and sink).
• VREF output voltage (VREF) – added min, typ, max.
• VREF voltage drift (VREF_VDRIFT) – added min, typ, max.
• VREF temperature drift (VREF_TDRIFT) – added min, typ, max.
• VREF current consumption (IVREF) – added typ, max, replacing IADCREF.
• ADC and DAC VREF matching (VREF_MATCH) – added typical.

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 EFM32LG Data Sheet
Revision History

• 4.12 Digital Analog Converter (DAC) – Updated the footnote for active average current (IDAC), and added the following new VREF
specs at each voltage reference:
• VREF output voltage (VREF) – added min, typ, max.
• VREF voltage drift (VREF_VDRIFT) – added min, typ, max.
• VREF temperature drift (VREF_TDRIFT) – added min, typ, max.
• VREF current consumption (IVREF) – added typ, max.
• ADC and DAC VREF matching (VREF_MATCH) – added typical.
• 4.13 Operational Amplifier (OPAMP) – Removed note specifying that OPAMP specs stem from simulations, and added new specifi-
cations for the following:
• Active Current (IOPAMP) – new specifications at various (new) bias program settings.
• Gain Bandwidth Product (GBWOPAMP) – new (typ) specifications at new bias program settings and DC bias settings.
• Input Offset Voltage (VOFFSET) – specified min, typ, max for Op Amps (OPA0-1).
• Input Bias Current (IOPAMPBIASIN) – new min and max specifications.
• Input Offset Current (IOPAMPOFF-SETIN) – new min and max specifications.
• Slew Rate (SROPAMP) – new specifications at new bias program settings.
• Updated footnote.
• 4.14 Analog Comparator (ACMP) – Added new specifications for the following:
• Input Bias Current (IACMPBIASIN) – added min and max.
• Input Offset Current (IACMPOFFSETIN) – added min and max.
• Active Current (IACMP) – added two new condition settings, and footnote.
• Negative Response Time (tRESPONSE_N) – added new specifications.
• Positive Response Times (tRESPONSE_P) – added new specifications.
• Offset Voltage (VACMPOFFSET) – added specifications at new bias program settings.
• ACMP Hysteresis (VACMPHYST) – added specifications for negative and positive hysteresis at various bias program settings.
• VDD SCALED Input Accuracy (VVDDSCALED) – added new specifications (typical).
• 4.15 Voltage Comparator (VCMP) – Added the following new specifications:
• Negative hysteresis (VVCMPHYST_N), replacing VCMP hysteresis.
• Positive hysteresis (VVCMPHYST_P), replacing VCMP hysteresis.
• Hysteresis Delta (VVCMPHYST_DELTA).
• Negative Response Time (tRESPONSE_N).
• Positive Response Time (tRESPONSE_P).
• Footnote for active current, IVCMP.
• 4.19 USART SPI – Corrected parameter descriptions for tCS_DIS_MI.
• 4.20 Digital Peripherals – Added (typical) LE Peripheral Interface Clock Current (ILFCLK) specifications with both the LFXO-LFA and
LFXO-LFB clock trees.
• Removed MSL information (Moisture Sensitivity Level). Instead, MSL information can be found in the Qual report that is available on
the Silicon Labs website.
• New formatting throughout.

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 EFM32LG Data Sheet
Revision History

Revision 1.31

December 16th, 2015

• Removed Environmental section from General Operating Conditions.
• Added max current consumption numbers for energy modes.
• For devices with an ADC, added clarification on conditions for INLADC and DNLADC parameters.
• For devices with an EBI, updated EBI ready/wait figure.
• Updated memory map.
• Removed DCHFRCO and DCAUXHFRCO parameters.
• For CSP81 package, updated typical and added min/max values for fHFRCO and fAUXHFRCO.
• For devices in CSP81 package with a DAC, updated OPAMP table.
• Fixed typos.
• Added OPAMP, ADC, and ACMP Input Bias Current and Input Offset Current specifications.
• Added lower limit for GPIO Input Leakage Current and updated the upper limit for this specification.
• Removed the "by simulation and/or technology characterization" phrase from the Electrical Characteristics Test Conditions section.

Revision 1.30

June 13th, 2014

• This revision applies the following devices:
• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995
• Removed "Preliminary" markings.
• Updated electrical characteristics and updated/added plots.
• Updated orderable part numbers.
• Added AUXHFRCO to block diagram and electrical characteristics.
• For devices with EBI, added EBI timing chapter.

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 EFM32LG Data Sheet
Revision History

Revision 1.21

November 21st, 2013

• This revision applies the following devices:
• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995
• Updated figures.
• Updated errata-link.
• Updated chip marking.
• Added link to Environmental and Quality information.
• For devices with a DAC, re-added missing DAC-data.

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 EFM32LG Data Sheet
Revision History

Revision 1.20

March 16th, 2015

• This revision applies the following devices:
• EFM32LG900
• Corrected pad numbers and the order of the pads in the padout table so that it matches the drawing.

March 16th, 2015

• This revision applies the following devices:
• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995
• Added I2C characterization data.
• Added SPI characterization data.
• Corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section.
• Corrected GPIO operating voltage from 1.8 V to 1.85 V.
• For devices with USB, added the USB bootloader information.
• Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
• For QFN64 packages, removed UART mentioned incorrectly in the QFN64 parts.
• Updated Environmental information.
• Updated trademark, disclaimer and contact information.
• Other minor corrections.

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 EFM32LG Data Sheet
Revision History

Revision 1.11

November 17th, 2010

• This revision applies the following devices:
• EFM32G200
• EFM32G210
• EFM32G230
• EFM32G280
• EFM32G290
• EFM32G840
• EFM32G880
• EFM32G890
• Corrected maximum DAC clock speed for continuous mode.
• Added DAC sample-hold mode voltage drift rate.
• Added pulse widths detected by the HFXO glitch detector.
• Added power sequencing information to Power Management section.

Revision 1.10

December 12th, 2014

• This revision applies the following devices:
• EFM32LG900
• Added recommendation to use gold bond wire.

June 28th, 2013

• This revision applies the following devices:

• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995

• Updated power requirements in the Power Management section.

• For BGA packages, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures.
• Removed minimum load capacitance figure and table. Added reference to application note.
• Other minor corrections.

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 EFM32LG Data Sheet
Revision History

Revision 1.00

October 15th, 2014

• This revision applies the following devices:
• EFM32LG360
• EFM32LG900
September 11th, 2012
• This revision applies the following devices:
• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995

• Updated the HFRCO 1 MHz band typical value to 1.2 MHz.

• Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
• For BGA112 and BGA120 packages, corrected BGA solder balls material from Sn96.5/Ag3/Cu0.5 to SAC105.

Revision 0.92
May 25th, 2012

• This revision applies the following devices:

• EFM32LG290
• EFM32LG295
• EFM32LG390
• EFM32LG395
• EFM32LG890
• EFM32LG895
• EFM32LG990
• EFM32LG995
• Corrected BGA solder balls material description.
• Corrected EM3 current consumption in the Electrical Characteristics section.

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 EFM32LG Data Sheet
Revision History

Revision 0.90
April 27th, 2012

• This revision applies the following devices:

• EFM32LG230
• EFM32LG232
• EFM32LG280
• EFM32LG290
• EFM32LG295
• EFM32LG330
• EFM32LG332
• EFM32LG380
• EFM32LG390
• EFM32LG395
• EFM32LG840
• EFM32LG842
• EFM32LG880
• EFM32LG890
• EFM32LG895
• EFM32LG940
• EFM32LG942
• EFM32LG980
• EFM32LG990
• EFM32LG995
• Initial preliminary release.

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