Introduction to FPGA programming

Using Xilinx Vivado and VHDL

Dott. Luca Pacher

[email protected]

University of Torino
A.Y. 2019/2020, Spring 2020
Introduction to digital systems
design using VHDL
 References

− Digital Systems Design Using VHDL, C.H. Roth, Jr

− Circuit Design with VHDL, V.A. Pedroni
− Introduction to Digital Design Using Digilent FPGA Boards - Block
Diagram/VHDL Examples, R.E. Haskell, D.M. Hanna
 Additional references

A lot of material in form of tutorials and YouTube videos is available

on the web :

− https://www.fpga4fun.com
− https://www.nandland.com/vhdl/tutorials/index.html
− http://www.asic-world.com/vhdl/index.html
 Digital systems

analog signals :
− continuous in both time and amplitude
− usually a voltage v(t) or a current i(t) as a function of time
− reach of information (e.g. frequency spectrum, FFT)

digital signals :
− usually continuous in time but discrete in amplitude
− only two possible values e.g. high/low voltage levels, true/false, on/off,
closed/open etc.
− less information, but more robust against noise
− can be either asynchronous signals or synchronous signals
 Classification of digital circuits

Digital circuits are classified as :

− combinational circuits

− sequential circuits
− asynchronous
− synchronous
 Hardware Description Languages (HDL)

COMPLEX digital system (e.g. micro-processor)

⇒ HDL description and simulation of the system, that is... write CODE !
⇒ a SYNTHESIS tool generates the real HARDWARE for you !
 Verilog vs. VHDL

Verilog and VHDL are the two most widespread HDLs in the world for this job :
− approx. 50% market each one
− Verilog more popular in US and Japan, VHDL in Europe
− Verilog more used (and integrated with professional CAD tools) to design
Application-Specific Integrated Circuits (ASIC) design
− traditionally VHDL more used for FPGA programming instead
− both equally and well supported by Xilinx Vivado flows
− Verilog is easier to learn, but also potentially more error-prone due to its
relaxed data typing
− if you will do my job at the end you will learn both, or at least you will be able
to read both codes
− if you start alone (but I’m here ...) from scratch... learn VHDL first, then move
to Verilog once really annoyed with VHDL ”verbose” coding
VHDL fundamentals
 History

VHDL = VHSIC-HDL (Hardware Description Language)

VHSIC = Very High Speed Integrated Circuit
born in 1983 as a project from US Department of Defense
syntax derived from the ADA programming language (similar to PASCAL)
1983: first standardization as IEEE Std. 1076-1987
1993: first major revision of the language as IEEE Std. 1076-1993
(aka ”VHDL 93”)
2008: second major revision of the language as IEEE Std. 1076-2008
(aka ”VHDL 2008”)
provides constructs for both physical implementation (synthesizable) and
simulation
very reach syntax
extremely verbose and strongly typed !
 Syntax fundamentals

− VHDL is case insensitive (on the contrary, Verilog is case sensitive)

− blanks between statements and empty lines are ignored by the compiler
− comments starts with two dashes

-- this is a single - line VHDL comment

-- this is a multiple - lines

-- VHDL
-- comment
 Code indentation

Always indent your code to improve readability but ...

DO NOT USE TABs !!!

 Entity declaration

Any digital block implementing some functionality in VHDL is called entity :

entity BlockName is

port (
...
... ) ;

end [ entity ] BlockName ;

A VHDL entity has I/O ports that can be declared as :

− in
− out
− inout
 Port list

Input ports :

clk : in std_logic ,
rst : in std_logic , ...

Output ports :

busy : out std_logic ,

LED : out std_logic_vector (3 downto 0)

Inout (bidirectional) ports :

sda : inout std_logic

 Architecture declaration

The actual digital block implementation is coded in the architecture instead :

architecture someName of BlockName is

-- initial declarations
...

begin

-- actual block implementation

...
...

end [ architecture ] someName ;

 Testbench

In order to simulate the functionality of the digital block we also need a testbench that
generates stimuli fed to input ports of our Device Under Test (DUT):

entity tb_BlockName is
end entity ;

architecture testbench of tb_BlockName is

...
...
begin
...

-- Device Under Test ( DUT )

DUT : BlockName port map (....) ;
...
end architecture ;

The module under test is always instantiated inside the testbench module, which
contains non-synthesizable code.
Boolean algebra
 Logic constants

Fundamental logic constants in VHDL are '1' and '0' :

single quotes for 1-bit logic constants

'1 ' '0 '

double quotes for multiple-bits logic values

"0010" "1010"
 Unresolved logic values

built-in VHDL logic types :

− bit for single-bit signals
− bit_vector for multiple-bits signals (buses, see later)

signal clock : bit ;

signal oneByte : bit_vector (7 downto 0) ;

unresolved data types

 Extended logic values /1
extended VHDL logic values :
− std_logic for single-bit signals
− std_logic_vector for multiple-bits signals (buses, see later)
require external library as defined by IEEE Std. 1164

-- include resolved types

library IEEE ;
use IEEE . std_logic_1164 . all ;

...
...

signal clock : std_logic ;

signal oneByte : std_logic_vector (7 downto 0) ;

Source code :
<install dir>/data/vhdl/src/ieee/distributable/std_logic_1164.vhd
 Extended logic values /2

1 logic one
0 logic zero
Z high-impedance
U uninitialized (sim. only)
X unknown (driven)
- don’t care
H weak high
L weak low
W weak signal
 Buses and endianess

Most Significant Bit (MSB) vs. Least Significant Bit (LSB)

the ordering of bits within a multi-bit string is referred to as endianess
big endian :

signal someSignal : std_logic_vector (11 downto 0)

”little endian”

signal someSignal : std_logic_vector (0 to 4)

 Binary codes (most important... )

”straight” binary (the usual ”power of 2”)

Gray code
thermometer
one-hot / one-cold

Many many others : e.g. Hamming (for SEU protection)

 Straight binary code

Usual binary strings interpreted as usual as ”power of 2” integer numbers :

"000" -- 0
"001" -- 1
"010" -- 2
"011" -- 3
"100" -- 4
"101" -- 5
"110" -- 6
"111" -- 7

N
X −1
x = b0 × 20 + b1 × 21 + b2 × 22 + ... + bN −1 2N −1 = bi 2i
i=0
 Gray code

Only one bit change from a code to the next one :

"000" -- 0
"001" -- 1
"011" -- 2
"010" -- 3
"110" -- 4
"111" -- 5
"101" -- 6
"100" -- 7
 Thermometer code

Continue to ”padd” the code with a '1' on the right :

"0000000" -- 0
"0000001" -- 1
"0000011" -- 2
"0000111" -- 3
"0001111" -- 4
"0011111" -- 5
"0111111" -- 6
"1111111" -- 7
 One-hot code

Only one bit set to one, then moving to the left :

"0000000" -- 0
"0000001" -- 1
"0000010" -- 2
"0000100" -- 3
"0001000" -- 4
"0010000" -- 5
"0100000" -- 6
"1000000" -- 7

The complementary is sometimes called ”one cold”

 NOT gate

Z=X
VHDL syntax :

Z <= not X ;
 AND gate

Z =A·B
VHDL syntax :

Z <= A and B ;
 OR gate

Z =A+B
VHDL syntax :

Z <= A or B ;
 NAND gate

Z =A·B
VHDL syntax :

Z <= A nand B ;
 NOR gate

Z =A+B
VHDL syntax :

Z <= A nor B ;
 De Morgan’s theorem /1

A·B =A+B
 De Morgan’s theorem /2

A+B =A·B
 XOR gate

Z = A ⊕ B = (A · B) + (A · B)
VHDL syntax :

Z <= A xor B ;
 XNOR gate

Z = A ⊕ B = (A · B) + ( A · B )
VHDL syntax :

Z <= A xnor B ;
 Propagation delays

VHDL syntax :

SUM <= A xor B after 5 ns ;

CARRY <= A and B after 3 ns ;

Only for simulation purposes !

 Multiple-inputs gates

Z <= X (0) and X (1) and X (2) and ... and X (N -1) ;

Z <= X (0) or X (1) or X (2) or ... or X (N -1) ;

 Multiple-inputs gates

Z <= X (0) nand X (1) nand X (2) nand ... nand X (N -1) ;
WRONG !

Z <= not ( X (0) and X (1) and X (2) and ... and X (N -1)) ;
 When/Else conditional signal assignment

b <= "1000" when a = "00" else

"0100" when a = "01" else
"0010" when a = "10" else
"0001" when a = "11" ;
Lab 1 - Simulate a simple inverter in VHDL
Lab 2- Fundamental logic gates in VHDL