Revision no.

: PPT/2K804/04
PPT/2K403/02

Processor
 Revision no.: PPT/2K804/04

Microprocessors

• A microprocessor is an integrated circuit (IC) that contains a

complete CPU on a single chip.

• Microprocessors can be viewed as little black boxes that

provide answers or perform a variety of chores on command.

• The CPU accesses system resources by the external buses

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Packaging

• Most common CPU Packages

• DIPP (Dual In-Line Pin Package)
• PGA (Pin Grid Array)
• SPGA (Staggered Pin Grid Array)
• PQFP
• SECC (Single Edge Contact Cartridge)
• FC – PGA (Flip Chip Pin Grid Array)

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

8086 CPU Family

• The very first member of Intel's 8086/8088 family is 8086

microprocessor.

• It has 20-bit address bus and 16-bit data bus.

• All its internal architecture is 16 bit only.

• 8088 was a downward compatible version of 8086.

• 8088 was having 20 bit address bus with 8 bit external data bus
and 16 bit internal architecture

• The next processor was 80186.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

8086 CPU Family (contd.)

• 80186 possess 8086 plus some support IC's such as 8259,

8253, 8237 & address decoding logic on chip.
• This processor is also a 16 bit processor having 16 data lines
& 20 address lines.
• The 80286 doesn't included support IC's on-chip.
• It has virtual memory management circuitry
• 24 bit address lines
• Time-sharing ability that allowed multi-tasking, multi user
capabilities.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

80386 CPU Family

• The next Microprocessor introduced was

80386.

• This is a true 32 bit Microprocessor.

• The memory management circuitry &

protection circuitry in this Microprocessor
is much more improved.

• The segment size in this can be as large

as 4GB instead of 64K possible in 80286.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

80386 CPU Family (contd.)

• Instruction pipelining, on chip address translation, and high

bus bandwidth ensure short average instruction execution
times and high system throughput.
• The 80386 is available in two versions, the 80386SX &
80386DX.
• The 80386 SX is available in Quad plastic flat package (QPFP)
IC
• 80386DX comes in a 132 Pin ceramic Pin Grid Array packages
(PGA).
• The 386 DX is also manufactured in QPFP form by a company
named AMD (Advanced Micro Devices).

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

80386 CPU Family (contd.)

• The 386 is available in clock needs ranging from 16MHz to

33MHz.
• The 386 operates in 3 modes, real mode, protected mode and
virtual 8086 mode.
• It can switch to and form protected mode
• 80386 SX is identical to 386 DX except that it has a 16 bit data
bus.
• It can address a maximum of 16MB of physical memory. 386DX
can address it is available in clock needs 16MHz to 33MHz

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

80486 CPU Family

• 80486 = 80386 + 80387 + 8 KB cache + cache

controller.
• 25 MHz and went up to 100 MHz with clock
doubling
• Address 4 GB of RAM and 64 TB of virtual
memory.
• Provided a built-in math coprocessor (e.g. 80387).
• 486SX was the cheaper version of the 486,which
did not have the math coprocessor
• Included System Memory Management (SMM)
mode, which could dim the liquid crystal display
(LCD) screen and power down the hard disk drive,
extending the life of the battery.
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

80486 CPU Family (contd.)

• 486 has a built-in math coprocessor.

• This coprocessor is essentially the same as the 387 processor

used with a 386,

• Integrated on the chip allows it to execute math instructions

about three times as fast as a 386/387 combination.

• 8-Kbyte code and data cache.

• 486 implements the five-stage instruction pipeline scheme that

allows it to execute instructions much faster than a 386.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

80486 CPU Family (contd.)

• The 486 fetch several instructions ahead of time, and while it is

executing one instruction, it decode and as soon as possible,
start the execution of the next instruction.
• Clock Doubling technique
• Makes the processor work internally at twice the speed of the
external clock frequency.
• The 486SX without a coprocessor is slow .
• To implement the clock doubling on the 486SX motherboard
we have the overdrive processor.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Pentium

• 32-bit
• 3.1 million-transistor
• 112 MIPS
• 66-MHz Pentium processor
• Dual pipeline design(U – Pipelining & V – Pipelining) Process
multiple instructions simultaneously at varying stages of
execution
• Processor Types
• CISC (Complex Instruction Set Computing)
• RISC (Reduced Instruction Set Computing)

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Pentium (contd.)

CISC RISC
• Rich instruction set Reduced instruction
• Micro program Hardwired control med. control unit
• Instruction set are Instruction set are uniform
variable in length
• Poor floating pt Excellent floating pt
• Less no of on chip Large no of on chip registers
• No branch predic Branch prediction

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Pentium (contd.)

• Use fast memory Extensively use techniques

Cache, Pipelining (optional)
• Complex addressing Simple addressing
• Slower Faster
• eg. X86 family eg., Sun SPARC
PowerPC 601, 604
DEC ALPHA 21164 HP PA 8000
MIPS Silicon Graph

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Pentium (contd.)

• Why Still CISC

• Inspire of all advantages RISC don't have Software
compatibility.
• Win95 and ix86 based Application do not run on RISC (Except
WinNT, OS/2 etc.)

• CRISC
• Intel saw the advantages of RISC and implemented CRISC
processors combining advantages of both.
• Intel have stolen some RISC techniques like Cache, Pipelining,
Branch prediction on chip large number of registers.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Different 32 bit processor

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel's Competitors

• Competitors have moved away from simply making clones of

the Intel processors.

• They are currently designing their own processors with unique

features.

• AMD and Cyrix are among the best known.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
Intel MMX Revision no.: PPT/2K804/04

Media Enhancement Technology

• The technology is based on new instructions

that are dedicated to processing video, audio
and graphical data efficiently.

• Chips with Intel MMX technology, when

combined with software designed for MMX
technology, deliver’s
– High performance multimedia experience

– Rich with color and sound

– Fast graphics, and smooth video.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

MMX

• 57 new multimedia instructions (single-instruction multiple-

data)

• Use dynamic branch prediction using the branch target buffer

(BTB)

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel's Pentium® II Processor

• The Pentium II processor, from Intel, delivers outstanding

integer, floating-point, and multimedia performance.

• The Pentium II processor is available in 233-, 266-, 300-, 400-,

500-, 550-, 600-, 633-MHz desktop systems.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Dual Independent Bus Architecture

• Data travels between a processor and other parts of a

computer (e.g., its keyboard, monitor, CD-ROM drive, floppy
drive, and other memory storage areas) via a single, one-lane
pathway called a system bus.

• Pentium II processor has both a system bus and high-speed

memory.

• The high-speed memory, called the "level 2 cache" or "cache

memory" provides nearby storage for instructions the
processor needs to access quickly.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Dual Independent Bus Architecture (contd.)

• The system bus and the cache bus can be used

simultaneously

• Much more data can move in and out of the Pentium- II

processor in a given amount of time, as compared to a single-
bus design such as the Pentium processor

• The Pentium II processor's system bus can handle eight data

transactions simultaneously,

• while Pentium processor bus can only work on one

transaction at a time.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Dual Independent Bus Architecture (contd.)

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Dynamic Execution

• This technology reduce the amount of time the processor sits

idle between processing instructions.

• With dynamic execution, the processor looks ahead several

steps and intelligently predicts which groups of instructions
are most likely to be processed next

• Analyzes which instructions are dependent upon each other's

results

• Creates an efficient schedule for dispatching instructions, and

carries them out.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Single Edge Contact (S.E.C) Cartridge

• To achieve high performance, Intel has moved processor

packaging to a cartridge format.

• The Pentium II processor along with its high-speed bus and

cache memory are packaged in a black plastic and metal
cartridge measuring 5.5 inches wide by 2.5 inches high by 0.5
of an inch thick.

• Packaging the cache close to the processor, and linking the

two by a dedicated pathway allow the processor to achieve
higher performance.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Single Edge Contact (S.E.C) Cartridge (contd.)

• The cartridge attaches to a "slot" on the computer's

motherboard via.a single edge connector.

• The system bus along the single edge connector is capable of

evolving to higher speeds, like raising the speed limit, to boost

overall computer performance.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Processors

• AMD-K6®-2 Processor with 3DNow!™ Technology

• Provides Vibrant Images

• Graphics Rich Sound

• Video Enhanced Internet Experience 3D Processing

using DirectX 6 and OpenGL libraries.

• AMD-K6-III

• AMD's TriLevel Cache design enables the largest total

system cache on currently available desktop PC

• Resulting in excellent performance on Windows

applications.
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Types of Tri-level cache

• Larger
• An AMD-K6-III processor-based PC can deliver up to 2,368KB
of total system cache
• more than four times the size of the 544KB maximum system
cache of a Pentium III processor-based PC.
• In general, the larger the cache, the better the system
performance.
• Faster
• 320KB of internal cache including
• 256KB Level 2 (L2) cache
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Types of Tri-level cache (contd.)

– 64KB Level 1 (L1) cache that's standard in AMD-K6 family

processors-races along at the full speed of the processor.

• More flexible
– AMD-K6-III is the first desktop PC processor to offer a 100-MHz
front side bus to an optional Level 3 (L3) external cache on the
Super7 platform.

AMD K6-III / Pentium-III AMD-K6®-III Pentium-III

Maximum total system cache 2368 KB 544 KB
Total Internal Cache 320 KB 32 KB
L2 cache speed (relative to CPU) Full-Speed
Half-Speed
Enables external L3 cache Yes No
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Types of Tri-level cache (contd.)

• Celeron

• Intel's value-priced
processor

• Provides good
performance.

• Clock speeds range from

333 to 866 MHz

• 128Kb of full-speed L2
cache
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium III Processor

• Features of PIII Processor

• The Pentium III Processor is available at
speeds ranging from 450 MHz to 1.13 GHz
Versions
• Available with either a 133 MHz or a 100 MHz
system bus.
• Designed to support the Intel® 840, 820, 810e,
440GX and 440BX chipsets.
• 256 KB Advanced Transfer Cache (on-die, full-
speed level 2 (L2) cache with Error Correcting
Code (ECC)
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium III Processor (contd.)

• Half-speed, 512 KB in package L2 cache with ECC.

• 32 KB (16 KB/16 KB) non-blocking, level 1 (L1) cache.

• P6 Dynamic Execution micro architecture including multiple

branch prediction, data flow analysis and speculative

execution.

• Intel MMX™ media enhancement technology.

• Both dual-processor capable and uni-processor only versions.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium III Processor (contd.)

• Internet Streaming SIMD Extensions, consisting of 70 new

instructions that enable advanced imaging 3D, streaming
audio and video, speech recognition and an enhanced Internet
experience.

• Dual Independent Bus (DIB) architecture increases bandwidth

and performance over single-bus processors.

• Memory cacheable up to 4 GB of addressable memory space

• System memory scalability up to 64 GB of physical memory.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium III Processor (contd.)

• Some of the processors are having a notification of E, B, EB

for eg. 500E MHz, 600EB MHz, 533B MHz.
• Note
• 'E', 'B' and 'EB' nomenclature is used to differentiate processors
within a processor speed designation when there is an overlap
between processor frequencies and functionality.
• 'E' designates Advanced Transfer Cache and Advanced System
Buffering support.
• 'B' designates 133 MHz System Bus support.
• 'EB' designates Advanced Transfer Cache, Advanced System
Buffering and 133 MHz System Bus support.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium III Processor (contd.)

• All processors greater than 600 MHz include the Advanced

Transfer Cache and the Advanced System Buffering
functionality.

• Note

• Pentium® III processor at 1.13 GHz does not support Dual

Processor.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium III Processor (contd.)

• Processor Package Options

• Pentium III processors are available in two different package

options

– Single Edge Contact Cartridge 2 (S.E.C.C.2)

– Flip-Chip Pin Grid Array (FC-PGA).

• The FC-PGA package is designed for the new breed of sleek,

powerful, small form factor PCs.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Advanced System Buffering

• The Advanced System Buffering consists of optimizations in

the system bus buffer sizes and bus queue entries

• This result in an increase in the utilization of the available

bandwidth on the 100 and 133 MHz system bus.

• 4 writeback buffers , 6 fill buffers , 8 bus queue entries.

• A pipelined Floating-Point Unit (FPU) for supporting the 32-bit

and 64-bit formats specified in IEEE standard 754, as well as

an 80-bit format.
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Advanced System Buffering (contd.)

• Coppermine
• Clock speeds range from 533 to
733MHz
• 256k full-speed L2 cache.
• High-end Pentium III processor run on
the new 133MHz front-side bus
• Helps in preventing data bottlenecks.
• These processors also work with the
new Rambus memory, which boasts
an impressive 800MHz internal clock.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Advanced System Buffering (contd.)

• Other Copper mine motherboards use PC133 memory, which

isn't as fast.

• Coppermine PCs performs excellent at computation intensive

tasks, such as
– 3D rendering

– Streaming video

– Animation

– Speech recognition.

• Delivers faster Web browsing.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor

• Available in initial speed grades of 650,

600, 550 and 500 MHz on 0.25-micron
process technology.
• The industry’s first nine-issue super
pipelined, super scalar x86 processor
micro architecture designed for high clock
frequencies.
• Multiple parallel x86 instruction decoders.
• Three out-of-order, super scalar, fully
pipelined floating point execution units,
which execute all x87 (floating point), MMX
and 3DNow! instructions.
• Advanced dynamic branch prediction.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor (contd.)

– Enhanced 3DNow! technology for leading-edge 3D performance.

– 21 original 3DNow! instructions-the first technology enabling
super scalar SIMD.
– 19 new instructions to enable improved integer math calculations
for speech or video encoding
– Improved data movement for Internet plug-ins and other
streaming applications.
– 5 new DSP instructions to improve soft modem, soft ADSL, Dolby
Digital surround sound, and MP3 applications.
– Compatible with Windows 98, Windows 95, and Windows NT 4.x
without software patches.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor (contd.)

– 200-MHz AMD Athlon system bus (scalable beyond 400 MHz)

enabling leading-edge system bandwidth for data movement-
intensive applications.
– Source synchronous clocking (clock forwarding) technology.
– Support for 8-bit ECC for data bus integrity.
– Peak bandwidth of 1.6 to 3.2 GB/s.
– Multiprocessing support point-to-point topology, with number of
processors in SMP systems determined by chipset
implementation.
– Support for 24 outstanding transactions per processor.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor (contd.)

• High-performance cache architecture featuring an

integrated 128KB L1 cache and a programmable, high-
speed backside L2 cache interface.

• Slot A infrastructure design based on optimized, high-

performance platforms.

• Available in processor cartridge with mechanical

dimensions comparable to Pentium III.

• Leverages existing physical/mechanical Slot 1 PC

infrastructure, including mechanical connector, but with
different bus protocols and electrical definitions.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor (contd.)

– Electrical interface compatible with 200-MHz AMD Athlon system

bus, based on Alpha EV6 bus protocol.

– Supported by a full line of optimized Slot A infrastructure

solutions (chipsets, motherboards, BIOS).

– Manufactured using AMD’s state-of-the-art 0.25-micron, six-layer-

metal process technology at AMD’s Fab 25 wafer fabrication
facility.

– Die size: approximately 22 million transistors on 184 mm2 die on

0.25-micron process technology.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor (contd.)

• AMD - Athlon - Thunderbird (Athlon with

• Performance Enhancing Cache) - Athlon-C
• The Thunderbird core Athlon is available in the Socket A form
factor with 256K of on-die L2 cache.
• The L2 cache on the Thunderbird is 16-set associative and
uses a 64-bit bus, as compared to the Pentium III's
(Coppermine) 256-bit cache bus.
• Capable of running in multi -processor configurations
• Eventually uses a 200 or 266MHz system bus, which actually
runs at 100MHz x 2 or 133MHz x 2 for the Athlon-C.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Athlon Processor (contd.)

• The bus speed may eventually be pushed up to 166MHz x 2 for

use with PC2600 DDR memory.

• It speed grades from 650MHz to 1GHz, in increments of 50MHz,

much like the original Athlon.

• The AMD launches 650 and 700MHz speeds of Thunderbird.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD DURON

• High-Speed System Bus

• The AMD Duron processor features a

200MHz front side system bus

• Offering more available bus bandwidth

than that of Intel's Celeron processor.

• Delivers exceptional performance on data

-rich applications, such as MP3 encoders,
video encoders, soft DVD players, and
basic video-editing packages.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Sophisticated Cache Architecture

• The AMD Duron processor features 192K of total on-chip

cache.

• Large on-chip cache combined with the sophisticated cache

architecture

• Delivers superior performance in comparison to Intel's Celeron

processor on memory-intensive applications.

• Such applications include business and personal productivity

suites, as well as basic 3D content creation and photo-editing
packages.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Sophisticated Cache Architecture (contd.)

• Superscalar Floating Point Unit with Enhanced

• 3DNow!™ Technology
• The AMD Duron processor offers three floating point pipelines
• Intel's Celeron processor offers only one
• 3DNow!™ multimedia technology, enables the AMD Duron
processor to deliver superior performance on applications rich
in graphics.
• Examples of these applications include web-design tools, as
well as entertainment and edutainment products.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4

• Features of P4 Processor

• The Pentium 4 processor is

available at speeds ranging from

1.30 to 3.2 GHz.

• Featuring the new Intel Net - Burst

micro-architecture. Supported by

the Intel® 850, 860, 870 series

chipset.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• Fully compatible with existing Intel Architecture-based

software

• Internet Streaming SIMD Extensions.

• Intel® MMX™ media enhancement technology.

• Memory cacheability up to 4 GB of addressable memory space

• System memory scalability up to 64 GB of physical memory.

• Support for uni-processor designs.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• Intel® NetBurst™ Micro-architecture

• The NetBurst micro-architecture delivers a number of new and
innovative features including
– Hyper Pipelined Technology
– 400 MHz System Bus
– Execution Trace Cache
– Rapid Execution Engine)
• Enhanced features
• Advanced Transfer Cache
• Advanced Dynamic Execution
• Enhanced Floating-point and Multi-media Unit.
• Streaming SIMD Extensions 2 (SSE2)
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• Hyper Pipelined Technology

• The hyper-pipelined technology of the NetBurst micro-
architecture doubles the pipeline depth compared to the P6
micro-architecture used in Pentium III processors.
• 400 MHz System Bus
• The Pentium 4 processor supports highest performance
desktop system bus
• It delivers 3.2 GB of data per second into and out of the
processor through a physical signaling scheme of quad
pumping

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• The data transfers over a 100-MHz clocked system bus

• The buffering scheme allows for sustained 400-MHz data

transfers.

• Level 1 Execution Trace Cache

• In addition to the 8 KB data cache, the Pentium 4 processor

includes an Execution Trace Cache

• It stores up to 12 K decoded micro-ops in the order of program

execution.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• Rapid Execution Engine

• Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor

are clocked at twice the core processor frequency.

• This allows basic integer instructions such as Add, Subtract,

Logical AND, Logical OR, etc. to execute in ½ a clock cycle.

• For example, the Rapid Execution Engine on a 1.50 GHz

Pentium 4 processor runs at 3 GHz.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• 256 KB, Level 2 Advanced Transfer Cache

• The Level 2 Advanced Transfer Cache (ATC) is 256KB in size
• Delivers much higher data throughput channel between the
Level 2 cache and the processor core.
• The Pentium 4 processor 1.50 GHz can deliver a data transfer
rate of 48 GB/s.
• This compares to a transfer rate of 16 GB/s on the Pentium - III
processor at 1 GHz.
• Enhanced Floating-point and Multi-media Unit

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• Internet Streaming SIMD Extensions 2 (SSE2)

• With the introduction of SSE2, the Net Burst micro-architecture

extends the SIMD capabilities that delivered by adding 144 new

instructions.

• These instructions include

– 128-bit SIMD integer arithmetic

– 128-bit SIMD double-precision floating-point operations.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• Intel Pentium® III Xeon™ Processors

• Variety of cache sizes
• Speed options to meet server and workstation solution needs
• Available cache sizes
• Available MHz speeds
– front-end
– 1-2 way 256K
– 1 GHz, 933 MHz, 866 MHz, 800 MHz,
– 733 MHz, 667 MHz, 600MHz
– mid-tier
– 4-8 way 1MB, 2MB 700MHz, 900MHz
– Greater 1MB, 2MB 700MHz, 900MHz

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Intel Pentium 4 (contd.)

• All cache is L2 on-die Advanced Transfer Cache

• This are special server based processor used in most of Intel

based branded machine.

• Eg:-IBM - Tivoli, IBM – Net infinity, COMPAQ - Presario etc.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

64-bit Processors

• In 1992, DEC (Digital Equipment Corporation - now part of HP-

Compaq) released the Alpha 64-bit processor, running at the
then blistering speed of 200MHz - remember, this was a time
when the 66MHz 486 DX2 was top of the line in the consumer
space.
• A number of 64-bit processors hit the market all targeted at
high-end computing applications, such as scientific analysis,
or running large back-end servers.
• 64-bit computing now comes to the masses in the form of
AMD's Hammer architectures (also known as AMD64) as well
as Intel's IA64-based processors.
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

AMD Opteron

• AMD Opteron is based on the AMD64 architecture from

AMD.

• It has eight more general purpose registers, and eight

more SIMD registers (for SSE and SSE2 code), all of
which are 64-bit.

• Features
– Designed to enable 64-bit computing while remaining
compatible with the vast x86 software infrastructure.

– Represents a new class of computing, enabling a single

architecture across 32- and 64-bit environments.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Itanium Processor

• Based on EPIC (Explicitly Parallel Instruction Computing).

• Features
• Large memory address ability
• Error detection & correction
• World class floating point performance
• High bandwidth
• 2.1 gigabyte per second bus speed
• 2 and 4 MB Level 3 "memory reservoir" cache
• Production frequencies of 800 and 733 MHz.
© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Itanium 2

• Intel Itanium 2 processor is uniquely architected for

demanding enterprise and technical applications.

• Itanium 2 processors are binary-compatible with existing

Itanium-based software to provide investment protection.

• It is available at 1.50 GHz, 1.40 GHz, 1.30 GHz, having around

Level 3 integrated cache of 6MB, 4MB, and 3MB, Level 2 cache
of 256 KB and Level 1 cache of 32 KB (Instruction and data).

• It operates with a chipset of Intel E8870 and with a system bus

speed of 400 MHz, 128-bit wide and having 6.4 GB/s bandwidth.

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute
 Revision no.: PPT/2K804/04

Design & Published by:

CMS Institute, Design & Development Centre, CMS House, Plot No. 91, Street No.7,
MIDC, Marol, Andheri (E), Mumbai –400093,
www.cmsinstitute.co.in

© CMS INSTITUTE, 2006. All rights reserved. No part of this material may be reproduced, stored or emailed without the prior permission of Programme Director, CMS Institute