UNIT - II (PART-II)

8086 MEMORY INTERFACING

By
Dr. J.KRISHNA CHAITHANYA
ASSOCIATE PROFESSOR
DEPT. OF ECE
VCE, SHAMSHABAD – 501 218.
 Contents at a glance
•8086 addressing
•Address decoding
•Interfacing RAM, ROM, EPROM to 8086
•Direct Memory Access (DMA) Data Transfer
•Interface 8257 DMA controller
 8086 ADDRESSING
Address space: It refers to set of all addresses that can be generated by
the microprocessor. There are 2 types of address spaces. They are: I/O
Address space, Memory address space.
Memory mapped I/O: When designing with microprocessors that
provide only one address space for both I/O, memory and the I/O
device locations are assigned addresses from the memory address
space itself.This is known as memory mapped I/O.

I/O

EPROM

RAM

I/O mapped I/O: When designing with microprocessors that provide

two address spaces and the I/O device locations are assigned addresses
from the I/O address space.This is known as I/O mapped I/O.
Address map or Address Partition: Microprocessor is generally
interfaced to several memory chips and I/O devices. This requires the
partitioning of address space into subsets of addresses by the
microprocessor. Each subset of address is assigned to specific
memory chip or I/O. This partitioning of address space is called
Address map or Address partition.
Memory map: A memory map is passed on from the firmware in
order to instruct an operating system kernel about memory layout. It
contains the information regarding the size of total memory, any
reserved regions and may also provide other details specific….
architecture.
The diagram is called a memory
map. This is because, like a road
map, it is a guide showing how the
system memory is allocated. This
type of information is vital to the
programmer, who must know exactly
where his or her programs can be
safely loaded.
 ADDRESS DECODING
It is the process of generating chip select (CS*) signals from the address bus
for each device in the system. The address bus lines are split into two
sections . The N most significant bits are used to generate the CS* signals
for the different devices. The M least significant signals are passed to the
devices as addresses to the different memory cells or internal registers.

•Different portions of memory are used for different purposes: RAM,

ROM, I/O devices.
•Even if all the memory was of one type, we still have to implement it
using multiple ICs.
•This means that for a given valid address, one and only one memory-
mapped component must be accessed.
Types of address decoding:
• If only a portion of the addressable space is going to be implemented
there are two basic address decoding strategies.
Full address decoding
• All the address lines are used to specify a memory location.
• Each physical memory location is identified by a unique address n.
Partial address decoding
• Since not all the address space is implemented, only a subset of the
address lines are needed to point to the physical memory locations.
• Each physical memory location is identified by several possible
addresses (using all combinations of the address lines that were not
used).
Address decoders are implemented by the following techniques
• By using discreet logic(random logic).
• Simple NAND gate decoder( used in partial addressing decoding mode).
• Data decoders(selection is done by wires, USED in FULL ADDRESSING
DECODING MODE).
• By using PROM.
 8086 addressing and address decoding
 Most the memory ICs are byte oriented i.e., each memory location
can store only one byte of data.
 The 8086 is a 16-bit microprocessor, it can transfer 16-bit data.
 So in addition to byte, word (16-bit) has to be stored in the memory.
 To implement this , the entire memory is divided into two memory
banks: Bank0 and Bank1.
 Bank0 is selected only when A0 is zero and Bank1 is selected only
when BHE’ is zero.
 A0 is zero for all even addresses, so Bank0 is usually referred as even
addressed memory bank.
 BHE’ is used to access higher order memory bank, referred to as odd
addressed memory bank.

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 8086 addressing and address decoding

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 8086 addressing and address decoding
 Every microprocessor based system has a memory system.
 Almost all systems contain two basic types of memory, read only
memory (ROM) and random access memory (RAM) or read/write
memory.
 ROM contains system software and permanent system data such as
lookup tables, IVT..etc.
 RAM contains temporary data and application software.
 ROMs/PROMs/EPROMs are mapped to cover the CPU’s reset address,
since these are non-volatile.
 When the 8086 is reset, the next instruction is fetched from the
memory location FFFF0H.
 So in the 8086 system the location FFFF0H must be in ROM location.
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 8086 addressing and address decoding
 Address Decoding Techniques
1. Absolute decoding
2. Linear decoding
3. Block decoding
1. Absolute Decoding:
 In the absolute decoding technique the memory chip is selected only for the
specified logic level on the address lines: no other logic levels can select the
chip.
 Below figure the memory interface with absolute decoding. Two 8K EPROMs
(2764) are used to provide even and odd memory banks.
 Control signals BHE and A0 are use to enable output of odd and even memory
banks respectively. As each memory chip has 8K memory locations, thirteen
address lines are required to address each locations, independently.
 All remaining address lines are used to generate an unique chip select signal.
This address technique is normally used in large memory systems.
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Absolute Decoding:

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 8086 addressing and address decoding

Linear Decoding:
 In small system hardware for the decoding logic can be eliminated
by using only required number of addressing lines (not all).
 Other lines are simple ignored. This technique is referred as linear
decoding or partial decoding. Control signals BHE and A0 are used
to enable odd and even memory banks, respectively. Figure shows
the addressing of 16K RAM (6264) with linear decoding.
 The address line A19 is used to select the RAM chips. When A19 is
low, chip is selected, otherwise it is disabled.
 The status of A14 to A18 does not affect the chip selection logic.
This gives you multiple addresses (shadow addresses).
 This technique reduces the cost of decoding circuit, but it gas
drawback of multiple addresses.
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 Linear Decoding:

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 8086 addressing and address decoding
Block Decoding:
 In a microcomputer system the memory array is often consists of
several blocks of memory chips.
 Each block of memory requires decoding circuit. To avoid
separate decoding for each memory block special decoder IC is
used to generate chip select signal for each block.
 Figure shows the Block decoding technique using 74138, 3:8
decoder

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 Block Decoding:

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 Interfacing RAM, ROM and EPROM
• The semiconductor memories are arranged as two dimensional arrays of
memory locations.
For example, 1K X 8 memory chip contains 1024 locations and each of
them is one byte wide. i.e. 1024 bytes of information can be stored in that chip .
Each location should have an address. So, there has to be certain number of
address lines on the memory chips.
• If we designate it as n, then n = logN, where N is the number of locations that
could be addresses in that chip. For 1K chip n would be 10, for 2K it is 11, for 4k
it will be 13 etc
I. ROM
•PROM
•EPROM( versions-- EPROM 2704-size(512 bytes),EPROM 2708-
size(1KB), EPROM 2716-size(2 KB), EPROM 2764-size(8 KB))
•EEPROM
II. RAM
•Static RAM
•Dynamic RAM
 ROM and EPROM
• ROMS and EPROMs are the simplest memory chips to
interface to the 8086. Since ROMs and EPROMs are read-only
devices, A0 and BHE are not required to be part of the chip
enable/select decoding.
• The 8086 address lines must be connected to the
ROM/EPROM chip chips starting with A1 and higher to all the
address lines of the ROM/EPROM chips. The 8086 unused
address lines can be used as chip enable/select decoding.
• To interface the ROMs/RAMs directly to the 8086-
multiplexed bus, they must have output enable signals. The
figure below shows the 8086 interfaced to two 2716s.
• Byte accesses are obtained by reading the full 16-bit word
onto the bus with the 8086 discarding the unwanted byte and
accepting the desired byte.
ROM pin diagram & Two ROM’s
connected in parallel
Interfacing of ROM/EPROM
Static RAMS

Static RAM’s are volatile in nature

as they can’t retain data without
power. Since static RAMs are
read/write memories, both A0 and
BHE must be included in the chip
select/enable decoding of the
devices and write timing must be
considered in the compatibility
analysis.
The general procedure for interfacing any memory to
8086 is as follows:
1. Arrange the available memory chips so that they form a 16–
bit data bus and there should be a provision to access bytes as
well as words.
2. Connect address lines, control signals like read, write of the
microprocessor with those of memory chip.
3. Remaining address lines along with A0 and BHE are used for
decoding the required chip select signals for odd and even
banks.
NOTE:
Absolute decoding is preferred even though we may have to go
for linear decoding sometimes when an application demands.
As far as possible, there should not be any windowing in
memory map unless otherwise specified and try to avoid fold
back.
 Example of static RAM interfacing Problem:
Interface two 4K X 8 EPROMs and two 4K X 8 RAM chips with 8086

• First we have to write the memory map for the problem given. It reveal the
logic to be used for decoding circuit.
• Since the first instruction is fetched from FFFF0h after the microprocessor
is reset, we will make that address to be present in EPROM and write the
memory map as above. And, to avoid windowing let us keep the locations to
be present in the RAM as immediate addresses.
• Locations having addresses from FFFFFH to FE000H are allocated to
EPROM1 and 2. Immediate address map FDFFFH to FD000H is allocated to
RAM1 and 2. The line which is differentiating EPROM from RAM is A13. Let
us use it along with A0 and BHE to identify odd and even banks.
Interfacing diagram for above given problem
Problem2: Design an interface between 8086 CPU and two chips of
16K×8 EPROM and two chips of 32K×8 RAM. Select the starting
address of EPROM suitably. The RAM address must start at 00000 H.
Solution:
•The last address in the map of 8086 is FFFFF H. after resetting, the
processor starts from FFFF0 H. hence this address must lie in the
address range of EPROM.
•It is better not to use a decoder to implement the above map
because it is not continuous, i.e. there is some unused address space
between the last RAM address (0FFFF H) and the first EPROM address
(F8000 H). Hence the logic is implemented using logic gates.
Problem3: It is required to interface two chips of 32K×8 ROM and four
chips of 32K×8 RAM with 8086, according to following map.
ROM 1 and ROM 2 F0000H - FFFFFH, RAM 1 and RAM 2 D0000H -
DFFFFH, RAM 3 and RAM 4 E0000H - EFFFFH. Show the
implementation of this memory system.
Solution:
INTERFACING I/O PORTS
•I/O ports or Input/output ports are the devices through which the
microprocessor communicates with other devices or external data
source/destinations.
•Input activity, as one may expect, is the activity that enables the
microprocessor to read data from external devices, and for example
keyboards. These devices are known as input devices as they feed data into
microprocessor system.
•Output activity transfers data from the microprocessor to the external
devices, for example CRT display. These devices which accept the data from
a microprocessor system are called output devices.
•Thus for a microprocessor the input activity is similar to read operation,
while the output activity is similar to write operation.
Steps in Interfacing an I/O Device
•Connect the data bus of the microprocessor system with the data bus of
the I/O port.
•Derive a device address pulse by decoding the required address of the
device and use it as the chip select of the device.
•Use a suitable control signal i.e. IORD and IOWR to carry out device
operations.
 Memory Mapping I/O mapping

1. 20-bit addresses are provided for IO 1. 8-bit or 16-bit address are provided
devices. for IO devices

2. The IO ports or peripherals can be

treated like memory locations and 2. Only IN and OUT instructions can be
so all instructions related to used for data transfer between IO
memory can be used for data device and the processor.
transfer.

3. In memory mapped ports, the data 3. In IO mapped ports, the data transfer
can be moved from any register to can take only between the
port and vice versa accumulator and the ports

4. When memory mapping is used for

4. When IO mapping is used for IO
IO devices, the full memory address
devices, then the full address space
space cannot be used for addressing
can be used for addressing memory.
memory.
 Dynamic RAM
Dynamic RAM store information as charges in capacitors. Since
capacitors can hold charges for a few milliseconds, refresh circuitry is
necessary in dynamic RAMs for retaining these charges. Therefore,
dynamic RAMs are complex devices to design a system.
The features of Dynamic RAM are:
•Available up to 256M  8 (2G bits).
•DRAM is essentially the same as SRAM, except that it retains data for
only 2 or 4 ms on an integrated capacitor.
•After 2 or 4 ms, the contents of the DRAM must be completely
rewritten (refreshed) because the capacitors, which store a logic 1 or
logic 0, lose their charges.
•In DRAM, the entire contents are refreshed with 256 reads in a 2- or
4-ms interval, also occurs during a write, a read, or during a special
refresh cycle.
•DRAM requires so many address pins that manufacturers
multiplexed address inputs.
 INTERFACING AND REFRESHING DYNAMIC
RAMS
•Each chip is of 16K * 1-bit dynamic RAM cell array. The system contains two 16K byte
dynamic RAM units. All the address and data lines are assumed to be available from an
8086 microprocessor system.
GENERAL INTERFACING PROCEDURE OF DRAM
 DIRECT MEMORY ACCESS (DMA)
•Direct memory access (DMA) is a feature of modern computer systems that allows
certain hardware subsystems to read/write data to/from memory without
microprocessor intervention, allowing the processor to do other work.
DMA series of steps when peripheral is
sending data through DMA controller to
memory:
1.DREQ(from peripheral drive to DMA
controller)
2.HRQ(from DMA controller to 8086 HOLD pin)
3.HLDA (from 8086 to DMA controller)
4.DMA controller takes control over system
buses
5.DACK(from DMA controller to peripheral
drive)
6.Peripheral Starts copying data to memory
The 8237 DMA controller:
•CLK: System clock
•CS΄: Chip select (decoder output)
•RESET: Clears registers, sets mask register
•READY: 0 for inserting wait states
•HLDA: Signals that the μp has relinquished buses
•DREQ3 – DREQ0: DMA request input for each
channel
•DB7-DB0: Data bus pins
•IOR΄: Bidirectional pin used during programming and
Pin during a DMA write cycle
names •IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
•EOP΄: End of process is a bidirectional signal used as
input to terminate a DMA process or as output to
signal the end of the DMA transfer
•A3-A0: Address pins for selecting internal registers
•A7-A4: Outputs that provide part of the DMA
transfer address
•HRQ: DMA request output
•DACK3-DACK0: DMA acknowledge for each channel.
•AEN: Address enable signal
•ADSTB: Address strobe
•MEMR΄: Memory read output used in DMA read
cycle
•MEMW΄: Memory write output used in DMA write
cycle
 8237 DMA controller registers

•CAR (Current Address Register): Holds the 16-bit

memory address used for the DMA transfer (one for
each channel), either incremented or decremented
during the operation
•CWCR (Current Word Count Register): Programs a
channel for the number of bytes (up to 64K) transferred
during a DMA operation
•BA (Base Address) and WC (Word Count): Used when
auto-initialization is selected for a channel, to reload
the CAR and CWCR when DMA is complete.
CR (Command Register): Programs the operation of
the controller
MR (Mode Register): Programs the mode of operation
for a channel (one for each channel)
 RR (Request Register): Used to request DMA transfer
via software (memory-to-memory transfers)

The mask register set/reset (MRSR) sets or clears the channel

mask to disable or enable particular DMA channels.
• The mask register (MSR) clears or sets all of the masks with
one command instead of individual channels as with the MRSR.
• The status register (SR) shows the status of each DMA
channel.
 Modes of 8237(data transfer methods):
The 8237 operates in different modes, depending upon the number of
bytes transferred per cycle and number of ICs used:
•Single - One DMA cycle, one CPU cycle interleaved until address
counter reaches zero
•Block - Transfer progresses until the word count reaches zero or the
EOP signal goes active.
•Demand - Transfers continue until TC or EOP goes active or DRQ goes
inactive. The CPU is permitted to use the bus when no transfer is
requested
•Cascade - Used to cascade additional DMA controllers. DREQ and DACK
is matched with HRQ and HLDA from the next chip to establish a priority
chain. Actual bus signals is executed by cascaded chip.
•Memory-to-memory transfer - This means data can be transferred
from one memory device to another memory device. The channel 0
Current Address register is the source for the data transfer and channel
1 and the transfer terminates when Current Word Count register
becomes 0. Channel 0 is used for DRAM refresh on IBM PC compatibles.
8203 DMA Controller