International Journal of

Applied Sciences, Engineering and Technology

Vol. 01, No. 01, Jan-Dec 2012

Implementation of FPGA based 3-Phase Inverter FED BLDC Motor

K. ALFONI JOSE and S. M. PADMAJA
Department of Electrical & Electronics Engg., Shri Vishnu Engineering College for Women, A.P, India
Email: [email protected], [email protected]

Abstract: Advance in Power Electronics has led to an increased interest in three-phase inverters with PWM
control of ac drives. Most of the AC drives and Universal PWM inverters in use today are adapting micro-
processor based digital control strategy. Field Programmable Gate Arrays (FPGA) is increasingly being used in
motor control applications due to their robustness and customizability. FPGA implementation has the capability
of executing several processes in parallel. Hence, the total control of the inverter together with the motor can be
implemented in a single FPGA chip [1]. The use of Pulse Width modulation (PWM) in power electronics to
control high energy with maximum efficiency & power saving is not new but, interesting is to generate PWM
signals using Hardware Descriptive Language (HDL) and implementing it in FPGA [3],[7].FPGA
implementation of PWM is selected because it has provided an economic solution & fast circuit response due to
its simultaneous instead of sequential execution. In this paper the FPGA based controller for BLDC motor is an
experimental model implementation of Sinusoidal PWM strategy (SPWM) control scheme. The proposed
control scheme can be realized and the Simulation results are verified using FPGA SPARTAN-3A DSP Trainer
kit from Xilinx with the help of VHDL programming algorithm of digital PWM Generator topology.

Keywords: BLDC Motor, Field Programming Gate Array (FPGA), Sinusoidal PWM (SPWM), VHDL, Voltage
Source Inverter (VSI).

Introduction:
Now-a-Days, Brushless DC (BLDC) motors are one Motor, known as the Permanent Magnet Synchronous
of the electrical drives that are rapidly gaining Motor (PMSM).Brushless DC motors usually consist
popularity, due to their high efficiency, good dynamic of three main parts: Stator, Rotor and Hall Sensor.
response and low maintenance and are widely used in  Stator which consists of three coils each
many motor applications developing high torque with including three elements in series, an
good speed response. inductance, a resistance and one back
electromotive force. In many motors the number
The speed of the motor is directly proportional to the of coils is replicated to have a smaller torque
applied voltage. By varying the average voltage ripple.
across the windings, the speed can be altered. This is  A Rotor which consists of an even number of
achieved by altering the duty cycle of the base PWM permanent magnets. The number of magnetic
signal.PWM Inverters are mostly used for industrial poles in the rotor also affects the step size and
applications because of their superior performance. torque ripple of the motor. More poles give
smaller steps and less torque ripple.
The use of PWM in power electronics to control high  Hall Sensors are placed every 120° for the
energy with maximum efficiency & power saving is estimation of the rotor position in the motor
not new but, interesting is to generate PWM signals
using HDL and implementing it in FPGA [1], [5]. Brushless DC motors are used in a growing number of
motor applications as they have many advantages:
The paper presents the simulation of the speed control
of BLDC motor, which can be done using the 1. They have no brushes so they require little or no
software XILINX with the help of VHDL maintenance.
programming. An FPGA based speed controller is 2. They generate less acoustic and electrical noise
designed for closed loop operation of the BLDC than universal brushed DC motors.
motor so that the motor runs much close to the 3. They can be used in hazardous operation
reference speed. environments (with flammable products).

Methodology: B. Proposed Topology of BLDC Motor

A. Principle of Operation The block diagram of the proposed system is shown
Brushless DC Motors are a type of Synchronous in Fig.1.The drive system consists of a 3 phase AC
motor. This means that the magnetic field generated supply, 3 phase Diode bridge Rectifier, 3 phase six
by the stator & the rotor rotate at the same frequency. switch Inverter, Brushless DC Motor and controlled
These motors do not experience the “Slip” that is circuits (Xilinx processor and Driver circuit).
normally seen in Induction Motors. The construction
of modern Brushless motors is very similar to the AC

IJASET 010106 Copyright © 2012 BASHA RESEARCH CENTRE. All rights reserved.
 K. ALFONI JOSE, S. M. PADMAJA

communication interfaces and pre-determined analog

triggering. The solution is to use an FPGA.
Since, the performance of the FPGA has not been
fully utilized, the combination of FPGA & DSP is the
conventional control scheme used for the motor
control. The FPGA acts as a buffer for PWM
generation unit of the DSP. The tasks taken by FPGA
& DSP were divided according to the functions
needed in motor control [1], [7].The functions taken
by FPGA include- generating the PWM signals,
calculating of motor rotational speed, generating the
phase conversion control signals, data exchanging
Fig 1: Block Diagram of Three Phase Inverter Drive between FPGA & DSP and calculation of current loop
where as the function taken by DSP include
The standard AC power supply is converted to a DC
calculation of rotational speed loop and receiving
by using a 3-phase diode bridge rectifier. A voltage
speed instruction [3], [7].
source Inverter is used to convert the DC voltage to
the controlled AC voltage. The output of Inverter is
fed to Brushless DC motor [4]. VHDL program is PWM generation using FPGA
PWM signals are generated from the Spartan-3A
used in Xilinx software to generate the controlled
processor by writing VHDL program to control the
PWM pulses at different duty ratio for Inverter to
inverter switches [3], [4]. The switching signal
drive the Brushless DC Motor at different speeds [6].
parameters namely switching frequency, the duty ratio
Hardware Implementation Using FPGA: and the number of pulses are easily controlled via
A. Experimental Set-Up VHDL programming language.
The power circuit of the Voltage Source Inverter fed
BLDC Motor drive is shown in Fig. 2. The inverter A. Principle of generating PWM
has six switches, S1, S2, S3, S4, S5 and S6 and a DC The principle of generating PWM waveform is shown
Link connected to a Diode Bridge Rectifier [2]. in Fig.3.Bidirectional counter is used to generate
triangular wave. The value of compare register is
compared with triangular wave .If the value of
compare register is less than the value of triangular
wave, then PWM is ‘1’, else PWM is ‘0’[1],[4].
FPGA implementation of PWM is selected because
FPGA has provided an economic solution & fast
circuit response due to its simultaneous instead of
sequential execution [3].

Fig 2: Voltage Source Inverter Fed BLDC

Motor Drive
Fig 3: Principal of Generating PWM Wave Form
B. System Description
A complete overview of the system can be seen on B. Proposed Technique
Fig. 2, which includes the FPGA, a three phase Sinusoidal PWM (SPWM) technique is the proposed
inverter, a Brushless DC motor, and a linear encoder technique used to generate the PWM signals to the
attached to the motor [2]. The entire System is VSI in this paper. SPWM is based on the comparison
interfaced through a PC. PC acts a Man-Machine of a sinusoidal control signal with a triangular carrier.
Interface in which the user can set the reference speed The switches on a single branch are turned on or off
of the motor, and read the actual speed. depending on whether the control signal is greater or
Functions of FPGA: smaller than the carrier. Working with three phase
FPGAs are increasingly being used in motor control loads, the control signals must be standard three phase
applications due to their robustness and sine waves.
customizability. Microcontrollers have typically been
used to implement motor controls, with computation The signals, , , , (Fig.4b) generated by
algorithms executed by software. Some of the comparison of one triangular with three sine waves
challenges in this implementation are response time, a (Fig. 4a), are directly used to drive the switches of
fixed number of PWM channels, limited each leg of the VSI are shown in figure 4.

International Journal of Applied Sciences, Engineering and Technology

Vol. 01, No. 01, Jan-Dec 2012, pp 26-30
 Implementation of FPGA based 3-Phase Inverter FED BLDC Motor

Once the program is dump to FPGA kit, it acts as a

controller and generates gate signal.
B. Algorithm for Generating PWM Pulses
The algorithm for generating PWM pulses by using
SPWM technique is given in following steps:
1. Initializing the inputs and the outputs.
i. Inputs- Clock, Frequency and Amplitude
ii. Output-Pulses
Fig. 4 SPWM Technique 2. Declaring Capturing Signals a, b, c.
HDL Code Generation: 3. Interrupt is given based on Capture Values.
Writing VHDL is tedious and the hand written code 4. Declaring the array of 256 Sine values.
still needs to be verified with Simulink and Simulink 5. Let xx=Carrier Signal yy=Comparing Value
HDL coder, once we have simulated the model we 6. From the Ramp signal, C, triangular wave is
can generate VHDL directly and prototype an FPGA. generated.
It also saves a lot of time and the generated code 7. Compare Sine values with the Triangular wave
contains optimizations we hadn’t thought of. 8. Pulses are generated.
9. Now set the Frequency and Amplitude of
A. Xilinx ISE Software Overview Carrier and Sine.
The ISE Design Suite is the Xilinx design
environment which allows us to take the design from Simulation and Experimental Results:
design entry to Xilinx device programming [6]. Digital computer simulation model of 3-Phase
The figure 5 shows the flow chart of FPGA design Voltage Source Inverter fed BLDC motor drive has
and embedded in a single chip for generating gate been developed by using XILINX 12.1.[1],[5],[6].The
signals to drive the three phase inverter. Simulation work has been performed for this drive
system and the HDL code is written for generating
PWM pulses using SPWM technique.
The generated code is simulated and the verified
generated HDL code is observed with the Mentor
Graphics Model-Sim Simulator. The Simulation
results observed in Model-Sim Simulator are as
shown in figure 6(a), 6(b)

Fig 5: Flow chart of FPGA design and Embedded

Single chip

The corresponding VHDL program code is generated

from the Simulink HDL Coder after verification and
simulation of the design. The VHDL program is
verified and simulated using Xilinx-ISE 12.1
software. 6(a)
The FPGA design flow comprises the following steps:
1. Design entry – it should assign constraints such
as timing, pin location, and area constraints,
including user constraints (UCF) file.
2. Design synthesis- Synthesize the project design.
3. Design implementation- Implement the design
which includes the Translate, Map, Place and
Route.
4. Design verification- includes both functional
verification (also known as RTL simulation) and
timing verification.
5. Xilinx® device programming- Create a
programming BIT file program debugging or to 6(b)
download to target device of
XILINX/SPARTAN-3A processor kit. Fig 6(a), (b): Simulation results of SPWM

International Journal of Applied Sciences, Engineering and Technology

Vol. 01, No. 01, Jan-Dec 2012, pp 26-30
 K. ALFONI JOSE, S. M. PADMAJA

In the Experimental work the components used are an Figure 9 shows the Fluke Meter readings of voltage
FPGA board, Personal Computer, Inverter module, and current of the Inverter Module.
and BLDC motor, as shown in Fig.1.The IGBT
Inverter module consists of Converter, Driver circuit,
Split capacitor and Driver circuit as shown in Fig.2.
The generated PWM pulses observed in the digital
CRO are as shown in figure 7(a), 7(b)

Fig- 9 Voltage and Current readings observed in

Fluke Meter

The graphs between the Set Speed and the Actual

speed for the forward and reverse direction are
observed in the PC for the closed loop operation of
the BLDC Motor at different loads.

The Speed response of a closed loop BLDC Motor in

forward direction is shown in figure 10
7(a)

Fig 10: Speed response of a Closed Loop BLDC

Motor in Forward Direction

Figure 11 shows the Speed response of a Closed Loop

BLDC Motor in Reverse Direction.
7(b)
Fig. 7(a), (b): Digital CRO outputs
The Inverter module outputs are measured by using a
Fluke Meter while performing the experiment on the
set-up. Figure 8 shows the waveform of output
voltages of the inverter module observed in the Fluke
Meter.

Fig 11: Speed Response of a Closed Loop BLDC

Motor in Reverse Direction

The Hardware details of the experimental set-up are

tabulated in the Table-1

Fig.8 Output Voltage Waveform of Inverter Module

International Journal of Applied Sciences, Engineering and Technology

Vol. 01, No. 01, Jan-Dec 2012, pp 26-30
 Implementation of FPGA based 3-Phase Inverter FED BLDC Motor

Table 1: Hardware Details [5] Jayaram Bhasker, “VHDL-Primer”, 3rd Edition,

Components Ratings Pearson Prentice Hall,1999 Xilinx 12.1
FPGA Board 1.Xilinx XC3SD1800A-FG676-4 application notes.
Spartan 3A DSP FPGA [6] Z. Bielewicz, L. Debowski, and E. Lowiec, "A
2.16×2 LCD interface DSP and FPGA based integrated controller
3.ADC & DAC interface development solutions for high performance
4.USb 2.0 Complaint interface electric drives", Proceedings of the IEEE
(480 Mbits/sec) International Symposium on Industrial
Inverter Module IGBT:25A,1200V,Driver Circuit, Electronics, Vol 2, pp: 679 - 684, June,
3-Phase Diode Bridge Rectifier, 1996.
Vin=400,I=220mA [7] O. Al-Ayasrah, T. Alukaidey, G. Pissanidis. DSP
BLDC Motor 4600 rpm @ 310 Vdc Based N-Motor Speed Control of Brushless DC
Motors Using External FPGA Design. IEEE
International Conference on Industrial
Conclusion:
Technology, 2006. ICIT 2006
This paper presents the design of FPGA Controller for
[8] A. Halvaei Niasar, H. Moghbelli, A. Vahedi, “A
BLDC motor drive. An FPGA based implementation
Low-Cost Sensorless Control for Reduced-Parts,
of Voltage Source fed BLDC Motor drive using PWM
Brushless DC Motor Drives”, IEEE
control is successfully carried out in simulation and
Transaction,2008
real-time experiment. XILINX 12.1 is used for
[9] E. F. Fuchs *, M. H. Myat, “Speed and Torque
simulation where the Simulation results observed in
Range Increases of Electric Drives Through
Model-Sim Simulator and the hardware
Compensation of Flux Weakening”, International
implementation is carried out using SPARTAN-3A
Symposium on Power Electronics, Electrical
processor. VHDL (Very high speed description
Drives, Automation and Motion, SPEEDAM
language) program is developed in XILINX to
2010
generate the controlled PWM pulses to drive the
[10] Kuang-Yao Cheng, Ying-Yu Tzou. Fuzzy
system [1], [5].
Optimization Techniques Applied to the Design
of a Digital PMSM Servo Drive [J]. IEEE
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International Journal of Applied Sciences, Engineering and Technology

Vol. 01, No. 01, Jan-Dec 2012, pp 26-30