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HCF4047BE

The HCF4047B is a low power monostable/astable multivibrator integrated circuit that can operate in monostable (one-shot) or astable (free-running) modes using only one external resistor and capacitor. It has true and complemented buffered outputs and permits positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. The device is available in DIP and SOP packages and meets JEDEC specifications for CMOS devices.

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0% found this document useful (0 votes)
369 views12 pages

HCF4047BE

The HCF4047B is a low power monostable/astable multivibrator integrated circuit that can operate in monostable (one-shot) or astable (free-running) modes using only one external resistor and capacitor. It has true and complemented buffered outputs and permits positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options. The device is available in DIP and SOP packages and meets JEDEC specifications for CMOS devices.

Uploaded by

Jesus Pelaez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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HCF4047B

LOW POWER MONOSTABLE/ASTABLE MULTIVIBRATOR

■ LOW POWER CONSUMPTION : SPECIAL


CMOS OSCILLATOR CONFIGURATION
■ MONOSTABLE (one - shot) OR ASTABLE
(free-running) OPERATION
■ TRUE AND COMPLEMENTED BUFFERED
OUTPUTS
■ ONLY ONE EXTERNAL R AND C REQUIRED DIP SOP
■ BUFFERED INPUTS
■ QUIESCENT CURRENT SPECIFIED UP TO
20V ORDER CODES
■ STANDARDIZED, SYMMETRICAL OUTPUT PACKAGE TUBE T&R
CHARACTERISTICS DIP HCF4047BEY
■ 5V, 10V AND 15V PARAMETRIC RATINGS SOP HCF4047BM1 HCF4047M013TR
■ INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
permit positive or negative edge-triggered
■ 100% TESTED FOR QUIESCENT CURRENT
monostable multivibrator action with retriggering
■ MEETS ALL REQUIREMENTS OF JEDEC and external counting options. Inputs include
JESD13B " STANDARD SPECIFICATIONS +TRIGGER -TRIGGER, ASTABLE, ASTABLE,
FOR DESCRIPTION OF B SERIES CMOS RETRIGGER, and EXTERNAL RESET. Buffered
DEVICES" outputs are Q, Q and OSCILLATOR. In all modes
of operation, an external capacitor must be
DESCRIPTION connected between C-Timing and RC-Common
The HCF4047B is a monolithic integrated circuit terminals, and an external resistor must be
fabricated in Metal Oxide Semiconductor connected between the R-Timing and
technology available in DIP and SOP packages. RC-Common terminals.
The HCF4047B consist of a gatable astable For operating modes see functional terminal
multivibrator with logic techniques incorporated to connections and application notes.

PIN CONNECTION

September 2001 1/12


HCF4047B

INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION


1 C External Capacitor
2 R External Resistor
RC COM- External Connection to (1)
3
MON and (2)
Complement Astable
4 ASTABLE
Pulse
5 ASTABLE True Astable Pulse
6 -TRIGGER Negative Trigger Pulse
8 +TRIGGER Positive Trigger Pulse
9 EXT. RESET External Reset
RETRIG-
12 Retrigger Mode Pulse
GER
13 OSC. OUT Oscillator Output
10,11 Q, Q Q Outputs
7 VSS Negative Supply Voltage
14 VDD Positive Supply Voltage

BLOCK DIAGRAM

2/12
HCF4047B

FUNCTIONAL TERMINAL CONNECTIONS

TERMINAL CONNECTIONS OUTPUT


OUTPUT PERIOD OR
FUNCTION* Input Pulse PULSE
to VDD to VSS PULSE WIDTH
to FROM

Astable Multivibrator
Free Running 4, 5, 6, 14 7, 8, 9, 12 - 10, 11, 13 tA (10,11) = 4.40RC
True Gating 4, 6, 14 7, 8, 9, 12 5 10, 11, 13
Complement Gating 6, 14 5, 7, 8, 9, 12 4 10, 11, 13 tA (13) = 2.20RC
Monostable Multivibrator
Positive - Edge Trigger 4, 14 5, 6, 7, 9, 12 8 10, 11
Negative - Edge Trigger 4, 8, 14 5, 7, 9, 12 6 10, 11
Retriggerable 4, 14 5, 6, 7, 9 8, 12 10, 11 tM (10,11) = 2.48RC
External Countdown** 14 5, 6, 7, 8, 9, - 10, 11
12
* In all cases external capacitor and resistor between pins, 1, 2 and 3 (see logic diagrams).
** Input pulse to Reset of External Counting Chip.
External Counting Chip Output to pin 4.

LOGIC DIAGRAM

3/12
HCF4047B

DETAIL FOR FLIP-FLOPS FF1 AND FF3 (a) AND FOR FLIP-FLOPS FF2 AND FF4 (b)

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit


VDD Supply Voltage -0.5 to +22 V
VI DC Input Voltage -0.5 to VDD + 0.5 V
II DC Input Current ± 10 mA
PD Power Dissipation per Package 200 mW
Power Dissipation per Output Transistor 100 mW
Top Operating Temperature -55 to +125 °C
Tstg Storage Temperature -65 to +150 °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit


VDD Supply Voltage 3 to 20 V
VI Input Voltage 0 to VDD V
Top Operating Temperature -55 to 125 °C

4/12
HCF4047B

DC SPECIFICATIONS

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit


VI VO |IO| VDD
(V) (V) (µA) (V)
Min. Typ. Max. Min. Max. Min. Max.
IL Quiescent Current 0/5 5 0.01 1 30 30
0/10 10 0.01 2 60 60
µA
0/15 15 0.01 4 120 120
0/20 20 0.02 20 600 600
VOH High Level Output 0/5 <1 5 4.95 4.95 4.95
Voltage 0/10 <1 10 9.95 9.95 9.95 V
0/15 <1 15 14.95 14.95 14.95
VOL Low Level Output 5/0 <1 5 0.05 0.05 0.05
Voltage 10/0 <1 10 0.05 0.05 0.05 V
15/0 <1 15 0.05 0.05 0.05
VIH High Level Input 0.5/4.5 <1 5 3.5 3.5 3.5
Voltage 1/9 <1 10 7 7 7 V
1.5/13.5 <1 15 11 11 11
VIL Low Level Input 4.5/0.5 <1 5 1.5 1.5 1.5
Voltage 9/1 <1 10 3 3 3 V
13.5/1.5 <1 15 4 4 4
IOH Output Drive 0/5 2.5 <1 5 -1.36 -3.2 -1.15 -1.1
Current 0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
mA
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
IOL Output Sink 0/5 0.4 <1 5 0.44 1 0.36 0.36
Current 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 mA
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
II Input Leakage
0/18 Any Input 18 ±10-5 ±0.1 ±1 ±1 µA
Current
CI Input Capacitance Any Input 5 7.5 pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

5/12
HCF4047B

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

Test Condition Value (*) Unit


Symbol Parameter
VDD (V) Min. Typ. Max.
tPLH tPHL Propagation Delay Astable, Astable 5 200 400
Time to Osc. Out 10 100 200
15 80 160
Astable, Astable 5 350 700
to Q, Q 10 175 350
15 125 250
+ or - Trigger to 5 500 1000
Q, Q 10 225 450 ns
15 150 300
Retrigger to Q, Q 5 300 600
10 150 300
15 100 200
External Reset 5 250 500
to Q, Q 10 100 200
15 70 140
tTHL tTLH Transition Time Osc. Out Q, Q 5 100 200
10 50 100 ns
15 40 80
tW Input Pulse Width + Trigger 5 200 400
- Trigger 10 80 160
15 50 100
Reset 5 100 200
10 50 100 ns
15 30 60
Retrigger 5 300 600
10 115 230
15 75 150
tr, tf Input Rise and Fall Time All Inputs 5
10 Unlimited µs
15
Q or Q Deviation from 50% Duty 5 ±0.5 ±1
Factor 10 ±0.5 ±1 %
15 ±0.1 ±0.5
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.

APPLICATION INFORMATION mode, positive-edge triggering is accomplished by


application of a leading-edge pulse to the
1 - CIRCUIT DESCRIPTION +TRIGGER input and a low level to the -TRIGGER
Astable operation is enabled by a high level on the input. For negative-edge triggering, a trailing-edge
ASTABLE input. The period of the square wave at pulse is applied to the -TRIGGER and a high level
the Q and Q Outputs in this mode of operation is a is applied to the +TRIGGER. Input pulses may be
function of the external components employed. of any duration relative to the output pulse. The
"True" input pulses on the ASTABLE input or multivibrator can be retriggered (on the leading
"Complement" pulses on the ASTABLE input edge only) by applying a common pulse to both
allow the circuit to be used as a gatable the RETRIGGER and +TRIGGER inputs. In this
multivibrator. The OSCILLATOR output period will mode the output pulse remains high as long as the
be half of the Q terminal output in the astable input pulse period is shorter than the period
mode. However, a 50% duty cycle is not determined by the RC components. An external
guaranteed at this output. In the monostable countdown option can be implemented by
6/12
HCF4047B

coupling "Q" to an external "N" counter and power-on reset pulse, must be applied to the
resetting the counter with the trigger pulse. The EXTERNAL RESET whenever VDD is applied.
counter output pulse is fed back to the ASTABLE
input and has a duration equal to N times the
2 - ASTABLE MODE
period of the multivibrator. A high level on the
EXTERNAL RESET input assures no output pulse The following analysis presents worst-case
during an "ON" power condition. This input can variations from unit-to-unit as a function of
also be activated to terminate the output pulse at transfer-voltage (VTR) shift (33% - 67% VDD) for
any time. In the monostable mode, a high-level or free-running (astable) operation.

ASTABLE MODE WAVEFORMS

VTR
t1 = -RC In —————
VDD + VTR
VDD - VTR
t2 = -RC In —————
2VDD - VTR
(VTR)(VDD - VTR)
t3 = 2(t1+t2)= -2RC In ———————————
(VDD + VTR)(2VDD - VTR)

Typ : VTR = 0.5 VDD tA = 4.40 RC 3 - MONOSTABLE MODE


Min : VTR = 0.33 VDD tA = 4.62 RC The following analysis presents worst-case
Max : VTR = 0.67 VDD tA = 4.62 RC variations from unit-to-unit as a function of
thus if tA = 4.40 RC is used, the maximum transfer-voltage (VTR) shift (33% - 67% VDD) for
variation will be (+ 5.0%, -0.0%) one-shot (monostable) operation.
In addition to variations from unit-to-unit, the
astable period may vary as a function of frequency
with respect to VDD and temperature.

MONOSTABLE WAVEFORMS

VTR
t1 = -RC In ———
2VDD
VDD - VTR
t2 = -RC In —————
2VDD - VTR
(VTR)(VDD - VTR)
tM = (t1+t2)= -RC In —————————
(2VDD - VTR)(2VDD)

7/12
HCF4047B

Where tM = monostable mode pulse width. Values to extend the output-pulse duration, or to compare
for tM are as follows : the frequency of an input signal with that of the
Typ : VTR = 0.5 VDD tM = 2.48 RC internal oscillator. In the retrigger mode the input
Min : VTR = 0.33 VDD tM = 2.71 RC pulse is applied to terminals 8 and 12, and the
Max : VTR = 0.67 VDD tM = 2.48 RC output is taken from terminal 10 or 11. As shown in
Thus if tM = 2.48 RC is used, the maximum fig.A normal monostable action is obtained when
variation will be (+ 9.3%, - 0.0%). one retrigger pulse is applied. Extended pulse
Note : In the astable mode, the first positive half
duration is obtained when more than one pulse is
cycle has a duration of TM ; succeeding durations
are tA/2. applied. For two input pulses, tRE = t 1’ + t1 + 2t2.
In addition to variations from unit to unit, the For more than two pulses, tRE (Q OUTPUT)
monostable pulse width may vary as a function of terminates at some variable time tD after the
frequency with respect to VDD and temperature. termination of the last retrigger pulse. tD is variable
because tRE (Q OUTPUT) terminates after the
4 - RETRIGGER MODE second positive edge of the oscillator output
The HCF4047B can be used in the retrigger mode appears at flip-flop 4 (see logic diagram).

FIGURE A : Retrigger-mode waveforms

5 - EXTERNAL COUNTER OPTION A typical implementation is shown in fig. B. The


pulse duration at the output is
Time tM can be extended by any amount with the text = (N - 1) (tA) + (tM + tA/2)
use of external counting circuitry. Advantages Where text = pulse duration of the circuitry, and N
include digitally controlled pulse duration, small is the number of counts used.
timing capacitors for long time periods, and
extremely fast recovery time.

FIGURE B : Implementation of external counter option

8/12
HCF4047B

6 - POWER CONSUMPTION The capacitor used in the circuit should be


In the standby mode (Monostable or Astable), non-polarized and have low leakage (i.e. the
power dissipation will be a function of leakage parallel resistance of the capacitor should be an
current in the circuit, as shown in the static order of magnitude greater than the external
electrical characteristics. For dynamic operation, resistor used). Three is no upper or lower limit for
the power needed to charge the external timing either R or C value to maintain oscillation.
capacitor C is given by the following formula : However, in consideration of accuracy, C must be
Astable Mode : much larger than the inherent stray capacitance in
P = 2CV2f. (Output at Pin 13) the system (unless this capacitance can be
P = 4CV2f. (Output at Pin 10 and 11) measured and taken into account). R must be
(2.9CV2) (Duty Cycle) much larger than the COS/MOS "ON" resistance
Monostable Mode : P = ——————————
T in series with it, which typically is hundreds of
(Output at Pin 10 and 11) ohms. In addition, with very large values of R,
The circuit is designed so that most of the total some short-term instability with respect to time
power is consumed in the external components. In may be noted.
practice, the lower the values of frequency and
The recommended values for these components
voltage used, the closer the actual power
to maintain agreement with previously calculated
dissipation will be to the calculated value.
formulas without trimming should be :
Because the power dissipation does not depend
on R, a design for minimum power dissipation C > 100pF, up to any practical value, for astable
would be a small value of C. The value of R would modes ;
depend on the desired period (within the C > 1000pF, up to any practical value, for
limitations discussed above). monostable modes.
7 - TIMING-COMPONENT LIMITATIONS 10KΩ< R < 1MΩ.

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)


RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)

9/12
HCF4047B

Plastic DIP-14 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 1.39 1.65 0.055 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 15.24 0.600

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 2.54 0.050 0.100

P001A

10/12
HCF4047B

SO-14 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S 8° (max.)

PO13G

11/12
HCF4047B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics

© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved


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