IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO.

7, JULY 2018 849

A Novel 0.8-V 79-nW CMOS-Only Voltage

Reference With −55-dB PSRR @ 100 Hz
Jihai Duan, Member, IEEE, Zhiyong Zhu, Jinli Deng, Weilin Xu, and Baolin Wei

Abstract—A novel 79-nW CMOS-only subthreshold voltage

reference with 328-mV output voltage, which works down to
0.8-V supply voltage, is presented in this brief. In order to reduce
the area and power consumption, the proposed circuit avoids the
use of resistors and bipolar transistors. A current subtracting
technique is proposed to realize the temperature compensation of
reference current. Instead of the op-amp in traditional circuits,
some cascode current mirrors are used to enhance the power
supply rejection ratio (PSRR). A novel structure consisting of
a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to Fig. 1. Main idea of the proposed voltage reference core.
accomplish the voltage temperature compensation and to further
reduce the power consumption of VREF generator. The proposed
voltage reference was fabricated in 0.18-µm CMOS process. The
measured results show that the temperature coefficient of the some resistor-less voltage references operated at nanowatt
output voltage is 33.8 ppm/◦ C in the range from 10 ◦ C to 100 power consumption [5]–[8]. The circuits needed parasitic ver-
◦ C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and tical bipolar junction transistors (BJTs) in a standard CMOS
the line regulation is 0.21%/V in a supply voltage range of 0.8 to process. Unfortunately, the parasitic BJTs are not characterized
3.4 V. What is more, the power dissipation is 79 nW, and the well [9], and a large area is occupied. The circuit presented
chip area is 0.01 mm2 . It is suitable for low-power applications. in [1] is without BJTs and resistors. It generates two voltages
Index Terms—CMOS-only, current subtracting technique, having opposite temperature coefficients (TCs) and adds them
power consumption, cascode current mirrors, power supply to produce an output voltage. Because there are three branches
rejection ratio. in its voltage generator, the circuit needs three times of refer-
ence current to drive the voltage generator. Its power supply
rejection ratio (PSRR) is poor and the chip area is not small
I. I NTRODUCTION enough.
ITH the development of integrated circuit fabrica- In light of this background, a novel subthreshold voltage
W tion technology, the development of ultra-low power
Application Specific Integrated Circuits (ASICs) has been
reference with nanowatt power dissipation and high PSRR is
proposed in this brief. The circuit consists of only MOSFETs.
one of the promising areas of research in microelectronics. It was preferentially implemented with the standard CMOS
Developing a voltage reference circuit that can operate with an process. The main idea of the proposed voltage reference core
ultra-low current of several tens of nano amperes or less is the is illustrated in Fig. 1. Two current source circuits are used to
first step toward such ASICs. Designing the circuit which be obtain two proportional-to-absolute-temperature (PTAT) cur-
operated in the subthreshold region of MOSFETs can achieve rents. A temperature-independent reference current, obtained
such low power operation [1]. by subtracting the currents, is converted to voltage by the VREF
Several voltage references have been developed. However, generator. The circuit just needs one branch in the voltage
the power consumptions of them were several sub-uW [2]–[4]. generator.
The circuits required some passive resistors to realize volt-
age to current conversion and/or vice versa. Large resistance II. C IRCUIT D ESIGN
is needed to achieve such a power consumption level, which Fig. 2 shows the architecture of the proposed voltage refer-
increases the chip area substantially. Recent studies presented ence. It consists of PTAT-A current source [3], PTAT-Bcurrent
source, VREF generator and a start-up circuit. The two cur-
Manuscript received March 23, 2017; revised June 7, 2017; accepted
July 9, 2017. Date of publication July 19, 2017; date of current version
rent sources generate two PTAT currents, namely, IPa and
June 27, 2018. This work was supported in part by the National Natural IPb , respectively. The VREF generator realizes subtracting two
Science Foundation of China under Grant 61161003, Grant 61264001, and PTAT currents in a proportion by some current mirrors to
Grant 61166004, and in part by the Guangxi Key Laboratory of Precision generate a reference current IREF . IREF drives the core cir-
Navigation Technology and Application Foundation under Grant DH201501.
cuit consisting of MR1 and MR2 to obtain an output voltage
This brief was recommended by Associate Editor T. B. Tarim. (Corresponding
author: Jihai Duan.) insensitive to supply voltage and temperature variations. The
The authors are with the Guangxi Key Laboratory of Precision Navigation cascode current mirrors are used to enhance the PSRR of pro-
Technology and Application, Guilin University of Electronic Technology, posed bandgap voltage reference circuit. The start-up circuit
Guilin 541004, China (e-mail: [email protected]; [email protected]; is used to get rid of the degenerate bias points and to ensure
[email protected]; [email protected]; [email protected]).
Color versions of one or more of the figures in this paper are available
that the proposed voltage reference works normally.
online at http://ieeexplore.ieee.org. In traditional designs, the TC of resistors is ignored, but it
Digital Object Identifier 10.1109/TCSII.2017.2728700 has influence on temperature range. Therefore, the proposed
1549-7747 c 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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850 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 7, JULY 2018

From (7), the TC of Ipa is positive. Therefore, IPa will

increase as temperature increases.

B. The PTAT-B Current Source Circuit

A nano-ampere current source is used to reduce static cur-
rent based on the Oguey current reference source [10]. In the
PTAT-B current source circuit shown in Fig. 2, transistor M16
and M15 work in saturation and linear region, respectively.
The others work in subthreshold region. IPb is determined
by MOS resistor M15 with gate-source voltage VGS15 and
Fig. 2. Schematic of the proposed voltage reference. drain-source voltage VDS15 . Additional transistor M16 provides
a gate-voltage for transistor M15 .
The drain current of transistor M15 is given by
 
voltage reference uses MOSFETs working in deep-triode 1 2
region to replace resistors. ID15 = μCOX K15 (VGS15 − VTH15 )VDS15 − VDS15 (8)
2
A. The PTAT-A Current Source Circuit The voltage VDS15 is expressed by [5]


The PTAT-A current source shown in Fig. 2 uses CMOS VDS15 = VGS18 − VGS17 = ηVT ln K17 K18 (9)
source-coupled differential pairs to generate a nano-ampere The drain current of M16 is given by
PTAT current. In this current source circuit, transistor M2 and
M3 work in saturation region, transistor M1 works in linear μCOX
ID16 = K16 (VGS16 − VTH16 )2 (10)
region and others work in sub-threshold region. The difference 2
voltage Vp between gate-source voltages of M2 and that of else,
M3 can be given by
   ID16 = Q2 ID15 , ID15 =IPb , VGS16 = VGS15 (11)
  1 1 where Q2 is a scale factor. Taking (8), (9), (10) and (11) into
Vp = VGS2 − VGS3 = 2IPa μCOX − (1)
K2 K3 account, IPb could be given by [1]

2−m
where μ(= μ0 (T0 /T)m ) is the carrier mobility, T is the abso- IPb = μ0 COX K15 VT0
2
Q2 η2 Keff T T0 (12)
lute temperature, u0 is the carrier mobility at room temperature with
T0 , m is the mobility temperature exponent, COX is the gate-    
oxide capacitance, K is the aspect ratio of a transistor, VGS is Keff = S2 − 0.5 + S2 (S2 − 1) 2 ln2 (S1 )
the gate-source voltage, and VTH is the threshold voltage.  
The drain current ID of a MOSFET working in sub- S1 = K17 K18 S2 = Q2 K15 K16 (13)
threshold region is rewritten as [1] Because the value of m is about 1.5, the TC of IPb can be
   expressed as
ID = KI0 exp (VGS − VTH ) ηV T (2)
∂IPb 1 1
else, = μ0 COX K15 VT02
Keff Q2 η2 √ (14)
∂T 2 TT0
I0 = μCOX (η − 1)VT2 (3) From (14), the TC of Ipb is positive. Therefore, IPb will
where VT (= kB T/q) is the thermal voltage, kB is the increase as temperature increases.
Boltzmann constant, q is the elementary charge, and η is the
sub-threshold slope factor [5]. Vp can also be expressed as C. The VREF Generator Circuit
The simplified model of VREF generator circuit is shown
Vp = VGS4 − VGS5 + VGS6 − VGS7

in Fig. 3. Transistor MR2 (indicated with a symbol having
= ηVT ln K5 K7 K4 K6 (4) a thicker line for the gate) is a 3.3-V MOS transistor, and
the other transistors are 1.8-V MOS transistors. A current
From (1) to (4), current Ipa can be written as
  subtracting technique is used to control the temperature char-
IPa = μ0 · VT0
2 acteristic of the reference current IREF . The current is injected
 into the core of temperature-compensated circuit consisting of
2  2−m MR2 and MR1 .
COX K3 K5 K7 T
× · η ln · · (5) Some current mirrors are utilized to realize subtracting the
2(N − 1) 2 K4 K6 T0
two PTAT currents in a proportion, IREF can be expressed as
else, IREF = Q2 IPb − Q1 IPa (15)

N = K3 /K2 (6) where Q1 is a scale factor. The TC of IREF can be given by
where VT0 is the value of VT at room temperature T0 . Because ∂IREF 1 2 2 1
= μ0 COX VT0 η √
the value of m is about 1.5 for ordinary MOSFETs [5], the TC ∂T 2 TT0
of Ipa can be given by  2 
K3 Q1 K5 K7
2 C K η2 2 × K15 Keff Q2 −2
ln
∂IPa μ0 VT0 OX 3 K5 K7 2(N − 1)2 K4 K6
= √ · ln · (7)
∂T 4(N − 1)2 T0 T K4 K6 (16)

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DUAN et al.: NOVEL 0.8-V 79-nW CMOS-ONLY VOLTAGE REFERENCE WITH −55-dB PSRR @ 100 Hz 851

Fig. 4. IPTC , IREF and INTC .

Fig. 3. Simplified model of proposed VREF generator circuit.

From (16), it is obvious that the TC of IREF could be zero

by adjust Q1 , Q2 and the aspect ratios of transistors M2 -M7
and M15 -M18 . The IREF in [11] is the sum of a PTAT current
and a complementary to absolute temperature (CTAT) current,
however the power consumption is much larger than that of
this design.
The reference voltage generator in [1] had three branches Fig. 5. Simulated TCs of VREF with different drive currents.
to realize voltage temperature compensation and it needed
three times of reference current. A novel voltage temperature-
compensated circuit containing only one branch is proposed. same value according to (19), and then it is obvious that VREF
The operating principle of the circuit is described as follows. is about zero from (17). For this reason, a 1.8-V MOSFET
VREF in Fig. 3 can be expressed by the difference between the (MR1 ) and a 3.3-V MOSFET (MR2 ) are utilized to realize the
gate-source voltages of transistor MR1 and MR2 . According to voltage temperature compensation. VTH and tOX of a 1.8-V
the characteristics of sub-threshold current of MOSFET given MOSFET are about 490 mV and 3.45 nm in the process,
by (2) and [12], the reference voltage VREF can be given by respectively. Those of a 3.3-V MOSFET are about 705 mV
and 8.45 nm, respectively.
VREF = VGS,R2 − VGS,R1 By properly designing the size of the transistors, the ref-

KR1 · tOX,R1 erence voltage can have better immunity on temperature
= VTH + ηVT ln (17)
KR2 · tOX,R2 variation. A capacitor C was used to improve the PSRR of
proposed voltage reference.
where VTH (= VTH2 − VTH1 ) is the difference of VTH . A positive TC current (IPTC ), a negative TC current (INTC )
tOX,R1 and tOX,R2 are the oxide thickness of MR1 and MR2 , and IREF , shown in Fig. 4, are utilized to drive the volt-
respectively. age temperature-compensated circuit. The simulated TCs of
Substituting the expression for VTH [12], the TC of VREF VREF with different drive currents are shown in Fig. 5. From
can be given by Fig. 5, it is obvious that the TC of drive current has an
   effect on the TC of VREF . Therefore, the voltage temperature-
dVREF  tOX,R2 − tOX,R1 2NA εsi
= √
compensated circuit needs a drive currentwhich doesn’t change
dT T0 εOX 2kB T0 ln NA Nc Nv + Eg with temperature.
 
NA ηkB KR1 tOX,R2
× kB ln √ + ln D. Dependence of VREF and TC on Process Variation
Nc Nv q KR2 tOX,R1
 −1 Reference [1] discussed the dependence of VTH on process
√ variation including within-die (WID) variation and die-to-die
2qεsi NA
× 1+  (18) (D2D) variation. It presented VTH has little dependence on
2COX VREF |T0 + ψsi process variation. If we assumed that η and tOX are constant
where T0 is the concerned temperature and all other afore- parameters, according to (17) and (18), VREF and TC are quite
mentioned physical parameters have the same meanings as insensitive to process variation. However, η and tOX are not
defined in [12]. Equating (18) to zero, the condition of voltage constant parameters in actual devices [12], and this must be
temperature compensation can be expressed as taken into account in high-accuracy applications. We show
 these characteristics with the aid of computer simulation in
KR1 tOX,R1 tOX,R2 − tOX,R1 Fig. 7, Section III.
= · exp
KR2 tOX,R2 ηεOX
 √  III. S IMULATION R ESULTS
2NA εsi q2 Nc Nv The proposed voltage reference was simulated by
× √
× ln
2kB T0 ln NA Nc Nv + Eg NA SPECTRE. The TC of IREF , the TC of VREF , the PSRR and
(19) the line regulation were simulated at different process corners.
IREF is stable from -20 to 110◦ C at every process corners as
If transistor MR1 and MR2 belong to the same kinds of tran- shown in Fig. 6. Therefore, the current subtracting technique
sistors, tOX,R1 is equal to tOX,R2 . Hence, KR1 and KR2 have the realized current temperature compensation. Fig. 7 presents the

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852 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 65, NO. 7, JULY 2018

TABLE II
P ERFORMANCE C OMPARISON OF P ROPOSED VOLTAGE R EFERENCE

Fig. 6. Simulated TC of IREF . Fig. 9. Simulated line regulation.

Fig. 10. Chip microphotograph.

Fig. 7. Simulated TC of VREF .

TABLE I
K EY T RANSISTOR S IZES

Fig. 8. Simulated PSRR.

IV. M EASUREMENT R ESULTS

The proposed voltage reference with a buffer circuit was
temperature characteristics of VREF , and it is obvious that the implemented in 0.18-µm CMOS process, and its die photo-
temperature dependence is small in a wide temperature range. graph is shown in Fig. 10. Except the buffer circuit which is
Because the proposed design is connected with a low dropout used for test, the occupied chip area is 0.014 mm2 . Table I
regulator (LDO) to provide a reference voltage, the process presents the sizes of the key components in the proposed cir-
variation of VREF (about 47mV in Fig. 7) is tolerated [13]. cuit. The circuit consumes a total power of 79 nW under 1.2-V
Fig. 8 shows the PSRR is about -60dB @100Hz. It is evi- power supply at room temperature.
dent from Fig. 9 that the average of line regulation is about Fig. 11 plots the measured temperature behavior of three
0.20%/V. samples from 10 to 100◦ C. The mean output voltage was

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DUAN et al.: NOVEL 0.8-V 79-nW CMOS-ONLY VOLTAGE REFERENCE WITH −55-dB PSRR @ 100 Hz 853

Table II. It is obvious that the presented circuit performance

is superior to others in PSRR, area and power consumption.

V. C ONCLUSION
A voltage reference with ultra-low power consumption,
higher PSRR and smaller chip area has been designed and
implemented in 0.18-µm CMOS process. Unlike conven-
tional voltage references, the proposed circuit does not include
bipolar transistors and resistors. The current subtracting tech-
nique is proposed to realize the temperature compensation
of reference current (IREF ). It utilized the difference between
Fig. 11. Measured temperature behaviour. gate-source voltage of a 3.3-V MOS transistor and that of
a 1.8-V MOS transistor to generate the reference voltage. The
circuit operates down to a minimum input voltage of 0.8 V
and the quiescent current is in nano-ampere level. This kind
of circuit is especially important in a market where demand is
growing for battery-powered electronics requiring increasing
efficiency and longevity.

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