IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 1

A survey of FPGA-based LDPC decoders

Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi and Lajos Hanzo
School of ECS, University of Southampton, SO17 1BJ, UK
Corresponding author: [email protected]

Abstract—Low-Density Parity Check (LDPC) error correction including WiFi [3], WiMAX [4], DVB-S2 [5], CCSDS [6] and
decoders have become popular in communications systems, as ITU G.hn [7].
a benefit of their strong error correction performance and LDPC codes benefit from a number of appealing features
their suitability to parallel hardware implementation. A great
deal of research effort has been invested into LDPC decoder that make them very attractive for implementation. The LDPC
designs that exploit the flexibility, the high processing speed decoding algorithm can be implemented using low-complexity
and the parallelism of Field-Programmable Gate Array (FPGA) calculations, resulting in a relatively low design and im-
devices. FPGAs are ideal for design prototyping and for the plementation cost for the processing hardware. Like turbo
manufacturing of small-production-run devices, where their in- codes, LDPC codes are decoded iteratively, achieving an error
system programmability makes them far more cost-effective
than Application-Specific Integrated Circuits (ASICs). However, correction performance that is close to the theoretical limit
the FPGA-based LDPC decoder designs published in the open when decoding messages that have large block lengths [8].
literature vary greatly in terms of design choices and performance However, in contrast to turbo codes, there is a wide variety
criteria, making them a challenge to compare. This paper of possible algorithms and levels of parallelisation that may
explores the key factors involved in FPGA-based LDPC decoder be considered for the design of LDPC decoders, presenting
design and presents an extensive review of the current literature.
In-depth comparisons are drawn amongst 140 published designs designers with a range of options that may be relied upon to
(both academic and industrial) and the associated performance achieve the desired characteristics.
trade-offs are characterised, discussed and illustrated. Seven key However, while the design of the individual processing com-
performance characteristics are described, namely their process- ponents is relatively simple, the design of a complete LDPC
ing throughput, processing latency, hardware resource require- decoder is subject to a complex interplay between a number
ments, error correction capability, processing energy efficiency,
bandwidth efficiency and flexibility. We offer recommendations of system characteristics, namely the processing throughput,
that will facilitate fairer comparisons of future designs, as well processing latency, hardware resource requirements, error cor-
as opportunities for improving the design of FPGA-based LDPC rection capability, processing energy efficiency, bandwidth
decoders. efficiency and flexibility. These characteristics depend on a
Index Terms—Digital communication, error correction codes, number of system parameters, namely the architecture, the
low-density parity check (LDPC) codes, field programmable gate LDPC code employed, the algorithm used and the number of
array, iterative decoding decoding iterations. This relationship is shown in Fig. 1. Note
that the bandwidth efficiency also depends on the modulation
scheme chosen, as does the transmission energy efficiency,
I. I NTRODUCTION which furthermore depends on the coding gain and the error
correction capability of the chosen LDPC code. To elaborate
L OW-Density Parity Check (LDPC) codes may be em-
ployed for correcting transmission errors in communica-
tion systems. They represent a class of Forward Error Correc-
a little further in the context of Fig. 1, we can improve the
error correction capability in many different ways, for example
tion (FEC) codes that are currently the focus of much research by using a stronger LDPC code or more decoding iterations.
within the communications community. They were first pro- Naturally, increasing the number of iterations increases the
posed by Gallager in 1962 [1], but they were considered to complexity and hence reduces the processing energy effi-
be too complex for practical simulation and implementation at ciency, but increases the transmit energy efficiency. Hence the
the time of their conception, hence they were left largely un- total energy dissipation should be considered holistically, when
touched for decades. Apart from their excellent performance, designing an LDPC decoder. Further similar trade-offs will
perhaps partially motivated by the fact that the turbo codes emerge throughout our forthcoming discussions.
patented during the early 1990s attracted a license-fee, in 1996 In order to fully characterise an LDPC decoder design, it
LDPC codes were rediscovered by Mackay and Neal [2], and is necessary to physically implement it. Perhaps the simplest
ever since have enjoyed a renaissance. Given the increased way of doing so is to use a Field-Programmable Gate Array
computing power available today they have become a key (FPGA) device, which facilitates rapid prototyping and fast
component of many commercialised communication systems, parallel logic processing. This approach is especially useful
for measuring the Bit Error Rate (BER) performance, since
The financial support of the PhD studentship provided by Altera, California simulations that would take days on a computer can be
USA, the grants EP/J015520/1 and EP/L010550/1 provided by EPSRC, completed in only hours when using a custom FPGA imple-
Swindon UK, the grant TS/L009390/1 provided by Innovate UK, Swindon mentation [9]. These advantages are evident from the sheer
UK, as well as the Advanced Fellow grant provided by the European Research
Council is gratefully acknowledged. The research data for this paper is number of published FPGA-based LDPC decoder designs
available at http://dx.doi.org/10.5258/SOTON/384946. that exist in the open literature, which will be compared
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 2

Algorithm Architecture a brief tutorial on the LDPC code structure and encoding,
as well as describing variations on the decoding algorithms,
decoder architectures and FPGA devices. Section III provides
LDPC No. of
our comparison of all FPGA-based LDPC decoders that we are
code iterations
aware of, whilst discussing the parameters and characteristics
Parameters of an LDPC decoder in more detail. Section IV illustrates and
characterises the observed trade-offs and relationships between
the various parameters and characteristics of FPGA-based
LDPC decoders. Recommendations for readers interested in
Processing Characteristics developing their own FPGA-based LDPC decoders are offered
throughput Flexibility
in Section V, along with suggestions for further work in the
Processing Bandwidth area. Finally, we offer our conclusions in Section VI. This
latency efficiency structure is depicted in Fig. 2.
Hardware Transmission
requirements energy
Processing efficiency
energy Background
efficiency LDPC codes and encoding
Fig. 1. FPGA-based LDPC decoder system parameters and characteristics Decoding algorithms
Code structures
Decoder architectures
later in this paper. Furthermore, the decoding techniques and
implementation-oriented research presented alongside these FPGA devices
designs has been of significant benefit to the wider com- Comparison
munications research community [10]–[15]. In particular, the
Table of survey results
implementational characteristics of these FPGA-based LDPC
decoders are increasingly informing the holistic design of Description of parameters
communication systems. Description of characteristics
In addition to their suitability for prototyping, FPGAs con-
stitute a viable alternative to Application-Specific Integrated
Discussions
Circuits (ASICs) for the LDPC decoders of small-production- Trade-offs
run communication devices, while their programmability has Influence of parameters on certain characteristics
made them attractive for software-defined radios. This pa- Processing throughput
per focuses exclusively on FPGA implementations of LDPC Processing latency
decoders, since they cannot be fairly compared to ASIC Hardware resource requirements
implementations, which are designed at a significantly higher Transmission energy efficiency
development cost to have particularly high performance for
Recommendations and further work
high-production-run applications. Indeed, ASIC implementa-
tions are even difficult to compare with each other, because Conclusion
some papers provide post-synthesis results, while others offer
post-layout results. Meanwhile, some papers consider only Fig. 2. Structure of this paper
the ASIC core, while others include both the memory and
Input/Output (I/O) resources.
This paper has been conceived for achieving the following II. BACKGROUND
aims:
This section presents a tutorial on FPGA-based LDPC
• Provide a tutorial on LDPC decoding, discussing both the
decoders. Section II-A commences by discussing FEC, before
parameters and characteristics that affect the performance LDPC codes are introduced in Section II-B. This is followed
of FPGA implementations. by a discussion of how LDPC codes are decoded and designed
• Accurately compare all implementations of FPGA-based
in Sections II-C and II-D, respectively. The practicalities of
LDPC decoders that we are aware of. LDPC decoder implementations are then discussed in Sec-
• Characterise the observed trade-offs and relationships
tion II-E, which is followed by a brief introduction to FPGAs
between the system parameters and characteristics. in Section II-F.
• Recommend good practice to aid future designs of FPGA-
based LDPC decoders, and to make published designs
more comparable with each other. A. Forward error correction
• Identify opportunities for the further enhancement of Fig. 3 shows a schematic of a simplified communications
FPGA-based LDPC decoders. system, where the information message word m = {mi }K i=1
The structure of the paper is as follows. Section II presents is a vector of K bits, which is FEC encoded in order to obtain
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 3

the codeword c = {cj }N

j=1 , which is a vector of N > K bits. SNR per bit according to
The FEC encoder converts the K-bit message word m into Eb 1 Es
the N -bit codeword c by adding M = N − K parity bits to = × . (3)
N0 R N0
the message. The ratio of the message length K to the total
codeword length N is referred to as the coding rate R, The corruption imposed by the channel causes y to differ
from x in an unpredictable manner, potentially resulting in the
K N −M demodulation of a perturbed received codeword ĉ, potentially
R= = . (1)
N N including some transmission errors. The decoder of Figure 3
The M additional parity bits are derived from the K message is employed to recover the message word m̂, and without this
bits and hence they do not carry any information of their own. there would be no way of correcting (or even detecting the
However, they are used during the FEC decoding process to presence of) these errors.
allow transmission errors to be detected and even corrected, The error correction capability of a FEC decoder is affected
depending on the specific scheme used and on the severity of by the form of the information provided by the demodulator.
the corruption, as will be discussed below. Rather than using hard decisions to convert received symbols
into demodulated bits, superior error correction capability can
be obtained if the demodulator provides soft decisions, which
x are commonly expressed using the Logarithmic-Likelihood
m c
message Ratio (LLR) [16]. The sign of an LLR (positive or negative)
encoder modulator
channel expresses what the most likely value for the corresponding bit
is (0 or 1, respectively). Meanwhile, the magnitude of an LLR
expresses how likely this value is, where 0 represents complete
y uncertainty and ∞ represents absolute certainty. The value of
m̂ ĉ an LLR is calculated as
decoded de-
decoder P (ci = 0 | yi )
message modulator
c̃i = log , (4)
P (ci = 1 | yi )
Fig. 3. A communications system where c̃i is the output LLR, ci is the transmitted bit and yi is
the received symbol.
Various modulation schemes can be used for modulating Here, the logarithm is used because it reduces the dynamic
the codeword c onto the channel. As we shall show in range of the likelihood ratio, tending to produce values in
Section IV-B4, Binary Phase-Shift Keying (BPSK) modulation the range of −10 to +10, rather than 0.0001 to 10, 000.
is assumed for nearly all FPGA-based LDPC decoder research. This also allows probability intersections to be calculated
For this reason, we also assume the employment of BPSK using additions, rather than hardware-intensive multiplication
modulation throughout this tutorial discussion. It is important operations. LLRs are extensively used throughout the LDPC
to note however, that BPSK is a very simple modulation decoding process, as will be detailed below.
scheme, which is rarely employed alone in practical commu- When using BPSK modulation over an AWGN channel,
nication schemes. Therefore, considering BPSK modulation the demodulator can convert the received signals into LLRs
exclusively during the design phase could result in an LDPC according to
decoder which does not necessarily work satisfactorily in Eb
practical systems, where higher-order modulation schemes are c̃i = 4 × R × × Re(yi ). (5)
N0
employed. Note that our analysis in Section IV will take the
specific modulation scheme that was used into consideration,
B. LDPC codes
when comparing the error correction performance of various
FPGA-based LDPC decoders. This section provides an introduction to LDPC codes,
N commencing with their structure and the encoding process
BPSK generates the √ modulated symbol vector x = √ {xj }j=1 in Section II-B1. Following this, the decoder’s Parity-Check
according to xj = + Es when cj = 0 and xj = − Es when
Matrix (PCM) is introduced in Section II-B2 together with its
cj = 1, where Es is the transmission energy per symbol. Simi-
graphical representation using factor graphs in Section II-B3.
larly, there are several different ways of modelling the random
1) Encoding: Decoding an LDPC codeword is associated
corruption that is imposed by the channel upon the signal x
with a significantly higher complexity than the encoding
as it is transformed into the received signal y = {yj }N j=1 . In
process, because the decoder must consider every possible
common with most FPGA-based LDPC research, we assume
message word simultaneously, while operating on the basis
the Additive White Gaussian Noise (AWGN) channel model,
of soft decision LLRs rather than hard decision bits. For this
in which a random noise signal is added to the transmitted
reason, we focus our attention on LDPC decoders in this paper,
signal,
but the encoding process is explained briefly here for the sake
yj = xj + CN (0, N0 ), (2)
of completeness.
where CN (·) is the complex normal distribution and N0 is As described previously, LDPC codes permit the correction
the noise power spectral density. The Signal to Noise Ratio of transmission errors by supplementing each K-bit message
(SNR) is given by Es /N0 , and may also be expressed as the word with M parity bits in order to produce an N -bit
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 4

codeword, where N = K + M [17]. Codes which include the received codeword ĉ. Since all of the codeword bits involved
K bits of the message word within the N bits of the codeword in a parity check (including the parity bit itself) should have
are referred to as systematic, while non-systematic codes have a modulo-2 summation of 0, Equations (7a)–(7d) can be re-
codewords which do not directly contain the original message written as follows:
bits. There are 2K possible permutations of the K-bit message
c4 ⊕ c6 ⊕ c7 = 0 (10a)
word, each of which is mapped by the LDPC encoder to a
corresponding one of 2K legitimate codeword permutations. c1 ⊕ c3 ⊕ c4 ⊕ c6 ⊕ c8 = 0 (10b)
The error correction capability of the LDPC code depends on c2 ⊕ c5 ⊕ c9 = 0 (10c)
the minimum Hamming distance between any pair of these 2K c1 ⊕ c2 ⊕ c6 ⊕ c10 = 0. (10d)
legitimate codeword permutations. Naturally high minimum
distances are preferred, since these make it unlikely for a These equations are more commonly viewed as a PCM
legitimate codeword to be transformed into another by the H, which has N columns corresponding to the bits of the
distortion introduced during transmission. codeword and M rows corresponding to the parity checks. A
For example, a code with a message word length of K = 6 non-zero entry in any position Hji indicates that the i-th bit
and a codeword length of N = 10 employs M = N − K = 4 ci takes part in the j-th parity check. In the case of systematic
parity bits and has a coding rate of R = K/N = 3/5. In the codes H is related to G according to
case where the code is systematic, each codeword c may be H = A T IM .
 
(11)
of the form
Continuing our example from above, we have
c = [c1 , c2 , c3 , c4 , c5 , c6 , c7 , c8 , c9 , c10 ], (6)  
0 0 0 1 0 1 1 0 0 0
where c1 . . . c6 are the K = 6 bits of the message word m 1 0 1 0 1 1 0 1 0 0
and c7 . . . c10 are the M = 4 parity bits. Each of the parity H= 0 1 0 0 1 0
. (12)
0 0 1 0
bits represents a parity check covering a specific subset of the 1 1 0 0 0 1 0 0 0 1
message bits. As an example, the parity check bits may be
obtained according to the following modulo-2 summations of Upon obtaining a received codeword ĉ, the syndrome s can
message bits: be calculated according to s = ĉ × HT . In the case where ĉ is
a legitimate codeword permutation, the syndrome will equate
c7 = c4 ⊕ c6 (7a) to a vector of zeros. This may be demonstrated by re-using the
c8 = c1 ⊕ c3 ⊕ c5 ⊕ c6 (7b) codeword calculated in the previous subsection, which equates
to a (1 × M )-element vector of 0s when multiplied by HT .
c9 = c2 ⊕ c5 (7c)
Note however that an LDPC H matrix of the form shown
c10 = c1 ⊕ c2 ⊕ c6 . (7d) in (12) is very unusual in practice. As it will be explained in
The design of an LDPC code’s parity check equations is Section II-C1, the decoder’s error correction ability is dictated
subject to many complex factors, as will be briefly described by the number of non-zero entries in each row or column,
in Section II-D. Using these equations, a (K × N )-element which is referred to as its weight. More specifically, columns
generator matrix G can be constructed to efficiently describe with a weight of 1 can result in the decoder being unable
the encoding process. In a systematic code, G may adopt the to correct some transmission errors. This can be avoided
form by modifying the PCM H using elementary row operations
(modulo-2 additions and swaps). In the case of the above
 
G = IK A , (8)
example, this may lead to:
where IK is the (K × K)-element identity matrix and the  
columns of A represent each of the parity checks. The 1 0 0 1 1 0 1 0 1 1
0 1 1 0 1 0 0 1 0 1
generator matrix of the systematic code described above would H= 1 1 1 0 0 1 0 1 1 0 . (13)

therefore be
  0 1 0 1 1 1 1 0 1 0
1 0 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1
  This modified H avoids any weight-1 columns, while still
0 0 1 0 0 0 0 1 0 0 checking the same distribution of parity bits that was added
G=  . (9) to codewords by the generator matrix G of (9). Note however
0 0 0 1 0 0 1 0 0 0

0 0 0 0 1 0 0 1 1 0 that this toy-example PCM is still unusual for a realistic LDPC
0 0 0 0 0 1 1 1 0 1 code. Specifically, the PCM used in LDPC decoding should be
sparse, containing far fewer non-zero entries than 0s. Clearly,
Codewords can be calculated using this matrix by finding the H of (13) does not satisfy this constraint, owing to its
the modulo-2 matrix product of the message m and the gener- codeword length of N = 10, which is very short compared
ator matrix G, according to c = m × G. For example, it may to practical LDPC codewords, which tend to be hundreds or
be readily verified that the message m = [0 1 1 1 0 1] has the even thousands of bits long.
corresponding codeword c = m × G = [0 1 1 1 0 1 0 0 1 0]. Owing to its significance in the decoding process, the PCM
2) Parity-check matrix: In the decoder, the parity checks H is commonly used to define a particular LDPC code design.
are used to detect the presence of transmission errors in the As discussed later in Section II-D, creating a H matrix that
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 5

achieves a strong error correction capability is a complex task, output messages that are sent back to the nodes it is connected
so this is usually the first aspect of the code to be designed. to. Thus the processing of the LDPC decoder is delegated to
Following this, the generator matrix G can be derived from the many individual calculations performed by the individual
H, by following the reverse of the process described above. nodes, rather than being a single monolithic global equation.
3) Factor graphs: The PCM H can also be visualised An important facet of the belief propagation algorithm is that
graphically using a factor graph, which is also known as a any message sent to a particular node does not depend on
Tanner graph [18]. This is exemplified in Fig. 4 for the PCM the message received from that node. For example, CN c2
of (13). A factor graph is comprised of two sets of connected is connected to VNs v2 , v3 , v5 , v8 and v10 ; however, the
nodes, namely N Variable Nodes (VNs) for representing the message r̃2−5 it sends to v5 will be calculated based only
columns of H and M Check Nodes (CNs) for representing on the messages it has received from v2 , v3 , v8 and v10 .
the rows. Nodes are activated in an order determined by the LDPC de-
coder’s schedule. This has a significant effect upon the LDPC
Variable nodes
P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10
decoder’s error correction capability, as well as on its other
characteristics. Many different schedules exist and the most
v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 common options will be outlined in Section II-C1. Following
this, variations of the specific calculations performed within
CNs and VNs will be presented in Sections II-C2 and II-C3
respectively.
q̃4−1 r̃4−9
1) Scheduling: The schedule of the LDPC decoding pro-
Edges
cess determines the order in which VNs and CNs are pro-
cessed, as well as whether multiple nodes are processed in
c1 c2 c3 c4
parallel. Many scheduling variations exist, but the three most
common schedules are described here, namely flooding [20],
Check nodes Layered Belief Propagation (LBP) [21] and Informed Dynamic
Scheduling (IDS) [22].
Fig. 4. A factor graph for an example LDPC code
Flooding is perhaps the most conceptually simple LDPC
decoding schedule. Here, the factor graph is processed in an
The connections P̃i above each VN in Fig. 4 pertain to
iterative manner, where each iteration comprises the simul-
LLRs associated with the N codeword bits of ĉ. An edge
taneous activation of all CNs, followed by the simultaneous
connects the i-th VN vi to the j-th CN cj if there is a non-
activation of all VNs [19]. An example of this schedule is
zero element in the i-th column and j-th row of H, Hji = 1.
depicted in Fig. 5. It can be seen that at first the CNs c1 –c4
To illustrate this, all of the edges that are connected to the 1st
shown in dark grey calculate their messages, which are then
CN c1 in Fig. 4 are shown with thicker lines. These edges are
connected to the 1st , 4th , 5th , 9th and 10th VNs, in accordance
to the position of the 1s in the top row of H in (13). P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10
The degree of a node is defined as the number of other nodes
that it is connected to and is equal to the corresponding row or v1 v2 v3 v4 v5 v6 v7 v8 v9 v10
column weight in H. The degree of the CNs Dc and the degree
of the VNs Dv are important parameters in an LDPC code. If
all CNs have the same degree Dc and all VNs have the same
degree Dv , the LDPC code is said to be regular. If either value
varies from node to node, the code is said to be irregular and
Dc and Dv can be expressed as the average degree over all
nodes. For example, the factor graph of Fig. 4 is irregular with c1 c2 c3 c4
Dc = 5.75 and Dv = 2.3. In any case, the number of 1s in
the PCM H must be the same regardless, whether it is viewed
row-by-row or column-by-column, giving Dc ×M = Dv ×N , P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10

with Dv = Dc × (1 − R).
v1 v2 v3 v4 v5 v6 v7 v8 v9 v10
C. LDPC decoding
LDPC codes are typically decoded using a belief propa-
gation (BP) algorithm in which messages – typically in the
form of LLRs – are iteratively passed in both directions along
the edges between connected nodes [19]. For example, Fig. 4
illustrates a message q̃4−1 sent from the 4th VN v4 to the 1st
c1 c2 c3 c4
CN c1 , while the message r̃4−9 is sent from the 4th CN c4
to the 9th VN v9 . The messages provided as inputs to a node
are processed by activating that node, causing it to create new Fig. 5. An example of the flooding schedule
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 6

sent along every edge (in bold) to every receiving VN, shown P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10
in light grey. In the second half-iteration, the VNs are shown
in dark grey to indicate that they are performing calculations, v1 v2 v3 v4 v5 v6 v7 v8 v9 v10
while the CNs are only receiving messages, so they are shown
in light grey.
While Layered Belief Propagation also operates in an
iterative manner, it processes the nodes more sequentially
within each iteration, activating only one or a specific subset
of nodes at a time [21]. LBP is commonly operated in a CN-
centric manner, processing each CN in turn. Once a CN has c1 c2 c3 c4
been activated, all of its connected VNs are activated before
moving on to the next CN. Once every CN has been processed,
P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10
the iteration is complete. Using Fig. 6 as an example, LBP
may commence each decoding iteration by activating CN c1
v1 v2 v3 v4 v5 v6 v7 v8 v9 v10
first, sending messages to each of its connected VNs: v1 , v4 ,
v5 , v7 , v9 and v10 . Each of these VNs may then be activated,
sending new messages to each of their connected CNs, except
c1 . Following this, c2 may be activated, allowing it to make
use of the new information received from v5 and v10 alongside
the information previously received from its other connected
VNs. This process continues until every CN has been activated,
which then marks the end of one decoding iteration. c1 c2 c3 c4
LBP has the advantage that the information obtained during
an iteration is available to aid the remainder of the iteration. P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10
Owing to this however, it does not have the same high level
of parallelism as the flooding schedule, possibly resulting in a v1 v2 v3 v4 v5 v6 v7 v8 v9 v10
lower processing throughput and a higher processing latency.
It can also be seen that M CN activations and Dc × M VN
activations occur per iteration, resulting in a higher computa-
tional complexity per iteration, when compared to the flooding
schedule. However, it will also be shown in Section II-C2
that CN activations can be significantly more computationally
expensive than the VN activations, hence the increased cost c1 c2 c3 c4
is manageable. Additionally, LBP tends to converge to the
correct codeword using fewer iterations and therefore with
Fig. 6. An example of the layered belief propagation schedule
lower computational complexity than flooding [17], resulting
in lower complexity overall.
Informed Dynamic Scheduling inspects the messages that
are passed between the various nodes, selecting to activate All of the residuals in the graph are then compared for the
whichever node is expected to offer the greatest improvement sake of identifying the new maximum, before the process is
in belief [22]. This requires IDS to perform additional calcula- repeated.
tions in order to determine which node to activate at each stage Using Fig. 7 as before, suppose that at the start of the
of the decoding process. However, IDS facilitates convergence iterative decoding process, the message r̃3−8 from CN c3 is
using fewer node activations than in either flooding or LBP, identified as having the highest magnitude of all the check-to-
which may lead to a lower complexity overall. variable messages in the graph. Owing to this, r̃3−8 is passed
During IDS, the difference between the previous message to the VN v8 , which is then activated, in order to obtain
sent over an edge and the message that is obtained using the message q̃8−2 which is then passed to c2 . The CN c2
recently-updated information [23] is calculated. This differ- can then be activated to calculate new residuals for its other
ence is termed the residual, and represents the improvement four edges, as the difference between their previous messages
in belief that is achieved by the new message. Like the LBP and their new messages that have been obtained using the
schedule, IDS is commonly centred on the CNs. At the start updated information from v8 . These new residuals are then
of the iterative decoding process, the residual for each output compared with the others from the previous step, allowing a
of each CN is calculated as the magnitude of the message to new global maximum to be identified, to inform the next step
be sent over that edge. The message with the greatest residual of the decoding process. Note that the next highest residual
is identified, and the receiving VN is then activated, sending within the factor graph does not necessarily have to originate
updated messages to each of its connected CNs. These CNs from the most recently updated CN c2 . In the example seen in
then calculate new residuals for each of their edges as the Fig. 7, it can be seen that c2 is activated to calculate residuals
difference between its new message and its previous message. but it is r̃1−4 from CN c1 to VN v4 that is sent. This implies
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 7

P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10 for which we use the notation ã
b̃, referred to as the boxplus
operator [27]. Inverting (4) and substituting into (14) yields:
v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 !
−1 ã b̃
ã
b̃ = 2 tanh tanh × tanh (15)
2 2


 
= sign ã × sign b̃ × min |ã|, |b̃|
   
+ log 1 + e−|ã+b̃| − log 1 + e−|ã−b̃| . (16)

c1 c2 c3 c4 The SPA uses the full version of (15) given above, which
leads to strong error correction performance but a high compu-
tational complexity. The MSA, on the other hand, is a reduced-
P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10
complexity approximation of the SPA [28], using (16) without
the correction factor terms, according to
v1 v2 v3 v4 v5 v6 v7 v8 v9 v10  



ã
b̃ = sign ã × sign b̃ × min |ã|, |b̃| . (17)

Note however that the complexity reduction offered by the

MSA is attained at the cost of a degraded LDPC error correc-
tion capability. This degradation may be mitigated by adding
a low-complexity approximation to the correction factor terms
to (17) or by multiplying (17) by a scaling factor, which may
c1 c2 c3 c4
be optimised during the design of the LDPC decoder.
3) Variable node calculations: The calculations performed
P̃1 P̃2 P̃3 P̃4 P̃5 P̃6 P̃7 P̃8 P̃9 P̃10 in the VNs do not generally vary between algorithms. As in
the operation of the CNs, the message q̃i−j passed from VN
v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 vi to CN cj is obtained as the sum of the LLRs received
from all other edges, including the LLR P̃i provided on the
edge from the demodulator [26]. When using a schedule that
requires the simultaneous update of the outputs provided to
all of the VN’s edges (such as the flooding schedule), the
forward-backward algorithm [24] may be used to minimise the
number of additions required by the VN. In other schedules,
c1 c2 c3 c4 small internal memories may be used to store the results of
some intermediate additions [21].
Fig. 7. An example of informed dynamic scheduling
The VNs are also used for deciding the values of the
reconstructed codeword bits. Each corresponding codeword
LLR L̃i is calculated as the sum of the LLRs received on the
edges from all connected CNs, as well as on the edge from the
that there is no single straightforward concept of iterations in demodulator. The polarity of the resultant LLR is then used
IDS, since it is possible for a particular CN to be updated to make a hard decision for the value of the corresponding bit
several times before another is updated once. of the reconstructed codeword ĉ. More specifically, if L̃i < 0
2) Check node calculations: The calculations performed then ĉi is set to 1, whereas if L̃i ≥ 0 then ĉi is set to 0.
within the CNs vary between different LDPC decoding al- If the reconstructed codeword has a zero-valued syndrome
gorithms. Of the many that exist, the two most common s = ĉ × HT , then the iterative decoding process may be
LDPC decoding algorithms are the Sum-Product Algorithm considered to have been a success and the process may be
(SPA) [24] and the Min-Sum Algorithm (MSA) [25]. terminated. If not, then the iterative decoding process may be
continued until a zero-valued syndrome is obtained or until
When the j-th CN is activated, the LLR r̃j−i that it passes
an affordable complexity limit is reached. Practical LDPC
to VN vi is a function of the inputs gleaned from all other
decoder designs may also include other stopping criteria, as
connected VNs, except for vi [26]. In CN cj , this message
discussed later in Section II-E3.
will represent the probabilities that the bit at vi should be 0 or
1, which is determined by whether parity check j has already
been fulfilled by the bits of the other connected VNs. This is D. LDPC code construction
achieved by calculating the probability that cj is receiving an In addition to the size of the factor graph and the degrees
even number of 1s from its other edges. For two LLR operands of its nodes, the position of the edges within the factor graph
ã and b̃ this equates to also has a significant impact on the associated error correction
P (a = 0)P (b = 0) + P (a = 1)P (b = 1) performance, as well as upon the decoding complexity. Some
r̃j−i = log , (14) of the main objectives when designing the PCM H is to avoid
P (a = 0)P (b = 1) + P (a = 1)P (b = 0)
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 8

creating stopping sets [29] and short cycles [30] in the cor- standards, including DVB-S2 [5], IEEE 802.11 (WiFi) [3] and
responding factor graph, which are associated with an eroded IEEE 802.16 (Mobile WiMAX) [4].
error correction performance. A number of techniques have 4) Repeat-accumulate codes: Repeat-accumulate (RA)
been proposed for placing edges within the factor graph have codes constitute another type of semi-structured codes. Like
been proposed, as summarised in the following subsections. QC codes, RA codes benefit from simpler encoding/decoding
1) Random codes: Unstructured randomly-designed codes than random codes, without imposing an unacceptable loss
potentially achieve the best LDPC error correction perfor- in error correction performance. The PCMs of RA codes are
mance, owing to the maximised degree of freedom that is composed of two horizontally-concatenated submatrices H1
afforded, when placing edges in this manner [31]. However, and H2 , where H2 is an (M × M )-element dual-diagonal
this is achieved at the cost of having to implement complex matrix. This structure allows each parity bit to be calculated
unstructured routing or memory lookup tables, in order to ex- using only the previous parity bit and a subset of the message
change LLRs between the variable and CNs. A straightforward bits, leading to the accumulation alluded to in the code’s name.
recursive algorithm for creating unstructured PCMs of this 5) Progressive edge growth algorithm: Whilst not a code
form involves placing a 1 at a random unfilled location in H, structure itself, the Progressive Edge Growth (PEG) algo-
then checking to see whether doing so has violated any design rithm [34] is an important technique of constructing codes
constraints, such as the maximum node degrees, stopping sets having an excellent error correction performance. The oper-
or cycle lengths. If the placement is valid, the algorithm will ation of the PEG algorithm is VN-centric, focusing on each
continue and repeat the process for the next randomly placed VN in turn in order to place edges. The algorithm repeatedly
1. This is repeated until the desired number of edges have constructs a set of CNs as candidates for the VN to connect to.
been positioned. If a randomly placed 1 is not valid, then it From this set, the subset of nodes having the lowest degree is
will be rejected and a new location will be tried instead. This extracted and one of these is randomly selected. This approach
algorithm is conceptually very simple, but whether the process results in LDPC codes that have approximately regular degree
can successfully complete and how quickly is unpredictable. distributions.
2) Pseudorandom codes: The original LDPC code con- The PEG algorithm constructs a tree structure, alternating
struction method proposed by Gallager [1] involves stack- between the connection of VNs to CNs and vice versa. At
ing Dc number of submatrices on top of each other. Each each stage only nodes that are not already in the tree are
submatrix has the dimensions M/Dc × N , with each column considered for inclusion. This process continues until there
having a weight of 1 and each row having a weight of Dv . are no remaining options meeting this constraint. The PEG
The top matrix is pseudo-randomly generated, and random algorithm then places an edge in the location that is identified
column permutations are applied to it in order to obtain all as maximising the length of the resultant cycle within the
other submatrices. graph, before continuing the algorithm with the selection of a
Similarly to this, Mackay [2] proposed a code construction different VN. In this way, a factor graph having no short cycles
method, which involves constructing the PCM H on a column- can be created, yielding a strong error correction performance.
by-column basis, where the columns are generated pseudo-
randomly with appropriate weight, before being concatenated E. LDPC decoding architectures
horizontally. Again, this process must be performed in a The implementation of a practical LDPC decoder is subject
recursive manner, so that the row weights can be checked after to numerous design decisions, such as the degree of paral-
each column is added. If Dc has been exceeded for any row, lelism, the representation of the LLRs and the stopping criteria.
then the current column is regenerated. These three factors are discussed in the following subsections.
3) Quasi-cyclic codes: An LDPC code wherein the cyclic 1) Parallelism: The inherent parallelism of the belief prop-
shift of any legitimate codeword permutation by s places to the agation algorithm facilitates the design of fully-parallel LDPC
left or right yields another legitimate codeword permutation is decoder architectures, in which every VN and CN in the factor
termed Quasi-Cyclic (QC), while the code is termed cyclic graph is implemented separately in hardware [35]. Fully-
in the special case of s = 1. The PCMs of QC codes parallel decoders can achieve very high processing throughputs
are semi-structured, based on an upper matrix of elements by performing all of the VN updates and all of the CN
which each represent an equally-sized square submatrix [32]. updates simultaneously, using the flooding schedule of Fig. 5.
If a particular element in the upper matrix has a value However, this is achieved at the cost of excessive hardware
of -1, then the corresponding submatrix is a null matrix. resource consumption. For long codes comprising thousands
Otherwise, the submatrix is an identity matrix, which has of bits, the inter-node routing may require a greater area
been cyclically shifted a number of times according to the than the nodes themselves [36], rendering this architecture
corresponding value in the upper matrix [33]. Adopting this impractical for many decoder designs. Additionally, significant
structure facilitates low complexity memory addressing and further hardware resources are required for implementing
routing for the hardware implementation, since the location of flexible routing, using a Beneš network [37], for example.
every edge in each submatrix can be determined using only Otherwise, fully-parallel decoders are completely inflexible,
knowledge of the relatively small upper matrix. This advantage only supporting the single code that they are designed for.
can be achieved without incurring a significant sacrifice in By contrast, decoders associated with a fully-serial archi-
error correction performance. Owing to this benefit, QC- tecture implement just a single one of each node type in hard-
LDPC codes are employed by a number of communications ware. This hardware is time-multiplexed between the various
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 9

nodes of the LDPC decoder, using memories to store interim iteration to determine whether the current state of the recov-
results [35]. Fully-serial decoders require few hardware re- ered codeword is a legitimate permutation or not, signalling
sources but suffer from a very low processing throughput, whether or not decoding has been successful. These checks
since each decoding iteration could require thousands of clock are performed based on the output of the VNs, as mentioned
cycles. However, since all of the factor graph edges are previously in Section II-C3.
represented by memory addresses, fully-serial decoders can Occasionally however, a received frame is corrupted in such
be readily adapted at run-time to implement a different LDPC a way that it can never be corrected. In this case, the iterative
factor graph, by rearranging the memory accesses. decoding process would loop infinitely, unless other criteria
In order to strike a compromise between the high processing for stopping it were implemented. Owing to this, a maximum
throughput of fully-parallel architectures and the more mod- iteration or complexity limit may be imposed. When this limit
est hardware requirement of fully-serial architectures, many is reached, the iterative decoding process is terminated and
LDPC decoders implement a number of time-multiplexed decoding is deemed to have failed. In implementations where
nodes in a so-called partially-parallel fashion. This parametriz- a low hardware resource requirement is a greater priority than
able degree of parallelism facilitates control over the trade- high processing throughput, the iteration limit may be the only
off between processing throughput and hardware resource re- stopping criterion imposed. Here, every received message is
quirements. Furthermore, this approach is of particular benefit decoded using the same number of iterations, without early
when any structure within the PCM H can be exploited in the stopping. In this case, the parity checks are only used at the
configuration of the nodes implemented in hardware. For this end of the iterative decoding process, in order to determine
reason, QC codes are particularly suited to partially-parallel whether the recovered codeword is valid or not. Early stopping
implementations. can also be used to detect that no error correction progress is
2) Representation of LLRs: Another architectural consider- being made with successive decoding iterations, allowing the
ation is the digital representation of the LLRs passed between decoding process to fail and terminate before the iteration limit
nodes. The algorithms described earlier can be modified to is reached.
replace the LLRs with single-bit hard decisions, but this causes
them to suffer from a significant error correction performance
F. FPGAs
loss. In general, increasing the resolution and range of the
two’s complement fixed point LLR representation by using a FPGAs are digital logic devices that can be flexibly pro-
greater bit width has a positive effect on the error correction grammed to perform a variety of digital functions, using
performance [38], at the cost of increasing the hardware a Hardware Description Language (HDL). Their main ad-
resources required. vantages are their in-field-programmability, as well as their
It is therefore desirable for a designer to quantify the effect high-speed very-parallel logic processing. Owing to these
of the fixed-point bit width on the performance of a chosen benefits, FPGAs are desirable for a multitude of applications,
decoding algorithm, in order to determine the smallest number including software-defined radio, ASIC prototyping, digital
of bits that are required in order to achieve a satisfactory error signal processing, cryptography and computer hardware emu-
correction performance. This may be achieved using Extrinsic lation. This section presents a simplified view of their internal
Information Transfer (EXIT) charts [39], which have been structure, followed by a discussion of the main differences and
conceived by ten Brink for characterising the operation of similarities between different makes and models of FPGAs,
iterative decoding algorithms. More specifically, EXIT charts and how they may be compared to each other.
visualize the quality of the LLRs output by the VNs and 1) Structure: The internal structure of an FPGA typically
CNs as functions of the quality of the LLRs provided to the comprises a variable number of three main programmable ele-
corresponding inputs. By plotting these EXIT functions for ments, namely logic blocks, RAM blocks and I/O blocks [44].
LDPC decoders employing a range of fixed-point bit widths, The inputs and outputs of these blocks are linked by pro-
a designer can quantify at a glance, how each representation grammable routing, as shown in the sample schematic of
improves or degrades the quality of the LLRs and hence Fig. 8.
the resultant error correction performance of the LDPC de- The most fundamental design of a logic block comprises
coder [40]. This eliminates the requirement to run multiple a Lookup Table (LUT) and a Flip-Flop (FF), as shown in
time-consuming BER simulations. Fig. 8. A LUT is a digital structure that can be programmed
Further to this, some designs have demonstrated that the to perform any combinatorial function of its inputs, thus
hardware requirement can be reduced by using non-uniform mimicking any possible combination of logic gates. Typically,
quantisation schemes [41], by sending the bits of the LLR in FPGA LUTs have 4–6 inputs, which are used to select a value
a serial fashion rather than in parallel [42], or by utilising for a single output bit. Increasing the number of LUT inputs
stochastic [36] or non-binary [43] number representations. typically allows the same HDL design to be implemented
However, these methods can also have adverse effects on the using fewer LUTs, therefore reducing the amount of FPGA
node complexity and the decoding throughput, requiring yet routing required. However, the hardware resources required by
further investigation. a LUT increase exponentially with its number of input bits,
3) Stopping criteria: The design of an LDPC decoder hence very large LUTs are impractical [44]. The output of
also has to consider how to terminate the decoding process. each LUT can optionally be connected to a corresponding FF,
Commonly, checks are carried out following each decoding for facilitating synchronous operation. Alternatively, the LUT
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 10

generation of the FPGA. Earlier models of Xilinx FPGAs, such

Logic blocks as the Virtex 2, employ a simple slice structure which is based
on 4LUTs, while more recent models utilise 6-input Lookup
Tables (6LUTs) and a more complex slice structure that allows
them to be used in a larger number of configurations.
RAM blocks 3) Comparing FPGAs: Due to the differences outlined
above, comparing the hardware resources employed by the var-
ious designs implemented on different FPGAs is not straight-
forward. To this end, we propose an approximate metric based
Programmable on the fundamental building blocks of FPGAs, namely the
interconnect 4LUT and the FF [45]. We refer to this metric as equivalent
logic blocks (ELBs), since it attempts to approximate the
number of simple logic blocks comprising one 4LUT and
I/O blocks one FF that would be required to implement each design.
When calculating the number of ELBs, the LUT resources
within each Altera ALM are considered to be equal to two
4LUTs, since this is one of the operating modes they offer.
L Similarly, to compensate for the increased size of 6LUTs
U compared to 4LUTs, and the additional logic that accompanies
T 6LUTs within Xilinx slices, each Xilinx 6LUT is considered
FF to be approximately equal to two 4LUTs. Once this has been
taken into consideration, we assume that the number of ELBs
required by a design is given by the maximum of the number
4LUTs and the number of FFs that it requires.
Table I presents an overview of the main generations and
Fig. 8. FPGA structure models of FPGAs available from Altera and Xilinx, along with
the year of their release and the maximum number of ELBs
available within the largest FPGA from each family.
output can be connected directly to the inter-block routing
channels. These channels can be programmed to connect any
set of logic block outputs to any set of logic block inputs, TABLE I: Comparison of FPGAs available from Altera and Xilinx
subject to the FPGA size constraints.
Technology Max.
Instead of logic blocks, some locations within an FPGA Manufacturer Model Year
scale (nm) ELBs
structure may contain a RAM block for storing intermediate Xilinx Virtex 1998 220 24,576
calculation results. The size of these RAM blocks depends Xilinx Virtex E 1999 180 64,896
on the particular FPGA being used, as does their access Xilinx Virtex 2 2000 150 93,184
control. More specifically, some FPGAs provide dual-port Altera Cyclone 2002 130 20,060
RAMs, which allow reading and writing to two different Altera Stratix 2002 130 79,040
Xilinx Spartan 3 2003 90 66,560
locations simultaneously. Some FPGAs may also include
Altera Cyclone 2 2004 90 68,416
additional heterogeneous blocks, such as hardware multipliers
Altera Stratix 2 2004 90 143,520
and embedded processor cores, alongside non-volatile memory Xilinx Virtex 4 2004 90 178,176
for storing the FPGA configuration when it is turned off [44]. Altera Stratix 3 2006 65 270,000
2) FPGA vendor conventions: The two main vendors of Xilinx Virtex 5 2006 65 414,720
FPGAs are Xilinx and Altera. Their respective FPGAs share Altera Arria 2007 90 72,172
a number of similarities, but also exhibit some differences. Altera Cyclone 3 2007 65 198,464
Some Altera FPGAs, such as the first four generations of the Altera Stratix 4 2008 40 650,440
Cyclone family, follow the structure outlined above, operating Altera Cyclone 4 2009 60 149,760
on the basis of so-called “Logic Elements” (LEs), each of Altera Arria 2 2009 40 278,800
Xilinx Spartan 6 2009 45 184,304
which comprises one 4-input Lookup Table (4LUT) and one
Xilinx Virtex 6 2009 40 948,480
FF. However, more recent Altera FPGAs are structured around
Altera Stratix 5 2010 28 718,400
“Adaptive Logic Modules” (ALMs), each of which comprises Altera Cyclone 5 2011 28 227,120
two FFs and multiple small LUTs. These ALMs also contain Altera Arria 5 2011 28 380,480
extra logic that optionally allows the LUTs to be combined in Xilinx Artix 7 2011 28 269,200
a variety of ways, offering the functionality of larger LUTs. Xilinx Kintex 7 2011 28 597,200
By contrast, the logic resources of Xilinx FPGAs are quanti- Xilinx Virtex 7 2011 28 1,424,000
fied in terms of “slices”, each of which contains several LUTs
and FFs. The nature and quantity of the hardware resources Note that the proposed ELB metric is by no means per-
available within each slice varies depending on the model and fect, since it does not consider the overhead associated with
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 11

routing between logic elements or the use of additional FPGA is the degree of parallelism, which may be classified as fully-
blocks, such as memory or embedded multipliers. However, parallel, partially-parallel or fully-serial. This parameter may
it does serve as a functional approximation of the hardware be quantified by the total number of Processing Units (PUs)
requirements associated with each design considered, if they instantiated by the decoder, as listed in Table II. Frequently
were all implemented on the same FPGA. Measuring the usage these processors perform the function of individual VNs and
only in terms of these fundamental building blocks permits a CNs, although some designs use a different approach.
comparison between modern FPGA models and much older The operand width of the LLR representation, as listed in
designs, which would not otherwise be possible. Table II, is also a measurable parameter, which affects the
LDPC decoder’s error correction performance. Designs using
III. C OMPARISON OF DECODERS a higher number of bits may be expected to have superior
error correction performance than their counterparts employing
A comprehensive review of published FPGA-based LDPC fewer bits. However, this is typically achieved at the cost of
decoder designs is presented in this section. The analysis a larger hardware resource requirement or a lower processing
of Table II considers both the parameters that are chosen throughput.
by the designers, as well as the characteristics that may be The quantisation scheme used in the LLR representation
measured based on the design. Each of these is discussed and may be either uniform or non-uniform, as denoted by a ‘U’
characterised in Sections III-A and III-B, together with expla- or an ‘N’ in Table II, respectively. In uniform quantisation
nations and discussions of the symbols used in Table II where schemes, the entire range of representable LLR values has
applicable. The entries in Table II have been sourced from a constant resolution, allowing the VN and CN functions to
both academic publications and commercially-available soft IP be implemented using straightforward binary arithmetic. By
cores. Unfortunately, the licensers of these commercial designs contrast, non-uniform quantisation schemes typically adopt
were often unwilling to divulge many of the parameters and a finer resolution for lower LLR magnitudes and a lower
characteristics required for this analysis, resulting in several resolution for larger magnitudes. This facilitates a more ben-
incomplete sets of results. Furthermore, none of the licensers eficial trade-off between range and resolution, but makes
were willing to provide pricing information for the purposes the associated processing significantly more complex. Many
of this survey, preventing the comparison of this interesting authors (e.g. [42], [47], [48]) mention the number of bits used
but non-technical characteristic of their IP. in their FPGA-based LDPC decoders, but do not detail the
Note that Table II presents a condensed version of our quantisation scheme employed. Since non-uniform schemes
findings, showing only the most significant parameters and require significantly more details than uniform representations,
characteristics. In the case of references that present multiple these cases are assumed to employ uniform quantisation and
FPGA-based LDPC decoder designs, only a representative are marked with an asterisk in Table II.
subset has been reproduced here. A full version of our survey The maximum achievable clock frequency of an FPGA-
results may be downloaded from [46]. based LDPC decoder depends largely on the capabilities of
the FPGA employed, but also on some design decisions such
as the critical path length. For example, designs that process
A. Parameters
entire VNs or CNs in a single clock cycle typically have long
In this section, we consider the parameters of FPGA-based critical paths, while designs that only perform one arithmetic
LDPC decoders, which include all factors of the design that are or logical operation per clock cycle typically have much
specified by the designer. These include which LDPC PCMs shorter critical paths. Based on this observation, the clock
to support, the decoding algorithm to employ and the number frequency is included as a parameter in this analysis. The
of decoding iterations used. These parameters are discussed in majority of authors have explicitly stated the clock frequency
Sections III-A1, III-A3 and III-A4 respectively. Section III-A2 at which their decoder operates. However, in some cases
describes the architectural parameters, namely the degree of (eg. [76]) we have derived the clock frequency from other
parallelism, LLR representation, clock frequency, flexibility data, as indicated by an asterisk in Table II.
and choice of FPGA. Many decoder architectures are highly optimised to the
1) LDPC PCMs: One of the most fundamental features specific characteristics of the single LDPC PCM that they
of an LDPC decoder is the selection of the PCMs that it is are designed to support (eg. [43], [62], [74]). By contrast,
designed to support. Decoders may support just one PCM, be some other designs instead adopt a more general architecture
tailored to a family of related PCMs or may be designed to be (eg. [57], [60], [66]), sacrificing performance for the flexibility
completely flexible. As discussed in Section II-B, each PCM to switch between several supported PCMs at run-time. A
H has a number of parameters, namely N , M , Dc and Dv . decoder’s flexibility may be considered to be both a figure
However, the total number of edges in the corresponding factor of merit and an architectural decision that is made by the
graph can be considered to encompass all of these factors, designer, allowing it to be regarded as a characteristic or as a
representing the overall size and complexity of the code, as parameter. However, we show in Section IV-A that adding
listed in Table II. flexibility to a design can only be achieved as a trade-off
2) Architecture: Architectural decisions influence the phys- against some other desirable characteristics. For this reason,
ical implementation and hardware used by the decoder. As we treat flexibility as a characteristic in this paper.
described in Section II-E, the primary architectural parameter The selection of an FPGA for the implementation of an
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 12

TABLE II: Comparison of FPGA LDPC decoders

Bandwidth eff.
H dimensions

LLR bitwidth

(decoded bps)

(encoded bps)
Clock (MHz)

Eb /N0 (dB)
Throughput

Throughput
Algorithm

Iterations
Edges (k)

Run-time
flexibility
ELBs (k)
FPGA
Ref.

1022 x PUs N Xilinx Sum-product 172 197 38.3 0.

[41] 32.7 36 193 15 3.78 None
8176 6 Virtex 2 (modified) M M* * 88
4608 x U* Xilinx 27 54 15.9 0.
[49] 27.6 54 56 - 18 1.85 None
9216 5 Virtex E M* M * 50
125 x U* Altera Min-sum 481 650 0.
[42] - 605 61 15 66.6 4.69 None
480 3 Stratix (modified) M* M 74
432 x U Altera 16 668 954 31.6 0.
[50] 4.32 576 138 Min-sum 3.41 None
1440 4 Stratix 2 ** M** M* * 70
4044 x U Xilinx 40 80 72.6 0.
[51] - 24 44 Log-BP 25 - None
8088 6 Virtex 2 M M* * 50
1022 x Altera 70 80 8.0 0.
[52] 32.7 18 - 200 BP-based 18 3.8 None
8176 Cyclone 2 M M* * 88
1022 x Altera 560 640 38.0 0.
[52] 32.7 18 - 200 BP-based 18 3.8 None
8176 Stratix 2 M M* * 88
648 x U* Xilinx 8.4 86.6 173 10.8 0. 3 codes in
[53] 3.89 36 128 Min-sum 2.74
1296 4 Virtex 2 ** M** M* * 50 802.11 WiFi
1728 x U* Xilinx Turbo decoding 103 223 10.7 0.
[54] - 32 180 10 2.33 None
3200 5 Virtex 4 algorithm M* M * 46
6144 x U Altera 149 298 92.0 0.
[55] 36.9 288 96 Min-sum 15 1.48 None
12288 6 Stratix 2 M* M ** 50
576 x U Xilinx Min-sum 8.5 38 76.1 5.2 0. 3 codes in
[56] 3.46 32 64 3.27
1152 2 Virtex 2 (modified) ** M** M* * 50 802.16 WiMAX
512 x Xilinx 353 706 54.5 0.
[45] 3.07 1536 NA 212 Stochastic NA 2.43 None
1024 Virtex 4 M* M ** 50
[28] 1022 x U Xilinx Min-sum 11.7 23.4 78.0 0.
3.46 1728 138 6.8 - None
T 8176 2 Virtex 5 (modified) G G* * 50
[28] 1022 x U Xilinx Min-sum 8.5 9.35 18.7 78.0 0.
3.46 1728 138 3.43 None
E 8176 2 Virtex 5 (modified) ** G** G* * 50
U* Xilinx 21.6 25.9 38.0 0. Complete
[57] - - 8 160 - 20 -
6 Virtex 5 M M* * 83 802.16 WiMAX
188 x U* Altera Min-sum 108 118 23.5 5.12 0.
[58] 8.84 235 50 20 None
2209 6 Stratix (modified) M* M * ** 92
1552 x N Altera Belief 26 52 0.
[59] - 48 98 30 33.0 1.48 None
3104 6 Cyclone 2 propagation M* M 50
731 x U Xilinx Min-sum 10 1.45 1.2 3.52 0.
[60] 16.6 2 - Any code
4161 9 Virtex 2P with correction * M ** ** 82
4158 x U Xilinx Min-sum 60 15 30 53.3 1.17 0. 3 custom
[61] 27 54 100
9036 6 Virtex 2 with correction * M M* * * 50 codes
768 x U Xilinx Min-sum 397 794 18.2 0.
[17] 4.61 144 211 - - None
1536 5 Virtex 4 with scaling M M* * 50
432 x U Xilinx Min-sum 15 95 143 19.3 2.49 0. Complete
[17] 4.75 81 160
1296 8 Virtex 4 with correction * M M* * * 67 802.11 WiFi
2304 x U* Altera 233 465 17.3 0.
[62] - 12 155 Min-sum 8 1.94 None
1152 7 Stratix 2 M M* * 50
2304 x U* Altera 768 1.54 69.1 0.
[62] - 12 128 Min-sum 8 1.94 None
1152 7 Stratix 2 M G* * 50
3048 x Xilinx 32 64 12.3 0.
[63] - 72 - 64 - 24 - None
6096 Virtex E M* M * 50
3600 x Xilinx Min-sum 15 36.3 46.7 22.0 0. Complete
[64] 45 45 - 70.8 -
16200 Virtex 2P with scaling * M* M * 78 DVB-S2
3600 x Xilinx Min-sum 15 149 191 70.6 0. Complete
[64] 45 180 - 73.2 -
16200 Virtex 2P with scaling * M* M * 78 DVB-S2
519 x U* Xilinx 36 72 19.4 0.
[47] 3.11 9 26.3 - 18 - None
1038 4 Virtex E M* M * 50
4095 x U Xilinx Soft majority 1.56 1.9 21.3 0.
[65] 262 130 191 5 4.36 None
4095 1 Virtex E logic G* G ** 82
U Xilinx Normalized 5 10 30.6 0.
[66] - - 32 74 15 - Any code
8 Virtex 4 BP-based M** M* ** 50
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 13

TABLE II: Comparison of FPGA LDPC decoders (continued...)

Bandwidth eff.
H dimensions

LLR bitwidth

(decoded bps)

(encoded bps)
Clock (MHz)

Eb /N0 (dB)
Throughput

Throughput
Algorithm

Iterations
Edges (k)

Run-time
flexibility
ELBs (k)
FPGA
Ref.

[67] 324 x PUs U Xilinx Simplified 16.2 32.4 28.5 0.

1.94 972 188 3.8 - None
T 648 1 Virtex 5 MP G G* * 50
[67] 324 x U Xilinx Simplified 6.16 12.3 28.5 0.
1.94 972 188 10 5.41 None
E 648 1 Virtex 5 MP G** G* * 50
600 x U Xilinx Min-sum 8.9 8.3 16.6 58.1 0.
[68] 3.6 1800 123 3.38 None
1200 2 Virtex 4 (modified) ** G** G* * 50
324 x U Xilinx Min-sum 8.4 4.33 8.67 44.0 0.
[68] 1.94 972 113 3.64 None
648 2 Virtex 5 (modified) ** G** G* * 50
[69] 640 x U Xilinx Joint 1.33 2 0.
6.4 40 150 8 - - None
T 1920 8 Virtex 4 row-column G* G 66
[69] 640 x U Xilinx Joint 211 320 0.
6.4 40 150 50 - 2.29 None
E 1920 8 Virtex 4 row-column M* M** 66
[69] 640 x U Xilinx Joint 74.6 112 0.
6.4 1 300 8 - - None
T 1920 8 Virtex 4 row-column M* M 66
[69] 640 x U Xilinx Joint 11.8 17.9 0.
6.4 1 300 50 - 2.29 None
E 1920 8 Virtex 4 row-column M* M** 66
486 x Xilinx Min-sum 50 87.8 0.
[43] 2.43 18 - 131 20 2.49 None
972 Virtex 4 (nonbinary) M * 50
U Altera Min-sum 175 350 13.5 0. Within code
[70] - - 27 100 - -
8 Cyclone 2 (modified) M* M * 50 families
528 x Xilinx 348 697 68.2 0.
[36] 3.34 1584 NA 222 Stochastic NA 2.45 None
1056 Virtex 4 M* M** * 50
1022 x U Xilinx Sum-product 522 29.7 0.
[71] 4.75 12 228 - 2.61 None
8176 11 Virtex 5 (modified) M ** 66
384 x U Xilinx Message 19.5 24 13.7 4.07 0.
[72] 12.3 33 100 10 None
2048 6 Virtex 2P passing M* M** * *** 81
768 x U Xilinx 114 229 2.4 0.
[73] 4.61 9 162 Min-sum 3 - None
1536 8 Virtex 2 M* M * 50
756 x U Xilinx Normalized 82.4 102 10.0 0.
[73] 16.8 - 200 15 - None
3969 6 Virtex 4 min-sum M* M * 81
1022 x U Xilinx Normalized 625 714 27.2 0.
[73] 32.7 144 212 15 3.76 None
8176 6 Virtex 4 min-sum M* M * 88
600 x U Xilinx 6 12 69.0 0.
[74] 3.6 1800 100 Min-sum 10 3.76 None
1200 3 Virtex 4 G G* * 50
768 x U Xilinx 49.6 99.1 2.9 0.
[75] 4.61 9 149 Min-sum 3 - None
1536 8 Virtex 2 M* M * 50
768 x U* Xilinx 5.88 11.8 1.8 3.36 0.
[48] 4.61 9 100 Min-sum 7 None
1536 8 Virtex 2 M* M** * *** 50
768 x U 84 Xilinx Sum-product 4.3 8.59 3.9 0.
[76] 4.61 9 20 2.37 None
1536 8 * Virtex 2 (modified) M* M** * 50
768 x U 79.1 Xilinx Sum-product 4.04 8.08 3.4 0.
[76] 4.61 9 20 2.37 None
1536 8 * Virtex 2 (modified) M* M** * 50
768 x N 80.5 Xilinx Sum-product 4.21 8.42 4.9 0.
[76] 4.61 9 20 2.96 None
1536 8 * Virtex 2 (modified) M* M** * 50
336 x U Xilinx Min-sum 475 950 71.4 0. Within code
[77] 2.18 96 100 10 3.02
672 5 Virtex 5 with correction M* M * 50 families
U* Xilinx 15 1.7
[78] - - - 27 - - - - None
4 Virtex E M *
768 x U Xilinx Min-sum 63.5 127 20.4 0.
[79] 4.61 144 121 20 2.79 None
1536 5 Virtex 2 (modified) M* M * 50
298 x U Altera Improved 7 4.4 0.
[80] 2.83 2 136 - 1.0 None
980 6 Cyclone BP M ** 70
Xilinx 96 210 0. Complete
[81] - - - - 140 Min-sum - -
Virtex 5 M * 67 DVB-S2
Xilinx 206 388 0. Complete
[81] - - - - 140 Min-sum - -
Virtex 5 M * 25 DVB-S2
U* Xilinx Min-sum 600 64.6 Complete
[82] - - - 180 5 - 3.84 -
9 Virtex 5 with correction M ** CCSDS-C2
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 14

TABLE II: Comparison of FPGA LDPC decoders (continued...)

Bandwidth eff.
H dimensions

LLR bitwidth

(decoded bps)

(encoded bps)
Clock (MHz)

Eb /N0 (dB)
Throughput

Throughput
Algorithm

Iterations
Edges (k)

Run-time
flexibility
ELBs (k)
FPGA
Ref.

PUs U* Altera Min-sum 30 8.8 Complete

[82] - - - 150 12 - 3.71 -
9 Stratix 2 with correction M ** CCSDS-C2
1152 x U* Xilinx Min-sum 71 142 36.4 0. Complete
[83] 7.30 - 160 15 1.84
2304 8 Virtex 4 with correction M M* ** 50 802.16 WiMAX
1920 x U* Xilinx Min-sum 169 204 36.4 0. Complete
[83] 7.68 - 160 15 3.66
2304 8 Virtex 4 with correction M M* ** 83 802.16 WiMAX
Min-sum 866 Complete
[84] - - - - 240 - - - - -
with correction M 802.11 WiFi
1 Complete
[85] - - - - - - - - - - - -
G ITU G.hn
2.1 Complete
[86] - - - - - - - 10 - - - -
G 802.11ad WiGig
2048 x U* Altera 8 8.54 0.
[87] - - 126 Hard decision 12 40.0 - None
32640 1 Cyclone 4 G G* 94
Xilinx 200 101 320 custom
[88] - - - - - - - - -
Spartan 6 M * codes
Xilinx 25 22.4 320 custom
[88] - - - - - - - - -
Spartan 6 M * codes
972 x Min-sum 0. Complete
[89] - - - - - 15 - - - 1.66
1944 with correction 50 802.11 WiFi

LDPC decoder may have a significant impact upon its per- throughput, subject to the influence of the other parameters
formance. The selected FPGA dictates the number of logic outlined above. It is also worth noting that the maximum
elements, memory blocks and I/O pins that are available for all number of iterations is perhaps the easiest parameter to change
processing and routing. Additionally, some FPGAs facilitate at runtime. Owing to this, some designs (eg. [28], [67], [69])
higher clock frequencies than others when implementing the are presented with two sets of results, namely one employing a
same design, depending on the process technology employed. low number of iterations for maximum processing throughput
Unfortunately it is impossible to fairly compare the capabilities (marked with a ‘T’ in Table II), and one with a high number
of all FPGAs numerically. For this reason, Table II simply for maximum error correction (marked with an ‘E’ in Table II).
states which FPGA has been employed for each LDPC decoder Table II presents the fixed number of iterations that are
considered. employed in designs without early stopping functionality,
3) Algorithm: As discussed in Section II-C, several varia- while the average number of iterations is presented for designs
tions of the LDPC decoding algorithm exist. Some algorithms employing early stopping. However, some papers proposing
vary from each other only slightly, while others may employ early stopping designs (eg. [60], [61], [64]) do not present an
vastly different mathematical concepts. Furthermore, different average number of iterations, only providing the maximum
authors may use different terms to describe the same algo- limit imposed, as indicated with an asterisk in Table II.
rithm, making this parameter difficult to compare. Table II Likewise, some papers (eg. [50], [53]) do not state the number
therefore only includes the terms used by the authors to of iterations employed, but this parameter can be inferred as a
describe their algorithms and no direct comparison between function of other parameters and characteristics. These cases
them is inferred. are marked with a double-asterisk (**) in Table II.
4) Iterations: The limit placed on the maximum number of
decoding iterations has a significant effect upon the process-
B. Characteristics
ing throughput and error correction performance of decoders
operating without early stopping functionality, as well as in In this section, we consider all those characteristics of
cases where the received frame is too corrupted to be decoded FPGA-based LDPC decoders, which we plan to quantify.
successfully. Decreasing the maximum number of iterations Seven main characteristics are identified, namely processing
will increase the LDPC decoder’s processing throughput in throughput, processing latency, hardware resource require-
terms of the maximum achievable bitrate, but runs the risk ments, transmission energy efficiency, processing energy ef-
of allowing errors to remain in the recovered codeword that ficiency, bandwidth efficiency and flexibility, as seen Fig. 1.
could have otherwise been corrected. Generally, it can be Each of these is described in turn in the following sections.
assumed that the number of iterations used in each considered 1) Processing throughput: Perhaps the most frequently-
design was selected by the author to offer the most desirable stated characteristic of an FPGA-based LDPC decoder is its
trade-off between error correction performance and processing processing throughput, which is the number of bits that it can
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 15

process per second. A high processing throughput is required implemented on different FPGAs. However, the resource
for high-speed data transfers and video streaming applications, requirements stated by the various authors of LDPC-based
amongst other uses. A base station serving many users requires FPGA decoder designs often do not directly translate to ELBs,
the sum of the individual throughputs to be high, so that each hence requiring further analysis to be performed as follows:
user receives a satisfactory service.
• The conversion from 6LUTs to 4LUTs described in Sec-
In an LDPC decoder it is important to note the difference
tion II-F is first employed to ensure that all measurements
between encoded and decoded processing throughput. We refer
of LUTs consider an approximately equivalent quantity
to the number of codeword bits processed per second as
of hardware.
the encoded processing throughput, while we use decoded
• Subsequently, if the hardware requirement of a design is
processing throughput to quantify the number of message
quantified only in terms of either 4LUTs or FFs, then we
word bits per second. For example, half of the codeword bits
assume a numerically equal number of ELBs.
generated by a 1/2-rate LDPC code are parity bits, which carry
• If the hardware requirement of a design is quantified
no information of their own. Therefore if the encoded pro-
in terms of both 4LUTs and FFs, then we assume that
cessing throughput is 2 Gbps then the corresponding decoded
ELBs = max(4LUTs, FFs). These cases are identified
processing throughput would be 1 Gbps. Ultimately, it is the
using a single asterisk in Table II.
decoded processing throughput that matters most to the user of
• For designs based on Xilinx FPGAs having complex
the decoder, so we have deemed this to be the more important
multi-element slices, we have derived a “utilisation”
characteristic in comparisons. For designs where the author
figure of merit, which quantifies how many LUTs/FFs are
has only presented encoded processing throughput, we have
commonly used per slice. We obtained this by calculating
inferred the decoded processing throughput by multiplying
the average utilisation of designs for which both the num-
by the coding rate, as denoted by an asterisk in Table II.
ber of slices and the number of LUTs/FFs used is stated.
In some cases it is unclear whether the stated processing
These utilisation figures were found to be approximately
throughput is encoded or decoded. This is reflected in the
0.83 for LUTs and 0.36 for FFs, demonstrating that the
Table II by allowing the stated processing throughput to span
majority of slices are used for their LUTs. For designs
both columns. A double asterisk is used in Table II to identify
where the hardware utilisation is presented only in terms
designs in which the processing throughput was not explicitly
of slices, we assume ELBs = slices × 4LUTs per slice
stated, but has been inferred from other stated parameters and
× 0.83. These cases are indicated in Table II using a
characteristics.
double asterisk.
2) Processing latency: The processing latency of an FPGA-
based LDPC decoder is the amount of time it requires to 4) Transmission energy efficiency: Another fundamental
process a complete LDPC codeword. Low processing latency figure of merit for an LDPC decoder is its error correction
is therefore important for interactive cloud computing and capability, as a function of the channel’s signal to noise
safety-critical operations, where an immediate response is power ratio per bit Eb /N0 , which is typically expressed in
crucial. It may be observed that processing latency is strongly decibels. If a codeword is transmitted using a high energy
linked to processing throughput, since the processing latency per bit Eb , then the energy of the noise corrupting each bit
can often be calculated as the message word length K divided becomes relatively smaller, causing the BER at the receiver to
by the decoded processing throughput. However, some decoder decrease. However, energy-efficient transmitters are desirable,
designs achieve a high processing throughput by decoding because they are cheaper to run and can operate for longer
more than one codeword simultaneously. In these cases, the without requiring new batteries, particularly since transmission
associated processing latency would be much higher than that energy consumption is dominant in transmitter hardware. It
of a decoder which achieves the same processing throughput is therefore desirable for an LDPC decoder to be capable of
while decoding only a single codeword at a time. For example, correcting errors and achieving a satisfactorily low BER, even
a decoder that decodes a single 1000-bit message word with at low Eb /N0 values.
a processing throughput of 2 Gbps would have a processing The error correction performance of a decoder is typically
latency of 0.5 µs, while two 1 Gbps decoders operating in characterised in the form of a BER curve, showing how the
parallel would achieve the same processing throughput, but BER is reduced as the channel Eb /N0 increases. In order to
would have a processing latency of 1 µs. Processing latency convert these plots into a comparable metric, we specified a
is a key characteristic of an FPGA-based LDPC decoder, desirable target BER of 10−4 . For each considered design,
however most authors do not explicitly state it in their results, the Eb /N0 required by the decoder in order to achieve this
and it is therefore not included in Table II. BER was noted. In some publications however (eg. [17], [61]),
3) Hardware requirements: When implemented on an the error correction performance is quantified using the Frame
FPGA, the size and complexity of an LDPC decoder’s design Error Rate (FER) rather than BER. In these cases, we assumed
is represented by how much of the FPGA’s hardware resources that a BER of 10−4 equates to a FER of 10−2 [61], based on
it utilises. Larger designs require more resources and therefore the observation that the considered designs typically have a
a bigger, more expensive FPGA, making smaller designs message word length K of the order of 1000 bits, as well
preferable. as a minimum Hamming distance of the order of 10 bits.
The ELB metric described in Section II-F can be used These cases are indicated using a single asterisk in the Eb /N0
to compare the hardware resource requirements of designs column of Table II.
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 16

Quantifying the BER versus Eb /N0 facilitates a fair com- only be adapted to use a different PCM by reprogramming
parison of transmission energy for LDPC codes having differ- the FPGA, preventing a high degree of rapid reconfigurability.
ent coding rates R, since it considers the transmission energy The degree of design-time flexibility can also be difficult to
per message word bit. However, some publications present accurately quantify, since any design that is synthesised from
the BER as a function of the SNR Es /N0 , which does not a HDL can be modified and re-synthesised fairly rapidly.
allow a fair comparison of codes having different coding rates, Design-time flexibility has therefore not been considered in
since it considers the transmission energy per codeword bit, this survey.
Es = Eb × R. The corresponding Eb /N0 can therefore be
obtained by dividing by the SNR Es /N0 by the coding rate IV. D ISCUSSIONS
R, which is achieved in logarithmic terms according to The data presented in Section III inspires a great deal
Eb /N0 [dB] = SNR [dB] − 10 log10 (R). (18) of discussions and visualisation of the relationships amongst
the various parameters and characteristics of FPGA-based
Entries calculated in this way are denoted in Table II using a LDPC decoders. This section commences by characterising
double asterisk. Unfortunately some authors have erroneously the fundamental trade-off between desirable characteristics in
labelled the x-axis of BER plots as SNR, when Eb /N0 would Section IV-A, before identifying the parameters that affect
be more appropriate. Some of these cases were clarified via each characteristic in Section IV-B.
private correspondence with the authors. However, in some
cases there is other evidence that the presented results are in
terms of Eb /N0 rather than SNR, such as comparisons with A. Trade-offs
benchmarkers or capacity bounds. In these cases, Eb /N0 is As seen in Fig. 1 and discussed in Section III-B, the main
assumed and identified using a triple asterisk (***) in Table II. measurable characteristics of an FPGA-based LDPC decoder
5) Processing energy efficiency: As for any electronic are processing throughput, processing latency, hardware re-
system, low processing energy consumption is desirable in source utilisation, transmission energy efficiency, processing
the design of FPGA-based LDPC decoders. However, only energy efficiency, bandwidth efficiency and flexibility. Of
a few publications ([28], [56], [73]) have included energy these, it is the processing throughput, hardware resource util-
consumption measurements, hence this characteristic cannot isation, flexibility and transmission energy efficiency, which
be considered in our comparisons. provide the clearest and most fundamental trade-off, since the
6) Bandwidth efficiency: The bandwidth efficiency of a other characteristics are all in some way dependent on these.
communication system is given by the ratio of the information The relationship amongst these four characteristics is plotted
throughput that it can convey to the corresponding bandwidth in Fig. 9.
required. For example, a scheme that conveys 500 bits per Note that all scatter plots presented in this paper are
second over a channel having a bandwidth of 1 kHz has a organised so that a decoder with desirable values for all
bandwidth efficiency of 0.5 (bits/s)/Hz. For BPSK-modulated characteristics would correspond to a data point in the top-right
codewords using ideal Nyquist pulse shaping filters, bandwidth corner. In Fig. 9, the x-axis is plotted with the values reversed,
efficiency is numerically equal to the LDPC coding rate R. so that decoders with smaller hardware resource requirements
In this regard, LDPC codes with higher coding rates are more (preferred) are further to the right than larger ones. Meanwhile
desirable, since they make more efficient use of their channel’s the y-axis is plotted as normal, so that decoders with the
bandwidth. highest processing throughput are at the top. In this way, points
7) Flexibility: Flexibility is a desirable characteristic, be- above the trend line are superior to the average case, whilst
cause it allows an FPGA-based LDPC decoder to support points below it are inferior, notwithstanding the values of their
different parity check matrices, having different coding rates, other characteristics.
block lengths and node degrees. Some designs may support a It can be seen in Fig. 9 that most designs can only excel
selection of related PCMs from within a particular code family, in at most three of the four characteristics presented. The
such as the 21 PCMs included in the DVB-S2 standard [5]. trend line presents the average processing throughput vs size
Meanwhile, other designs may be completely flexible, sup- trade-off, and decoders that perform above this line generally
porting any PCM. tend to suffer from poor transmission energy efficiency, whilst
Decoders may exhibit flexibility either during their design decoders with a high energy efficiency tend to either have
or during their operation. True run-time flexibility allows a larger hardware resource requirements or lower processing
specific codeword to be decoded using a particular PCM, throughput than the average case. Any decoders that perform
immediately before decoding a different codeword using a well in all three of these characteristics tend to be totally
different PCM. This allows the communication system to inflexible to any PCM changes at run-time.
dynamically adapt to time-varying channel conditions, such as The five points in Fig. 9 having the highest processing
by decreasing the coding rate R in high-noise environments throughput are from [28], [74], [68] and [67], all of which
in order to improve the BER performance. However this employ fully-parallel architectures. The design of [67] has
advantage may only be achieved at the cost of requiring a the smallest hardware resource requirement of the four, owing
more sophisticated design, typically having higher hardware to its use of only one bit per LLR. By contrast, the designs
resource requirements or lower processing throughput. By of [28], [68] and [74] use two or three bits per LLR, which
contrast, decoders that are only flexible at design-time may is reflected in their relative hardware resource requirements.
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 17

5.5
Inflexible, with Eb /N0 data
Flexible, with Eb /N0 data 5
104 [28] Inflexible, without Eb /N0 data
[74] Flexible, without Eb /N0 data
Throughput vs size trend 4.5
[68]
Decoded throughput (Mbps)
[67]

Min Eb /N0 for low BER

[65] 4
103 [45]
[77] 3.5
[36]
102 [17] 3

2.5
[61]
101 2

[60] 1.5

100 1
105 104 103
Equivalent Logic Blocks (ELBs)

Fig. 9. Processing throughput vs. hardware requirements vs. transmission energy efficiency vs. flexibility

None of these high-throughput decoders have any run-time LDPC code. By contrast, the other flexible designs shown in
flexibility, as is typical of fully-parallel architectures. The Fig. 9, such as [17] and [61], are only flexible for a set of
next highest processing throughput is achieved by the design related PCMs.
of [65], which adopts a partially-parallel rather than fully- In addition to the trade-offs described above, Fig. 9 also
parallel architecture, but also uses only one bit per LLR. demonstrates that it is difficult to consider all of the character-
The effect of using these small numbers of bits can be seen istics of an FPGA-based LDPC decoder at once. For example,
in these decoders’ poor transmission energy efficiency, since Fig. 9 does not consider the capabilities of the FPGA that
reducing the resolution of the LLRs impedes the associated each decoder is implemented using. In particular, more recent
error correction capability. FPGAs may be able to operate identical designs at higher
In addition to employing single-bit LLRs, the design of [65] clock speeds than older FPGAs. This could be crudely factored
achieves a high processing throughput by decoding two frames into the results by dividing the processing throughput by the
at once. The designs presented in [77] use a similar technique, clock frequency, but doing so would then negate the impact of
processing three, four or even six frames in parallel using other parameters such as the critical path length. Furthermore,
multiple decoder copies in the same FPGA. Owing to this, no consideration is given in Fig. 9 to the processing latency
these designs have a larger processing throughput than the of each considered design. Note, however, that by plotting
average case, while also being flexible and having reasonable the decoded processing throughput rather than the encoded
error correction performance. However, as discussed in Sec- processing throughput, the coding rate and the bandwidth
tion III-B2, the processing latency of these decoders is much efficiency of the LDPC code has been taken into at least partial
higher than their processing throughput would imply, making consideration.
them less suitable for time-critical applications.
The decoders presented in [36] and [45] both achieve good
transmission energy efficiency, while also having higher pro- B. Relationships between parameters and each characteristic
cessing throughputs (or lower hardware requirements) than the Having established the fundamental trade-off that exists
average case. Both of these designs use stochastic bitstreams between the main characteristics of FPGA-based LDPC de-
to represent the LLRs, facilitating a fully-parallel architecture coders, namely processing throughput, processing latency,
having single-wire serial transmission between nodes, greatly hardware requirements and transmission energy efficiency, the
simplifying the hardware design. following subsections present discussions of the parameters
The points in the bottom-right of Fig. 9 correspond to the that affect each one. A discussion of bandwidth efficiency
designs presented in [60], which employ a fully-serial archi- is combined with transmission energy efficiency in Sec-
tecture and so have very low hardware resource requirements, tion IV-B4, but a quantitative discussion of flexibility and
but also low processing throughput. However, these designs processing energy efficiency could not be made, owing to the
also have the benefit of being truly run-time flexible for any lack of the required information in the publications considered.
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 18

105 9
9-15 iterations
[67] 16+ iterations
3-8 iterations 8
104 Data N/A
[68] Throughput vs parallelism trend 7
Decoded throughput (Mbps)

Number of bits per LLR

[69]
[65] 6
103

102 [75] 4

3
101
[76] [60] 2

100 1
103 102 101 100 10−1
PUs per 1000 edges in H

Fig. 10. Factors affecting the processing throughput

1) Processing throughput: Fig. 10 characterises the strong processing throughput than more complicated alternatives such
relationship between an FPGA-based LDPC decoder’s de- as the SPA [24] is also demonstrated by comparing the results
gree of parallelism and its decoded processing throughput, of [75] and [76], which present two very similar designs that
confirming the expectation that designs having more parallel vary in algorithm. The design in [76] suffers from a 4-5 Mbps
processors can decode a higher number of bits per second. processing throughput drop compared to [75], caused by its
Note that in Fig. 10 the number of parallel processing units employment of the SPA instead of the MSA, as well as by
has been divided by the number of edges in the PCM H, to using a non-uniform quantisation scheme for the LLRs.
remove the dependence on the LDPC code size. The shading The point furthest above the trend line corresponds to the
and shapes of the markers in Fig. 10 also indicate the influence design of [65], which achieves a high processing throughput
that the number of bits per LLR and the number of decoding by using only a single bit per LLR, five iterations per frame
iterations have on the processing throughput, respectively. and by decoding two frames simultaneously. This design
Points above the trend line typically employ a small number of also exploits the properties of quasi-cyclic LDPC codes to
bits per LLR or iterations, evidenced by their dark shading or implement an efficient partially-parallel architecture, reducing
circular point shape. By contrast, slower-than-average designs the number of processing units required to achieve its high
typically employ a larger number of bits per LLR or iterations, processing throughput.
and therefore have lighter shading or a square shape. 2) Processing latency: As discussed above, processing la-
Perhaps the most prominent points in Fig. 10 are the light tency is not treated as a quantifiable characteristic in our anal-
grey circles belonging to [69], which achieve a much higher ysis, because the majority of publications do not quantify this
processing throughput than the trend line, despite using 8 characteristic of their design. However, the processing latency
bits per LLR. This may be explained by this design’s use is dependent on the processing throughput, the message word
of layered belief propagation with the aid of a novel joint length K, the scheduling and the number of frames that are
row-column processor, which decreases the processing time decoded in parallel.
of each iteration and helps to avoid memory conflicts, thereby Some of the decoders considered, such as that of [65]
increasing the processing throughput. and [77], process multiple frames in parallel by instantiating
The light triangles in the bottom-right represent the fully- several independent copies of the decoder on the same FPGA.
serial decoders presented in [60], which achieve a low pro- In these cases the total processing throughput and resource
cessing throughput owing to their low number of processors. requirement could be divided by the number of decoders,
Conversely, the dark points in the top-left represent the fully in order to produce results that correspond to the processing
parallel decoders of [67] and [68], which achieve a very high latency of an equivalent design that only considers one frame
processing throughput by using few bits, few iterations, a at a time. However, other designs, such as [42], process
large degree of parallelism and operate on the basis of the multiple frames by making use of spare time within the
MSA [25]. The fact that the MSA can facilitate a higher decoding schedule, with the result that the hardware cost does
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 19

12
103 1k-10k edges
10k-50k edges
[48] 50k+ edges 10
Equivalent Logic Blocks (ELBs) Data N/A
[76] [75] Size vs parallelism trend

Number of bits per LLR

8

104
6
[47]
[58]
4

[61] 2
105 [77]

0
100 101 102 103
Processing Units (PUs)

Fig. 11. Factors affecting the hardware requirements

not increase linearly with the processing throughput. Owing designs of [61] also correspond to a set of points positioned
to this, it is not possible to normalise the data to only consider very far below the trend line.
the processing throughput and hardware resources required for The results of [75], [48] and [76] all sit above the trend
decoding one frame at a time, so the processing latency cannot line, despite employing a large number of bits per LLR, as
be fairly inferred. well as a moderate PCM size. This may be partially attributed
3) Hardware requirements: Unsurprisingly, the major con- to their implementation of quasi-cyclic LDPC codes, using
tributing factor to the hardware resource requirement of an partially-parallel architectures, leading to a very efficient use
FPGA-based LDPC decoder design is its degree of paralleli- of hardware resources. Additionally, the smallest hardware
sation, as shown in Fig. 11. Additionally, Fig. 11 shows that resource requirement of these designs is achieved by one
the number of bits employed per LLR and the number of edges that uses the MSA rather than the SPA, illustrating that this
employed in the parity check matrix also have some influence algorithm requires fewer hardware resources.
on the hardware resource requirement, though the effects of The design of [47] requires more FPGA resources than the
these parameters are quite varied. This may be attributed to trend line would suggest, which is remarkable considering its
the difficulty of accurately comparing the hardware resource small PCM and number of bits per LLR. At first glance this
requirements of different designs, as well as suggesting that may be attributed to its use of the uncommon array-based
other factors are involved. It is however noticeable that there is LDPC code. However, the design of [58] also uses an array-
a general reduction in the number of bits per LLR employed in based code but sits above the trend line, despite employing
designs with increased parallelism. This may be explained by a large number of bits per LLR and a large PCM. On closer
the explosion in routing complexity upon increasing the num- inspection, it can be observed that the design of [47] employs
ber of PUs, which would be exacerbated by the requirement a simple FPGA from an old generation, suggesting that its
for data buses having large operand widths. comparably large hardware resource requirement stems from
The dark grey circles corresponding to the designs of [77] inefficient FPGA synthesis.
towards the bottom of Fig. 11 seemingly have a much larger 4) Transmission energy efficiency and bandwidth efficiency:
hardware resource requirement than would be expected, con- The minimum SNR per bit Eb /N0 at which it becomes theo-
sidering the number of processing units, the number of PCM retically possible to reliably send information over a channel
edges and the number of bits employed per LLR. However, depends on the target bandwidth efficiency and therefore on
these designs are each run-time flexible for a different family the coding rate of the FEC code employed. A code having a
of codes, having HDL code that is automatically generated. lower coding rate may achieve a lower minimum transmission
This additional flexibility results in decoders that are not as energy, owing to the increased number of parity bits that it
fully optimised as one that was designed specifically for a employs for error correction. For this reason, we consider the
single PCM, explaining the associated hardware overhead. transmission energy efficiency and the bandwidth efficiency
This is confirmed by the observation that the run-time flexible jointly in this subsection.
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 20

For each FPGA-based LDPC decoder considered, the theo- 1

retical Discrete-input Continuous-output Memoryless Channel DCMC Capacity
(DCMC) capacity [90] was calculated, with consideration of [52]
0.9

Bandwidth efficiency (bits/s/Hz)

the coding rate, modulation type and channel model employed. [41]
This was then subtracted from the value recorded in Table II [60]
for the specific Eb /N0 at which a low BER is achieved, in 0.8
order to quantify the performance loss imposed by implemen-
[42]
tation factors. Here, a low performance loss is achieved by a
decoder that can function very close to the theoretical limit, 0.7
demonstrating that it is very good at correcting errors and very [80]
efficient in terms of transmission power and bandwidth.
0.6
Almost all of the publications considered characterised [61] [56] [74]
the error correction performance of their FPGA-based LDPC [67]
decoder designs using BPSK modulation for transmission over 0.5
an AWGN channel. This allows the BER performance of
[68]
these designs to be presented together graphically, as shown in
Fig. 12. Here, the plotted line represents the DCMC capacity, 0.4
0 1 2 3 4 5 6
while each plotted point corresponds to a different considered
decoder design. The performance loss associated with each SNR per bit Eb /N0 [dB]
point may be obtained as its horizontal distance from the
DCMC capacity curve. It can hence be seen that despite
requiring drastically different Eb /N0 levels to achieve the Fig. 12. Decoder performance loss from capacity
same BER, the designs of [41], [52], [60], [61] can all be con-
sidered to offer a strong error correction performance, when of iterations and bits per LLR. However, the PEG algorithm
their bandwidth efficiency is also taken into consideration. explained in Section II-D5 was used to construct the LDPC
Fig. 12 also illustrates that the designs of [42], [56], [67], code it uses, increasing its error correction capability at the
[68], [74], [80] are comparatively poor at correcting errors, cost of producing an unstructured factor graph, which is not
and therefore have a low transmission energy efficiency. This optimised for hardware implementation. A “cycle elimination
is at least partly due to the fact that these designs trade algorithm” was used in [61] to similar effect, while the designs
off their error correction performance against other desirable of [60] achieve high performance due to the completely
characteristics, as will be explained below. Note that this unstructured H matrix used.
analysis can be readily extended to LDPC decoders designed The lowest error correction performance loss is achieved
for other modulation schemes or channel models. This may by the design of [41], which uses a structured quasi-cyclic
be achieved by plotting the corresponding DCMC capacity code. In addition, this design also uses a sophisticated non-
curve and characterising the error correction performance with uniform quantisation scheme for the representation of LLRs,
respect to this bound. it employs a moderate number of bits per LLR and iterations,
It is well-known that LDPC codes having longer message as well as implementing the full SPA. By contrast, the designs
word lengths K are capable of performing closer to the DCMC of [76] and [48] operate further away from capacity than may
capacity [8]. Furthermore, a higher performance loss occurs be expected, which is due to their use of the MSA.
for more sparse PCMs, since these have fewer edges over
which to transfer information during the decoding process. V. R ECOMMENDATIONS AND FURTHER WORK
Motivated by this, Fig. 13 plots the performance loss of each
This section presents an overview of the future development
design versus the number of edges in its PCM H, combining
effort required of designers of FPGA-based LDPC decoders.
the message word length K with the complexity of the factor
Firstly, Section V-A provides a guide to the stages involved
graph. As shown in Fig. 13, the number of edges in the PCM
in designing an FPGA-based LDPC decoder. Following this,
H is the largest contributing factor to the error correction
Section V-B then provides a set of recommendations for
performance loss. As may be expected, the performance loss is
future publications which will facilitate more comprehensive
also influenced by the number of iterations performed and the
comparisons amongst FPGA-based LDPC decoders in the
number of bits used per LLR, as shown in Fig. 13. It may be
future. Finally, Section V-C presents a list of future research
observed that designs like those of [67], [65] and [74] perform
opportunities that we expect to be of significant benefit to the
poorly compared to the trend line, owing to their employment
field.
of a small number of bits per LLR or iterations. By contrast,
a good performance may be observed for designs employing
a large number of both, such as [69]. A. Recommended design methodology
The specific code construction principles used can explain As discussed above, the complex relationships between the
some of the unexpected results seen in Fig. 13. The design parameters and characteristics of FPGA-based LDPC decoders
of [50] performs closer to the DCMC capacity than would be imply that it is not possible to identify a single design which
expected from a general decoder using the same small number is superior to all others in every way. Having said this, the
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 21

9
[41] [61]
1 [60]
[69] 8

7
Distance from capacity (dB)
[50]

Number of bits per LLR

2 [65]
6
[76]
3 5
[48]

[74] 4
4
3-8 iterations 3
9-15 iterations
16+ iterations 2
5 Data N/A [67]
Performance loss vs edges trend
1
105 104 103
Number of edges in H

Fig. 13. Factors affecting the error correction performance

• Block length and coding rate completing each design element. More details about these
Choose which LDPC • Run-time vs. design-time PCM switching
issues can be found throughout Sections II-C — II-E.
PCM(s) to decode • Regular/irregular codes and node degrees
• Other code features (e.g. quasi-cyclic)

• Fully parallel, partially-parallel or serial

Choose a level of B. Recommendations
• Hardware requirements vs. throughput
parallelism • Routing complexity increases with parallelism In the process of collecting the data presented in this
paper, it has become apparent that fairer comparisons amongst
• Optimal fixed-point bit width
Choose an LLR FPGA-based LDPC decoders could be facilitated in the future,
• Uniform or non-uniform quantisation
representation • Other representations (e.g. stochastic)
by setting conventions for the type and format of data to
present when proposing a new design. The following list
• Choice of decoding algorithm represents our attempt at this. Our recommendation for future
Design VN and CN • Reduce critical path using pipeline registers publications of FPGA-based LDPC decoders is to:
architectures • Irregular codes require variable no. inputs
• provide values for every parameter and characteristic
• Choice of decoding schedule
presented in Table II;
Design data path and • Number/size of memory elements • ensure that all presented characteristics correspond to the
memory access • Maximum memory I/O bandwidth same set of parameters, and if more than one parameter
set is employed for demonstrating the flexibility of the
• Start/stop control signals design, include an equal number of full characteristic sets;
Design decoder
control unit
• Early stopping detection • state both the encoded and the decoded processing
• Run-time code selection control signals throughput, as well as the formula used for calculating
them;
• Input data from channel and buffering
Design data • state the processing latency of the decoder, or signify that
• Output decoding status/results
input/output • Limited by FPGA I/O resources
it can be derived simply from the processing throughput
and message word length K;
Fig. 14. Stages to consider when designing an FPGA-based LDPC decoder • provide BER simulation curves obtained using the physi-
cal hardware, plotting the results against Eb /N0 [dB] and
explicitly stating the channel model and modulation type
flowchart presented in Fig. 14 outlines a recommended series used, preferably BPSK modulation for transmission over
of stages for a prospective designer to complete, as a means of an AWGN channel;
assisting their design process. The bullet points accompanying • if possible, provide multiple BER plots for different
each stage list some of the key issues to be considered whilst maximum numbers of iterations;
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 22

• provide mathematical detail about the algorithm used and quasi-cyclic) LDPC codes such as those in [77] have the great-
endeavour to use established terminology if the same est potential for flexibility and high processing throughputs.
formulae have been used before; Recent research into hierarchical quasi-cyclic codes as in [56]
• provide power/energy consumption measurements ob- and [53] could be of particular interest.
tained during BER simulation; 2) Schedules: Unfortunately, different publications have
• when mentioning flexibility, explicitly state whether the used different terminology to describe the decoding schedules
changes can be made at run-time or whether they require adopted in their decoder designs, so a direct comparison could
a new synthesis run; not be easily drawn between them in this paper. However,
• endeavour to make it possible to compare new designs to there is an opportunity to investigate the effects of using
old ones by selecting a benchmarker, and implementing different schedules in two otherwise equal FPGA-based LDPC
a new design using exactly the same set of parameters decoders, assessing their effects not only on BER performance
on the same FPGA. and complexity as in previous research on scheduling, but
In addition to adhering to the above list of guidelines to fa- also on processing throughput, hardware resources, processing
cilitate fairer comparisons between different designs, it would energy and flexibility. In particular, none of the reviewed
be of significant benefit if authors of FPGA-based LDPC de- decoders operate on the basis of calculating residuals as in
coder designs were at liberty to make their source code freely IDS, implying that this schedule is largely under-represented
available online. Open-source code can be readily found for within the field despite claims of its superiority to others [22].
many of the signal processing blocks used in communications Further research is required to determine whether these claims
systems, but unfortunately there are very few freely-available are valid in practical implementations, and to investigate the
FPGA-based LDPC decoder designs. This inevitably hinders architectural constraints that employing IDS would impose on
innovation within the field, since every prospective designer an FPGA-based LDPC decoder design.
is required to commence by implementing a basic structure, 3) Stochastic decoders: The two stochastic decoders pre-
rather than improving an existing design. Additionally, if a sented in this report, [36] and [45], performed well in terms
reader of a published design had access to the source code, of processing throughput, BER performance and hardware
it would significantly aid their comprehension of the novel requirements. Stochastic designs are associated with their own
techniques that are being described. Finally, making source set of advantages and challenges, offering another opportunity
code freely available facilitates the employment of current for further research. The serial transmission of messages be-
FPGA-based LDPC decoder designs as benchmarkers for tween processing nodes facilitates a higher grade of feasibility
future designs. for fully-parallel designs, and allows the error correction per-
formance to be dynamically traded for processing throughput
C. Further work by simply increasing the number of bits used for each message.
Performing the analysis described above has enabled us to 4) Low processing energy consumption: It is unfortunate
identify several opportunities for further research and develop- that the majority of the designs reviewed in this report
ment in the field of FPGA-based LDPC decoders, as discussed did not present any information about the decoder’s energy
in the following subsections. consumption. As with all electronic devices, low energy con-
1) Flexible decoders: Perhaps the biggest gap illustrated sumption is a key figure of merit in communication systems,
by the trade-offs described in Section IV-A is for high- since it dictates how long mobile devices can function for
speed decoders having run-time flexibility and low hardware between battery recharges, as well as dictating the cost and
resource cost. Run-time flexibility has huge advantages for environmental impact of operating base station equipment.
commercial applications, since it allows a decoder to dynam- This provides a motivation to investigate the factors behind
ically support the variety of different LDPC codes within energy consumption in FPGA-based LDPC decoders, possibly
a particular communications standard, without incurring the by implementing some of the published designs and measuring
overhead of the time and technical intervention that is required their energy consumption directly. Drawing upon these results,
to reprogram an FPGA. Further to this, flexible decoders FPGA-based LDPC decoders having low energy consumption
can adapt automatically depending on the channel conditions could then be designed.
without any user input, increasing the efficiency of FPGA- 5) Low processing latency: Similarly to processing en-
based LDPC decoders in consumer applications. Run-time ergy consumption, processing latency is a crucial character-
flexibility can also be useful for research purposes, reducing istic of communications hardware that was curiously under-
the number of times an FPGA has to be re-synthesised when represented in the works reviewed here. While the processing
testing multiple different codes. latency may be approximated for many designs as a function
As seen in Section IV-A, decoders having a fully-serial of the processing throughput and message word length, the
architecture can be flexible with little or no extra hardware fact that it was rarely quantified implies that it was rarely
resource cost, but suffer in terms of their low processing a design focus. Some applications of FPGA-based LDPC
throughput. Meanwhile, the extra hardware required to make decoders may require ultra-low processing latency above all
a fully-parallel decoder flexible renders this approach im- other characteristics, suggesting that this is a gap in the market
practical, regardless of their capacity for high processing that is currently unfilled. Further research could be conducted
throughputs. Initial research therefore suggests that partially- to determine whether this is indeed the case, before devising
parallel decoder architectures utilising semi-structured (e.g. new designs having ultra-low processing latency. Such designs
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 23

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IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 25

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Modulation. Chichester: Wiley-IEEE Press, 2004.

Peter Hailes studied Electronic Engineering with

Mobile and Secure Systems with the department
of Electronics and Computer Science at the Uni-
versity of Southampton, and graduated with a first-
class masters degree in 2013. He then stayed on
to undertake research towards a Ph.D. in advanced
hardware implementations of LDPC decoders. His
Bashir M. Al-Hashimi (M99-SM01-F09) is a Pro-
other research interests include field-programmable
fessor of Computer Engineering and Dean of the
gate arrays, error correction coding, embedded hard-
Faculty of Physical Sciences and Engineering at Uni-
ware/software design and high-level software devel-
versity of Southampton, UK. He is ARM Professor
opment.
of Computer Engineering and Co-Director of the
ARM-ECS research centre. His research interests
include methods, algorithms and design automation
tools for energy efficient of embedded computing
systems. He has published over 300 technical papers,
authored or co-authored 5 books and has graduated
31 PhD students.
IEEE COMMUNICATIONS SURVEYS AND TUTORIALS 26

Lajos Hanzo (http://www-mobile.ecs.soton.ac.uk)

FREng, FIEEE, FIET, Fellow of EURASIP, DSc re-
ceived his degree in electronics in 1976 and his doc-
torate in 1983. In 2009 he was awarded an honorary
doctorate by the Technical University of Budapest,
while in 2015 by the University of Edinburgh.
During his 38-year career in telecommunications he
has held various research and academic posts in
Hungary, Germany and the UK. Since 1986 he has
been with the School of Electronics and Computer
Science, University of Southampton, UK, where he
holds the chair in telecommunications. He has successfully supervised about
100 PhD students, co-authored 20 John Wiley/IEEE Press books on mobile
radio communications totalling in excess of 10 000 pages, published 1500+
research entries at IEEE Xplore, acted both as TPC and General Chair of IEEE
conferences, presented keynote lectures and has been awarded a number of
distinctions. Currently he is directing a 60-strong academic research team,
working on a range of research projects in the field of wireless multimedia
communications sponsored by industry, the Engineering and Physical Sciences
Research Council (EPSRC) UK, the European Research Council’s Advanced
Fellow Grant and the Royal Society’s Wolfson Research Merit Award. He is
an enthusiastic supporter of industrial and academic liaison and he offers a
range of industrial courses. He is also a Governor of the IEEE VTS. During
2008 - 2012 he was the Editor-in-Chief of the IEEE Press and a Chaired
Professor also at Tsinghua University, Beijing. His research is funded by
the European Research Council’s Senior Research Fellow Grant. For further
information on research in progress and associated publications please refer
to http://www-mobile.ecs.soton.ac.uk Lajos has 22 000+ citations.