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Assignment 2 Set 3

This document provides details for Assignment 2 Question 1 and 2 for the course Digital Electronics 1. Question 1 asks students to design a 3-bit to 7-segment decoder logic circuit that displays the alphabet "765" based on the given input-output mapping and schematics of the 7-segment display. Question 2 asks students to (i) construct a truth table for a given SOP Boolean function and (ii) design a logic circuit using multiplexers to implement the function based on the truth table. The assignment is due on May 31st, 2023 and covers course outcomes on designing combinational logic circuits and engineering problem solving skills.

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amir zafrie
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28 views

Assignment 2 Set 3

This document provides details for Assignment 2 Question 1 and 2 for the course Digital Electronics 1. Question 1 asks students to design a 3-bit to 7-segment decoder logic circuit that displays the alphabet "765" based on the given input-output mapping and schematics of the 7-segment display. Question 2 asks students to (i) construct a truth table for a given SOP Boolean function and (ii) design a logic circuit using multiplexers to implement the function based on the truth table. The assignment is due on May 31st, 2023 and covers course outcomes on designing combinational logic circuits and engineering problem solving skills.

Uploaded by

amir zafrie
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CONFIDENTIAL

UNIVERSITI MALAYSIA PERLIS

ASSIGNMENT 2 : SET 3

NMJ10303 – Digital Electronic 1

Release date: 26 May 2023 - 12:00hrs


Due date : 31 May 2023 - 23:59hrs

COVERED COURSE OUTCOME


CO3: Ability to design and evaluate combinational logic circuits in terms of Boolean
Function.
COVERED PROGRAM OUTCOME
PO3 : Design and development of solutions: Design solutions for broadly-defined
engineering technology problems and contribute to the design of systems,
components or processes to meet specified needs with appropriate consideration for
public health and safety, cultural, societal, and environmental considerations.

This question paper has TWO (2) questions. Answer ALL questions.

MARKS

Q1 Q2 Total

25 10 35

Name : ……………………………………………………………

Matric No. : ……………………………………………………………

Program : ……………………………………………………………

Faculty of Electronic Engineering &


Technology
CONFIDENTIAL (NMJ10303)

Question 1
[CO3,PO3, C4]

Design a logic circuit for decoder that accepts 3-bit input and displays alphabet “765” at the
seven-segment as illustrated at Figure 1(a). The input-output mapping shown in Table 1(a).
Refer Figure 1(b) and Figure 1(c) for seven-segment display format showing arrangements of
segments using common anode connection. Show each steps clearly to produce the expressions
and required design.
[Rekabentuk litar logik untuk penyahkod yang menerima input 3-bit dan paparkan abjad "765" di tujuh-segmen
seperti digambarkan pada Rajah 1(a). Pemetaan masukan-keluaran ditunjukkan dalam Jadual 1(a). Rujuk Rajah
1(b) and Rajah 1(c) untuk format paparan tujuh-segmen yang menunjukkan susunan segmen menngunakan
sambungan ‘common anode’. Tunjukkan setiap langkah dengan jelas untuk menghasilkan ungkapan dan reka
bentuk yang dikehendaki.]
(25 marks / markah)

Figure 1(a) Figure 1(b)


[Rajah 1(a)] [Rajah 1(b)]

Figure 1(c)
[Rajah 1(c)]

Faculty of Electronic Engineering & Technology


CONFIDENTIAL (NMJ10303)

Table 1(a)
[Jadual 1 (a)]
Input Seven-Segment Output’s
[Masukan] [Keluaran Tujuh-Segmen]
000 BLANK
001 BLANK
010 BLANK
011 7
100 6
101 5
110 BLANK
111 BLANK

Question 2

Given the following standard SOP Boolean function F(A,B,C,D) = Σ (1,2,3,4,9,11,12,13,14),


whereby A is the Most Significant Bit (MSB).
[Diberikan fungsi Boolean piawaian hasil tambah hasil darab (SOP) seperti berikut F(A,B,C,D) = Σ
(1,2,3,4,9,11,12,13,14,), dimana A adalah bit paling signifikan (MSB).]

(i) Construct a truth table for the Boolean function given.


[Jana jadual kebenaran menggunakan fungsi Boolean yang diberikan.]
(4 marks / markah)

(ii) Design a logic circuit using a combination of (4:1) multiplexer and (2:1) multiplexer only, based on
the truth table obtained in Q2(i), and label all the input, output and selector clearly.
[Rekabentuk litar logik menggunakan beberapa pemultipleks (4:1) dan juga pemultipeks (2:1)
daripada jadual kebenaran yang didapati di Q2(i) dan labelkan semua input, output dan pemilih
secara jelas.]

(6 marks / markah)

Faculty of Electronic Engineering & Technology

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