Concurrent Signal

Assignment Statements
Outline
1. Combinational versus sequential circuit
2. Simple signal assignment statement
3. Conditional signal assignment statement
4. Selected signal assignment statement
5. Conditional vs. selected signal assignment

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1. Combinational vs. sequential
circuit
• Combinational circuit:
– No internal state
– Output is a function of inputs only
– No latches/FFs or closed feedback loop
• Sequential circuit:
– With internal state
– Output is a function of inputs and internal
state
• Sequential circuit to be discussed later

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2. Simple signal
assignment statement
• Simple signal assignment is a special case of
conditional signal assignment
• Syntax:
signal_name <= projected_waveform;
• E.g.,
y <= a + b + 1 after 10 ns;
• Timing info ignored in synthesis
and delta-delay is used:
signal_name <= value_expression

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• E.g.,
status <= '1';
even <= (p1 and p2) or (p3 and p4);
arith_result <= a + b + c - 1;
• Implementation of last statement

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Signal assignment statement
with a closed feedback loop
• a signal appears in both sides of a concurrent
assignment statement
• E.g.,
q <= ((not q) and (not en)) or (d and en);
• Syntactically correct
• Form a closed feedback loop
• Should be avoided

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Event and Delta Cycle
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY delta_cycle IS
PORT ( a,b : IN STD_LOGIC;
output : OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE example OF delta_cycle IS
SIGNAL int1,int2 : STD_LOGIC;
BEGIN
int1 <= NOT a;
int2 <= NOT b;
output <= (int1 xnor int2);
END example;
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Suppose that at time t=10 ns, a and b change from 0 to 1.

a b
Event list at t=10 ns Nil
0è1 0è1

int1 b
int1 <= NOT a; Nil
1è0 0è1

output b
output <= (int1 xnor int2); Nil
1è0 0è1
!
ns
10 b
e
tim Nil
on 0è1
pen
p
ha int2
y
ti vi t int2 <= NOT b; 1è0
Nil
ac
s
thi
l
Al output
Nil
output <= (int1 xnor int2); 0è1
Nil
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 Simulation without delta cycle expansion
0 2 4 6 8 10 12 14 16 18 20

int1

int2

output

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 Simulation with delta cycle expansion
10 10 12 14
6 8

a 10 + 1 delta cycle

10 + 4 delta cycle
b

int1
10 + 2 delta cycle

int2
10 + 5 delta cycle

output
10 + 6 delta cycle
10 + 3 delta cycle COEN313 - 11
3. Conditional signal
assignment statement
• Syntax
• Examples
• Conceptual implementation
• Detailed implementation examples

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Syntax

• Simplified syntax:
signal_name
<= value_expr_1 when boolean_expr_1 else
value_expr_2 when boolean_expr_2 else
value_expr_3 when boolean_expr_3 else
...
value_expr_n

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E.g., 4-to-1 mux

• Function table:

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E.g., 2-to-22 binary decoder

• Function table:

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E.g., 4-to-2 priority encoder

• Function table:

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E.g., simple ALU

• Function table:

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Conceptual implementation
• Syntax:
signal_name
<= value_expr_1 when boolean_expr_1 else
value_expr_2 when boolean_expr_2 else
value_expr_3 when boolean_expr_3 else
...
value_expr_n;
• Evaluation in ascending order
• Achieved by “priority-routing network”
• Top value expression has a “higher priority”
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2-to-1 “abstract” mux

• sel has a data type of boolean

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Detailed implementation
examples
• 2-to-1 mux

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• E.g.,

Conceptual Detailed
implementation ? implementation ?

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• E.g.,

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• E.g.,

Conceptual Detailed
implementation ? implementation ?

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• E.g.,

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• E.g.,

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4. Selected signal
assignment statement
• Syntax
• Examples
• Conceptual implementation
• Detailed implementation examples

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Syntax

• Simplified syntax:
with select_expression select
signal_name <=
value_expr_1 when choice_1,
value_expr_2 when choice_2,
value_expr_3 when choice_3,
...
value_expr_n when choice_n;

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• select_expression
– Discrete type or 1-D array
– With finite possible values
• choice_i
– A value of the data type
• Choices must be
– mutually exclusive
– all inclusive
– others can be used as last choice_i

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E.g., 4-to-1 mux

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• Can “11” be used to replace others?

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E.g., 2-to-22 binary decoder

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E.g., 4-to-2 priority encoder

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E.g., simple ALU

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E.g., Truth table

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Conceptual implementation

• Achieved by a multiplexing
circuit
• Abstract (k+1)-to-1
multiplexer
– sel is with a data type of
(k+1) values:
c0, c1, c2, . . . , ck

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– select_expression is with a data type of 5
values: c0, c1, c2, c3, c4

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Detailed implementation examples

• 4-to-1 mux

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• E.g.,

Conceptual
implementation ?

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• E.g.,

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3. Conditional vs.
selected signal
assignment
• Conversion between conditional vs.
selected signal assignment
• Comparison

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From selected
assignment to
conditional assignment

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From conditional assignment to
selected assignment

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 Comparison
• Selected signal assignment:
– good match for a circuit described by a functional table
– E.g., binary decoder, multiplexer
– Less effective when an input pattern is given a
preferential treatment

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• Conditional signal assignment:
– good match for a circuit that needs to give preferential
treatment for certain conditions or to prioritize the
operations
– E.g., priority encoder
– Can handle complicated conditions. e.g.,

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– May “over-specify” for a functional table based circuit.
– E.g., mux

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